diff options
| author | Jon Hunter <jonathanh@nvidia.com> | 2021-06-08 08:15:18 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-06-08 13:48:38 +0100 |
| commit | aceda401e84115bf9121454828f9da63c2a94482 (patch) | |
| tree | d8ce8736ad623e03360863182da777478ffecf67 /drivers/spi/spi-tegra20-slink.c | |
| parent | d38fa9a155b2829b7e2cfcf8a4171b6dd3672808 (diff) | |
| download | linux-aceda401e84115bf9121454828f9da63c2a94482.tar.gz linux-aceda401e84115bf9121454828f9da63c2a94482.tar.bz2 linux-aceda401e84115bf9121454828f9da63c2a94482.zip | |
spi: tegra20-slink: Ensure SPI controller reset is deasserted
Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling
clocks") removed some legacy code for handling resets on Tegra from
within the Tegra clock code. This exposed an issue in the Tegra20 slink
driver where the SPI controller reset was not being deasserted as needed
during probe. This is causing the Tegra30 Cardhu platform to hang on
boot. Fix this by ensuring the SPI controller reset is deasserted during
probe.
Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20210608071518.93037-1-jonathanh@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-tegra20-slink.c')
| -rw-r--r-- | drivers/spi/spi-tegra20-slink.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index f7c832fd4003..6a726c95ac7a 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c @@ -1118,6 +1118,11 @@ static int tegra_slink_probe(struct platform_device *pdev) pm_runtime_put_noidle(&pdev->dev); goto exit_pm_disable; } + + reset_control_assert(tspi->rst); + udelay(2); + reset_control_deassert(tspi->rst); + tspi->def_command_reg = SLINK_M_S; tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); |