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authorAndi Shyti <andi.shyti@samsung.com>2016-07-12 19:02:15 +0900
committerMark Brown <broonie@kernel.org>2016-07-14 17:28:32 +0100
commit0dbe70a1feb411d17fbcf8e73d61e6c7f33fda72 (patch)
tree327f15fd336469c556d18d311e3f5d94249e09cd /drivers/spi
parent7990b00819e765ca180d36b38969c2bde2734e53 (diff)
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spi: s3c64xx: restore removed comments
Patch a9e93e8 has erroneously removed some comments which are important to understand why the bus frequency is multiplied by two during the spi transfer. Reword the previous comment to a more appropriate message. Suggested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-s3c64xx.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index a1e84686c70c..3c09e94cf827 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -642,6 +642,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
writel(val, regs + S3C64XX_SPI_MODE_CFG);
if (sdd->port_conf->clk_from_cmu) {
+ /* The src_clk clock is divided internally by 2 */
clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
} else {
/* Configure Clock */