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| author | Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> | 2017-10-02 14:01:41 +0900 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2017-10-11 13:13:52 +0300 |
| commit | 29c7f3e68eec4ae94d85ad7b5dfdafdb8089f513 (patch) | |
| tree | 68c543373d9b2030f37dd28d823446e5740a599c /drivers/usb/renesas_usbhs | |
| parent | ab219221a5064abfff9f78c323c4a257b16cdb81 (diff) | |
| download | linux-29c7f3e68eec4ae94d85ad7b5dfdafdb8089f513.tar.gz linux-29c7f3e68eec4ae94d85ad7b5dfdafdb8089f513.tar.bz2 linux-29c7f3e68eec4ae94d85ad7b5dfdafdb8089f513.zip | |
usb: renesas_usbhs: Fix DMAC sequence for receiving zero-length packet
The DREQE bit of the DnFIFOSEL should be set to 1 after the DE bit of
USB-DMAC on R-Car SoCs is set to 1 after the USB-DMAC received a
zero-length packet. Otherwise, a transfer completion interruption
of USB-DMAC doesn't happen. Even if the driver changes the sequence,
normal operations (transmit/receive without zero-length packet) will
not cause any side-effects. So, this patch fixes the sequence anyway.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[shimoda: revise the commit log]
Fixes: e73a9891b3a1 ("usb: renesas_usbhs: add DMAEngine support")
Cc: <stable@vger.kernel.org> # v3.1+
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/renesas_usbhs')
| -rw-r--r-- | drivers/usb/renesas_usbhs/fifo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c index 68f26904c316..50285b01da92 100644 --- a/drivers/usb/renesas_usbhs/fifo.c +++ b/drivers/usb/renesas_usbhs/fifo.c @@ -857,9 +857,9 @@ static void xfer_work(struct work_struct *work) fifo->name, usbhs_pipe_number(pipe), pkt->length, pkt->zero); usbhs_pipe_running(pipe, 1); - usbhsf_dma_start(pipe, fifo); usbhs_pipe_set_trans_count_if_bulk(pipe, pkt->trans); dma_async_issue_pending(chan); + usbhsf_dma_start(pipe, fifo); usbhs_pipe_enable(pipe); xfer_work_end: |