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| author | Terry Bowman <terry.bowman@amd.com> | 2022-02-02 09:35:25 -0600 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@linux-watchdog.org> | 2022-03-27 17:04:33 +0200 |
| commit | 826270373f17fd8ebd10753ca0a5fd2ceb1dc38e (patch) | |
| tree | 31644e1f6baf4884fb47114b5179248756c1ebcb /drivers/watchdog/sp5100_tco.h | |
| parent | 0578fff4aae5bce3f09875f58e68e9ffbab8daf5 (diff) | |
| download | linux-826270373f17fd8ebd10753ca0a5fd2ceb1dc38e.tar.gz linux-826270373f17fd8ebd10753ca0a5fd2ceb1dc38e.tar.bz2 linux-826270373f17fd8ebd10753ca0a5fd2ceb1dc38e.zip | |
Watchdog: sp5100_tco: Enable Family 17h+ CPUs
The driver currently uses a CPU family match of 17h to determine
EFCH_PM_DECODEEN_WDT_TMREN register support. This family check will not
support future AMD CPUs and instead will require driver updates to add
support.
Remove the family 17h family check and add a check for SMBus PCI
revision ID 0x51 or greater. The MMIO access method has been available
since at least SMBus controllers using PCI revision 0x51. This revision
check will support family 17h and future AMD processors including EFCH
functionality without requiring driver changes.
Co-developed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Tested-by: Jean Delvare <jdelvare@suse.de>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220202153525.1693378-5-terry.bowman@amd.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Diffstat (limited to 'drivers/watchdog/sp5100_tco.h')
| -rw-r--r-- | drivers/watchdog/sp5100_tco.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/watchdog/sp5100_tco.h b/drivers/watchdog/sp5100_tco.h index 8ca1b215e3ce..6a0986d2c94b 100644 --- a/drivers/watchdog/sp5100_tco.h +++ b/drivers/watchdog/sp5100_tco.h @@ -89,3 +89,4 @@ #define EFCH_PM_ACPI_MMIO_PM_ADDR (EFCH_PM_ACPI_MMIO_ADDR + \ EFCH_PM_ACPI_MMIO_PM_OFFSET) #define EFCH_PM_ACPI_MMIO_PM_SIZE 8 +#define AMD_ZEN_SMBUS_PCI_REV 0x51 |