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| author | Takahisa Tanaka <mc74hc00@gmail.com> | 2013-03-03 14:48:00 +0900 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2013-03-22 23:21:55 +0100 |
| commit | 81fc933f176cd95f757bfc8a98109ef422598b79 (patch) | |
| tree | b939eeffde3fd3134ffbd8f22e94efbc0e405270 /drivers/watchdog | |
| parent | 18e4321276fcf083b85b788fee7cf15be29ed72a (diff) | |
| download | linux-81fc933f176cd95f757bfc8a98109ef422598b79.tar.gz linux-81fc933f176cd95f757bfc8a98109ef422598b79.tar.bz2 linux-81fc933f176cd95f757bfc8a98109ef422598b79.zip | |
watchdog: sp5100_tco: Set the AcpiMmioSel bitmask value to 1 instead of 2
The AcpiMmioSel bit is bit 1 in the AcpiMmioEn register, but the current
sp5100_tco driver is using bit 2.
See 2.3.3 Power Management (PM) Registers page 150 of the
AMD SB800-Series Southbridges Register Reference Guide [1].
AcpiMmioEn - RW – 8/16/32 bits - [PM_Reg: 24h]
Field Name Bits Default Description
AcpiMMioDecodeEn 0 0b Set to 1 to enable AcpiMMio space.
AcpiMMIoSel 1 0b Set AcpiMMio registers to be memory-mapped or IO-mapped space.
0: Memory-mapped space
1: I/O-mapped space
The sp5100_tco driver expects zero as a value of AcpiMmioSel (bit 1).
Fortunately, no problems were caused by this typo, because the default
value of the undocumented misused bit 2 seems to be zero.
However, the sp5100_tco driver should use the correct bitmask value.
[1] http://support.amd.com/us/Embedded_TechDocs/45482.pdf
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Cc: stable <stable@vger.kernel.org>
Diffstat (limited to 'drivers/watchdog')
| -rw-r--r-- | drivers/watchdog/sp5100_tco.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/watchdog/sp5100_tco.h b/drivers/watchdog/sp5100_tco.h index 71594a0c14b7..2b28c00da0df 100644 --- a/drivers/watchdog/sp5100_tco.h +++ b/drivers/watchdog/sp5100_tco.h @@ -57,7 +57,7 @@ #define SB800_PM_WATCHDOG_DISABLE (1 << 2) #define SB800_PM_WATCHDOG_SECOND_RES (3 << 0) #define SB800_ACPI_MMIO_DECODE_EN (1 << 0) -#define SB800_ACPI_MMIO_SEL (1 << 2) +#define SB800_ACPI_MMIO_SEL (1 << 1) #define SB800_PM_WDT_MMIO_OFFSET 0xB00 |