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authorSonic Zhang <sonic.zhang@analog.com>2012-06-13 16:22:43 +0800
committerWolfram Sang <w.sang@pengutronix.de>2012-07-13 08:36:07 +0200
commit2ee74eb95cf36b1a69e483f9ba2191bd8022b2c1 (patch)
tree9b7c67eec08cb2d43118cf570758e69fa2a1ab2f /drivers
parenta25733d6f6968240042ac94dc93c7ae3c9e8d68b (diff)
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i2c: i2c-bfin-twi: Tighten condition when failing I2C transfer if MEN bit is reset unexpectedly.
In order to mark I2C transfer fail when MEN bit in I2C controller is reset unexpectedly in MCOMP interrupt, interrupt status bits XMTSERV or RCVSERV should be checked. Master Transfer Complete (MCOMP). [1] The initiated master transfer has completed. In the absence of a repeat start, the bus has been released. [0] The completion of a transfer has not been detected. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> [wsa: fixed spaces around operators and typo in commit message] Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 5fb5f3ee13a2..71be486a224d 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -201,7 +201,8 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
return;
}
if (twi_int_status & MCOMP) {
- if ((read_MASTER_CTL(iface) & MEN) == 0 &&
+ if (twi_int_status & (XMTSERV | RCVSERV) &&
+ (read_MASTER_CTL(iface) & MEN) == 0 &&
(iface->cur_mode == TWI_I2C_MODE_REPEAT ||
iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
iface->result = -1;