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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2015-06-25 18:35:03 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-06-26 10:18:54 +0200 |
| commit | 5b7e4c9ce19038f88828309a0a61f5d5c6686d37 (patch) | |
| tree | 2aa996f613feb016a75d10f07cfc853d0e2a7b5e /drivers | |
| parent | 9e2ee2dd044e01e06e4a6389583f95bfa1058bf1 (diff) | |
| download | linux-5b7e4c9ce19038f88828309a0a61f5d5c6686d37.tar.gz linux-5b7e4c9ce19038f88828309a0a61f5d5c6686d37.tar.bz2 linux-5b7e4c9ce19038f88828309a0a61f5d5c6686d37.zip | |
drm/i915/gtt: Mark TLBS dirty for gen8+
When we touch gen8+ page maps, mark them dirty like we
do with previous gens.
v2: Update comment (Joonas)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 2279e030570c..bc4106375650 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -831,6 +831,16 @@ err_out: return -ENOMEM; } +/* PDE TLBs are a pain to invalidate on GEN8+. When we modify + * the page table structures, we mark them dirty so that + * context switching/execlist queuing code takes extra steps + * to ensure that tlbs are flushed. + */ +static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) +{ + ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; +} + static int gen8_alloc_va_range(struct i915_address_space *vm, uint64_t start, uint64_t length) @@ -916,6 +926,7 @@ static int gen8_alloc_va_range(struct i915_address_space *vm, } free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); + mark_tlbs_dirty(ppgtt); return 0; err_out: @@ -928,6 +939,7 @@ err_out: unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev); free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); + mark_tlbs_dirty(ppgtt); return ret; } @@ -1272,16 +1284,6 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, kunmap_atomic(pt_vaddr); } -/* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we - * are switching between contexts with the same LRCA, we also must do a force - * restore. - */ -static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) -{ - /* If current vm != vm, */ - ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; -} - static void gen6_initialize_pt(struct i915_address_space *vm, struct i915_page_table *pt) { |