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| author | Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> | 2012-02-02 23:11:20 +0530 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-02-10 12:01:56 -0800 |
| commit | 8161fe91d8da34c1a231b6e2d4454b4b3179a5d4 (patch) | |
| tree | cf7e7f08ff22f39abb6c748b121718149a6347b4 /drivers | |
| parent | 71f6bd4a23130cd2f4b036010c5790b1295290b9 (diff) | |
| download | linux-8161fe91d8da34c1a231b6e2d4454b4b3179a5d4.tar.gz linux-8161fe91d8da34c1a231b6e2d4454b4b3179a5d4.tar.bz2 linux-8161fe91d8da34c1a231b6e2d4454b4b3179a5d4.zip | |
PCI: set pci sriov page size before reading SRIOV BAR
For an SRIOV device, PCI_SRIOV_SYS_PGSIZE should be set before
the PCI_SRIOV_BAR are queried. The sys pagesize defaults to 4k,
so this change is required on powerpc box with 64k base page size.
This is a regression caused due to moving SRIOV init to sriov_enable().
| commit afd24ece5c76af87f6fc477f2747b83a764f161c
| Author: Ram Pai <linuxram@us.ibm.com>
| PCI: delay configuration of SRIOV capability
| The SRIOV capability, namely page size and total_vfs of a device are
| configured during enumeration phase of the device. This can potentially
| interfere with the PCI operations of the platform, if the IOV capability
| of the device is not enabled.
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Acked-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/iov.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 0321fa3b4226..0dab5ecf61bb 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -347,8 +347,6 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) return rc; } - pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz); - iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE; pci_cfg_access_lock(dev); pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl); @@ -466,6 +464,7 @@ found: return -EIO; pgsz &= ~(pgsz - 1); + pci_write_config_dword(dev, pos + PCI_SRIOV_SYS_PGSIZE, pgsz); nres = 0; for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |