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authorAbhilash Kesavan <a.kesavan@samsung.com>2014-10-28 16:48:55 +0530
committerSylwester Nawrocki <s.nawrocki@samsung.com>2014-10-31 10:45:54 +0100
commit932e98224d5602be17ed61d0e057e9326f12b59d (patch)
tree70aca870f3702329c26701766c955cfd5c212fc4 /drivers
parent2ab2dfe5d4eef6bad8cdd90dc6bba5a7660273d4 (diff)
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clk: samsung: exynos7: add gate clock for ADC block
Add clock support for the ADC interface in Exynos7. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/samsung/clk-exynos7.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 17e5cf4d2248..ea4483b8d62e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,6 +486,8 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 16, 0, 0),
+ GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
+ ENABLE_PCLK_PERIC0, 20, 0, 0),
GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 21, 0, 0),