diff options
| author | Bob Moore <robert.moore@intel.com> | 2012-02-14 18:29:55 +0800 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2012-03-22 01:44:54 -0400 |
| commit | 653f4b538f66d37db560e0f56af08117136d29b7 (patch) | |
| tree | 1728249946368a4befa5ade048bafeba9d9fddce /include/acpi/acpiosxf.h | |
| parent | 33620c5419e8a11814dd11e02a80e6ef77a43407 (diff) | |
| download | linux-653f4b538f66d37db560e0f56af08117136d29b7.tar.gz linux-653f4b538f66d37db560e0f56af08117136d29b7.tar.bz2 linux-653f4b538f66d37db560e0f56af08117136d29b7.zip | |
ACPICA: Expand OSL memory read/write interfaces to 64 bits
This change expands acpi_os_read_memory and acpi_os_write_memory to a
full 64 bits. This allows 64 bit transfers via the acpi_read and
acpi_write interfaces. Note: The internal acpi_hw_read and acpi_hw_write
interfaces remain at 32 bits, because 64 bits is not needed to
access the standard ACPI registers.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'include/acpi/acpiosxf.h')
| -rw-r--r-- | include/acpi/acpiosxf.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h index 7c9aebe8a7aa..1cd22045fbd4 100644 --- a/include/acpi/acpiosxf.h +++ b/include/acpi/acpiosxf.h @@ -217,14 +217,10 @@ acpi_status acpi_os_write_port(acpi_io_address address, u32 value, u32 width); * Platform and hardware-independent physical memory interfaces */ acpi_status -acpi_os_read_memory(acpi_physical_address address, u32 * value, u32 width); -acpi_status -acpi_os_read_memory64(acpi_physical_address address, u64 *value, u32 width); +acpi_os_read_memory(acpi_physical_address address, u64 *value, u32 width); acpi_status -acpi_os_write_memory(acpi_physical_address address, u32 value, u32 width); -acpi_status -acpi_os_write_memory64(acpi_physical_address address, u64 value, u32 width); +acpi_os_write_memory(acpi_physical_address address, u64 value, u32 width); /* * Platform and hardware-independent PCI configuration space access |