diff options
| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2005-06-24 23:11:31 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-06-24 23:11:31 +0100 |
| commit | 2966207c7e5945947c4db3a48aa4fa819807c5be (patch) | |
| tree | 07b447cf7769ae4be861650c24841ea9c12895ee /include/asm-arm/arch-ixp2000/io.h | |
| parent | 7533fca8e866ee7355ca53f1216e3fa4c718f991 (diff) | |
| download | linux-2966207c7e5945947c4db3a48aa4fa819807c5be.tar.gz linux-2966207c7e5945947c4db3a48aa4fa819807c5be.tar.bz2 linux-2966207c7e5945947c4db3a48aa4fa819807c5be.zip | |
[PATCH] ARM: 2748/1: ixp2000 implementation of the iomap api
Patch from Lennert Buytenhek
A number of ixp2000 models have a bug where the byte lanes for PCI I/O
transactions are swapped. We already work around this in our versions
of {in,out}{b,w,l}, but we also need to perform these workarounds in a
custom implementation of the new iomap API, provided in this patch.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Deepak Saxena
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-ixp2000/io.h')
| -rw-r--r-- | include/asm-arm/arch-ixp2000/io.h | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h index e5c742bc2330..5e56b47446e0 100644 --- a/include/asm-arm/arch-ixp2000/io.h +++ b/include/asm-arm/arch-ixp2000/io.h @@ -48,6 +48,78 @@ #define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) #define insl(p,d,l) __raw_readsl(___io(p),d,l) +#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE) + +#define ioread8(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readb(alignb(p)); \ + } else { \ + __v = __raw_readb(p); \ + } \ + \ + __v; \ + }) \ + +#define ioread16(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readw(alignw(p)); \ + } else { \ + __v = le16_to_cpu(__raw_readw(p)); \ + } \ + \ + __v; \ + }) + +#define ioread32(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readl(p); \ + } else { \ + __v = le32_to_cpu(__raw_readl(p)); \ + } \ + \ + __v; \ + }) + +#define iowrite8(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writeb((v), alignb(p)); \ + } else { \ + __raw_writeb((v), p); \ + } \ + }) + +#define iowrite16(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writew((v), alignw(p)); \ + } else { \ + __raw_writew(cpu_to_le16(v), p); \ + } \ + }) + +#define iowrite32(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writel((v), p); \ + } else { \ + __raw_writel(cpu_to_le32(v), p); \ + } \ + }) + +#define ioport_map(port, nr) ___io(port) + +#define ioport_unmap(addr) + #ifdef CONFIG_ARCH_IXDP2X01 /* |