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| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2006-06-23 02:04:13 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-23 07:42:56 -0700 |
| commit | f2c780c1fdbe5008c902c2d7e37242ac5e60f0b9 (patch) | |
| tree | f2fb215610897e06812548986f3c37a6d6dc38ca /include/asm-mips/mach-au1x00 | |
| parent | c52c17622e27876c2395f59cfe342497a399de41 (diff) | |
| download | linux-f2c780c1fdbe5008c902c2d7e37242ac5e60f0b9.tar.gz linux-f2c780c1fdbe5008c902c2d7e37242ac5e60f0b9.tar.bz2 linux-f2c780c1fdbe5008c902c2d7e37242ac5e60f0b9.zip | |
[PATCH] Au1550/1200: add missing PSC #define's, make OSS driver use the proper ones
Add missing PSC #define's required for the drivers using PSC on DBAu1550
board (also fixing Au1550 PSC3 address) and all Au1200-based boards as
well. Make the OSS driver use the correct PSC definitions fo each board.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-mips/mach-au1x00')
| -rw-r--r-- | include/asm-mips/mach-au1x00/au1xxx_psc.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h index 5c3e2a38ce12..d7cbacdd21fe 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_psc.h +++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h @@ -39,7 +39,12 @@ #define PSC0_BASE_ADDR 0xb1a00000 #define PSC1_BASE_ADDR 0xb1b00000 #define PSC2_BASE_ADDR 0xb0a00000 -#define PSC3_BASE_ADDR 0xb0d00000 +#define PSC3_BASE_ADDR 0xb0b00000 +#endif + +#ifdef CONFIG_SOC_AU1200 +#define PSC0_BASE_ADDR 0xb1a00000 +#define PSC1_BASE_ADDR 0xb1b00000 #endif /* The PSC select and control registers are common to @@ -227,6 +232,8 @@ typedef struct psc_i2s { #define PSC_I2SCFG_DD_DISABLE (1 << 27) #define PSC_I2SCFG_DE_ENABLE (1 << 26) #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) +#define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16) +#define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) #define PSC_I2SCFG_WI (1 << 15) #define PSC_I2SCFG_DIV_MASK (3 << 13) |