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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2007-05-08 16:27:28 +1000
committerPaul Mackerras <paulus@samba.org>2007-05-09 16:35:00 +1000
commit16c2d476232523260c495eafbf9cdc1be984b7df (patch)
treefb6614b9752b51864e121317478088978823792c /include/asm-powerpc/pgtable-4k.h
parentd0f13e3c20b6fb73ccb467bdca97fa7cf5a574cd (diff)
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[POWERPC] Add ability to 4K kernel to hash in 64K pages
This adds the ability for a kernel compiled with 4K page size to have special slices containing 64K pages and hash the right type of hash PTEs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc/pgtable-4k.h')
-rw-r--r--include/asm-powerpc/pgtable-4k.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-powerpc/pgtable-4k.h b/include/asm-powerpc/pgtable-4k.h
index 1744d6ac12a2..add5481fd7c7 100644
--- a/include/asm-powerpc/pgtable-4k.h
+++ b/include/asm-powerpc/pgtable-4k.h
@@ -80,7 +80,11 @@
#define pte_iterate_hashed_end() } while(0)
-#define pte_pagesize_index(pte) MMU_PAGE_4K
+#ifdef CONFIG_PPC_HAS_HASH_64K
+#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
+#else
+#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
+#endif
/*
* 4-level page tables related bits