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| author | Shawn Guo <shawn.guo@freescale.com> | 2014-09-01 14:17:48 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-09-16 10:06:48 +0800 |
| commit | b1f156db47ae914a308488ce28e84f3d4ad4f667 (patch) | |
| tree | aa6508f3f033301952702c5aaad01f520e78b118 /include/dt-bindings/clock | |
| parent | 19d863446a6b75b2f97b3012acf67c40b9f2ea1f (diff) | |
| download | linux-b1f156db47ae914a308488ce28e84f3d4ad4f667.tar.gz linux-b1f156db47ae914a308488ce28e84f3d4ad4f667.tar.bz2 linux-b1f156db47ae914a308488ce28e84f3d4ad4f667.zip | |
ARM: imx6q: add BYPASS support for PLL clocks
The imx6q clock driver currently hard-codes all PLL clocks to source
from OSC24M without BYPASS support. The patch adds the missing lvds_in
clock which is mutually exclusive with lvds_gate, and implements BYPASS
and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary
Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits
are implemented as mux clocks, and ENABLE bit of PLL clocks is
implemented as a gate clock after BYPASS mux.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/imx6qdl-clock.h | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 1e996135cfc7..c0d88ab013b4 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -222,6 +222,31 @@ #define IMX6QDL_CLK_ESAI_MEM 209 #define IMX6QDL_CLK_ASRC_IPG 210 #define IMX6QDL_CLK_ASRC_MEM 211 -#define IMX6QDL_CLK_END 212 +#define IMX6QDL_CLK_LVDS1_IN 212 +#define IMX6QDL_CLK_LVDS2_IN 213 +#define IMX6QDL_CLK_ANACLK1 214 +#define IMX6QDL_CLK_ANACLK2 215 +#define IMX6QDL_PLL1_BYPASS_SRC 216 +#define IMX6QDL_PLL2_BYPASS_SRC 217 +#define IMX6QDL_PLL3_BYPASS_SRC 218 +#define IMX6QDL_PLL4_BYPASS_SRC 219 +#define IMX6QDL_PLL5_BYPASS_SRC 220 +#define IMX6QDL_PLL6_BYPASS_SRC 221 +#define IMX6QDL_PLL7_BYPASS_SRC 222 +#define IMX6QDL_CLK_PLL1 223 +#define IMX6QDL_CLK_PLL2 224 +#define IMX6QDL_CLK_PLL3 225 +#define IMX6QDL_CLK_PLL4 226 +#define IMX6QDL_CLK_PLL5 227 +#define IMX6QDL_CLK_PLL6 228 +#define IMX6QDL_CLK_PLL7 229 +#define IMX6QDL_PLL1_BYPASS 230 +#define IMX6QDL_PLL2_BYPASS 231 +#define IMX6QDL_PLL3_BYPASS 232 +#define IMX6QDL_PLL4_BYPASS 233 +#define IMX6QDL_PLL5_BYPASS 234 +#define IMX6QDL_PLL6_BYPASS 235 +#define IMX6QDL_PLL7_BYPASS 236 +#define IMX6QDL_CLK_END 237 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ |