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author | Eric Anholt <eric@anholt.net> | 2017-01-18 07:31:55 +1100 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-01-20 16:22:54 -0800 |
commit | 55486091bd1e1c5ed28c43c0d6b3392468a9adb5 (patch) | |
tree | e4faf5b7fd4ed0f561cec23cdba2dee39610b7dc /include/dt-bindings | |
parent | 0c744ea4f77d72b3dcebb7a8f2684633ec79be88 (diff) | |
download | linux-55486091bd1e1c5ed28c43c0d6b3392468a9adb5.tar.gz linux-55486091bd1e1c5ed28c43c0d6b3392468a9adb5.tar.bz2 linux-55486091bd1e1c5ed28c43c0d6b3392468a9adb5.zip |
clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.
Our core PLLs are intended to be configured once and left alone. With
the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
change PLLD just to get closer to the requested DSI clock, thus
changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
it, and breaking ethernet.
We *do* want PLLH to change so that PLLH_AUX can be exactly the value
we want, though. Thus, we need to have a per-divider policy of
whether to pass rate changes up.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/dt-bindings')
0 files changed, 0 insertions, 0 deletions