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authorJiancheng Xue <xuejiancheng@huawei.com>2014-05-28 11:35:32 +0800
committerWei Xu <xuwei5@hisilicon.com>2014-09-28 10:27:01 +0800
commitcc855dd9994cfd179891cf5b966ebc8051d95a9f (patch)
tree88bfdf7ea09dca7cbf51e3cdb9dc6e4288146c23 /include/dt-bindings
parent20e075585973453515be6615b91901c959e0a573 (diff)
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clk: hix5hd2: add sd clk
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/hix5hd2-clock.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h
index e3286695382d..5bd4135c9544 100644
--- a/include/dt-bindings/clock/hix5hd2-clock.h
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -46,6 +46,7 @@
#define HIX5HD2_SFC_MUX 64
#define HIX5HD2_MMC_MUX 65
#define HIX5HD2_FEPHY_MUX 66
+#define HIX5HD2_SD_MUX 67
/* gate clocks */
#define HIX5HD2_SFC_RST 128
@@ -56,6 +57,9 @@
#define HIX5HD2_FWD_BUS_CLK 133
#define HIX5HD2_FWD_SYS_CLK 134
#define HIX5HD2_MAC0_PHY_CLK 135
+#define HIX5HD2_SD_CIU_CLK 136
+#define HIX5HD2_SD_BIU_CLK 137
+#define HIX5HD2_SD_CIU_RST 138
/* complex */
#define HIX5HD2_MAC0_CLK 192