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| author | Liu Ying <Ying.Liu@freescale.com> | 2015-02-12 14:01:29 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2015-03-02 20:52:13 +0800 |
| commit | 5ccc248cc53708337a2bfe4ea380c20948e8bbed (patch) | |
| tree | d0c9d3d0bcd14fe588e50d756bd6095abadbc858 /include/dt-bindings | |
| parent | 721fee59d26e46700476f4c70572e9e0f1cc8fd3 (diff) | |
| download | linux-5ccc248cc53708337a2bfe4ea380c20948e8bbed.tar.gz linux-5ccc248cc53708337a2bfe4ea380c20948e8bbed.tar.bz2 linux-5ccc248cc53708337a2bfe4ea380c20948e8bbed.zip | |
ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the hsi_tx_sel clock's output and the
video_27m clock's output. The MIPI DSI host controller embedded in the
i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and
MIPI core configuration clock. In order to gate/ungate the two MIPI DSI
host controller relevant clocks, this patch adds the mipi_core_cfg clock as
a shared clock gate.
Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/imx6qdl-clock.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 25625bf3927b..dbc828c23a17 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -249,6 +249,7 @@ #define IMX6QDL_PLL7_BYPASS 236 #define IMX6QDL_CLK_GPT_3M 237 #define IMX6QDL_CLK_VIDEO_27M 238 -#define IMX6QDL_CLK_END 239 +#define IMX6QDL_CLK_MIPI_CORE_CFG 239 +#define IMX6QDL_CLK_END 240 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ |