diff options
| author | Kevin Hilman <khilman@baylibre.com> | 2019-08-29 16:12:46 -0700 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2019-08-29 16:12:46 -0700 |
| commit | b8b1c9ad1c20cb1373baaed87aebe4f944a65e83 (patch) | |
| tree | b925c1919d6c70a3e7b82ec4cf00a8bee0400663 /include/dt-bindings | |
| parent | 77657b805b926b44b2545a352b209d85c0932e0b (diff) | |
| parent | cda4569137b90f200bee4922d894ca49d4188681 (diff) | |
| download | linux-b8b1c9ad1c20cb1373baaed87aebe4f944a65e83.tar.gz linux-b8b1c9ad1c20cb1373baaed87aebe4f944a65e83.tar.bz2 linux-b8b1c9ad1c20cb1373baaed87aebe4f944a65e83.zip | |
Merge tag 'clk-meson-dt-v5.4-3' of git://github.com/BayLibre/clk-meson into v5.4/dt64-2
Amlogic clk dt bindings changes for v5.4 - 3rd round
* add sm1 peripheral controller bindings
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/g12a-clkc.h | 5 | ||||
| -rw-r--r-- | include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h | 38 |
2 files changed, 43 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 8ccc29ac7a72..0837c1a7ae49 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -138,5 +138,10 @@ #define CLKID_VDEC_HEVCF 210 #define CLKID_TS 212 #define CLKID_CPUB_CLK 224 +#define CLKID_GP1_PLL 243 +#define CLKID_DSU_CLK 252 +#define CLKID_CPU1_CLK 253 +#define CLKID_CPU2_CLK 254 +#define CLKID_CPU3_CLK 255 #endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h new file mode 100644 index 000000000000..14b78dabed0e --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H + +#define AUD_RESET_PDM 0 +#define AUD_RESET_TDMIN_A 1 +#define AUD_RESET_TDMIN_B 2 +#define AUD_RESET_TDMIN_C 3 +#define AUD_RESET_TDMIN_LB 4 +#define AUD_RESET_LOOPBACK 5 +#define AUD_RESET_TODDR_A 6 +#define AUD_RESET_TODDR_B 7 +#define AUD_RESET_TODDR_C 8 +#define AUD_RESET_FRDDR_A 9 +#define AUD_RESET_FRDDR_B 10 +#define AUD_RESET_FRDDR_C 11 +#define AUD_RESET_TDMOUT_A 12 +#define AUD_RESET_TDMOUT_B 13 +#define AUD_RESET_TDMOUT_C 14 +#define AUD_RESET_SPDIFOUT 15 +#define AUD_RESET_SPDIFOUT_B 16 +#define AUD_RESET_SPDIFIN 17 +#define AUD_RESET_EQDRC 18 +#define AUD_RESET_RESAMPLE 19 +#define AUD_RESET_DDRARB 20 +#define AUD_RESET_POWDET 21 +#define AUD_RESET_TORAM 22 +#define AUD_RESET_TOACODEC 23 +#define AUD_RESET_TOHDMITX 24 +#define AUD_RESET_CLKTREE 25 + +#endif |