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authorLinus Walleij <linus.walleij@stericsson.com>2010-06-02 08:13:52 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-27 10:43:47 +0100
commitec489aa8f993f8d2ec962ce113071faac482aa27 (patch)
treefa7a56687acb12f7bf928da04296a83b5ce0be10 /include/linux/amba/serial.h
parentc58bbd39f876955be6e072748fdfe2b671f9d939 (diff)
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ARM: 6157/2: PL011 TX/RX split of LCR for ST-Ericssons derivative
In the ST-Ericsson version of the PL011 the TX and RX have different control registers. Cc: Alessandro Rubini <rubini@unipv.it> Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/linux/amba/serial.h')
-rw-r--r--include/linux/amba/serial.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index 5a5a7fd62490..93c96a66c518 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -38,10 +38,12 @@
#define UART01x_FR 0x18 /* Flag register (Read only). */
#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */
#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
+#define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
#define UART011_LCRH 0x2c /* Line control register. */
+#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
#define UART011_CR 0x30 /* Control register. */
#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
#define UART011_IMSC 0x38 /* Interrupt mask. */