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author | Tero Kristo <t-kristo@ti.com> | 2016-02-20 13:24:26 +0200 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-02-22 14:16:49 -0800 |
commit | b6f5128459a40410f9afefddc0ad688ea5b22c28 (patch) | |
tree | dfd2a78beabd091b5c49d8aa045497061c1d1855 /include/linux/clk | |
parent | 1e59403990acfb67d0e9ddf57fe6acc1c2aff4dc (diff) | |
download | linux-b6f5128459a40410f9afefddc0ad688ea5b22c28.tar.gz linux-b6f5128459a40410f9afefddc0ad688ea5b22c28.tar.bz2 linux-b6f5128459a40410f9afefddc0ad688ea5b22c28.zip |
clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrs
Convert DPLL support code to use clk_hw pointers for reference and bypass
clocks. This allows us to use clk_hw_* APIs for accessing any required
parameters for these clocks, avoiding some locking problems at least with
DPLL enable code; this used clk_get_rate which uses mutex but isn't
good under clk_enable / clk_disable.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/linux/clk')
-rw-r--r-- | include/linux/clk/ti.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 9a638601cb09..dc5164a6df29 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -23,8 +23,8 @@ * @mult_div1_reg: register containing the DPLL M and N bitfields * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input + * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input + * @clk_ref: struct clk_hw pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() @@ -69,8 +69,8 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; + struct clk_hw *clk_bypass; + struct clk_hw *clk_ref; void __iomem *control_reg; u32 enable_mask; unsigned long last_rounded_rate; |