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| author | Peter Chen <peter.chen@freescale.com> | 2014-09-22 16:45:39 +0800 |
|---|---|---|
| committer | Peter Chen <peter.chen@freescale.com> | 2015-08-14 09:13:11 +0800 |
| commit | df96ed8dced21426c54c7f69cf7513e75280957a (patch) | |
| tree | 863774459f0a85a6487545fe8bc8c9e0a899c525 /include/linux/usb | |
| parent | 1bd57127d4aaff518cf93f4809ec2f11b2baf865 (diff) | |
| download | linux-df96ed8dced21426c54c7f69cf7513e75280957a.tar.gz linux-df96ed8dced21426c54c7f69cf7513e75280957a.tar.bz2 linux-df96ed8dced21426c54c7f69cf7513e75280957a.zip | |
usb: chipidea: introduce ITC tuning interface
ITC (Interrupt Threshold Control) is used to set the maximum rate at which
the host/device controller will issue interrupts. The default value is 8 (1ms)
for it. EHCI core will modify it to 1, but device mode keeps it as default
value.
In some use cases like Android ADB, it only has one usb request for each
direction, and maximum payload data is only 4KB, so the speed is 4MB/s
at most, it needs controller to trigger interrupt as fast as possible
to increase the speed. The USB performance will be better if the interrupt
can be triggered faster.
Reduce ITC value is benefit for USB performance, but the interrupt number
is increased at the same time, it may increase cpu utilization too.
Most of use case cares about performance, but some may care about
cpu utilization, so, we leave a platform interface for user.
We set ITC as 1 (1 micro-frame) as default value which is aligned
with ehci core default value.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Diffstat (limited to 'include/linux/usb')
| -rw-r--r-- | include/linux/usb/chipidea.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index d1e1285a971d..1c5d7763990a 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -36,6 +36,8 @@ struct ci_hdrc_platform_data { void (*notify_event) (struct ci_hdrc *ci, unsigned event); struct regulator *reg_vbus; bool tpl_support; + /* interrupt threshold setting */ + u32 itc_setting; }; /* Default offset of capability registers */ |