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authorJunwei Zhang <Jerry.Zhang@amd.com>2017-04-27 11:12:07 +0800
committerAlex Deucher <alexander.deucher@amd.com>2017-04-28 17:33:13 -0400
commit408bfe7c3c5d036947b509356f494dc6b46025ff (patch)
treea21b4822d32cb8603697806281182eca8844ab56 /include/uapi
parent2c55b16bf0e1492ba662d884c81d324538cafce1 (diff)
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drm/amdgpu: export more gpu info for gfx9
v2: 64-bit aligned for gpu info v3: squash in wave_front_fix Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Qiang Yu <Qiang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/uapi')
-rw-r--r--include/uapi/drm/amdgpu_drm.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 95260e5043af..6c249e5cfb09 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -767,6 +767,25 @@ struct drm_amdgpu_info_device {
__u64 cntl_sb_buf_gpu_addr;
/* NGG Parameter Cache */
__u64 param_buf_gpu_addr;
+ __u32 prim_buf_size;
+ __u32 pos_buf_size;
+ __u32 cntl_sb_buf_size;
+ __u32 param_buf_size;
+ /* wavefront size*/
+ __u32 wave_front_size;
+ /* shader visible vgprs*/
+ __u32 num_shader_visible_vgprs;
+ /* CU per shader array*/
+ __u32 num_cu_per_sh;
+ /* number of tcc blocks*/
+ __u32 num_tcc_blocks;
+ /* gs vgt table depth*/
+ __u32 gs_vgt_table_depth;
+ /* gs primitive buffer depth*/
+ __u32 gs_prim_buffer_depth;
+ /* max gs wavefront per vgt*/
+ __u32 max_gs_waves_per_vgt;
+ __u32 _pad1;
};
struct drm_amdgpu_info_hw_ip {