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authorDave Airlie <airlied@redhat.com>2013-04-17 08:48:23 +1000
committerDave Airlie <airlied@redhat.com>2013-04-17 08:48:23 +1000
commitf18353eee7570412adca210b4968ecf2783754ba (patch)
treef42a655004a9ed7047bfca6bce694ea7a395f0e6 /include/uapi
parent62c8ba7c58e4163f975c5f8b5a3dd5f306a2deda (diff)
parent466476dfdcafbb4286ffa232a3a792731b9dc852 (diff)
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Merge branch 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes: This is the initial 3.10 pull request for radeon. The big changes here are UVD support and proper tiling support for SI. The rest is bug fixes. I hope to have another pull request later in the week with some new things we've been working on internally. * 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux: (28 commits) drm/radeon: Always flush the VM drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TN drm/radeon: cleanup properly if mmio mapping fails drm/radeon/evergreen+: don't enable HPD interrupts on eDP/LVDS drm/radeon: add si tile mode array query v3 drm/radeon: add ring working query drm/radeon: handle broken disabled rb mask gracefully drm/radeon: add pcie set/get lanes callbacks for newer asics drm/radeon: update r600 set/get pcie lane config drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT drm/radeon: remove unused blit remnants from si.c drm/radeon: add UVD tiling addr config v2 drm/radeon: init UVD clocks to sane defaults drm/radeon: add set_uvd_clocks callback for r7xx v3 drm/radeon: add set_uvd_clocks callback for SI drm/radeon: add set_uvd_clocks callback for evergreen drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4) drm/radeon: add radeon_atom_get_clock_dividers helper drm/radeon: add pm callback for setting uvd clocks drm/radeon: UVD bringup v8 ...
Diffstat (limited to 'include/uapi')
-rw-r--r--include/uapi/drm/radeon_drm.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index eeda91774c8a..321d4ac5c512 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -918,6 +918,7 @@ struct drm_radeon_gem_va {
#define RADEON_CS_RING_GFX 0
#define RADEON_CS_RING_COMPUTE 1
#define RADEON_CS_RING_DMA 2
+#define RADEON_CS_RING_UVD 3
/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
/* 0 = normal, + = higher priority, - = lower priority */
@@ -972,6 +973,13 @@ struct drm_radeon_cs {
#define RADEON_INFO_MAX_SE 0x12
/* max SH per SE */
#define RADEON_INFO_MAX_SH_PER_SE 0x13
+/* fast fb access is enabled */
+#define RADEON_INFO_FASTFB_WORKING 0x14
+/* query if a RADEON_CS_RING_* submission is supported */
+#define RADEON_INFO_RING_WORKING 0x15
+/* SI tile mode array */
+#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
+
struct drm_radeon_info {
uint32_t request;
@@ -979,4 +987,22 @@ struct drm_radeon_info {
uint64_t value;
};
+/* Those correspond to the tile index to use, this is to explicitly state
+ * the API that is implicitly defined by the tile mode array.
+ */
+#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
+#define SI_TILE_MODE_COLOR_1D 13
+#define SI_TILE_MODE_COLOR_1D_SCANOUT 9
+#define SI_TILE_MODE_COLOR_2D_8BPP 14
+#define SI_TILE_MODE_COLOR_2D_16BPP 15
+#define SI_TILE_MODE_COLOR_2D_32BPP 16
+#define SI_TILE_MODE_COLOR_2D_64BPP 17
+#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
+#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
+#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
+#define SI_TILE_MODE_DEPTH_STENCIL_2D 0
+#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
+#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
+#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
+
#endif