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| author | Dave Airlie <airlied@redhat.com> | 2019-01-10 05:53:51 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2019-01-10 05:58:52 +1000 |
| commit | 8c1a765bc62c93be2803f4541363a1c06355243e (patch) | |
| tree | be6a5a6a8f22147e8dfcacbfaa2869272ca97c79 /include/uapi | |
| parent | bfeffd155283772bbe78c6a05dec7c0128ee500c (diff) | |
| parent | 1c95f662fceeb8ae2f34e3de9478e21fd31f09dd (diff) | |
| download | linux-8c1a765bc62c93be2803f4541363a1c06355243e.tar.gz linux-8c1a765bc62c93be2803f4541363a1c06355243e.tar.bz2 linux-8c1a765bc62c93be2803f4541363a1c06355243e.zip | |
Merge tag 'drm-misc-next-2019-01-07-1' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for 5.1:
UAPI Changes:
Cross-subsystem Changes:
- Turn dma-buf fence sequence numbers into 64 bit numbers
Core Changes:
- Move to a common helper for the DP MST hotplug for radeon, i915 and
amdgpu
- i2c improvements for drm_dp_mst
- Removal of drm_syncobj_cb
- Introduction of an helper to create and attach the TV margin properties
Driver Changes:
- Improve cache flushes for v3d
- Reflection support for vc4
- HDMI overscan support for vc4
- Add implicit fencing support for rockchip and sun4i
- Switch to generic fbdev emulation for virtio
Signed-off-by: Dave Airlie <airlied@redhat.com>
[airlied: applied amdgpu merge fixup]
From: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190107180333.amklwycudbsub3s5@flea
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/drm/v3d_drm.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/uapi/drm/v3d_drm.h b/include/uapi/drm/v3d_drm.h index 35c7d813c66e..ea70669d2138 100644 --- a/include/uapi/drm/v3d_drm.h +++ b/include/uapi/drm/v3d_drm.h @@ -52,6 +52,14 @@ extern "C" { * * This asks the kernel to have the GPU execute an optional binner * command list, and a render command list. + * + * The L1T, slice, L2C, L2T, and GCA caches will be flushed before + * each CL executes. The VCD cache should be flushed (if necessary) + * by the submitted CLs. The TLB writes are guaranteed to have been + * flushed by the time the render done IRQ happens, which is the + * trigger for out_sync. Any dirtying of cachelines by the job (only + * possible using TMU writes) must be flushed by the caller using the + * CL's cache flush commands. */ struct drm_v3d_submit_cl { /* Pointer to the binner command list. |