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| author | Anatol Pomozov <anatol.pomozov@gmail.com> | 2015-10-08 09:37:51 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-10-23 01:21:14 +0900 |
| commit | 1d387a3fd86f2acf70803262c5a5a5a89df0e097 (patch) | |
| tree | 66fee8363e7379d59c09d7a14ecb219d1d820ee1 /include | |
| parent | 6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f (diff) | |
| download | linux-1d387a3fd86f2acf70803262c5a5a5a89df0e097.tar.gz linux-1d387a3fd86f2acf70803262c5a5a5a89df0e097.tar.bz2 linux-1d387a3fd86f2acf70803262c5a5a5a89df0e097.zip | |
ASoC: Document DAI signal polarity
Currently there is no clear definition of what FSYNC polarity is.
Different drivers use its own definition of what is "normal" and what is
"inverted" fsync. This leads to compatibility problems between drivers.
For example TegraX1 driver assumes that DSP-A format with frames
starting at rising FSYNC edge has "inverted" polarity,
while RT5677 assumes it is "normal" polarity.
Explicitly specify meaning of BCLK/FSYNC polarity to avoid future
compatibility problems.
Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/sound/soc-dai.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h index 2df96b1384c7..91e2e61d584c 100644 --- a/include/sound/soc-dai.h +++ b/include/sound/soc-dai.h @@ -48,10 +48,25 @@ struct snd_compr_stream; #define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */ /* - * DAI hardware signal inversions. + * DAI hardware signal polarity. * * Specifies whether the DAI can also support inverted clocks for the specified * format. + * + * BCLK: + * - "normal" polarity means signal is available at rising edge of BCLK + * - "inverted" polarity means signal is available at falling edge of BCLK + * + * FSYNC "normal" polarity depends on the frame format: + * - I2S: frame consists of left then right channel data. Left channel starts + * with falling FSYNC edge, right channel starts with rising FSYNC edge. + * - Left/Right Justified: frame consists of left then right channel data. + * Left channel starts with rising FSYNC edge, right channel starts with + * falling FSYNC edge. + * - DSP A/B: Frame starts with rising FSYNC edge. + * - AC97: Frame starts with rising FSYNC edge. + * + * "Negative" FSYNC polarity is the one opposite of "normal" polarity. */ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */ #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ |