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author | Abhishek Sahu <absahu@codeaurora.org> | 2016-11-25 21:11:28 +0530 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-12-21 15:57:25 -0800 |
commit | 4577aa01a5d12737c6f8109013651c97535a79b5 (patch) | |
tree | 43794dc9e7f8525c9ef0ba8f66b02a3818e3fe36 /include | |
parent | 2aab7a2055a1705c9e30920d95a596226999eb21 (diff) | |
download | linux-4577aa01a5d12737c6f8109013651c97535a79b5.tar.gz linux-4577aa01a5d12737c6f8109013651c97535a79b5.tar.bz2 linux-4577aa01a5d12737c6f8109013651c97535a79b5.zip |
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
The current ipq4019 clock driver registered the PLL clocks and
dividers as fixed clock. These fixed clock needs to be removed
from driver probe function and same need to be registered with
clock framework. These PLL clocks should be programmed only
once and the same are being programmed already by the boot
loader so the set rate operation is not required for these
clocks. Only the rate can be calculated by clock operations
in clock driver file so this patch adds the same.
The PLL takes the reference clock from XO and generates the
intermediate VCO frequency. This VCO frequency will be divided
down by different PLL internal dividers. Some of the PLL
internal dividers are fixed while other are programmable.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/dt-bindings/clock/qcom,gcc-ipq4019.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h index 6240e5b0e900..a906d46198b4 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h @@ -81,6 +81,15 @@ #define GCC_WCSS5G_CLK 62 #define GCC_WCSS5G_REF_CLK 63 #define GCC_WCSS5G_RTC_CLK 64 +#define GCC_APSS_DDRPLL_VCO 65 +#define GCC_SDCC_PLLDIV_CLK 66 +#define GCC_FEPLL_VCO 67 +#define GCC_FEPLL125_CLK 68 +#define GCC_FEPLL125DLY_CLK 69 +#define GCC_FEPLL200_CLK 70 +#define GCC_FEPLL500_CLK 71 +#define GCC_FEPLL_WCSS2G_CLK 72 +#define GCC_FEPLL_WCSS5G_CLK 73 #define WIFI0_CPU_INIT_RESET 0 #define WIFI0_RADIO_SRIF_RESET 1 |