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authorBrian Norris <computersforpeace@gmail.com>2016-01-29 11:25:36 -0800
committerBrian Norris <computersforpeace@gmail.com>2016-03-07 18:01:57 -0800
commit3dd8012a8eeb3702fa17450ec1a16a3f38af138d (patch)
tree699d4370d9e17fd294f695f7942debd3684c7a5c /include
parent76a4707de5e18dc32d9cb4e990686140c5664a15 (diff)
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mtd: spi-nor: add TB (Top/Bottom) protect support
Some flash support a bit in the status register that inverts protection so that it applies to the bottom of the flash, not the top. This yields additions to the protection range table, as noted in the comments. Because this feature is not universal to all flash that support lock/unlock, control it via a new flag. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mtd/spi-nor.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 62356d50815b..3c36113a88e1 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -85,6 +85,7 @@
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
+#define SR_TB BIT(5) /* Top/Bottom protect */
#define SR_SRWD BIT(7) /* SR write protect */
#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
@@ -116,6 +117,7 @@ enum spi_nor_ops {
enum spi_nor_option_flags {
SNOR_F_USE_FSR = BIT(0),
+ SNOR_F_HAS_SR_TB = BIT(1),
};
/**