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| author | Paul Burton <paul.burton@imgtec.com> | 2017-08-12 21:36:28 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-09-04 13:53:14 +0200 |
| commit | 3ee50dcbef374651056ea42d5eb543bbacb3ff41 (patch) | |
| tree | e500ce8acacabb04ea1fea62794d1a127bd262f1 /include | |
| parent | ba9cc4352e9c40ab3b158620a1bd9cd53295ea17 (diff) | |
| download | linux-3ee50dcbef374651056ea42d5eb543bbacb3ff41.tar.gz linux-3ee50dcbef374651056ea42d5eb543bbacb3ff41.tar.bz2 linux-3ee50dcbef374651056ea42d5eb543bbacb3ff41.zip | |
irqchip: mips-gic: Remove GIC_CPU_INT* macros
The GIC_CPU_INT* macros are never used. Remove the dead code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17038/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/irqchip/mips-gic.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 9546947d1842..e93aaf529baa 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -21,14 +21,6 @@ #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 -/* GIC nomenclature for Core Interrupt Pins. */ -#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ -#define GIC_CPU_INT1 1 /* . */ -#define GIC_CPU_INT2 2 /* . */ -#define GIC_CPU_INT3 3 /* . */ -#define GIC_CPU_INT4 4 /* . */ -#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ - /* Add 2 to convert GIC CPU pin to core interrupt */ #define GIC_CPU_PIN_OFFSET 2 |