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authorDave Airlie <airlied@redhat.com>2016-12-09 12:28:16 +1000
committerDave Airlie <airlied@redhat.com>2016-12-09 12:28:16 +1000
commitbfd5be0f9e0cdcaafaeaa1d59fbcfb5bacb1105a (patch)
tree40c7c5ad3dd63f1526eb0820ebebc72df2904e5d /include
parent6f21890989b761d2f5a0d89a4dac1f6531be7d44 (diff)
parent32859f7335d838ee373c40ee0b3c0c6ebc87a488 (diff)
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Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-next
Misc fixes and cleanups for 4.10. Highlights: - Cursor fixes for radeon and amdgpu - DPM fixes for some new SI variants - Powerplay fixes - Clock and powergating fixes * 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (39 commits) drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well drm/amdgpu: use pin rather than pin_restricted in a few cases drm/amd/powerplay: use pr_debug to print function not implemented message drm/amd/amdgpu: Add gpr reading for GFX v7 drm/amd/amdgpu: Add gpr reading for GFX v6 drm/amd/amdgpu: Add debugfs support for reading GPRs (v2) drm/amd/amdgpu: export vbios information (v2) drm/amd/amdgpu: stored bios_size drm/amdgpu: update golden setting of tonga drm/amdgpu/si: load the proper firmware on 0x87 oland boards drm/amdgpu: add additional pci revision to dpm workaround drm/radeon/si: load the proper firmware on 0x87 oland boards drm/radeon: add additional pci revision to dpm workaround drm/amd/powerplay: Fix potential NULL pointer issue drm/amdgpu: Don't touch GFX hw during HW fini drm/amd/powerplay: Adjust the position of data size initial drm/amd/powerplay: Ignore smu buffer usage drm/amd/powerplay: cut digest part drm/amdgpu: drop redundant vi_mqd define drm/amdgpu: fix gtt available page num accounting ...
Diffstat (limited to 'include')
-rw-r--r--include/uapi/drm/amdgpu_drm.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 2191a9e4f3db..396183628f3c 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -522,6 +522,12 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_MEMORY 0x19
/* Query vce clock table */
#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
+/* Query vbios related information */
+#define AMDGPU_INFO_VBIOS 0x1B
+ /* Subquery id: Query vbios size */
+ #define AMDGPU_INFO_VBIOS_SIZE 0x1
+ /* Subquery id: Query vbios image */
+ #define AMDGPU_INFO_VBIOS_IMAGE 0x2
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -580,6 +586,11 @@ struct drm_amdgpu_info {
} read_mmr_reg;
struct drm_amdgpu_query_fw query_fw;
+
+ struct {
+ __u32 type;
+ __u32 offset;
+ } vbios_info;
};
};