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| author | Shanker Donthineni <shankerd@codeaurora.org> | 2016-06-06 18:17:32 -0500 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-06-13 11:53:53 +0100 |
| commit | 3faf24ea894a34887c0ca412f1643540251b9d82 (patch) | |
| tree | d9a76efb52099343bbe054c007146995c35ee1aa /include | |
| parent | 0e0b0f69c5c528a750479c9bc9ba904df014517c (diff) | |
| download | linux-3faf24ea894a34887c0ca412f1643540251b9d82.tar.gz linux-3faf24ea894a34887c0ca412f1643540251b9d82.tar.bz2 linux-3faf24ea894a34887c0ca412f1643540251b9d82.zip | |
irqchip/gicv3-its: Implement two-level(indirect) device table support
Since device IDs are extremely sparse, the single, a.k.a flat table is
not sufficient for the following two reasons.
1) According to ARM-GIC spec, ITS hw can access maximum of 256(pages)*
64K(pageszie) bytes. In the best case, it supports upto DEVid=21
sparse with minimum device table entry size 8bytes.
2) The maximum memory size that is possible without memblock depends on
MAX_ORDER. 4MB on 4K page size kernel with default MAX_ORDER, so it
supports DEVid range 19bits.
The two-level device table feature brings us two advantages, the first
is a very high possibility of supporting upto 32bit sparse, and the
second one is the best utilization of memory allocation.
The feature is enabled automatically during driver probe if the memory
requirement is more than 2*ITS-pages and the hardware is capable of
two-level table walk.
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 01cf171ef97d..107eed475b94 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -204,6 +204,7 @@ #define GITS_BASER_NR_REGS 8 #define GITS_BASER_VALID (1UL << 63) +#define GITS_BASER_INDIRECT (1UL << 62) #define GITS_BASER_nCnB (0UL << 59) #define GITS_BASER_nC (1UL << 59) #define GITS_BASER_RaWt (2UL << 59) @@ -239,6 +240,8 @@ #define GITS_BASER_TYPE_RESERVED6 6 #define GITS_BASER_TYPE_RESERVED7 7 +#define GITS_LVL1_ENTRY_SIZE (8UL) + /* * ITS commands */ |