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| author | Markos Chandras <markos.chandras@imgtec.com> | 2015-07-09 10:40:49 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-08-26 15:23:17 +0200 |
| commit | 6f50c83529ac1fa3444ff4be5f5b0bf3d76db678 (patch) | |
| tree | 66c726e41d01b4808a6e94f22e94efa5b998f657 /include | |
| parent | c3f57f02e3a275d8b5c6dc692adb21525ccb392c (diff) | |
| download | linux-6f50c83529ac1fa3444ff4be5f5b0bf3d76db678.tar.gz linux-6f50c83529ac1fa3444ff4be5f5b0bf3d76db678.tar.bz2 linux-6f50c83529ac1fa3444ff4be5f5b0bf3d76db678.zip | |
IRQCHIP: irq-mips-gic: Add support for CM3 64-bit timer irqs
CM3 uses a 64-bit counter and compare registers so add support for
them in the GIC counter interrupt.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10648/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/irqchip/mips-gic.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 10e4a9073019..4e6861605050 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -41,6 +41,8 @@ /* Shared Global Counter */ #define GIC_SH_COUNTER_31_00_OFS 0x0010 +/* 64-bit counter register for CM3 */ +#define GIC_SH_COUNTER_OFS GIC_SH_COUNTER_31_00_OFS #define GIC_SH_COUNTER_63_32_OFS 0x0014 #define GIC_SH_REVISIONID_OFS 0x0020 @@ -104,6 +106,8 @@ #define GIC_VPE_WD_COUNT0_OFS 0x0094 #define GIC_VPE_WD_INITIAL0_OFS 0x0098 #define GIC_VPE_COMPARE_LO_OFS 0x00a0 +/* 64-bit Compare register on CM3 */ +#define GIC_VPE_COMPARE_OFS GIC_VPE_COMPARE_LO_OFS #define GIC_VPE_COMPARE_HI_OFS 0x00a4 #define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100 |