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author | Thor Thayer <tthayer@opensource.altera.com> | 2015-03-12 14:19:31 -0500 |
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committer | Mark Brown <broonie@kernel.org> | 2015-03-17 12:27:09 +0000 |
commit | dd11444327ce0fd549cce552b04aa441688ef2d3 (patch) | |
tree | 837d1035ba6b02b54d3691415feb81caeeccbd08 /lib/compat_audit.c | |
parent | 2306509605d3cb45b8480089af2d282600650e9e (diff) | |
download | linux-dd11444327ce0fd549cce552b04aa441688ef2d3.tar.gz linux-dd11444327ce0fd549cce552b04aa441688ef2d3.tar.bz2 linux-dd11444327ce0fd549cce552b04aa441688ef2d3.zip |
spi: dw-spi: Convert 16bit accesses to 32bit accesses
Altera's Arria10 SoC interconnect requires a 32-bit write for APB
peripherals. The current spi-dw driver uses 16-bit accesses in
some locations. This patch converts all the 16-bit reads and
writes to 32-bit reads and writes.
Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]
[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Request for test with platforms using the DesignWare SPI IP.
Tested On:
Altera CycloneV development kit
Altera Arria10 development kit
Compile tested for build errors on x86_64 (allyesconfigs)
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Reviewed-and-tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'lib/compat_audit.c')
0 files changed, 0 insertions, 0 deletions