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authorRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>2016-10-07 16:01:12 +0530
committerDarren Hart <dvhart@linux.intel.com>2016-12-13 09:28:54 -0800
commit8434709ba71473f75572245c247d3c1e92509cf3 (patch)
treec3b7e8a3f3fbecf9a9d4f028647c76b91c46d091 /mm/vmstat.c
parent5241b1938a4d33eee3d3b43f23067c8e5b96db45 (diff)
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platform/x86: intel_pmc_core: Fix PWRMBASE mask and mmio reg len
On Sunrise Point PCH, the Power Management Controller provides 4K bytes of memory space for various power management and debug registers. This fix is needed to access power management & debug registers that are mapped at a higher offset. Also, this provides a fix for correctly masking the PWRMBASE as the initial bits (0-11) are reserved. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>
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