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| author | Takashi Iwai <tiwai@suse.de> | 2017-10-17 16:38:55 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2017-10-18 12:26:44 +0200 |
| commit | 098a0a62c1554f5a3813ef1b8539563214ada8f6 (patch) | |
| tree | 9634274eb2a07dedefb0d21502d9a465b4e4ae1c /sound/hda | |
| parent | 8009d506a1dd00cf436b0c4cca0dcec130580a21 (diff) | |
| download | linux-098a0a62c1554f5a3813ef1b8539563214ada8f6.tar.gz linux-098a0a62c1554f5a3813ef1b8539563214ada8f6.tar.bz2 linux-098a0a62c1554f5a3813ef1b8539563214ada8f6.zip | |
ALSA: hda: Abort capability probe at invalid register read
The loop in snd_hdac_bus_parse_capabilities() may go to nirvana when
it hits an invalid register value read:
BUG: unable to handle kernel paging request at ffffad5dc41f3fff
IP: pci_azx_readl+0x5/0x10 [snd_hda_intel]
Call Trace:
snd_hdac_bus_parse_capabilities+0x3c/0x1f0 [snd_hda_core]
azx_probe_continue+0x7d5/0x940 [snd_hda_intel]
.....
This happened on a new Intel machine, and we need to check the value
and abort the loop accordingly.
[Note: the fixes tag below indicates only the commit where this patch
can be applied; the original problem was introduced even before that
commit]
Fixes: 6720b38420a0 ("ALSA: hda - move bus_parse_capabilities to core")
Cc: <stable@vger.kernel.org>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/hda')
| -rw-r--r-- | sound/hda/hdac_controller.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/sound/hda/hdac_controller.c b/sound/hda/hdac_controller.c index 978dc1801b3a..f6d2985b2520 100644 --- a/sound/hda/hdac_controller.c +++ b/sound/hda/hdac_controller.c @@ -284,6 +284,11 @@ int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus) dev_dbg(bus->dev, "HDA capability ID: 0x%x\n", (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF); + if (cur_cap == -1) { + dev_dbg(bus->dev, "Invalid capability reg read\n"); + break; + } + switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) { case AZX_ML_CAP_ID: dev_dbg(bus->dev, "Found ML capability\n"); |