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| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-02-02 11:24:44 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-02-02 11:24:44 -0800 |
| commit | bd1d462e13b278fc57752d0b9b15040e60e561a0 (patch) | |
| tree | e2fdf1c18a93aab02830bcb8a5db8cdddfbb63a8 /sound/soc/codecs/sgtl5000.c | |
| parent | d5c38b137ac8a6e3dbed13bc494d60df5b69dfc4 (diff) | |
| parent | 62aa2b537c6f5957afd98e29f96897419ed5ebab (diff) | |
| download | linux-bd1d462e13b278fc57752d0b9b15040e60e561a0.tar.gz linux-bd1d462e13b278fc57752d0b9b15040e60e561a0.tar.bz2 linux-bd1d462e13b278fc57752d0b9b15040e60e561a0.zip | |
Merge 3.3-rc2 into the driver-core-next branch.
This was done to resolve a merge and build problem with the
drivers/acpi/processor_driver.c file.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'sound/soc/codecs/sgtl5000.c')
| -rw-r--r-- | sound/soc/codecs/sgtl5000.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index f8863ebb4304..7f4ba819a9f6 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -987,12 +987,12 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec) /* restore regular registers */ for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { - /* this regs depends on the others */ + /* These regs should restore in particular order */ if (reg == SGTL5000_CHIP_ANA_POWER || reg == SGTL5000_CHIP_CLK_CTRL || reg == SGTL5000_CHIP_LINREG_CTRL || reg == SGTL5000_CHIP_LINE_OUT_CTRL || - reg == SGTL5000_CHIP_CLK_CTRL) + reg == SGTL5000_CHIP_REF_CTRL) continue; snd_soc_write(codec, reg, cache[reg]); @@ -1003,8 +1003,17 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec) snd_soc_write(codec, reg, cache[reg]); /* - * restore power and other regs according - * to set_power() and set_clock() + * restore these regs according to the power setting sequence in + * sgtl5000_set_power_regs() and clock setting sequence in + * sgtl5000_set_clock(). + * + * The order of restore is: + * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after + * SGTL5000_CHIP_ANA_POWER PLL bits set + * 2. SGTL5000_CHIP_LINREG_CTRL should be set before + * SGTL5000_CHIP_ANA_POWER LINREG_D restored + * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage, + * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored */ snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, cache[SGTL5000_CHIP_LINREG_CTRL]); |