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| author | Takashi Iwai <tiwai@suse.de> | 2015-11-02 09:00:37 +0100 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2015-11-02 09:00:37 +0100 |
| commit | bc88c9e923819b02f8cfaec1bb80d7e5530c0ac5 (patch) | |
| tree | 1731a322d153ee18017822a8fd66295a0ec7a4e2 /sound/soc/rockchip/rockchip_i2s.h | |
| parent | cadd16ea33a938d49aee99edd4758cc76048b399 (diff) | |
| parent | 2c8d08925272b9be383cd81f1973c6faf9fbf53a (diff) | |
| download | linux-bc88c9e923819b02f8cfaec1bb80d7e5530c0ac5.tar.gz linux-bc88c9e923819b02f8cfaec1bb80d7e5530c0ac5.tar.bz2 linux-bc88c9e923819b02f8cfaec1bb80d7e5530c0ac5.zip | |
Merge branch 'for-next' into for-linus
Diffstat (limited to 'sound/soc/rockchip/rockchip_i2s.h')
| -rw-r--r-- | sound/soc/rockchip/rockchip_i2s.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/sound/soc/rockchip/rockchip_i2s.h b/sound/soc/rockchip/rockchip_i2s.h index 93f456f518a9..dc6e2c74d088 100644 --- a/sound/soc/rockchip/rockchip_i2s.h +++ b/sound/soc/rockchip/rockchip_i2s.h @@ -49,6 +49,9 @@ * RXCR * receive operation control register */ +#define I2S_RXCR_CSR_SHIFT 15 +#define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT) +#define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) #define I2S_RXCR_HWT BIT(14) #define I2S_RXCR_SJM_SHIFT 12 #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) @@ -75,6 +78,12 @@ * CKR * clock generation register */ +#define I2S_CKR_TRCM_SHIFT 28 +#define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM_TXSHARE (1 << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM_RXSHARE (2 << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT) #define I2S_CKR_MSS_SHIFT 27 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) @@ -207,6 +216,13 @@ enum { ROCKCHIP_DIV_BCLK, }; +/* channel select */ +#define I2S_CSR_SHIFT 15 +#define I2S_CHN_2 (0 << I2S_CSR_SHIFT) +#define I2S_CHN_4 (1 << I2S_CSR_SHIFT) +#define I2S_CHN_6 (2 << I2S_CSR_SHIFT) +#define I2S_CHN_8 (3 << I2S_CSR_SHIFT) + /* I2S REGS */ #define I2S_TXCR (0x0000) #define I2S_RXCR (0x0004) |