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| author | Sugar Zhang <sugar.zhang@rock-chips.com> | 2015-10-08 20:40:09 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-10-23 01:51:00 +0900 |
| commit | b3f2dcddd576a2a6e59c407109610206c4062c8f (patch) | |
| tree | b4a15f759376b601695f0f2c30c0c9629310e861 /sound/soc/rockchip | |
| parent | d307e01e41e830adac15e91d8cea38d8a53060a5 (diff) | |
| download | linux-b3f2dcddd576a2a6e59c407109610206c4062c8f.tar.gz linux-b3f2dcddd576a2a6e59c407109610206c4062c8f.tar.bz2 linux-b3f2dcddd576a2a6e59c407109610206c4062c8f.zip | |
ASoC: rockchip: i2s: share tx/rx lrck when symmetric_rates enabled
share lrck_tx to lrck_rx when symmetric_rates enabled.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/rockchip')
| -rw-r--r-- | sound/soc/rockchip/rockchip_i2s.c | 8 | ||||
| -rw-r--r-- | sound/soc/rockchip/rockchip_i2s.h | 6 |
2 files changed, 14 insertions, 0 deletions
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index f07833b42edd..58ee64594f07 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -226,6 +226,7 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct rk_i2s_dev *i2s = to_info(dai); + struct snd_soc_pcm_runtime *rtd = substream->private_data; unsigned int val = 0; switch (params_format(params)) { @@ -278,6 +279,13 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, I2S_DMACR_RDL(16)); + val = I2S_CKR_TRCM_TXRX; + if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates) + val = I2S_CKR_TRCM_TXSHARE; + + regmap_update_bits(i2s->regmap, I2S_CKR, + I2S_CKR_TRCM_MASK, + val); return 0; } diff --git a/sound/soc/rockchip/rockchip_i2s.h b/sound/soc/rockchip/rockchip_i2s.h index a54ee35e1e5c..dc6e2c74d088 100644 --- a/sound/soc/rockchip/rockchip_i2s.h +++ b/sound/soc/rockchip/rockchip_i2s.h @@ -78,6 +78,12 @@ * CKR * clock generation register */ +#define I2S_CKR_TRCM_SHIFT 28 +#define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM_TXSHARE (1 << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM_RXSHARE (2 << I2S_CKR_TRCM_SHIFT) +#define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT) #define I2S_CKR_MSS_SHIFT 27 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) |