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| author | Oder Chiou <oder_chiou@realtek.com> | 2020-06-04 15:10:16 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-06-04 14:42:29 +0100 |
| commit | d605cbb64252071d6a74b4fbb626e1473d91838d (patch) | |
| tree | 64a8e042e2b9327223e95f80742651363d866e80 /sound | |
| parent | a6b675a89e51a1cdad0481b809b7840d3f86e4b5 (diff) | |
| download | linux-d605cbb64252071d6a74b4fbb626e1473d91838d.tar.gz linux-d605cbb64252071d6a74b4fbb626e1473d91838d.tar.bz2 linux-d605cbb64252071d6a74b4fbb626e1473d91838d.zip | |
ASoC: rl6231: Modify the target DMIC clock rate
Some DMIC components will not work correctly in the clock rate 3.072MHz.
We recommend the clock rate 1.536MHz in the gerenal case.
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Link: https://lore.kernel.org/r/20200604071016.3981-1-oder_chiou@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/codecs/rl6231.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/codecs/rl6231.c b/sound/soc/codecs/rl6231.c index 2586d1cafc0c..8c9daf32bab8 100644 --- a/sound/soc/codecs/rl6231.c +++ b/sound/soc/codecs/rl6231.c @@ -80,8 +80,8 @@ int rl6231_calc_dmic_clk(int rate) for (i = 0; i < ARRAY_SIZE(div); i++) { if ((div[i] % 3) == 0) continue; - /* find divider that gives DMIC frequency below 3.072MHz */ - if (3072000 * div[i] >= rate) + /* find divider that gives DMIC frequency below 1.536MHz */ + if (1536000 * div[i] >= rate) return i; } |