diff options
130 files changed, 2267 insertions, 3144 deletions
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README index d7b1f016bd62..f8efc21998bf 100644 --- a/Documentation/arm/sunxi/README +++ b/Documentation/arm/sunxi/README @@ -33,6 +33,11 @@ SunXi family - Next Thing Co GR8 (sun5i) + * Single ARM Cortex-A7 based SoCs + - Allwinner V3s (sun8i) + + Datasheet + http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf + * Dual ARM Cortex-A7 based SoCs - Allwinner A20 (sun7i) + User Manual @@ -71,9 +76,11 @@ SunXi family + Datasheet http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf - - Allwinner V3s (sun8i) + - Allwinner R40 (sun8i) + Datasheet - http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf + https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf + + User Manual + https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs - Allwinner A80 diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt new file mode 100644 index 000000000000..72f8d08198b6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt @@ -0,0 +1,18 @@ +Amlogic Meson8 and Meson8b power-management-unit: +------------------------------------------------- + +The pmu is used to turn off and on different power domains of the SoCs +This includes the power to the CPU cores. + +Required node properties: +- compatible value : depending on the SoC this should be one of: + "amlogic,meson8-pmu" + "amlogic,meson8b-pmu" +- reg : physical base address and the size of the registers window + +Example: + + pmu@c81000e4 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xc81000e0 0x18>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt new file mode 100644 index 000000000000..3473ddaadfac --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt @@ -0,0 +1,32 @@ +Amlogic Meson8 and Meson8b SRAM for smp bringup: +------------------------------------------------ + +Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. +Once the core gets powered up it executes the code that is residing at a +specific location. + +Therefore a reserved section sub-node has to be added to the mmio-sram +declaration. + +Required sub-node properties: +- compatible : depending on the SoC this should be one of: + "amlogic,meson8-smp-sram" + "amlogic,meson8b-smp-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram: sram@d9000000 { + compatible = "mmio-sram"; + reg = <0xd9000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd9000000 0x20000>; + + smp-sram@1ff80 { + compatible = "amlogic,meson8b-smp-sram"; + reg = <0x1ff80 0x8>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index b92f12bd5244..a0009b72e9be 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -197,6 +197,8 @@ described below. "actions,s500-smp" "allwinner,sun6i-a31" "allwinner,sun8i-a23" + "amlogic,meson8-smp" + "amlogic,meson8b-smp" "arm,realview-smp" "brcm,bcm11351-cpu-method" "brcm,bcm23550" diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt index 3a4e5901ce31..ce8dabf8c0f9 100644 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -21,6 +21,8 @@ Required properties: "ti,omap3-scm" "ti,omap4-scm-core" "ti,omap4-scm-padconf-core" + "ti,omap4-scm-wkup" + "ti,omap4-scm-padconf-wkup" "ti,omap5-scm-core" "ti,omap5-scm-padconf-core" "ti,dra7-scm-core" diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index d2c46449b4eb..e4beec3d9ad3 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,6 +14,8 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h2-plus allwinner,sun8i-h3 + allwinner-sun8i-r40 + allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 nextthing,gr8 diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt new file mode 100644 index 000000000000..fb1790e39398 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt @@ -0,0 +1,93 @@ +Texas Instruments sysc interconnect target module wrapper binding + +Texas Instruments SoCs can have a generic interconnect target module +hardware for devices connected to various interconnects such as L3 +interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc +is mostly used for interaction between module and PRCM. It participates +in the OCP Disconnect Protocol but other than that is mostly independent +of the interconnect. + +Each interconnect target module can have one or more devices connected to +it. There is a set of control registers for managing interconnect target +module clocks, idle modes and interconnect level resets for the module. + +These control registers are sprinkled into the unused register address +space of the first child device IP block managed by the interconnect +target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. + +Required standard properties: + +- compatible shall be one of the following generic types: + + "ti,sysc-omap2" + "ti,sysc-omap4" + "ti,sysc-omap4-simple" + + or one of the following derivative types for hardware + needing special workarounds: + + "ti,sysc-omap3430-sr" + "ti,sysc-omap3630-sr" + "ti,sysc-omap4-sr" + "ti,sysc-omap3-sham" + "ti,sysc-omap-aes" + "ti,sysc-mcasp" + "ti,sysc-usb-host-fs" + +- reg shall have register areas implemented for the interconnect + target module in question such as revision, sysc and syss + +- reg-names shall contain the register names implemented for the + interconnect target module in question such as + "rev, "sysc", and "syss" + +- ranges shall contain the interconnect target module IO range + available for one or more child device IP blocks managed + by the interconnect target module, the ranges may include + multiple ranges such as device L4 range for control and + parent L3 range for DMA access + +Optional properties: + +- clocks clock specifier for each name in the clock-names as + specified in the binding documentation for ti-clkctrl, + typically available for all interconnect targets on TI SoCs + based on omap4 except if it's read-only register in hwauto + mode as for example omap4 L4_CFG_CLKCTRL + +- clock-names should contain at least "fck", and optionally also "ick" + depending on the SoC and the interconnect target module + +- ti,hwmods optional TI interconnect module name to use legacy + hwmod platform data + + +Example: Single instance of MUSB controller on omap4 using interconnect ranges +using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): + + target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ + compatible = "ti,sysc-omap2"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2b000 0x1000>; + + usb_otg_hs: otg@0 { + compatible = "ti,omap4-musb"; + reg = <0x0 0x7ff>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + usb-phy = <&usb2_phy>; + ... + }; + }; + +Note that other SoCs, such as am335x can have multipe child devices. On am335x +there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA +instance as children of a single interconnet target module. diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt index 0db60470ebb6..fd823d6091b2 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it. Required properties: - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev> - is the IP revision of the specific EMIF instance. - For am437x should be ti,emif-am4372. + is the IP revision of the specific EMIF instance. For newer controllers, + compatible should be one of the following: + "ti,emif-am3352" + "ti,emif-am4372" - phy-type : <u32> indicating the DDR phy type. Following are the allowed values diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt new file mode 100644 index 000000000000..9780957c9115 --- /dev/null +++ b/Documentation/devicetree/bindings/power/ti-smartreflex.txt @@ -0,0 +1,47 @@ +Texas Instruments SmartReflex binding + +SmartReflex is used to set and adjust the SoC operating points. + + +Required properties: + +compatible: Shall be one of the following: + "ti,omap3-smartreflex-core" + "ti,omap3-smartreflex-iva" + "ti,omap4-smartreflex-core" + "ti,omap4-smartreflex-mpu" + "ti,omap4-smartreflex-iva" + +reg: Shall contain the device instance IO range + +interrupts: Shall contain the device instance interrupt + + +Optional properties: + +ti,hwmods: Shall contain the TI interconnect module name if needed + by the SoC + + +Example: + + smartreflex_iva: smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "smartreflex_iva"; + }; + + smartreflex_core: smartreflex@4a0dd000 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x4a0dd000 0x80>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "smartreflex_core"; + }; + + smartreflex_mpu: smartreflex@4a0d9000 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x4a0d9000 0x80>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "smartreflex_mpu"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index e25cc884a8f6..b549f4dd6160 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2162,7 +2162,6 @@ F: sound/soc/zte/ ARM/ZYNQ ARCHITECTURE M: Michal Simek <michal.simek@xilinx.com> -R: Sören Brinkmann <soren.brinkmann@xilinx.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) W: http://wiki.xilinx.com T: git https://github.com/Xilinx/linux-xlnx.git @@ -2937,6 +2936,7 @@ N: bcm583* N: bcm585* N: bcm586* N: bcm88312 +N: hr2 F: arch/arm64/boot/dts/broadcom/ns2* F: drivers/clk/bcm/clk-ns* F: drivers/pinctrl/bcm/pinctrl-ns* diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4f3ee0ef8fa7..51c8df561077 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -371,7 +371,7 @@ config ARCH_EBSA110 config ARCH_EP93XX bool "EP93xx-based" - select ARCH_HAS_HOLES_MEMORYMODEL + select ARCH_SPARSEMEM_ENABLE select ARM_AMBA imply ARM_PATCH_PHYS_VIRT select ARM_VIC diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 954ba8b81052..12b8c8f8ec07 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -170,6 +170,11 @@ choice depends on ARCH_BCM_5301X || ARCH_BCM_NSP select DEBUG_UART_8250 + config DEBUG_BCM_HR2 + bool "Kernel low-level debugging on Hurricane 2 UART2" + depends on ARCH_BCM_HR2 + select DEBUG_UART_8250 + config DEBUG_BCM_KONA_UART bool "Kernel low-level debugging messages via BCM KONA UART" depends on ARCH_BCM_MOBILE @@ -912,6 +917,13 @@ choice Say Y here if you want kernel low-level debugging support via SCIF2 on Renesas R-Car E2 (R8A7794). + config DEBUG_RCAR_GEN2_SCIF4 + bool "Kernel low-level debugging messages via SCIF4 on R8A7745" + depends on ARCH_R8A7745 + help + Say Y here if you want kernel low-level debugging support + via SCIF4 on Renesas RZ/G1E (R8A7745). + config DEBUG_RMOBILE_SCIFA0 bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4" depends on ARCH_R8A73A4 @@ -1452,6 +1464,7 @@ config DEBUG_LL_INCLUDE default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2 + default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4 @@ -1509,6 +1522,7 @@ config DEBUG_UART_PHYS default 0x11009000 if DEBUG_MT8135_UART3 default 0x16000000 if DEBUG_INTEGRATOR default 0x18000300 if DEBUG_BCM_5301X + default 0x18000400 if DEBUG_BCM_HR2 default 0x18010000 if DEBUG_SIRFATLAS7_UART0 default 0x18020000 if DEBUG_SIRFATLAS7_UART1 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 @@ -1571,6 +1585,7 @@ config DEBUG_UART_PHYS default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4 default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2 default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0 + default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4 default 0xe8008000 if DEBUG_R7S72100_SCIF2 default 0xf0000be0 if ARCH_EBSA110 default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE @@ -1605,6 +1620,7 @@ config DEBUG_UART_PHYS DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \ + DEBUG_RCAR_GEN2_SCIF4 || \ DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \ DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \ DEBUG_S3C64XX_UART || \ @@ -1624,6 +1640,7 @@ config DEBUG_UART_VIRT default 0xf01fb000 if DEBUG_NOMADIK_UART default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836 default 0xf1000300 if DEBUG_BCM_5301X + default 0xf1000400 if DEBUG_BCM_HR2 default 0xf1002000 if DEBUG_MT8127_UART0 default 0xf1006000 if DEBUG_MT6589_UART0 default 0xf1009000 if DEBUG_MT8135_UART3 @@ -1729,7 +1746,8 @@ config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART" depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \ - DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || DEBUG_OMAP7XXUART3 + DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \ + DEBUG_OMAP7XXUART3 default 2 config DEBUG_UART_8250_WORD diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 36ae4454554c..def8824fc71c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -149,6 +149,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000 endif textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 +textofs-$(CONFIG_ARCH_MESON) := 0x00208000 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 # Machine directory name. This list is sorted alphanumerically diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index e58fab8aec5d..1b81c4e75772 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -130,9 +130,11 @@ }; }; - pmu { + pmu@4b000000 { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; + reg = <0x4b000000 0x1000000>; + ti,hwmods = "debugss"; }; /* @@ -929,6 +931,12 @@ }; }; + emif: emif@4c000000 { + compatible = "ti,emif-am3352"; + reg = <0x4c000000 0x1000000>; + ti,hwmods = "emif"; + }; + gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 02a136a4661a..92b5cb40a9d5 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -457,6 +457,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; edma: edma@43300000 { @@ -1069,6 +1070,13 @@ max-frequency = <192000000>; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "hdq1w"; + }; + mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; @@ -1489,6 +1497,32 @@ }; }; + target-module@4a0dd000 { + compatible = "ti,sysc-omap4-sr"; + ti,hwmods = "smartreflex_core"; + reg = <0x4a0dd000 0x4>, + <0x4a0dd008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0dd000 0x001000>; + + /* SmartReflex child device marked reserved in TRM */ + }; + + target-module@4a0d9000 { + compatible = "ti,sysc-omap4-sr"; + ti,hwmods = "smartreflex_mpu"; + reg = <0x4a0d9000 0x4>, + <0x4a0d9008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0d9000 0x001000>; + + /* SmartReflex child device marked reserved in TRM */ + }; + omap_dwc3_1: omap_dwc3_1@48880000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss1"; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index bdaf30c8c405..90b5c7148feb 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -215,6 +215,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <96>; + ti,hwmods = "dma"; }; gpio1: gpio@48310000 { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 64d00f5893a6..f69de916b06a 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -51,6 +51,17 @@ }; }; + /* + * Note that 4430 needs cross trigger interface (CTI) supported + * before we can configure the interrupts. This means sampling + * events are not supported for pmu. Note that 4460 does not use + * CTI, see also 4460.dtsi. + */ + pmu { + compatible = "arm,cortex-a9-pmu"; + ti,hwmods = "debugss"; + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -163,6 +174,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2000 0x1000>; + ti,hwmods = "ctrl_module_core"; scm_conf: scm_conf@0 { compatible = "syscon"; @@ -175,9 +187,11 @@ omap4_padconf_core: scm@100000 { compatible = "ti,omap4-scm-padconf-core", "simple-bus"; + reg = <0x100000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x100000 0x1000>; + ti,hwmods = "ctrl_module_pad_core"; omap4_pmx_core: pinmux@40 { compatible = "ti,omap4-padconf", @@ -252,17 +266,33 @@ }; }; - omap4_pmx_wkup: pinmux@1e040 { - compatible = "ti,omap4-padconf", - "pinctrl-single"; - reg = <0x1e040 0x0038>; + omap4_scm_wkup: scm@c000 { + compatible = "ti,omap4-scm-wkup"; + reg = <0xc000 0x1000>; + ti,hwmods = "ctrl_module_wkup"; + }; + + omap4_padconf_wkup: padconf@1e000 { + compatible = "ti,omap4-scm-padconf-wkup", + "simple-bus"; + reg = <0x1e000 0x1000>; #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; + #size-cells = <1>; + ranges = <0 0x1e000 0x1000>; + ti,hwmods = "ctrl_module_pad_wkup"; + + omap4_pmx_wkup: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; }; }; }; @@ -282,6 +312,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; gpio1: gpio@4a310000 { @@ -351,6 +382,19 @@ #interrupt-cells = <2>; }; + target-module@48076000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "slimbus2"; + reg = <0x48076000 0x4>, + <0x48076010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48076000 0x001000>; + + /* No child device binding or driver in mainline */ + }; + elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0x2000>; @@ -411,6 +455,57 @@ clock-frequency = <48000000>; }; + target-module@4a0db000 { + compatible = "ti,sysc-sr"; + ti,hwmods = "smartreflex_iva"; + reg = <0x4a0db000 0x4>, + <0x4a0db008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0db000 0x001000>; + + smartreflex_iva: smartreflex@0 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0 0x80>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@4a0dd000 { + compatible = "ti,sysc-sr"; + ti,hwmods = "smartreflex_core"; + reg = <0x4a0dd000 0x4>, + <0x4a0dd008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0dd000 0x001000>; + + smartreflex_core: smartreflex@0 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0 0x80>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + target-module@4a0d9000 { + compatible = "ti,sysc-sr"; + ti,hwmods = "smartreflex_mpu"; + reg = <0x4a0d9000 0x4>, + <0x4a0d9008 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a0d9000 0x001000>; + + smartreflex_mpu: smartreflex@0 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0 0x80>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + hwspinlock: spinlock@4a0f6000 { compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; @@ -489,6 +584,13 @@ dma-names = "tx0", "rx0", "tx1", "rx1"; }; + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "hdq1w"; + }; + mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; @@ -565,6 +667,40 @@ dma-names = "tx", "rx"; }; + hsi: hsi@4a058000 { + compatible = "ti,omap4-hsi"; + reg = <0x4a058000 0x4000>, + <0x4a05c000 0x1000>; + reg-names = "sys", "gdd"; + ti,hwmods = "hsi"; + + clocks = <&hsi_fck>; + clock-names = "hsi_fck"; + + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a058000 0x4000>; + + hsi_port1: hsi-port@2000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x2000 0x800>, + <0x2800 0x800>; + reg-names = "tx", "rx"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + }; + + hsi_port2: hsi-port@3000 { + compatible = "ti,omap4-hsi-port"; + reg = <0x3000 0x800>, + <0x3800 0x800>; + reg-names = "tx", "rx"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; @@ -573,6 +709,19 @@ #iommu-cells = <0>; }; + target-module@52000000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "iss"; + reg = <0x52000000 0x4>, + <0x52000010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x52000000 0x1000000>; + + /* No child device binding, driver in staging */ + }; + mmu_ipu: mmu@55082000 { compatible = "ti,omap4-iommu"; reg = <0x55082000 0x100>; @@ -589,6 +738,14 @@ ti,hwmods = "wd_timer2"; }; + wdt3: wdt@40130000 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x40130000 0x80>, /* MPU private access */ + <0x49030000 0x80>; /* L3 Interconnect */ + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "wd_timer3"; + }; + mcpdm: mcpdm@40132000 { compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ @@ -659,6 +816,56 @@ status = "disabled"; }; + target-module@40128000 { + compatible = "ti,sysc-mcasp"; + ti,hwmods = "mcasp"; + reg = <0x40128004 0x4>; + reg-names = "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40128000 0x1000>, /* MPU */ + <0x49028000 0x49028000 0x1000>; /* L3 */ + + /* + * Child device unsupported by davinci-mcasp. At least + * TX path is disabled for omap4, and only DIT mode + * works with no I2S. See also old Android kernel + * omap-mcasp driver for more information. + */ + }; + + target-module@4012c000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "slimbus1"; + reg = <0x4012c000 0x4>, + <0x4012c010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */ + <0x4902c000 0x4902c000 0x1000>; /* L3 */ + + /* No child device binding or driver in mainline */ + }; + + target-module@401f1000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "aess"; + reg = <0x401f1000 0x4>, + <0x401f1010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */ + <0x490f1000 0x490f1000 0x1000>; /* L3 */ + + /* + * No child device binding or driver in mainline. + * See Android tree and related upstreaming efforts + * for the old driver. + */ + }; + mcbsp4: mcbsp@48096000 { compatible = "ti,omap4-mcbsp"; reg = <0x48096000 0xff>; /* L4 Interconnect */ @@ -747,6 +954,19 @@ }; }; + target-module@4a10a000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "fdif"; + reg = <0x4a10a000 0x4>, + <0x4a10a010 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a10a000 0x1000>; + + /* No child device binding or driver in mainline */ + }; + timer1: timer@4a318000 { compatible = "ti,omap3430-timer"; reg = <0x4a318000 0x80>; @@ -962,6 +1182,22 @@ status = "disabled"; }; + target-module@56000000 { + compatible = "ti,sysc-omap4"; + ti,hwmods = "gpu"; + reg = <0x5601fc00 0x4>, + <0x5601fc10 0x4>; + reg-names = "rev", "sysc"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + dss: dss@58000000 { compatible = "ti,omap4-dss"; reg = <0x58000000 0x80>; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index eaff2a5751dd..b86ac7df620d 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -295,6 +295,7 @@ #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; + ti,hwmods = "dma_system"; }; gpio1: gpio@4ae10000 { diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 27d9720f7207..bd0cf22f9ceb 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -34,6 +34,7 @@ CONFIG_DAVINCI_MUX_WARNINGS=y CONFIG_DAVINCI_RESET_CLOCKS=y CONFIG_PREEMPT=y CONFIG_AEABI=y +CONFIG_CMA=y CONFIG_SECCOMP=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -56,9 +57,11 @@ CONFIG_NETFILTER=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER is not set +CONFIG_DMA_CMA=y CONFIG_DA8XX_MSTPRI=y CONFIG_MTD=m CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=m CONFIG_MTD_BLOCK=m CONFIG_MTD_CFI=m CONFIG_MTD_CFI_INTELEXT=m @@ -195,7 +198,6 @@ CONFIG_USB_G_SERIAL=m CONFIG_USB_G_PRINTER=m CONFIG_USB_CDC_COMPOSITE=m CONFIG_MMC=y -# CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_DAVINCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 8c2a2619971b..f1d7834990ec 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -244,7 +244,7 @@ CONFIG_USB_STORAGE_ONETOUCH=m CONFIG_USB_STORAGE_KARMA=m CONFIG_USB_STORAGE_CYPRESS_ATACB=m CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=m +CONFIG_USB_UAS=y CONFIG_USB_DWC3=y CONFIG_USB_DWC2=y CONFIG_USB_HSIC_USB3503=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 32acac9ab81a..0d4494922561 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -250,6 +250,7 @@ CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_IMX=y CONFIG_DRM_IMX_PARALLEL_DISPLAY=y CONFIG_DRM_IMX_TVE=y @@ -365,6 +366,7 @@ CONFIG_PWM=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX=y CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_MUX_MMIO=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index f907869e0ddc..f710c192b33a 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig @@ -189,6 +189,8 @@ CONFIG_KEYSTONE_NAVIGATOR_DMA=y CONFIG_TI_SCI_PM_DOMAINS=y CONFIG_MEMORY=y CONFIG_TI_AEMIF=y +CONFIG_PWM=y +CONFIG_PWM_TIECAP=m CONFIG_KEYSTONE_IRQ=y CONFIG_RESET_TI_SCI=m CONFIG_RESET_TI_SYSCON=m diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index e15fa5f168bb..0b54b4024e51 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -108,11 +108,11 @@ CONFIG_GPIO_MAX7300=y CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCF857X=y -CONFIG_GPIO_SX150X=y CONFIG_GPIO_74X164=y CONFIG_GPIO_MAX7301=y CONFIG_GPIO_MC33880=y CONFIG_PINCTRL_MCP23S08=y +CONFIG_PINCTRL_SX150X=y CONFIG_SENSORS_DS620=y CONFIG_SENSORS_MAX6639=y CONFIG_WATCHDOG=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 0cacdbf84a71..61509c4b769f 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -31,6 +31,7 @@ CONFIG_SOC_SAMA5D3=y CONFIG_SOC_SAMA5D4=y CONFIG_ARCH_BCM=y CONFIG_ARCH_BCM_CYGNUS=y +CONFIG_ARCH_BCM_HR2=y CONFIG_ARCH_BCM_NSP=y CONFIG_ARCH_BCM_21664=y CONFIG_ARCH_BCM_281XX=y @@ -420,6 +421,7 @@ CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_EM=y CONFIG_GPIO_RCAR=y +CONFIG_GPIO_UNIPHIER=y CONFIG_GPIO_XILINX=y CONFIG_GPIO_ZYNQ=y CONFIG_GPIO_PCA953X=y @@ -689,10 +691,12 @@ CONFIG_USB_OHCI_EXYNOS=m CONFIG_USB_R8A66597_HCD=m CONFIG_USB_RENESAS_USBHS=m CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=m CONFIG_USB_MUSB_HDRC=m CONFIG_USB_MUSB_SUNXI=m CONFIG_USB_DWC3=y CONFIG_USB_DWC2=y +CONFIG_USB_HSIC_USB3503=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y @@ -727,6 +731,7 @@ CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP_HS=y CONFIG_MMC_ATMELMCI=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_MESON_MX_SDIO=y CONFIG_MMC_MVSDIO=y CONFIG_MMC_SDHI=y CONFIG_MMC_DW=y @@ -767,6 +772,7 @@ CONFIG_RTC_DRV_MAX8997=m CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_ST_LPC=y CONFIG_RTC_DRV_TWL4030=y @@ -849,6 +855,7 @@ CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_REMOTEPROC=m CONFIG_ST_REMOTEPROC=m +CONFIG_RPMSG_VIRTIO=m CONFIG_PM_DEVFREQ=y CONFIG_ARM_TEGRA_DEVFREQ=m CONFIG_MEMORY=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 879159e4ab58..c784d04e2ab7 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -1,5 +1,4 @@ CONFIG_SYSVIPC=y -CONFIG_FHANDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y @@ -28,9 +27,7 @@ CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCIE_QCOM=y CONFIG_SMP=y -CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_PREEMPT=y -CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_CLEANCACHE=y CONFIG_ARM_APPENDED_DTB=y @@ -57,14 +54,13 @@ CONFIG_CFG80211=y CONFIG_RFKILL=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_QCOM_EBI2=y CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_M25P80=y CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y +CONFIG_QCOM_COINCELL=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y CONFIG_CHR_DEV_SCH=y @@ -87,6 +83,7 @@ CONFIG_SLIP_MODE_SLIP6=y CONFIG_USB_USBNET=y # CONFIG_USB_NET_AX8817X is not set # CONFIG_USB_NET_ZAURUS is not set +CONFIG_BRCMFMAC=m CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y @@ -98,12 +95,15 @@ CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8XXX_VIBRATOR=y CONFIG_INPUT_PMIC8XXX_PWRKEY=y CONFIG_INPUT_UINPUT=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y CONFIG_SERIO_LIBPS2=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_QUP=y @@ -121,11 +121,10 @@ CONFIG_PINCTRL_MSM8X74=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y CONFIG_GPIOLIB=y -CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y -CONFIG_CHARGER_QCOM_SMBB=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_MSM=y +CONFIG_CHARGER_QCOM_SMBB=y CONFIG_THERMAL=y CONFIG_QCOM_TSENS=y CONFIG_MFD_PM8XXX=y @@ -135,8 +134,14 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_QCOM_RPM=y CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_MEDIA_SUPPORT=y CONFIG_FB=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_LP855X=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_DYNAMIC_MINORS=y @@ -155,15 +160,21 @@ CONFIG_USB_ACM=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_ULPI=y CONFIG_USB_SERIAL=y +CONFIG_USB_HSIC_USB4604=y CONFIG_USB_MSM_OTG=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ULPI_BUS=y CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_QCOM_DML=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y @@ -173,7 +184,6 @@ CONFIG_LEDS_GPIO=y CONFIG_LEDS_PM8058=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RPMSG_QCOM_SMD=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PM8XXX=y CONFIG_DMADEVICES=y @@ -187,15 +197,17 @@ CONFIG_IPQ_GCC_4019=y CONFIG_IPQ_LCC_806X=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_LCC_8960=y -CONFIG_MDM_GCC_9615=y CONFIG_MDM_LCC_9615=y CONFIG_MSM_MMCC_8960=y CONFIG_MSM_MMCC_8974=y +CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_REMOTEPROC=y CONFIG_QCOM_ADSP_PIL=y CONFIG_QCOM_Q6V5_PIL=y CONFIG_QCOM_WCNSS_PIL=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_QCOM_SMD=y CONFIG_QCOM_GSBI=y CONFIG_QCOM_PM=y CONFIG_QCOM_SMEM=y @@ -203,6 +215,7 @@ CONFIG_QCOM_SMD_RPM=y CONFIG_QCOM_SMP2P=y CONFIG_QCOM_SMSM=y CONFIG_QCOM_WCNSS_CTRL=y +CONFIG_EXTCON_QCOM_SPMI_MISC=y CONFIG_IIO=y CONFIG_IIO_BUFFER_CB=y CONFIG_IIO_SW_TRIGGER=y @@ -211,9 +224,11 @@ CONFIG_MPU3050_I2C=y CONFIG_AK8975=y CONFIG_IIO_HRTIMER_TRIGGER=y CONFIG_BMP280=y +CONFIG_PWM=y CONFIG_PHY_QCOM_APQ8064_SATA=y CONFIG_PHY_QCOM_IPQ806X_SATA=y -CONFIG_NVMEM=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_PHY_QCOM_USB_HSIC=y CONFIG_QCOM_QFPROM=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y @@ -234,7 +249,4 @@ CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y -CONFIG_LOCKUP_DETECTOR=y -# CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set -CONFIG_TIMER_STATS=y diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 90e5c46913a5..bb358ffde7d2 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -18,7 +18,6 @@ CONFIG_EMBEDDED=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set # CONFIG_MMU is not set -CONFIG_ARM_SINGLE_ARMV7M=y CONFIG_ARCH_STM32=y CONFIG_CPU_V7M_NUM_IRQ=240 CONFIG_SET_MEM_PARAM=y @@ -44,18 +43,18 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_UNIX98_PTYS is not set # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_DEVKMEM is not set CONFIG_SERIAL_STM32=y CONFIG_SERIAL_STM32_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_STM32F4=y +CONFIG_I2C_STM32F7=y +CONFIG_GPIO_STMPE=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y -CONFIG_REGULATOR=y -CONFIG_GPIO_STMPE=y CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_USB_SUPPORT is not set CONFIG_NEW_LEDS=y @@ -67,6 +66,8 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_STM32=y CONFIG_DMADEVICES=y CONFIG_STM32_DMA=y +CONFIG_STM32_DMAMUX=y +CONFIG_STM32_MDMA=y CONFIG_IIO=y CONFIG_STM32_ADC_CORE=y CONFIG_STM32_ADC=y @@ -81,8 +82,6 @@ CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_FTRACE is not set CONFIG_CRYPTO=y -CONFIG_CRYPTO_DEV_STM32=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 800f5228939f..b818e5d0cd78 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -28,6 +28,8 @@ static inline unsigned long scu_a9_get_base(void) #ifdef CONFIG_HAVE_ARM_SCU unsigned int scu_get_core_count(void __iomem *); int scu_power_mode(void __iomem *, unsigned int); +int scu_cpu_power_enable(void __iomem *, unsigned int); +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu); #else static inline unsigned int scu_get_core_count(void __iomem *scu_base) { @@ -37,6 +39,16 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode) { return -EINVAL; } +static inline int scu_cpu_power_enable(void __iomem *scu_base, + unsigned int mode) +{ + return -EINVAL; +} +static inline int scu_get_cpu_power_mode(void __iomem *scu_base, + unsigned int logical_cpu) +{ + return -EINVAL; +} #endif #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU) diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index 52aaed2b936f..c826f15d2f80 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -58,6 +58,7 @@ /* Check SUN_TOP_CTRL base */ ldr \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA ldr \rv, [\rp, #0] @ get register contents +ARM_BE8( rev \rv, \rv ) and \rv, \rv, #0xffffff00 @ strip revision bits [7:0] /* Chip specific detection starts here */ @@ -98,11 +99,13 @@ .endm .macro store, rd, rx:vararg +ARM_BE8( rev \rd, \rd ) str \rd, \rx .endm .macro load, rd, rx:vararg ldr \rd, \rx +ARM_BE8( rev \rd, \rd ) .endm .macro senduart,rd,rx diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h index 3287d790c83c..e61c65b4018d 100644 --- a/arch/arm/include/uapi/asm/ptrace.h +++ b/arch/arm/include/uapi/asm/ptrace.h @@ -58,6 +58,7 @@ #endif #define FIQ_MODE 0x00000011 #define IRQ_MODE 0x00000012 +#define MON_MODE 0x00000016 #define ABT_MODE 0x00000017 #define HYP_MODE 0x0000001a #define UND_MODE 0x0000001b diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 72f9241ad5db..c6b33074c393 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -21,6 +21,7 @@ #define SCU_STANDBY_ENABLE (1 << 5) #define SCU_CONFIG 0x04 #define SCU_CPU_STATUS 0x08 +#define SCU_CPU_STATUS_MASK GENMASK(1, 0) #define SCU_INVALIDATE 0x0c #define SCU_FPGA_REVISION 0x10 @@ -72,6 +73,24 @@ void scu_enable(void __iomem *scu_base) } #endif +static int scu_set_power_mode_internal(void __iomem *scu_base, + unsigned int logical_cpu, + unsigned int mode) +{ + unsigned int val; + int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0); + + if (mode > 3 || mode == 1 || cpu > 3) + return -EINVAL; + + val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu); + val &= ~SCU_CPU_STATUS_MASK; + val |= mode; + writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu); + + return 0; +} + /* * Set the executing CPUs power mode as defined. This will be in * preparation for it executing a WFI instruction. @@ -82,15 +101,27 @@ void scu_enable(void __iomem *scu_base) */ int scu_power_mode(void __iomem *scu_base, unsigned int mode) { + return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode); +} + +/* + * Set the given (logical) CPU's power mode to SCU_PM_NORMAL. + */ +int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu) +{ + return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL); +} + +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu) +{ unsigned int val; - int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); + int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0); - if (mode > 3 || mode == 1 || cpu > 3) + if (cpu > 3) return -EINVAL; - val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; - val |= mode; - writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu); + val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu); + val &= SCU_CPU_STATUS_MASK; - return 0; + return val; } diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile index c0f116241da7..13831037d8cd 100644 --- a/arch/arm/mach-actions/Makefile +++ b/arch/arm/mach-actions/Makefile @@ -1,3 +1 @@ -obj-${CONFIG_SMP} += platsmp.o headsmp.o - -AFLAGS_headsmp.o := -Wa,-march=armv7-a +obj-${CONFIG_SMP} += platsmp.o diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S deleted file mode 100644 index 65f53bdb69e7..000000000000 --- a/arch/arm/mach-actions/headsmp.S +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2012 Actions Semi Inc. - * Author: Actions Semi, Inc. - * - * Copyright (c) 2017 Andreas Färber - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/linkage.h> -#include <linux/init.h> - -ENTRY(owl_v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(owl_v7_invalidate_l1) - -ENTRY(owl_secondary_startup) - bl owl_v7_invalidate_l1 - b secondary_startup diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c index 12a9e331b432..3efaa10efc43 100644 --- a/arch/arm/mach-actions/platsmp.c +++ b/arch/arm/mach-actions/platsmp.c @@ -71,7 +71,7 @@ static int s500_wakeup_secondary(unsigned int cpu) /* wait for CPUx to run to WFE instruction */ udelay(200); - writel(virt_to_phys(owl_secondary_startup), + writel(__pa_symbol(secondary_startup), timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); writel(OWL_CPUx_FLAG_BOOT, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 53efe8b22126..c2f3b0d216a4 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -37,6 +37,15 @@ config ARCH_BCM_CYGNUS BCM11300, BCM11320, BCM11350, BCM11360, BCM58300, BCM58302, BCM58303, BCM58305. +config ARCH_BCM_HR2 + bool "Broadcom Hurricane 2 SoC support" + depends on ARCH_MULTI_V7 + select ARCH_BCM_IPROC + help + Enable support for the Hurricane 2 family, + which includes the following variants: + BCM53342, BCM53343, BCM53344, BCM53346. + config ARCH_BCM_NSP bool "Broadcom Northstar Plus SoC Support" depends on ARCH_MULTI_V7 diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 980f5850097c..8fd23b263c60 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -13,6 +13,9 @@ # Cygnus obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o +# Hurricane 2 +obj-$(CONFIG_ARCH_BCM_HR2) += bcm_hr2.o + # Northstar Plus obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o @@ -43,6 +46,11 @@ endif # BCM2835 obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o +ifeq ($(CONFIG_ARCH_BCM2835),y) +ifeq ($(CONFIG_ARM),y) +obj-$(CONFIG_SMP) += platsmp.o +endif +endif # BCM5301X obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o diff --git a/arch/arm/mach-bcm/bcm_hr2.c b/arch/arm/mach-bcm/bcm_hr2.c new file mode 100644 index 000000000000..c104f28995d7 --- /dev/null +++ b/arch/arm/mach-bcm/bcm_hr2.c @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2017 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <asm/mach/arch.h> + +static const char * const bcm_hr2_dt_compat[] __initconst = { + "brcm,hr2", + NULL, +}; + +DT_MACHINE_START(BCM_HR2_DT, "Broadcom Hurricane 2 SoC") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, + .dt_compat = bcm_hr2_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index 0c1edfc98696..8cff865ace04 100644 --- a/arch/arm/mach-bcm/board_bcm2835.c +++ b/arch/arm/mach-bcm/board_bcm2835.c @@ -15,15 +15,11 @@ #include <linux/init.h> #include <linux/irqchip.h> #include <linux/of_address.h> -#include <linux/clk/bcm2835.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -static void __init bcm2835_init(void) -{ - bcm2835_init_clocks(); -} +#include "platsmp.h" static const char * const bcm2835_compat[] = { #ifdef CONFIG_ARCH_MULTI_V6 @@ -31,11 +27,12 @@ static const char * const bcm2835_compat[] = { #endif #ifdef CONFIG_ARCH_MULTI_V7 "brcm,bcm2836", + "brcm,bcm2837", #endif NULL }; DT_MACHINE_START(BCM2835, "BCM2835") - .init_machine = bcm2835_init, - .dt_compat = bcm2835_compat + .dt_compat = bcm2835_compat, + .smp = smp_ops(bcm2836_smp_ops), MACHINE_END diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c index 9e3f275934eb..7d954830eb57 100644 --- a/arch/arm/mach-bcm/platsmp.c +++ b/arch/arm/mach-bcm/platsmp.c @@ -17,6 +17,7 @@ #include <linux/errno.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/irqchip/irq-bcm2836.h> #include <linux/jiffies.h> #include <linux/of.h> #include <linux/of_address.h> @@ -287,6 +288,38 @@ out: return ret; } +static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + void __iomem *intc_base; + struct device_node *dn; + char *name; + + name = "brcm,bcm2836-l1-intc"; + dn = of_find_compatible_node(NULL, NULL, name); + if (!dn) { + pr_err("unable to find intc node\n"); + return -ENODEV; + } + + intc_base = of_iomap(dn, 0); + of_node_put(dn); + + if (!intc_base) { + pr_err("unable to remap intc base register\n"); + return -ENOMEM; + } + + writel(virt_to_phys(secondary_startup), + intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu); + + dsb(sy); + sev(); + + iounmap(intc_base); + + return 0; +} + static const struct smp_operations kona_smp_ops __initconst = { .smp_prepare_cpus = bcm_smp_prepare_cpus, .smp_boot_secondary = kona_boot_secondary, @@ -305,3 +338,8 @@ static const struct smp_operations nsp_smp_ops __initconst = { .smp_boot_secondary = nsp_boot_secondary, }; CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); + +const struct smp_operations bcm2836_smp_ops __initconst = { + .smp_boot_secondary = bcm2836_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops); diff --git a/arch/arm/mach-bcm/platsmp.h b/arch/arm/mach-bcm/platsmp.h new file mode 100644 index 000000000000..b8b8b3fa350d --- /dev/null +++ b/arch/arm/mach-bcm/platsmp.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + */ + +extern const struct smp_operations bcm2836_smp_ops; diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index e61f3dee24c2..41aa57581356 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -42,60 +42,12 @@ static struct ep93xxfb_mach_info __initdata simone_fb_info = { .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, }; -/* - * GPIO lines used for MMC card detection. - */ -#define MMC_CARD_DETECT_GPIO EP93XX_GPIO_LINE_EGPIO0 - -/* - * MMC card detection GPIO setup. - */ - -static int simone_mmc_spi_init(struct device *dev, - irqreturn_t (*irq_handler)(int, void *), void *mmc) -{ - unsigned int gpio = MMC_CARD_DETECT_GPIO; - int irq, err; - - err = gpio_request(gpio, dev_name(dev)); - if (err) - return err; - - err = gpio_direction_input(gpio); - if (err) - goto fail; - - irq = gpio_to_irq(gpio); - if (irq < 0) - goto fail; - - err = request_irq(irq, irq_handler, IRQF_TRIGGER_FALLING, - "MMC card detect", mmc); - if (err) - goto fail; - - printk(KERN_INFO "%s: using irq %d for MMC card detection\n", - dev_name(dev), irq); - - return 0; -fail: - gpio_free(gpio); - return err; -} - -static void simone_mmc_spi_exit(struct device *dev, void *mmc) -{ - unsigned int gpio = MMC_CARD_DETECT_GPIO; - - free_irq(gpio_to_irq(gpio), mmc); - gpio_free(gpio); -} - static struct mmc_spi_platform_data simone_mmc_spi_data = { - .init = simone_mmc_spi_init, - .exit = simone_mmc_spi_exit, .detect_delay = 500, .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .flags = MMC_SPI_USE_CD_GPIO, + .cd_gpio = EP93XX_GPIO_LINE_EGPIO0, + .cd_debounce = 1, }; static struct spi_board_info simone_spi_devices[] __initdata = { diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index 8745162ec05d..f386ebae0163 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -18,7 +18,10 @@ #include <linux/io.h> #include <linux/mtd/rawnand.h> #include <linux/mtd/partitions.h> +#include <linux/spi/spi.h> +#include <linux/platform_data/spi-ep93xx.h> +#include <mach/gpio-ep93xx.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -186,24 +189,22 @@ static struct platform_device ts72xx_rtc_device = { .num_resources = ARRAY_SIZE(ts72xx_rtc_resources), }; +/************************************************************************* + * Watchdog (in CPLD) + *************************************************************************/ +#define TS72XX_WDT_CONTROL_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03800000) +#define TS72XX_WDT_FEED_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03c00000) + static struct resource ts72xx_wdt_resources[] = { - { - .start = TS72XX_WDT_CONTROL_PHYS_BASE, - .end = TS72XX_WDT_CONTROL_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = TS72XX_WDT_FEED_PHYS_BASE, - .end = TS72XX_WDT_FEED_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01), + DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01), }; static struct platform_device ts72xx_wdt_device = { .name = "ts72xx-wdt", .id = -1, - .num_resources = ARRAY_SIZE(ts72xx_wdt_resources), .resource = ts72xx_wdt_resources, + .num_resources = ARRAY_SIZE(ts72xx_wdt_resources), }; static struct ep93xx_eth_data __initdata ts72xx_eth_data = { @@ -232,6 +233,27 @@ static struct platform_device ts73xx_fpga_device = { #endif +/************************************************************************* + * SPI Bus + *************************************************************************/ +static struct spi_board_info ts72xx_spi_devices[] __initdata = { + { + .modalias = "tmp122", + .max_speed_hz = 2 * 1000 * 1000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static int ts72xx_spi_chipselects[] __initdata = { + EP93XX_GPIO_LINE_F(2), /* DIO_17 */ +}; + +static struct ep93xx_spi_info ts72xx_spi_info __initdata = { + .chipselect = ts72xx_spi_chipselects, + .num_chipselect = ARRAY_SIZE(ts72xx_spi_chipselects), +}; + static void __init ts72xx_init_machine(void) { ep93xx_init_devices(); @@ -244,6 +266,8 @@ static void __init ts72xx_init_machine(void) if (board_is_ts7300()) platform_device_register(&ts73xx_fpga_device); #endif + ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices, + ARRAY_SIZE(ts72xx_spi_devices)); } MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") diff --git a/arch/arm/mach-ep93xx/ts72xx.h b/arch/arm/mach-ep93xx/ts72xx.h index b89850f1a965..8a3206a54b39 100644 --- a/arch/arm/mach-ep93xx/ts72xx.h +++ b/arch/arm/mach-ep93xx/ts72xx.h @@ -39,9 +39,6 @@ #define TS72XX_OPTIONS2_TS9420 0x04 #define TS72XX_OPTIONS2_TS9420_BOOT 0x02 -#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000 -#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000 - #ifndef __ASSEMBLY__ static inline int ts72xx_model(void) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 0a99140b6ba2..44fa753bd79c 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -85,11 +85,6 @@ config CPU_EXYNOS4210 default y depends on ARCH_EXYNOS4 -config SOC_EXYNOS4212 - bool "SAMSUNG EXYNOS4212" - default y - depends on ARCH_EXYNOS4 - config SOC_EXYNOS4412 bool "SAMSUNG EXYNOS4412" default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 9424a8a9f308..3f715524c9d6 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -18,7 +18,6 @@ #define EXYNOS3_SOC_MASK 0xFFFFF000 #define EXYNOS4210_CPU_ID 0x43210000 -#define EXYNOS4212_CPU_ID 0x43220000 #define EXYNOS4412_CPU_ID 0xE4412200 #define EXYNOS4_CPU_MASK 0xFFFE0000 @@ -39,7 +38,6 @@ static inline int is_samsung_##name(void) \ IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK) IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) -IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) @@ -59,12 +57,6 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos4210() 0 #endif -#if defined(CONFIG_SOC_EXYNOS4212) -# define soc_is_exynos4212() is_samsung_exynos4212() -#else -# define soc_is_exynos4212() 0 -#endif - #if defined(CONFIG_SOC_EXYNOS4412) # define soc_is_exynos4412() is_samsung_exynos4412() #else @@ -105,8 +97,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5800() 0 #endif -#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \ - soc_is_exynos4412()) +#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4412()) #define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ soc_is_exynos5420() || soc_is_exynos5800()) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index c404c15ad07f..9a9caac1125a 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -195,7 +195,6 @@ static void __init exynos_dt_machine_init(void) exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data; #endif if (of_machine_is_compatible("samsung,exynos4210") || - of_machine_is_compatible("samsung,exynos4212") || (of_machine_is_compatible("samsung,exynos4412") && of_machine_is_compatible("samsung,trats2")) || of_machine_is_compatible("samsung,exynos3250") || @@ -208,7 +207,6 @@ static char const *const exynos_dt_compat[] __initconst = { "samsung,exynos3250", "samsung,exynos4", "samsung,exynos4210", - "samsung,exynos4212", "samsung,exynos4412", "samsung,exynos5", "samsung,exynos5250", diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index e81a78b125d9..2a51e4603a6f 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -70,12 +70,7 @@ static int exynos_cpu_boot(int cpu) /* * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. - * But, Exynos4212 has only one secondary CPU so second parameter - * isn't used for informing secure firmware about CPU id. */ - if (soc_is_exynos4212()) - cpu = 0; - exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); return 0; } diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 1a7e5b5d08d8..c9740d96db9e 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -167,8 +167,7 @@ void exynos_enter_aftr(void) exynos_pm_central_suspend(); - if (of_machine_is_compatible("samsung,exynos4212") || - of_machine_is_compatible("samsung,exynos4412")) { + if (of_machine_is_compatible("samsung,exynos4412")) { /* Setting SEQ_OPTION register */ pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, S5P_CENTRAL_SEQ_OPTION); diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index b529ba04ed16..370d37ded7e7 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -225,7 +225,6 @@ static int __init exynos_pmu_irq_init(struct device_node *node, EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); -EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); @@ -617,9 +616,6 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { .compatible = "samsung,exynos4210-pmu", .data = &exynos4_pm_data, }, { - .compatible = "samsung,exynos4212-pmu", - .data = &exynos4_pm_data, - }, { .compatible = "samsung,exynos4412-pmu", .data = &exynos4_pm_data, }, { diff --git a/arch/arm/mach-imx/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c index cda330c93d61..0015abe9cb2b 100644 --- a/arch/arm/mach-imx/3ds_debugboard.c +++ b/arch/arm/mach-imx/3ds_debugboard.c @@ -20,7 +20,7 @@ #include <linux/smsc911x.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> - +#include "3ds_debugboard.h" #include "hardware.h" /* LAN9217 ethernet base address */ diff --git a/arch/arm/mach-imx/cpuidle-imx5.c b/arch/arm/mach-imx/cpuidle-imx5.c index 3feca526d16b..db0127606aed 100644 --- a/arch/arm/mach-imx/cpuidle-imx5.c +++ b/arch/arm/mach-imx/cpuidle-imx5.c @@ -9,6 +9,7 @@ #include <linux/cpuidle.h> #include <linux/module.h> #include <asm/system_misc.h> +#include "cpuidle.h" static int imx5_cpuidle_enter(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index b5f89fdbbb4b..7d80a0ae723c 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -289,10 +289,13 @@ static void __init imx6q_init_machine(void) static void __init imx6q_init_late(void) { /* - * WAIT mode is broken on TO 1.0 and 1.1, so there is no point - * to run cpuidle on them. + * WAIT mode is broken on imx6 Dual/Quad revision 1.0 and 1.1 so + * there is no point to run cpuidle on them. + * + * It does work on imx6 Solo/DualLite starting from 1.1 */ - if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) + if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) || + (cpu_is_imx6dl() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0)) imx6q_cpuidle_init(); if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index f033a57d5694..a3250bc7f114 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c @@ -245,7 +245,7 @@ static struct map_desc mx31lite_io_desc[] __initdata = { /* * Set up static virtual mappings. */ -void __init mx31lite_map_io(void) +static void __init mx31lite_map_io(void) { mx31_map_io(); iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c index 1e91a0918e83..3c224f41e68e 100644 --- a/arch/arm/mach-imx/mx31moboard-devboard.c +++ b/arch/arm/mach-imx/mx31moboard-devboard.c @@ -22,6 +22,7 @@ #include <linux/usb/otg.h> +#include "board-mx31moboard.h" #include "common.h" #include "devices-imx31.h" #include "ehci.h" diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c index 922d49175cb4..9a5a869be1ae 100644 --- a/arch/arm/mach-imx/mx31moboard-marxbot.c +++ b/arch/arm/mach-imx/mx31moboard-marxbot.c @@ -24,6 +24,7 @@ #include <linux/usb/otg.h> +#include "board-mx31moboard.h" #include "common.h" #include "devices-imx31.h" #include "ehci.h" diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index a5a4470db482..71b97ffe8d32 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -8,6 +8,4 @@ obj-y := core.o lm.o obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o - -obj-$(CONFIG_PCI) += pci_v3.o obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index a1af634f8709..8efe484fac13 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -36,7 +36,6 @@ #include "hardware.h" #include "cm.h" #include "common.h" -#include "pci_v3.h" #include "lm.h" /* Regmap to the AP system controller */ @@ -74,7 +73,6 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = { static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); - pci_v3_early_init(); } #ifdef CONFIG_PM diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c deleted file mode 100644 index 2565f0e7b5cf..000000000000 --- a/arch/arm/mach-integrator/pci_v3.c +++ /dev/null @@ -1,900 +0,0 @@ -/* - * linux/arch/arm/mach-integrator/pci_v3.c - * - * PCI functions for V3 host PCI bridge - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000-2001 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/of_pci.h> -#include <video/vga.h> - -#include <asm/mach/map.h> -#include <asm/signal.h> -#include <asm/mach/pci.h> -#include <asm/irq_regs.h> - -#include "pci_v3.h" -#include "hardware.h" - -/* - * Where in the memory map does PCI live? - * - * This represents a fairly liberal usage of address space. Even though - * the V3 only has two windows (therefore we need to map stuff on the fly), - * we maintain the same addresses, even if they're not mapped. - */ -#define PHYS_PCI_MEM_BASE 0x40000000 /* 256M */ -#define PHYS_PCI_PRE_BASE 0x50000000 /* 256M */ -#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */ -#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */ -#define PHYS_PCI_V3_BASE 0x62000000 /* 64K */ - -#define PCI_MEMORY_VADDR IOMEM(0xe8000000) -#define PCI_CONFIG_VADDR IOMEM(0xec000000) - -/* - * V3 Local Bus to PCI Bridge definitions - * - * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 - * All V3 register names are prefaced by V3_ to avoid clashing with any other - * PCI definitions. Their names match the user's manual. - * - * I'm assuming that I20 is disabled. - * - */ -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CFG 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* PCI COMMAND REGISTER bits - */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -/* SYSTEM REGISTER bits - */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits - */ -#define V3_PCI_CFG_M_I2O_EN (1 << 15) -#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) -#define V3_PCI_CFG_M_IO_DIS (1 << 13) -#define V3_PCI_CFG_M_EN3V (1 << 12) -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI_BASE register bits (PCI -> Local Bus) - */ -#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 -#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH (1 << 3) -#define V3_PCI_BASE_M_TYPE (3 << 1) -#define V3_PCI_BASE_M_IO (1 << 0) - -/* PCI MAP register bits (PCI -> Local bus) - */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) -#define V3_PCI_MAP_M_SWAP (3 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -/* - * LB_BASE0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_ADR_BASE 0xfff00000 -#define V3_LB_BASE_SWAP (3 << 8) -#define V3_LB_BASE_ADR_SIZE (15 << 4) -#define V3_LB_BASE_PREFETCH (1 << 3) -#define V3_LB_BASE_ENABLE (1 << 0) - -#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) -#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) -#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) -#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) -#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) -#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) -#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) -#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) -#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) -#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) -#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) -#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) - -#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) - -/* - * LB_MAP0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_MAP_MAP_ADR 0xfff0 -#define V3_LB_MAP_TYPE (7 << 1) -#define V3_LB_MAP_AD_LOW_EN (1 << 0) - -#define V3_LB_MAP_TYPE_IACK (0 << 1) -#define V3_LB_MAP_TYPE_IO (1 << 1) -#define V3_LB_MAP_TYPE_MEM (3 << 1) -#define V3_LB_MAP_TYPE_CONFIG (5 << 1) -#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) - -#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) - -/* - * LB_BASE2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_BASE2_ADR_BASE 0xff00 -#define V3_LB_BASE2_SWAP (3 << 6) -#define V3_LB_BASE2_ENABLE (1 << 0) - -#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) - -/* - * LB_MAP2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_MAP2_MAP_ADR 0xff00 - -#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) - -/* - * The V3 PCI interface chip in Integrator provides several windows from - * local bus memory into the PCI memory areas. Unfortunately, there - * are not really enough windows for our usage, therefore we reuse - * one of the windows for access to PCI configuration space. The - * memory map is as follows: - * - * Local Bus Memory Usage - * - * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable - * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable - * 60000000 - 60FFFFFF PCI IO. 16M - * 61000000 - 61FFFFFF PCI Configuration. 16M - * - * There are three V3 windows, each described by a pair of V3 registers. - * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. - * Base0 and Base1 can be used for any type of PCI memory access. Base2 - * can be used either for PCI I/O or for I20 accesses. By default, uHAL - * uses this only for PCI IO space. - * - * Normally these spaces are mapped using the following base registers: - * - * Usage Local Bus Memory Base/Map registers used - * - * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 - * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 - * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 - * Cfg 61000000 - 61FFFFFF - * - * This means that I20 and PCI configuration space accesses will fail. - * When PCI configuration accesses are needed (via the uHAL PCI - * configuration space primitives) we must remap the spaces as follows: - * - * Usage Local Bus Memory Base/Map registers used - * - * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 - * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 - * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 - * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 - * - * To make this work, the code depends on overlapping windows working. - * The V3 chip translates an address by checking its range within - * each of the BASE/MAP pairs in turn (in ascending register number - * order). It will use the first matching pair. So, for example, - * if the same address is mapped by both LB_BASE0/LB_MAP0 and - * LB_BASE1/LB_MAP1, the V3 will use the translation from - * LB_BASE0/LB_MAP0. - * - * To allow PCI Configuration space access, the code enlarges the - * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes - * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can - * be remapped for use by configuration cycles. - * - * At the end of the PCI Configuration space accesses, - * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window - * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to - * reveal the now restored LB_BASE1/LB_MAP1 window. - * - * NOTE: We do not set up I2O mapping. I suspect that this is only - * for an intelligent (target) device. Using I2O disables most of - * the mappings into PCI memory. - */ - -/* Filled in by probe */ -static void __iomem *pci_v3_base; -/* CPU side memory ranges */ -static struct resource conf_mem; /* FIXME: remap this instead of static map */ -static struct resource io_mem; -static struct resource non_mem; -static struct resource pre_mem; -/* PCI side memory ranges */ -static u64 non_mem_pci; -static u64 non_mem_pci_sz; -static u64 pre_mem_pci; -static u64 pre_mem_pci_sz; - -// V3 access routines -#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o)) -#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o))) - -#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o)) -#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o))) - -#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o)) -#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o))) - -/*============================================================================ - * - * routine: uHALir_PCIMakeConfigAddress() - * - * parameters: bus = which bus - * device = which device - * function = which function - * offset = configuration space register we are interested in - * - * description: this routine will generate a platform dependent config - * address. - * - * calls: none - * - * returns: configuration address to play on the PCI bus - * - * To generate the appropriate PCI configuration cycles in the PCI - * configuration address space, you present the V3 with the following pattern - * (which is very nearly a type 1 (except that the lower two bits are 00 and - * not 01). In order for this mapping to work you need to set up one of - * the local to PCI aperatures to 16Mbytes in length translating to - * PCI configuration space starting at 0x0000.0000. - * - * PCI configuration cycles look like this: - * - * Type 0: - * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - * 31:11 Device select bit. - * 10:8 Function number - * 7:2 Register number - * - * Type 1: - * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - * 31:24 reserved - * 23:16 bus number (8 bits = 128 possible buses) - * 15:11 Device number (5 bits) - * 10:8 function number - * 7:2 register number - * - */ - -#undef V3_LB_BASE_PREFETCH -#define V3_LB_BASE_PREFETCH 0 - -static void __iomem *v3_open_config_window(struct pci_bus *bus, - unsigned int devfn, int offset) -{ - unsigned int address, mapaddress, busnr; - - busnr = bus->number; - - /* - * Trap out illegal values - */ - BUG_ON(offset > 255); - BUG_ON(busnr > 255); - BUG_ON(devfn > 255); - - if (busnr == 0) { - int slot = PCI_SLOT(devfn); - - /* - * local bus segment so need a type 0 config cycle - * - * build the PCI configuration "address" with one-hot in - * A31-A11 - * - * mapaddress: - * 3:1 = config cycle (101) - * 0 = PCI A1 & A0 are 0 (0) - */ - address = PCI_FUNC(devfn) << 8; - mapaddress = V3_LB_MAP_TYPE_CONFIG; - - if (slot > 12) - /* - * high order bits are handled by the MAP register - */ - mapaddress |= 1 << (slot - 5); - else - /* - * low order bits handled directly in the address - */ - address |= 1 << (slot + 11); - } else { - /* - * not the local bus segment so need a type 1 config cycle - * - * address: - * 23:16 = bus number - * 15:11 = slot number (7:3 of devfn) - * 10:8 = func number (2:0 of devfn) - * - * mapaddress: - * 3:1 = config cycle (101) - * 0 = PCI A1 & A0 from host bus (1) - */ - mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; - address = (busnr << 16) | (devfn << 8); - } - - /* - * Set up base0 to see all 512Mbytes of memory space (not - * prefetchable), this frees up base1 for re-use by - * configuration memory - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | - V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); - - /* - * Set up base1/map1 to point into configuration space. - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) | - V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, mapaddress); - - return PCI_CONFIG_VADDR + address + offset; -} - -static void v3_close_config_window(void) -{ - /* - * Reassign base1 for use by prefetchable PCI memory - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) | - V3_LB_MAP_TYPE_MEM_MULTIPLE); - - /* - * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); -} - -static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *val) -{ - int ret = pci_generic_config_read(bus, devfn, where, size, val); - v3_close_config_window(); - return ret; -} - -static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - int ret = pci_generic_config_write(bus, devfn, where, size, val); - v3_close_config_window(); - return ret; -} - -static struct pci_ops pci_v3_ops = { - .map_bus = v3_open_config_window, - .read = v3_read_config, - .write = v3_write_config, -}; - -static int __init pci_v3_setup_resources(struct pci_sys_data *sys) -{ - if (request_resource(&iomem_resource, &non_mem)) { - printk(KERN_ERR "PCI: unable to allocate non-prefetchable " - "memory region\n"); - return -EBUSY; - } - if (request_resource(&iomem_resource, &pre_mem)) { - release_resource(&non_mem); - printk(KERN_ERR "PCI: unable to allocate prefetchable " - "memory region\n"); - return -EBUSY; - } - - /* - * the mem resource for this bus - * the prefetch mem resource for this bus - */ - pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); - pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); - - return 1; -} - -/* - * These don't seem to be implemented on the Integrator I have, which - * means I can't get additional information on the reason for the pm2fb - * problems. I suppose I'll just have to mind-meld with the machine. ;) - */ -static void __iomem *ap_syscon_base; -#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 -#define INTEGRATOR_SC_LBFADDR_OFFSET 0x20 -#define INTEGRATOR_SC_LBFCODE_OFFSET 0x24 - -static int -v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - unsigned long pc = instruction_pointer(regs); - unsigned long instr = *(unsigned long *)pc; -#if 0 - char buf[128]; - - sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", - addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255, - v3_readb(V3_LB_ISTAT)); - printk(KERN_DEBUG "%s", buf); -#endif - - v3_writeb(V3_LB_ISTAT, 0); - __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); - - /* - * If the instruction being executed was a read, - * make it look like it read all-ones. - */ - if ((instr & 0x0c100000) == 0x04100000) { - int reg = (instr >> 12) & 15; - unsigned long val; - - if (instr & 0x00400000) - val = 255; - else - val = -1; - - regs->uregs[reg] = val; - regs->ARM_pc += 4; - return 0; - } - - if ((instr & 0x0e100090) == 0x00100090) { - int reg = (instr >> 12) & 15; - - regs->uregs[reg] = -1; - regs->ARM_pc += 4; - return 0; - } - - return 1; -} - -static irqreturn_t v3_irq(int irq, void *devid) -{ -#ifdef CONFIG_DEBUG_LL - struct pt_regs *regs = get_irq_regs(); - unsigned long pc = instruction_pointer(regs); - unsigned long instr = *(unsigned long *)pc; - char buf[128]; - extern void printascii(const char *); - - sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " - "ISTAT=%02x\n", irq, pc, instr, - __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), - __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255, - v3_readb(V3_LB_ISTAT)); - printascii(buf); -#endif - - v3_writew(V3_PCI_STAT, 0xf000); - v3_writeb(V3_LB_ISTAT, 0); - __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); - -#ifdef CONFIG_DEBUG_LL - /* - * If the instruction being executed was a read, - * make it look like it read all-ones. - */ - if ((instr & 0x0c100000) == 0x04100000) { - int reg = (instr >> 16) & 15; - sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]); - printascii(buf); - } -#endif - return IRQ_HANDLED; -} - -static int __init pci_v3_setup(int nr, struct pci_sys_data *sys) -{ - int ret = 0; - - if (!ap_syscon_base) - return -EINVAL; - - if (nr == 0) { - sys->mem_offset = non_mem.start; - ret = pci_v3_setup_resources(sys); - } - - return ret; -} - -/* - * V3_LB_BASE? - local bus address - * V3_LB_MAP? - pci bus address - */ -static void __init pci_v3_preinit(void) -{ - unsigned int temp; - phys_addr_t io_address = pci_pio_to_address(io_mem.start); - - pcibios_min_mem = 0x00100000; - - /* - * Hook in our fault handler for PCI errors - */ - hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); - hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); - hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); - hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); - - /* - * Unlock V3 registers, but only if they were previously locked. - */ - if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) - v3_writew(V3_SYSTEM, 0xa05f); - - /* - * Setup window 0 - PCI non-prefetchable memory - * Local: 0x40000000 Bus: 0x00000000 Size: 256MB - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) | - V3_LB_MAP_TYPE_MEM); - - /* - * Setup window 1 - PCI prefetchable memory - * Local: 0x50000000 Bus: 0x10000000 Size: 256MB - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) | - V3_LB_MAP_TYPE_MEM_MULTIPLE); - - /* - * Setup window 2 - PCI IO - */ - v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); - - /* - * Disable PCI to host IO cycles - */ - temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN; - temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS; - v3_writew(V3_PCI_CFG, temp); - - printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n", - v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY)); - - /* - * Set the V3 FIFO such that writes have higher priority than - * reads, and local bus write causes local bus read fifo flush. - * Same for PCI. - */ - v3_writew(V3_FIFO_PRIORITY, 0x0a0a); - - /* - * Re-lock the system register. - */ - temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK; - v3_writew(V3_SYSTEM, temp); - - /* - * Clear any error conditions, and enable write errors. - */ - v3_writeb(V3_LB_ISTAT, 0); - v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10)); - v3_writeb(V3_LB_IMASK, 0x28); - __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); -} - -static void __init pci_v3_postinit(void) -{ - unsigned int pci_cmd; - phys_addr_t io_address = pci_pio_to_address(io_mem.start); - - pci_cmd = PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; - - v3_writew(V3_PCI_CMD, pci_cmd); - - v3_writeb(V3_LB_ISTAT, ~0x40); - v3_writeb(V3_LB_IMASK, 0x68); - -#if 0 - ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL); - if (ret) - printk(KERN_ERR "PCI: unable to grab local bus timeout " - "interrupt: %d\n", ret); -#endif - - register_isa_ports(non_mem.start, io_address, 0); -} - -/* - * A small note about bridges and interrupts. The DECchip 21050 (and - * later) adheres to the PCI-PCI bridge specification. This says that - * the interrupts on the other side of a bridge are swizzled in the - * following manner: - * - * Dev Interrupt Interrupt - * Pin on Pin on - * Device Connector - * - * 4 A A - * B B - * C C - * D D - * - * 5 A B - * B C - * C D - * D A - * - * 6 A C - * B D - * C A - * D B - * - * 7 A D - * B A - * C B - * D C - * - * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. - * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 - */ - -/* - * This routine handles multiple bridges. - */ -static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp) -{ - if (*pinp == 0) - *pinp = 1; - - return pci_common_swizzle(dev, pinp); -} - -static struct hw_pci pci_v3 __initdata = { - .swizzle = pci_v3_swizzle, - .setup = pci_v3_setup, - .nr_controllers = 1, - .ops = &pci_v3_ops, - .preinit = pci_v3_preinit, - .postinit = pci_v3_postinit, -}; - -static int __init pci_v3_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct of_pci_range_parser parser; - struct of_pci_range range; - struct resource *res; - int irq, ret; - - /* Remap the Integrator system controller */ - ap_syscon_base = devm_ioremap(&pdev->dev, INTEGRATOR_SC_BASE, 0x100); - if (!ap_syscon_base) { - dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); - return -ENODEV; - } - - /* Device tree probe path */ - if (!np) { - dev_err(&pdev->dev, "no device tree node for PCIv3\n"); - return -ENODEV; - } - - if (of_pci_range_parser_init(&parser, np)) - return -EINVAL; - - /* Get base for bridge registers */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "unable to obtain PCIv3 base\n"); - return -ENODEV; - } - pci_v3_base = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (!pci_v3_base) { - dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); - return -ENODEV; - } - - /* Get and request error IRQ resource */ - irq = platform_get_irq(pdev, 0); - if (irq <= 0) { - dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n"); - return -ENODEV; - } - ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0, - "PCIv3 error", NULL); - if (ret < 0) { - dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret); - return ret; - } - - for_each_of_pci_range(&parser, &range) { - if (!range.flags) { - ret = of_pci_range_to_resource(&range, np, &conf_mem); - conf_mem.name = "PCIv3 config"; - } - if (range.flags & IORESOURCE_IO) { - ret = of_pci_range_to_resource(&range, np, &io_mem); - io_mem.name = "PCIv3 I/O"; - } - if ((range.flags & IORESOURCE_MEM) && - !(range.flags & IORESOURCE_PREFETCH)) { - non_mem_pci = range.pci_addr; - non_mem_pci_sz = range.size; - ret = of_pci_range_to_resource(&range, np, &non_mem); - non_mem.name = "PCIv3 non-prefetched mem"; - } - if ((range.flags & IORESOURCE_MEM) && - (range.flags & IORESOURCE_PREFETCH)) { - pre_mem_pci = range.pci_addr; - pre_mem_pci_sz = range.size; - ret = of_pci_range_to_resource(&range, np, &pre_mem); - pre_mem.name = "PCIv3 prefetched mem"; - } - - if (ret < 0) { - dev_err(&pdev->dev, "missing ranges in device node\n"); - return ret; - } - } - - pci_v3.map_irq = of_irq_parse_and_map_pci; - pci_common_init_dev(&pdev->dev, &pci_v3); - - return 0; -} - -static const struct of_device_id pci_ids[] = { - { .compatible = "v3,v360epc-pci", }, - {}, -}; - -static struct platform_driver pci_v3_driver = { - .driver = { - .name = "pci-v3", - .of_match_table = pci_ids, - }, -}; - -static int __init pci_v3_init(void) -{ - return platform_driver_probe(&pci_v3_driver, pci_v3_probe); -} - -subsys_initcall(pci_v3_init); - -/* - * Static mappings for the PCIv3 bridge - * - * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) - * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) - * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) - */ -static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = { - { - .virtual = (unsigned long)PCI_MEMORY_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = (unsigned long)PCI_CONFIG_VADDR, - .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), - .length = SZ_16M, - .type = MT_DEVICE - } -}; - -int __init pci_v3_early_init(void) -{ - iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc)); - vga_base = (unsigned long)PCI_MEMORY_VADDR; - pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); - return 0; -} diff --git a/arch/arm/mach-integrator/pci_v3.h b/arch/arm/mach-integrator/pci_v3.h deleted file mode 100644 index cafc7174baab..000000000000 --- a/arch/arm/mach-integrator/pci_v3.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Simple oneliner include to the PCIv3 early init */ -#ifdef CONFIG_PCI -extern int pci_v3_early_init(void); -#else -static inline int pci_v3_early_init(void) -{ - return 0; -} -#endif diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index ee30511849ca..aff6164b2083 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -9,6 +9,7 @@ menuconfig ARCH_MESON select PINCTRL_MESON select COMMON_CLK select COMMON_CLK_AMLOGIC + select HAVE_ARM_SCU if SMP if ARCH_MESON @@ -28,5 +29,6 @@ config MACH_MESON8B default ARCH_MESON select MESON6_TIMER select COMMON_CLK_MESON8B + select MESON_IRQ_GPIO endif diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 9d7380eeeedd..bc26c85a7e8f 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_ARCH_MESON) += meson.o +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c new file mode 100644 index 000000000000..2555f9056a33 --- /dev/null +++ b/arch/arm/mach-meson/platsmp.c @@ -0,0 +1,440 @@ +/* + * Copyright (C) 2015 Carlo Caione <carlo@endlessm.com> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <linux/smp.h> +#include <linux/mfd/syscon.h> + +#include <asm/cacheflush.h> +#include <asm/cp15.h> +#include <asm/smp_scu.h> +#include <asm/smp_plat.h> + +#define MESON_SMP_SRAM_CPU_CTRL_REG (0x00) +#define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2)) + +#define MESON_CPU_AO_RTI_PWR_A9_CNTL0 (0x00) +#define MESON_CPU_AO_RTI_PWR_A9_CNTL1 (0x04) +#define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0 (0x14) + +#define MESON_CPU_PWR_A9_CNTL0_M(c) (0x03 << ((c * 2) + 16)) +#define MESON_CPU_PWR_A9_CNTL1_M(c) (0x03 << ((c + 1) << 1)) +#define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4))) +#define MESON_CPU_PWR_A9_CNTL1_ST(c) (0x01 << (c + 16)) + +static void __iomem *sram_base; +static void __iomem *scu_base; +static struct regmap *pmu; + +static struct reset_control *meson_smp_get_core_reset(int cpu) +{ + struct device_node *np = of_get_cpu_node(cpu, 0); + + return of_reset_control_get_exclusive(np, NULL); +} + +static void meson_smp_set_cpu_ctrl(int cpu, bool on_off) +{ + u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG); + + if (on_off) + val |= BIT(cpu); + else + val &= ~BIT(cpu); + + /* keep bit 0 always enabled */ + val |= BIT(0); + + writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG); +} + +static void __init meson_smp_prepare_cpus(const char *scu_compatible, + const char *pmu_compatible, + const char *sram_compatible) +{ + static struct device_node *node; + + /* SMP SRAM */ + node = of_find_compatible_node(NULL, NULL, sram_compatible); + if (!node) { + pr_err("Missing SRAM node\n"); + return; + } + + sram_base = of_iomap(node, 0); + if (!sram_base) { + pr_err("Couldn't map SRAM registers\n"); + return; + } + + /* PMU */ + pmu = syscon_regmap_lookup_by_compatible(pmu_compatible); + if (IS_ERR(pmu)) { + pr_err("Couldn't map PMU registers\n"); + return; + } + + /* SCU */ + node = of_find_compatible_node(NULL, NULL, scu_compatible); + if (!node) { + pr_err("Missing SCU node\n"); + return; + } + + scu_base = of_iomap(node, 0); + if (!scu_base) { + pr_err("Couln't map SCU registers\n"); + return; + } + + scu_enable(scu_base); +} + +static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus) +{ + meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", + "amlogic,meson8b-smp-sram"); +} + +static void __init meson8_smp_prepare_cpus(unsigned int max_cpus) +{ + meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", + "amlogic,meson8-smp-sram"); +} + +static void meson_smp_begin_secondary_boot(unsigned int cpu) +{ + /* + * Set the entry point before powering on the CPU through the SCU. This + * is needed if the CPU is in "warm" state (= after rebooting the + * system without power-cycling, or when taking the CPU offline and + * then taking it online again. + */ + writel(__pa_symbol(secondary_startup), + sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu)); + + /* + * SCU Power on CPU (needs to be done before starting the CPU, + * otherwise the secondary CPU will not start). + */ + scu_cpu_power_enable(scu_base, cpu); +} + +static int meson_smp_finalize_secondary_boot(unsigned int cpu) +{ + unsigned long timeout; + + timeout = jiffies + (10 * HZ); + while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) { + if (!time_before(jiffies, timeout)) { + pr_err("Timeout while waiting for CPU%d status\n", + cpu); + return -ETIMEDOUT; + } + } + + writel(__pa_symbol(secondary_startup), + sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu)); + + meson_smp_set_cpu_ctrl(cpu, true); + + return 0; +} + +static int meson8_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + struct reset_control *rstc; + int ret; + + rstc = meson_smp_get_core_reset(cpu); + if (IS_ERR(rstc)) { + pr_err("Couldn't get the reset controller for CPU%d\n", cpu); + return PTR_ERR(rstc); + } + + meson_smp_begin_secondary_boot(cpu); + + /* Reset enable */ + ret = reset_control_assert(rstc); + if (ret) { + pr_err("Failed to assert CPU%d reset\n", cpu); + goto out; + } + + /* CPU power ON */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't wake up CPU%d\n", cpu); + goto out; + } + + udelay(10); + + /* Isolation disable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), + 0); + if (ret < 0) { + pr_err("Error when disabling isolation of CPU%d\n", cpu); + goto out; + } + + /* Reset disable */ + ret = reset_control_deassert(rstc); + if (ret) { + pr_err("Failed to de-assert CPU%d reset\n", cpu); + goto out; + } + + ret = meson_smp_finalize_secondary_boot(cpu); + if (ret) + goto out; + +out: + reset_control_put(rstc); + + return 0; +} + +static int meson8b_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + struct reset_control *rstc; + int ret; + u32 val; + + rstc = meson_smp_get_core_reset(cpu); + if (IS_ERR(rstc)) { + pr_err("Couldn't get the reset controller for CPU%d\n", cpu); + return PTR_ERR(rstc); + } + + meson_smp_begin_secondary_boot(cpu); + + /* CPU power UP */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, + MESON_CPU_PWR_A9_CNTL0_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't power up CPU%d\n", cpu); + goto out; + } + + udelay(5); + + /* Reset enable */ + ret = reset_control_assert(rstc); + if (ret) { + pr_err("Failed to assert CPU%d reset\n", cpu); + goto out; + } + + /* Memory power UP */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0, + MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't power up the memory for CPU%d\n", cpu); + goto out; + } + + /* Wake up CPU */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't wake up CPU%d\n", cpu); + goto out; + } + + udelay(10); + + ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val, + val & MESON_CPU_PWR_A9_CNTL1_ST(cpu), + 10, 10000); + if (ret) { + pr_err("Timeout while polling PMU for CPU%d status\n", cpu); + goto out; + } + + /* Isolation disable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), + 0); + if (ret < 0) { + pr_err("Error when disabling isolation of CPU%d\n", cpu); + goto out; + } + + /* Reset disable */ + ret = reset_control_deassert(rstc); + if (ret) { + pr_err("Failed to de-assert CPU%d reset\n", cpu); + goto out; + } + + ret = meson_smp_finalize_secondary_boot(cpu); + if (ret) + goto out; + +out: + reset_control_put(rstc); + + return 0; +} + +#ifdef CONFIG_HOTPLUG_CPU +static void meson8_smp_cpu_die(unsigned int cpu) +{ + meson_smp_set_cpu_ctrl(cpu, false); + + v7_exit_coherency_flush(louis); + + scu_power_mode(scu_base, SCU_PM_POWEROFF); + + dsb(); + wfi(); + + /* we should never get here */ + WARN_ON(1); +} + +static int meson8_smp_cpu_kill(unsigned int cpu) +{ + int ret, power_mode; + unsigned long timeout; + + timeout = jiffies + (50 * HZ); + do { + power_mode = scu_get_cpu_power_mode(scu_base, cpu); + + if (power_mode == SCU_PM_POWEROFF) + break; + + usleep_range(10000, 15000); + } while (time_before(jiffies, timeout)); + + if (power_mode != SCU_PM_POWEROFF) { + pr_err("Error while waiting for SCU power-off on CPU%d\n", + cpu); + return -ETIMEDOUT; + } + + msleep(30); + + /* Isolation enable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), + 0x3); + if (ret < 0) { + pr_err("Error when enabling isolation for CPU%d\n", cpu); + return ret; + } + + udelay(10); + + /* CPU power OFF */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3); + if (ret < 0) { + pr_err("Couldn't change sleep status of CPU%d\n", cpu); + return ret; + } + + return 1; +} + +static int meson8b_smp_cpu_kill(unsigned int cpu) +{ + int ret, power_mode, count = 5000; + + do { + power_mode = scu_get_cpu_power_mode(scu_base, cpu); + + if (power_mode == SCU_PM_POWEROFF) + break; + + udelay(10); + } while (++count); + + if (power_mode != SCU_PM_POWEROFF) { + pr_err("Error while waiting for SCU power-off on CPU%d\n", + cpu); + return -ETIMEDOUT; + } + + udelay(10); + + /* CPU power DOWN */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, + MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3); + if (ret < 0) { + pr_err("Couldn't power down CPU%d\n", cpu); + return ret; + } + + /* Isolation enable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu), + 0x3); + if (ret < 0) { + pr_err("Error when enabling isolation for CPU%d\n", cpu); + return ret; + } + + udelay(10); + + /* Sleep status */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3); + if (ret < 0) { + pr_err("Couldn't change sleep status of CPU%d\n", cpu); + return ret; + } + + /* Memory power DOWN */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0, + MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf); + if (ret < 0) { + pr_err("Couldn't power down the memory of CPU%d\n", cpu); + return ret; + } + + return 1; +} +#endif + +static struct smp_operations meson8_smp_ops __initdata = { + .smp_prepare_cpus = meson8_smp_prepare_cpus, + .smp_boot_secondary = meson8_smp_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = meson8_smp_cpu_die, + .cpu_kill = meson8_smp_cpu_kill, +#endif +}; + +static struct smp_operations meson8b_smp_ops __initdata = { + .smp_prepare_cpus = meson8b_smp_prepare_cpus, + .smp_boot_secondary = meson8b_smp_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = meson8_smp_cpu_die, + .cpu_kill = meson8b_smp_cpu_kill, +#endif +}; + +CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops); +CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops); diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c index 0170e99fd70f..6ae057c2cf9f 100644 --- a/arch/arm/mach-mxs/pm.c +++ b/arch/arm/mach-mxs/pm.c @@ -30,7 +30,7 @@ static int mxs_suspend_enter(suspend_state_t state) return 0; } -static struct platform_suspend_ops mxs_suspend_ops = { +static const struct platform_suspend_ops mxs_suspend_ops = { .enter = mxs_suspend_enter, .valid = suspend_valid_only_mem, }; diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 6cbc69c92913..52e8e53ca154 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -156,7 +156,7 @@ static struct map_desc ams_delta_io_desc[] __initdata = { } }; -static struct omap_lcd_config ams_delta_lcd_config __initdata = { +static const struct omap_lcd_config ams_delta_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index b93ad58b0a63..69bd601feb83 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -266,7 +266,7 @@ static struct platform_device *devices[] __initdata = { &kp_device, }; -static struct omap_lcd_config fsample_lcd_config = { +static const struct omap_lcd_config fsample_lcd_config = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 6a38c7603064..ab51f8554697 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -357,7 +357,7 @@ static struct omap_usb_config h2_usb_config __initdata = { .pins[1] = 3, }; -static struct omap_lcd_config h2_lcd_config __initdata = { +static const struct omap_lcd_config h2_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 302260583e8e..ad339f51cc78 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -376,7 +376,7 @@ static struct omap_usb_config h3_usb_config __initdata = { .pins[1] = 3, }; -static struct omap_lcd_config h3_lcd_config __initdata = { +static const struct omap_lcd_config h3_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index e424df901dbd..67d46690a56e 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -391,7 +391,7 @@ static struct omap_usb_config htcherald_usb_config __initdata = { }; /* LCD Device resources */ -static struct omap_lcd_config htcherald_lcd_config __initdata = { +static const struct omap_lcd_config htcherald_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 67e188271643..8c286a29f24b 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -302,7 +302,7 @@ static struct omap_usb_config innovator1510_usb_config __initdata = { .pins[0] = 2, }; -static struct omap_lcd_config innovator1510_lcd_config __initdata = { +static const struct omap_lcd_config innovator1510_lcd_config __initconst = { .ctrl_name = "internal", }; #endif @@ -323,7 +323,7 @@ static struct omap_usb_config h2_usb_config __initdata = { .pins[1] = 3, }; -static struct omap_lcd_config innovator1610_lcd_config __initdata = { +static const struct omap_lcd_config innovator1610_lcd_config __initconst = { .ctrl_name = "internal", }; #endif diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 06243c0b12d2..eb41db78cd47 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -103,7 +103,7 @@ static struct mipid_platform_data nokia770_mipid_platform_data = { .shutdown = mipid_shutdown, }; -static struct omap_lcd_config nokia770_lcd_config __initdata = { +static const struct omap_lcd_config nokia770_lcd_config __initconst = { .ctrl_name = "hwa742", }; diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index d579f4e04137..c66372ed29e2 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -295,7 +295,7 @@ static struct omap_usb_config osk_usb_config __initdata = { }; #ifdef CONFIG_OMAP_OSK_MISTRAL -static struct omap_lcd_config osk_lcd_config __initdata = { +static const struct omap_lcd_config osk_lcd_config __initconst = { .ctrl_name = "internal", }; #endif diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index e5288cda1a6a..2dc5deb19803 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -178,7 +178,7 @@ static struct omap_usb_config palmte_usb_config __initdata = { .pins[0] = 2, }; -static struct omap_lcd_config palmte_lcd_config __initdata = { +static const struct omap_lcd_config palmte_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index d672495f7441..a23327682df0 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -241,7 +241,7 @@ static struct omap_usb_config palmtt_usb_config __initdata = { .pins[0] = 2, }; -static struct omap_lcd_config palmtt_lcd_config __initdata = { +static const struct omap_lcd_config palmtt_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index aaf741b0aff6..30b07096197b 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -206,7 +206,7 @@ static struct omap_usb_config palmz71_usb_config __initdata = { .pins[0] = 2, }; -static struct omap_lcd_config palmz71_lcd_config __initdata = { +static const struct omap_lcd_config palmz71_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index e994a78bdd09..b4951eb82898 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -225,7 +225,7 @@ static struct platform_device *devices[] __initdata = { &kp_device, }; -static struct omap_lcd_config perseus2_lcd_config __initdata = { +static const struct omap_lcd_config perseus2_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 6c482254b37c..ec27bb3e370f 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -297,7 +297,7 @@ static struct omap_usb_config sx1_usb_config __initdata = { /*----------- LCD -------------------------*/ -static struct omap_lcd_config sx1_lcd_config __initdata = { +static const struct omap_lcd_config sx1_lcd_config __initconst = { .ctrl_name = "internal", }; diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index e31a5a22e171..00b1f17f8d44 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -104,6 +104,7 @@ config ARCH_OMAP2PLUS select OMAP_GPMC select PINCTRL select SOC_BUS + select TI_SYSC select OMAP_IRQCHIP select CLKSRC_TI_32K help diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 38f1748a4500..2f722a805948 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -199,15 +199,12 @@ obj-y += omap_hwmod_common_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o -obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o -obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o -obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index b5ad7fcb80ed..bc202835371b 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -225,7 +225,6 @@ extern struct device *omap2_get_iva_device(void); extern struct device *omap2_get_l3_device(void); extern struct device *omap4_get_dsp_device(void); -unsigned int omap4_xlate_irq(unsigned int hwirq); void omap_gic_of_init(void); #ifdef CONFIG_CACHE_L2X0 diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 694ce0939d50..a005e2a23b86 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -223,7 +223,7 @@ static struct omap_system_dma_plat_info dma_plat_info __initdata = { .dma_read = dma_read, }; -static struct platform_device_info omap_dma_dev_info = { +static struct platform_device_info omap_dma_dev_info __initdata = { .name = "omap-dma-engine", .id = -1, .dma_mask = DMA_BIT_MASK(32), diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c index f3897d82e53e..2bc4db23ca56 100644 --- a/arch/arm/mach-omap2/hdq1w.c +++ b/arch/arm/mach-omap2/hdq1w.c @@ -75,25 +75,3 @@ int omap_hdq1w_reset(struct omap_hwmod *oh) return 0; } - -#ifndef CONFIG_OF -static int __init omap_init_hdq(void) -{ - int id = -1; - struct platform_device *pdev; - struct omap_hwmod *oh; - char *oh_name = "hdq1w"; - char *devname = "omap_hdq"; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) - return 0; - - pdev = omap_device_build(devname, id, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", - devname, oh->name); - - return 0; -} -omap_arch_initcall(omap_init_hdq); -#endif diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 16cb1c195fd8..df2c29edbbcd 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -693,9 +693,12 @@ void __init dra7xxx_check_revision(void) omap_revision = DRA722_REV_ES1_0; break; case 1: - default: omap_revision = DRA722_REV_ES2_0; break; + case 2: + default: + omap_revision = DRA722_REV_ES2_1; + break; } break; diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index cf65ab8bb004..b226c8aaf8b1 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -299,30 +299,6 @@ static const struct of_device_id intc_match[] = { static struct device_node *intc_node; -unsigned int omap4_xlate_irq(unsigned int hwirq) -{ - struct of_phandle_args irq_data; - unsigned int irq; - - if (!intc_node) - intc_node = of_find_matching_node(NULL, intc_match); - - if (WARN_ON(!intc_node)) - return hwirq; - - irq_data.np = intc_node; - irq_data.args_count = 3; - irq_data.args[0] = 0; - irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START; - irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH; - - irq = irq_create_of_mapping(&irq_data); - if (WARN_ON(!irq)) - irq = hwirq; - - return irq; -} - void __init omap_gic_of_init(void) { struct device_node *np; diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index acbede082b5b..d45cbfdb4be6 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -35,6 +35,8 @@ #include <linux/pm_domain.h> #include <linux/pm_runtime.h> #include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/notifier.h> #include "common.h" @@ -309,88 +311,6 @@ int omap_device_get_context_loss_count(struct platform_device *pdev) } /** - * omap_device_count_resources - count number of struct resource entries needed - * @od: struct omap_device * - * @flags: Type of resources to include when counting (IRQ/DMA/MEM) - * - * Count the number of struct resource entries needed for this - * omap_device @od. Used by omap_device_build_ss() to determine how - * much memory to allocate before calling - * omap_device_fill_resources(). Returns the count. - */ -static int omap_device_count_resources(struct omap_device *od, - unsigned long flags) -{ - int c = 0; - int i; - - for (i = 0; i < od->hwmods_cnt; i++) - c += omap_hwmod_count_resources(od->hwmods[i], flags); - - pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n", - od->pdev->name, c, od->hwmods_cnt); - - return c; -} - -/** - * omap_device_fill_resources - fill in array of struct resource - * @od: struct omap_device * - * @res: pointer to an array of struct resource to be filled in - * - * Populate one or more empty struct resource pointed to by @res with - * the resource data for this omap_device @od. Used by - * omap_device_build_ss() after calling omap_device_count_resources(). - * Ideally this function would not be needed at all. If omap_device - * replaces platform_device, then we can specify our own - * get_resource()/ get_irq()/etc functions that use the underlying - * omap_hwmod information. Or if platform_device is extended to use - * subarchitecture-specific function pointers, the various - * platform_device functions can simply call omap_device internal - * functions to get device resources. Hacking around the existing - * platform_device code wastes memory. Returns 0. - */ -static int omap_device_fill_resources(struct omap_device *od, - struct resource *res) -{ - int i, r; - - for (i = 0; i < od->hwmods_cnt; i++) { - r = omap_hwmod_fill_resources(od->hwmods[i], res); - res += r; - } - - return 0; -} - -/** - * _od_fill_dma_resources - fill in array of struct resource with dma resources - * @od: struct omap_device * - * @res: pointer to an array of struct resource to be filled in - * - * Populate one or more empty struct resource pointed to by @res with - * the dma resource data for this omap_device @od. Used by - * omap_device_alloc() after calling omap_device_count_resources(). - * - * Ideally this function would not be needed at all. If we have - * mechanism to get dma resources from DT. - * - * Returns 0. - */ -static int _od_fill_dma_resources(struct omap_device *od, - struct resource *res) -{ - int i, r; - - for (i = 0; i < od->hwmods_cnt; i++) { - r = omap_hwmod_fill_dma_resources(od->hwmods[i], res); - res += r; - } - - return 0; -} - -/** * omap_device_alloc - allocate an omap_device * @pdev: platform_device that will be included in this omap_device * @oh: ptr to the single omap_hwmod that backs this omap_device @@ -407,8 +327,7 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev, { int ret = -ENOMEM; struct omap_device *od; - struct resource *res = NULL; - int i, res_count; + int i; struct omap_hwmod **hwmods; od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); @@ -424,74 +343,6 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev, od->hwmods = hwmods; od->pdev = pdev; - - /* - * Non-DT Boot: - * Here, pdev->num_resources = 0, and we should get all the - * resources from hwmod. - * - * DT Boot: - * OF framework will construct the resource structure (currently - * does for MEM & IRQ resource) and we should respect/use these - * resources, killing hwmod dependency. - * If pdev->num_resources > 0, we assume that MEM & IRQ resources - * have been allocated by OF layer already (through DTB). - * As preparation for the future we examine the OF provided resources - * to see if we have DMA resources provided already. In this case - * there is no need to update the resources for the device, we use the - * OF provided ones. - * - * TODO: Once DMA resource is available from OF layer, we should - * kill filling any resources from hwmod. - */ - if (!pdev->num_resources) { - /* Count all resources for the device */ - res_count = omap_device_count_resources(od, IORESOURCE_IRQ | - IORESOURCE_DMA | - IORESOURCE_MEM); - } else { - /* Take a look if we already have DMA resource via DT */ - for (i = 0; i < pdev->num_resources; i++) { - struct resource *r = &pdev->resource[i]; - - /* We have it, no need to touch the resources */ - if (r->flags == IORESOURCE_DMA) - goto have_everything; - } - /* Count only DMA resources for the device */ - res_count = omap_device_count_resources(od, IORESOURCE_DMA); - /* The device has no DMA resource, no need for update */ - if (!res_count) - goto have_everything; - - res_count += pdev->num_resources; - } - - /* Allocate resources memory to account for new resources */ - res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL); - if (!res) - goto oda_exit3; - - if (!pdev->num_resources) { - dev_dbg(&pdev->dev, "%s: using %d resources from hwmod\n", - __func__, res_count); - omap_device_fill_resources(od, res); - } else { - dev_dbg(&pdev->dev, - "%s: appending %d DMA resources from hwmod\n", - __func__, res_count - pdev->num_resources); - memcpy(res, pdev->resource, - sizeof(struct resource) * pdev->num_resources); - _od_fill_dma_resources(od, &res[pdev->num_resources]); - } - - ret = platform_device_add_resources(pdev, res, res_count); - kfree(res); - - if (ret) - goto oda_exit3; - -have_everything: pdev->archdata.od = od; for (i = 0; i < oh_cnt; i++) { @@ -501,8 +352,6 @@ have_everything: return od; -oda_exit3: - kfree(hwmods); oda_exit2: kfree(od); oda_exit1: @@ -522,6 +371,93 @@ void omap_device_delete(struct omap_device *od) } /** + * omap_device_copy_resources - Add legacy IO and IRQ resources + * @oh: interconnect target module + * @pdev: platform device to copy resources to + * + * We still have legacy DMA and smartreflex needing resources. + * Let's populate what they need until we can eventually just + * remove this function. Note that there should be no need to + * call this from omap_device_build_from_dt(), nor should there + * be any need to call it for other devices. + */ +static int +omap_device_copy_resources(struct omap_hwmod *oh, + struct platform_device *pdev) +{ + struct device_node *np, *child; + struct property *prop; + struct resource *res; + const char *name; + int error, irq = 0; + + if (!oh || !oh->od || !oh->od->pdev) { + error = -EINVAL; + goto error; + } + + np = oh->od->pdev->dev.of_node; + if (!np) { + error = -ENODEV; + goto error; + } + + res = kzalloc(sizeof(*res) * 2, GFP_KERNEL); + if (!res) + return -ENOMEM; + + /* Do we have a dts range for the interconnect target module? */ + error = omap_hwmod_parse_module_range(oh, np, res); + + /* No ranges, rely on device reg entry */ + if (error) + error = of_address_to_resource(np, 0, res); + if (error) + goto free; + + /* SmartReflex needs first IO resource name to be "mpu" */ + res[0].name = "mpu"; + + /* + * We may have a configured "ti,sysc" interconnect target with a + * dts child with the interrupt. If so use the first child's + * first interrupt for "ti-hwmods" legacy support. + */ + of_property_for_each_string(np, "compatible", prop, name) + if (!strncmp("ti,sysc-", name, 8)) + break; + + child = of_get_next_available_child(np, NULL); + + if (name) + irq = irq_of_parse_and_map(child, 0); + if (!irq) + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + error = -EINVAL; + goto free; + } + + /* Legacy DMA code needs interrupt name to be "0" */ + res[1].start = irq; + res[1].end = irq; + res[1].flags = IORESOURCE_IRQ; + res[1].name = "0"; + + error = platform_device_add_resources(pdev, res, 2); + +free: + kfree(res); + +error: + WARN(error, "%s: %s device %s failed: %i\n", + __func__, oh->name, dev_name(&pdev->dev), + error); + + return error; +} + +/** * omap_device_build - build and register an omap_device with one omap_hwmod * @pdev_name: name of the platform_device driver to use * @pdev_id: this platform_device's connection ID @@ -540,45 +476,24 @@ struct platform_device __init *omap_device_build(const char *pdev_name, struct omap_hwmod *oh, void *pdata, int pdata_len) { - struct omap_hwmod *ohs[] = { oh }; - - if (!oh) - return ERR_PTR(-EINVAL); - - return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata, - pdata_len); -} - -/** - * omap_device_build_ss - build and register an omap_device with multiple hwmods - * @pdev_name: name of the platform_device driver to use - * @pdev_id: this platform_device's connection ID - * @oh: ptr to the single omap_hwmod that backs this omap_device - * @pdata: platform_data ptr to associate with the platform_device - * @pdata_len: amount of memory pointed to by @pdata - * - * Convenience function for building and registering an omap_device - * subsystem record. Subsystem records consist of multiple - * omap_hwmods. This function in turn builds and registers a - * platform_device record. Returns an ERR_PTR() on error, or passes - * along the return value of omap_device_register(). - */ -struct platform_device __init *omap_device_build_ss(const char *pdev_name, - int pdev_id, - struct omap_hwmod **ohs, - int oh_cnt, void *pdata, - int pdata_len) -{ int ret = -ENOMEM; struct platform_device *pdev; struct omap_device *od; - if (!ohs || oh_cnt == 0 || !pdev_name) + if (!oh || !pdev_name) return ERR_PTR(-EINVAL); if (!pdata && pdata_len > 0) return ERR_PTR(-EINVAL); + if (strncmp(oh->name, "smartreflex", 11) && + strncmp(oh->name, "dma", 3)) { + pr_warn("%s need to update %s to probe with dt\na", + __func__, pdev_name); + ret = -ENODEV; + goto odbs_exit; + } + pdev = platform_device_alloc(pdev_name, pdev_id); if (!pdev) { ret = -ENOMEM; @@ -591,7 +506,16 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, else dev_set_name(&pdev->dev, "%s", pdev->name); - od = omap_device_alloc(pdev, ohs, oh_cnt); + /* + * Must be called before omap_device_alloc() as oh->od + * only contains the currently registered omap_device + * and will get overwritten by omap_device_alloc(). + */ + ret = omap_device_copy_resources(oh, pdev); + if (ret) + goto odbs_exit1; + + od = omap_device_alloc(pdev, &oh, 1); if (IS_ERR(od)) goto odbs_exit1; diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h index 78c02b355179..786b9c00fdb9 100644 --- a/arch/arm/mach-omap2/omap_device.h +++ b/arch/arm/mach-omap2/omap_device.h @@ -75,10 +75,6 @@ struct platform_device *omap_device_build(const char *pdev_name, int pdev_id, struct omap_hwmod *oh, void *pdata, int pdata_len); -struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id, - struct omap_hwmod **oh, int oh_cnt, - void *pdata, int pdata_len); - struct omap_device *omap_device_alloc(struct platform_device *pdev, struct omap_hwmod **ohs, int oh_cnt); void omap_device_delete(struct omap_device *od); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2dbd63239c54..104256a5f0f7 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -994,6 +994,34 @@ static int _enable_clocks(struct omap_hwmod *oh) } /** + * _omap4_clkctrl_managed_by_clkfwk - true if clkctrl managed by clock framework + * @oh: struct omap_hwmod * + */ +static bool _omap4_clkctrl_managed_by_clkfwk(struct omap_hwmod *oh) +{ + if (oh->prcm.omap4.flags & HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK) + return true; + + return false; +} + +/** + * _omap4_has_clkctrl_clock - returns true if a module has clkctrl clock + * @oh: struct omap_hwmod * + */ +static bool _omap4_has_clkctrl_clock(struct omap_hwmod *oh) +{ + if (oh->prcm.omap4.clkctrl_offs) + return true; + + if (!oh->prcm.omap4.clkctrl_offs && + oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET) + return true; + + return false; +} + +/** * _disable_clocks - disable hwmod main clock and interface clocks * @oh: struct omap_hwmod * * @@ -1030,7 +1058,8 @@ static int _disable_clocks(struct omap_hwmod *oh) */ static void _omap4_enable_module(struct omap_hwmod *oh) { - if (!oh->clkdm || !oh->prcm.omap4.modulemode) + if (!oh->clkdm || !oh->prcm.omap4.modulemode || + _omap4_clkctrl_managed_by_clkfwk(oh)) return; pr_debug("omap_hwmod: %s: %s: %d\n", @@ -1061,8 +1090,10 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh) if (oh->flags & HWMOD_NO_IDLEST) return 0; - if (!oh->prcm.omap4.clkctrl_offs && - !(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET)) + if (_omap4_clkctrl_managed_by_clkfwk(oh)) + return 0; + + if (!_omap4_has_clkctrl_clock(oh)) return 0; return omap_cm_wait_module_idle(oh->clkdm->prcm_partition, @@ -1071,215 +1102,6 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh) } /** - * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh - * @oh: struct omap_hwmod *oh - * - * Count and return the number of MPU IRQs associated with the hwmod - * @oh. Used to allocate struct resource data. Returns 0 if @oh is - * NULL. - */ -static int _count_mpu_irqs(struct omap_hwmod *oh) -{ - struct omap_hwmod_irq_info *ohii; - int i = 0; - - if (!oh || !oh->mpu_irqs) - return 0; - - do { - ohii = &oh->mpu_irqs[i++]; - } while (ohii->irq != -1); - - return i-1; -} - -/** - * _count_sdma_reqs - count the number of SDMA request lines associated with @oh - * @oh: struct omap_hwmod *oh - * - * Count and return the number of SDMA request lines associated with - * the hwmod @oh. Used to allocate struct resource data. Returns 0 - * if @oh is NULL. - */ -static int _count_sdma_reqs(struct omap_hwmod *oh) -{ - struct omap_hwmod_dma_info *ohdi; - int i = 0; - - if (!oh || !oh->sdma_reqs) - return 0; - - do { - ohdi = &oh->sdma_reqs[i++]; - } while (ohdi->dma_req != -1); - - return i-1; -} - -/** - * _count_ocp_if_addr_spaces - count the number of address space entries for @oh - * @oh: struct omap_hwmod *oh - * - * Count and return the number of address space ranges associated with - * the hwmod @oh. Used to allocate struct resource data. Returns 0 - * if @oh is NULL. - */ -static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) -{ - struct omap_hwmod_addr_space *mem; - int i = 0; - - if (!os || !os->addr) - return 0; - - do { - mem = &os->addr[i++]; - } while (mem->pa_start != mem->pa_end); - - return i-1; -} - -/** - * _get_mpu_irq_by_name - fetch MPU interrupt line number by name - * @oh: struct omap_hwmod * to operate on - * @name: pointer to the name of the MPU interrupt number to fetch (optional) - * @irq: pointer to an unsigned int to store the MPU IRQ number to - * - * Retrieve a MPU hardware IRQ line number named by @name associated - * with the IP block pointed to by @oh. The IRQ number will be filled - * into the address pointed to by @dma. When @name is non-null, the - * IRQ line number associated with the named entry will be returned. - * If @name is null, the first matching entry will be returned. Data - * order is not meaningful in hwmod data, so callers are strongly - * encouraged to use a non-null @name whenever possible to avoid - * unpredictable effects if hwmod data is later added that causes data - * ordering to change. Returns 0 upon success or a negative error - * code upon error. - */ -static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, - unsigned int *irq) -{ - int i; - bool found = false; - - if (!oh->mpu_irqs) - return -ENOENT; - - i = 0; - while (oh->mpu_irqs[i].irq != -1) { - if (name == oh->mpu_irqs[i].name || - !strcmp(name, oh->mpu_irqs[i].name)) { - found = true; - break; - } - i++; - } - - if (!found) - return -ENOENT; - - *irq = oh->mpu_irqs[i].irq; - - return 0; -} - -/** - * _get_sdma_req_by_name - fetch SDMA request line ID by name - * @oh: struct omap_hwmod * to operate on - * @name: pointer to the name of the SDMA request line to fetch (optional) - * @dma: pointer to an unsigned int to store the request line ID to - * - * Retrieve an SDMA request line ID named by @name on the IP block - * pointed to by @oh. The ID will be filled into the address pointed - * to by @dma. When @name is non-null, the request line ID associated - * with the named entry will be returned. If @name is null, the first - * matching entry will be returned. Data order is not meaningful in - * hwmod data, so callers are strongly encouraged to use a non-null - * @name whenever possible to avoid unpredictable effects if hwmod - * data is later added that causes data ordering to change. Returns 0 - * upon success or a negative error code upon error. - */ -static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, - unsigned int *dma) -{ - int i; - bool found = false; - - if (!oh->sdma_reqs) - return -ENOENT; - - i = 0; - while (oh->sdma_reqs[i].dma_req != -1) { - if (name == oh->sdma_reqs[i].name || - !strcmp(name, oh->sdma_reqs[i].name)) { - found = true; - break; - } - i++; - } - - if (!found) - return -ENOENT; - - *dma = oh->sdma_reqs[i].dma_req; - - return 0; -} - -/** - * _get_addr_space_by_name - fetch address space start & end by name - * @oh: struct omap_hwmod * to operate on - * @name: pointer to the name of the address space to fetch (optional) - * @pa_start: pointer to a u32 to store the starting address to - * @pa_end: pointer to a u32 to store the ending address to - * - * Retrieve address space start and end addresses for the IP block - * pointed to by @oh. The data will be filled into the addresses - * pointed to by @pa_start and @pa_end. When @name is non-null, the - * address space data associated with the named entry will be - * returned. If @name is null, the first matching entry will be - * returned. Data order is not meaningful in hwmod data, so callers - * are strongly encouraged to use a non-null @name whenever possible - * to avoid unpredictable effects if hwmod data is later added that - * causes data ordering to change. Returns 0 upon success or a - * negative error code upon error. - */ -static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, - u32 *pa_start, u32 *pa_end) -{ - int j; - struct omap_hwmod_ocp_if *os; - bool found = false; - - list_for_each_entry(os, &oh->slave_ports, node) { - - if (!os->addr) - return -ENOENT; - - j = 0; - while (os->addr[j].pa_start != os->addr[j].pa_end) { - if (name == os->addr[j].name || - !strcmp(name, os->addr[j].name)) { - found = true; - break; - } - j++; - } - - if (found) - break; - } - - if (!found) - return -ENOENT; - - *pa_start = os->addr[j].pa_start; - *pa_end = os->addr[j].pa_end; - - return 0; -} - -/** * _save_mpu_port_index - find and save the index to @oh's MPU port * @oh: struct omap_hwmod * * @@ -1330,32 +1152,6 @@ static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) }; /** - * _find_mpu_rt_addr_space - return MPU register target address space for @oh - * @oh: struct omap_hwmod * - * - * Returns a pointer to the struct omap_hwmod_addr_space record representing - * the register target MPU address space; or returns NULL upon error. - */ -static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) -{ - struct omap_hwmod_ocp_if *os; - struct omap_hwmod_addr_space *mem; - int found = 0, i = 0; - - os = _find_mpu_rt_port(oh); - if (!os || !os->addr) - return NULL; - - do { - mem = &os->addr[i++]; - if (mem->flags & ADDR_TYPE_RT) - found = 1; - } while (!found && mem->pa_start != mem->pa_end); - - return (found) ? mem : NULL; -} - -/** * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * @@ -1847,7 +1643,8 @@ static int _omap4_disable_module(struct omap_hwmod *oh) { int v; - if (!oh->clkdm || !oh->prcm.omap4.modulemode) + if (!oh->clkdm || !oh->prcm.omap4.modulemode || + _omap4_clkctrl_managed_by_clkfwk(oh)) return -EINVAL; /* @@ -2362,6 +2159,75 @@ static int of_dev_hwmod_lookup(struct device_node *np, } /** + * omap_hwmod_parse_module_range - map module IO range from device tree + * @oh: struct omap_hwmod * + * @np: struct device_node * + * + * Parse the device tree range an interconnect target module provides + * for it's child device IP blocks. This way we can support the old + * "ti,hwmods" property with just dts data without a need for platform + * data for IO resources. And we don't need all the child IP device + * nodes available in the dts. + */ +int omap_hwmod_parse_module_range(struct omap_hwmod *oh, + struct device_node *np, + struct resource *res) +{ + struct property *prop; + const __be32 *ranges; + const char *name; + u32 nr_addr, nr_size; + u64 base, size; + int len, error; + + if (!res) + return -EINVAL; + + ranges = of_get_property(np, "ranges", &len); + if (!ranges) + return -ENOENT; + + len /= sizeof(*ranges); + + if (len < 3) + return -EINVAL; + + of_property_for_each_string(np, "compatible", prop, name) + if (!strncmp("ti,sysc-", name, 8)) + break; + + if (!name) + return -ENOENT; + + error = of_property_read_u32(np, "#address-cells", &nr_addr); + if (error) + return -ENOENT; + + error = of_property_read_u32(np, "#size-cells", &nr_size); + if (error) + return -ENOENT; + + if (nr_addr != 1 || nr_size != 1) { + pr_err("%s: invalid range for %s->%s\n", __func__, + oh->name, np->name); + return -EINVAL; + } + + ranges++; + base = of_translate_address(np, ranges++); + size = be32_to_cpup(ranges); + + pr_debug("omap_hwmod: %s %s at 0x%llx size 0x%llx\n", + oh->name, np->name, base, size); + + res->start = base; + res->end = base + size - 1; + res->flags = IORESOURCE_MEM; + + return 0; +} + +/** * _init_mpu_rt_base - populate the virtual address for a hwmod * @oh: struct omap_hwmod * to locate the virtual address * @data: (unused, caller should pass NULL) @@ -2381,8 +2247,9 @@ static int of_dev_hwmod_lookup(struct device_node *np, static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, int index, struct device_node *np) { - struct omap_hwmod_addr_space *mem; void __iomem *va_start = NULL; + struct resource res; + int error; if (!oh) return -EINVAL; @@ -2397,28 +2264,22 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, if (oh->_int_flags & _HWMOD_NO_MPU_PORT) return -ENXIO; - mem = _find_mpu_rt_addr_space(oh); - if (!mem) { - pr_debug("omap_hwmod: %s: no MPU register target found\n", - oh->name); + if (!np) { + pr_err("omap_hwmod: %s: no dt node\n", oh->name); + return -ENXIO; + } - /* Extract the IO space from device tree blob */ - if (!np) { - pr_err("omap_hwmod: %s: no dt node\n", oh->name); - return -ENXIO; - } + /* Do we have a dts range for the interconnect target module? */ + error = omap_hwmod_parse_module_range(oh, np, &res); + if (!error) + va_start = ioremap(res.start, resource_size(&res)); + /* No ranges, rely on device reg entry */ + if (!va_start) va_start = of_iomap(np, index + oh->mpu_rt_idx); - } else { - va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); - } - if (!va_start) { - if (mem) - pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); - else - pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n", - oh->name, index, np); + pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n", + oh->name, index, np); return -ENXIO; } @@ -2829,8 +2690,10 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh) if (!_find_mpu_rt_port(oh)) return 0; - if (!oh->prcm.omap4.clkctrl_offs && - !(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET)) + if (_omap4_clkctrl_managed_by_clkfwk(oh)) + return 0; + + if (!_omap4_has_clkctrl_clock(oh)) return 0; /* XXX check module SIDLEMODE, hardreset status */ @@ -2986,8 +2849,7 @@ static int _omap4_disable_direct_prcm(struct omap_hwmod *oh) if (!oh) return -EINVAL; - oh->prcm.omap4.clkctrl_offs = 0; - oh->prcm.omap4.modulemode = 0; + oh->prcm.omap4.flags |= HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK; return 0; } @@ -3322,189 +3184,6 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) */ /** - * omap_hwmod_count_resources - count number of struct resources needed by hwmod - * @oh: struct omap_hwmod * - * @flags: Type of resources to include when counting (IRQ/DMA/MEM) - * - * Count the number of struct resource array elements necessary to - * contain omap_hwmod @oh resources. Intended to be called by code - * that registers omap_devices. Intended to be used to determine the - * size of a dynamically-allocated struct resource array, before - * calling omap_hwmod_fill_resources(). Returns the number of struct - * resource array elements needed. - * - * XXX This code is not optimized. It could attempt to merge adjacent - * resource IDs. - * - */ -int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags) -{ - int ret = 0; - - if (flags & IORESOURCE_IRQ) - ret += _count_mpu_irqs(oh); - - if (flags & IORESOURCE_DMA) - ret += _count_sdma_reqs(oh); - - if (flags & IORESOURCE_MEM) { - struct omap_hwmod_ocp_if *os; - - list_for_each_entry(os, &oh->slave_ports, node) - ret += _count_ocp_if_addr_spaces(os); - } - - return ret; -} - -/** - * omap_hwmod_fill_resources - fill struct resource array with hwmod data - * @oh: struct omap_hwmod * - * @res: pointer to the first element of an array of struct resource to fill - * - * Fill the struct resource array @res with resource data from the - * omap_hwmod @oh. Intended to be called by code that registers - * omap_devices. See also omap_hwmod_count_resources(). Returns the - * number of array elements filled. - */ -int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) -{ - struct omap_hwmod_ocp_if *os; - int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; - int r = 0; - - /* For each IRQ, DMA, memory area, fill in array.*/ - - mpu_irqs_cnt = _count_mpu_irqs(oh); - for (i = 0; i < mpu_irqs_cnt; i++) { - unsigned int irq; - - if (oh->xlate_irq) - irq = oh->xlate_irq((oh->mpu_irqs + i)->irq); - else - irq = (oh->mpu_irqs + i)->irq; - (res + r)->name = (oh->mpu_irqs + i)->name; - (res + r)->start = irq; - (res + r)->end = irq; - (res + r)->flags = IORESOURCE_IRQ; - r++; - } - - sdma_reqs_cnt = _count_sdma_reqs(oh); - for (i = 0; i < sdma_reqs_cnt; i++) { - (res + r)->name = (oh->sdma_reqs + i)->name; - (res + r)->start = (oh->sdma_reqs + i)->dma_req; - (res + r)->end = (oh->sdma_reqs + i)->dma_req; - (res + r)->flags = IORESOURCE_DMA; - r++; - } - - list_for_each_entry(os, &oh->slave_ports, node) { - addr_cnt = _count_ocp_if_addr_spaces(os); - - for (j = 0; j < addr_cnt; j++) { - (res + r)->name = (os->addr + j)->name; - (res + r)->start = (os->addr + j)->pa_start; - (res + r)->end = (os->addr + j)->pa_end; - (res + r)->flags = IORESOURCE_MEM; - r++; - } - } - - return r; -} - -/** - * omap_hwmod_fill_dma_resources - fill struct resource array with dma data - * @oh: struct omap_hwmod * - * @res: pointer to the array of struct resource to fill - * - * Fill the struct resource array @res with dma resource data from the - * omap_hwmod @oh. Intended to be called by code that registers - * omap_devices. See also omap_hwmod_count_resources(). Returns the - * number of array elements filled. - */ -int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) -{ - int i, sdma_reqs_cnt; - int r = 0; - - sdma_reqs_cnt = _count_sdma_reqs(oh); - for (i = 0; i < sdma_reqs_cnt; i++) { - (res + r)->name = (oh->sdma_reqs + i)->name; - (res + r)->start = (oh->sdma_reqs + i)->dma_req; - (res + r)->end = (oh->sdma_reqs + i)->dma_req; - (res + r)->flags = IORESOURCE_DMA; - r++; - } - - return r; -} - -/** - * omap_hwmod_get_resource_byname - fetch IP block integration data by name - * @oh: struct omap_hwmod * to operate on - * @type: one of the IORESOURCE_* constants from include/linux/ioport.h - * @name: pointer to the name of the data to fetch (optional) - * @rsrc: pointer to a struct resource, allocated by the caller - * - * Retrieve MPU IRQ, SDMA request line, or address space start/end - * data for the IP block pointed to by @oh. The data will be filled - * into a struct resource record pointed to by @rsrc. The struct - * resource must be allocated by the caller. When @name is non-null, - * the data associated with the matching entry in the IRQ/SDMA/address - * space hwmod data arrays will be returned. If @name is null, the - * first array entry will be returned. Data order is not meaningful - * in hwmod data, so callers are strongly encouraged to use a non-null - * @name whenever possible to avoid unpredictable effects if hwmod - * data is later added that causes data ordering to change. This - * function is only intended for use by OMAP core code. Device - * drivers should not call this function - the appropriate bus-related - * data accessor functions should be used instead. Returns 0 upon - * success or a negative error code upon error. - */ -int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, - const char *name, struct resource *rsrc) -{ - int r; - unsigned int irq, dma; - u32 pa_start, pa_end; - - if (!oh || !rsrc) - return -EINVAL; - - if (type == IORESOURCE_IRQ) { - r = _get_mpu_irq_by_name(oh, name, &irq); - if (r) - return r; - - rsrc->start = irq; - rsrc->end = irq; - } else if (type == IORESOURCE_DMA) { - r = _get_sdma_req_by_name(oh, name, &dma); - if (r) - return r; - - rsrc->start = dma; - rsrc->end = dma; - } else if (type == IORESOURCE_MEM) { - r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); - if (r) - return r; - - rsrc->start = pa_start; - rsrc->end = pa_end; - } else { - return -EINVAL; - } - - rsrc->flags = type; - rsrc->name = name; - - return 0; -} - -/** * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain * @oh: struct omap_hwmod * * diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index a8f779381fd8..df2239a58555 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -21,7 +21,6 @@ * * To do: * - add interconnect error log structures - * - add pinmuxing * - init_conn_id_bit (CONNID_BIT_VECTOR) * - implement default hwmod SMS/SDRC flags? * - move Linux-specific data ("non-ROM data") out @@ -151,50 +150,6 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; #endif /** - * struct omap_hwmod_mux_info - hwmod specific mux configuration - * @pads: array of omap_device_pad entries - * @nr_pads: number of omap_device_pad entries - * - * Note that this is currently built during init as needed. - */ -struct omap_hwmod_mux_info { - int nr_pads; - struct omap_device_pad *pads; - int nr_pads_dynamic; - struct omap_device_pad **pads_dynamic; - int *irqs; - bool enabled; -}; - -/** - * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod - * @name: name of the IRQ channel (module local name) - * @irq: IRQ channel ID (should be non-negative except -1 = terminator) - * - * @name should be something short, e.g., "tx" or "rx". It is for use - * by platform_get_resource_byname(). It is defined locally to the - * hwmod. - */ -struct omap_hwmod_irq_info { - const char *name; - s16 irq; -}; - -/** - * struct omap_hwmod_dma_info - DMA channels used by the hwmod - * @name: name of the DMA channel (module local name) - * @dma_req: DMA request ID (should be non-negative except -1 = terminator) - * - * @name should be something short, e.g., "tx" or "rx". It is for use - * by platform_get_resource_byname(). It is defined locally to the - * hwmod. - */ -struct omap_hwmod_dma_info { - const char *name; - s16 dma_req; -}; - -/** * struct omap_hwmod_rst_info - IPs reset lines use by hwmod * @name: name of the reset line (module local name) * @rst_shift: Offset of the reset bit @@ -243,34 +198,6 @@ struct omap_hwmod_omap2_firewall { u8 flags; }; - -/* - * omap_hwmod_addr_space.flags bits - * - * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init. - * ADDR_TYPE_RT: Address space contains module register target data. - */ -#define ADDR_MAP_ON_INIT (1 << 0) /* XXX does not belong */ -#define ADDR_TYPE_RT (1 << 1) - -/** - * struct omap_hwmod_addr_space - address space handled by the hwmod - * @name: name of the address space - * @pa_start: starting physical address - * @pa_end: ending physical address - * @flags: (see omap_hwmod_addr_space.flags macros above) - * - * Address space doesn't necessarily follow physical interconnect - * structure. GPMC is one example. - */ -struct omap_hwmod_addr_space { - const char *name; - u32 pa_start; - u32 pa_end; - u8 flags; -}; - - /* * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this * interface to interact with the hwmod. Used to add sleep dependencies @@ -446,9 +373,12 @@ struct omap_hwmod_omap2_prcm { * HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL * offset of zero; this flag bit should be set in those cases to * distinguish from hwmods that have no clkctrl offset. + * HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK: Module clockctrl clock is managed + * by the common clock framework and not hwmod. */ #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0) #define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET (1 << 1) +#define HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK (1 << 2) /** * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data @@ -626,8 +556,6 @@ struct omap_hwmod_class { * @name: name of the hwmod * @class: struct omap_hwmod_class * to the class of this hwmod * @od: struct omap_device currently associated with this hwmod (internal use) - * @mpu_irqs: ptr to an array of MPU IRQs - * @sdma_reqs: ptr to an array of System DMA request IDs * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name * @_clk: pointer to the main struct clk (filled in at runtime) @@ -670,9 +598,6 @@ struct omap_hwmod { const char *name; struct omap_hwmod_class *class; struct omap_device *od; - struct omap_hwmod_mux_info *mux; - struct omap_hwmod_irq_info *mpu_irqs; - struct omap_hwmod_dma_info *sdma_reqs; struct omap_hwmod_rst_info *rst_lines; union { struct omap_hwmod_omap2_prcm omap2; @@ -691,7 +616,6 @@ struct omap_hwmod { struct lock_class_key hwmod_key; /* unique lock class */ struct list_head node; struct omap_hwmod_ocp_if *_mpu_port; - unsigned int (*xlate_irq)(unsigned int); u32 flags; u8 mpu_rt_idx; u8 response_lat; @@ -705,11 +629,16 @@ struct omap_hwmod { struct omap_hwmod *parent_hwmod; }; +struct device_node; + struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); int __init omap_hwmod_setup_one(const char *name); +int omap_hwmod_parse_module_range(struct omap_hwmod *oh, + struct device_node *np, + struct resource *res); int omap_hwmod_enable(struct omap_hwmod *oh); int omap_hwmod_idle(struct omap_hwmod *oh); @@ -724,7 +653,6 @@ int omap_hwmod_softreset(struct omap_hwmod *oh); int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); -int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res); int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, const char *name, struct resource *res); diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 65b1647092bd..1a15a347945a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -155,7 +155,6 @@ static struct omap_dma_dev_attr dma_dev_attr = { static struct omap_hwmod omap2420_dma_system_hwmod = { .name = "dma", .class = &omap2xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, .main_clk = "core_l3_ck", .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, @@ -371,7 +370,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_dma_system_hwmod, .clk = "sdma_ick", - .addr = omap2_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 79127b35fe60..3801850bccec 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -153,7 +153,6 @@ static struct omap_dma_dev_attr dma_dev_attr = { static struct omap_hwmod omap2430_dma_system_hwmod = { .name = "dma", .class = &omap2xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, .main_clk = "core_l3_ck", .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, @@ -572,7 +571,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { .master = &omap2xxx_l4_core_hwmod, .slave = &omap2430_dma_system_hwmod, .clk = "sdma_ick", - .addr = omap2_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c deleted file mode 100644 index 6d2e32462df9..000000000000 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3 - * - * Copyright (C) 2009-2011 Nokia Corporation - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * XXX handle crossbar/shared link difference for L3? - * XXX these should be marked initdata for multi-OMAP kernels - */ -#include <asm/sizes.h> - -#include "omap_hwmod.h" - -#include "omap_hwmod_common_data.h" - -struct omap_hwmod_addr_space omap2_dma_system_addrs[] = { - { - .pa_start = 0x48056000, - .pa_end = 0x48056000 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { }, -}; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index cfaeb0f78cc8..28665d29f23f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -65,21 +65,6 @@ struct omap_hwmod_class iva_hwmod_class = { .name = "iva", }; -/* Common MPU IRQ line data */ - -struct omap_hwmod_irq_info omap2_dispc_irqs[] = { - { .irq = 25 + OMAP_INTC_START, }, - { .irq = -1, }, -}; - -struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { - { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */ - { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ - { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ - { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ - { .irq = -1, }, -}; - struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { .rev_offs = 0x0, .sysc_offs = 0x14, diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index d190f1ad97b7..beec4cd617b1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -20,11 +20,6 @@ #include "prm-regbits-24xx.h" #include "wd_timer.h" -static struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { - { .name = "dispc", .dma_req = 5 }, - { .dma_req = -1, }, -}; - /* * 'dispc' class * display controller @@ -550,7 +545,6 @@ struct omap_hwmod omap2xxx_dss_core_hwmod = { .name = "dss_core", .class = &omap2_dss_hwmod_class, .main_clk = "dss1_fck", /* instead of dss_fck */ - .sdma_reqs = omap2xxx_dss_sdma_chs, .prcm = { .omap2 = { .prcm_reg_id = 1, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index 8236e5c49ec3..e0001232bb4f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -159,54 +159,24 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { - { - .pa_start = 0x48300000, - .pa_end = 0x48300000 + SZ_16 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_epwmss0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_epwmss0_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { - { - .pa_start = 0x48302000, - .pa_end = 0x48302000 + SZ_16 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_epwmss1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_epwmss1_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { - { - .pa_start = 0x48304000, - .pa_end = 0x48304000 + SZ_16 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_epwmss2_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_epwmss2_addr_space, .user = OCP_USER_MPU, }; @@ -250,92 +220,42 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { }; /* l4 ls -> mcasp0 */ -static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { - { - .pa_start = 0x48038000, - .pa_end = 0x48038000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mcasp0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mcasp0_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> mcasp1 */ -static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { - { - .pa_start = 0x4803C000, - .pa_end = 0x4803C000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mcasp1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mcasp1_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> mmc0 */ -static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { - { - .pa_start = 0x48060100, - .pa_end = 0x48060100 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mmc0_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mmc0_addr_space, .user = OCP_USER_MPU, }; /* l4 ls -> mmc1 */ -static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { - { - .pa_start = 0x481d8100, - .pa_end = 0x481d8100 + SZ_4K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { .master = &am33xx_l4_ls_hwmod, .slave = &am33xx_mmc1_hwmod, .clk = "l4ls_gclk", - .addr = am33xx_mmc1_addr_space, .user = OCP_USER_MPU, }; /* l3 s -> mmc2 */ -static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { - { - .pa_start = 0x47810100, - .pa_end = 0x47810100 + SZ_64K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { .master = &am33xx_l3_s_hwmod, .slave = &am33xx_mmc2_hwmod, .clk = "l3s_gclk", - .addr = am33xx_mmc2_addr_space, .user = OCP_USER_MPU, }; @@ -412,56 +332,26 @@ struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { }; /* l3 main -> tpcc0 */ -static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { - { - .pa_start = 0x49800000, - .pa_end = 0x49800000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_tptc0_hwmod, .clk = "l3_gclk", - .addr = am33xx_tptc0_addr_space, .user = OCP_USER_MPU, }; /* l3 main -> tpcc1 */ -static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { - { - .pa_start = 0x49900000, - .pa_end = 0x49900000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_tptc1_hwmod, .clk = "l3_gclk", - .addr = am33xx_tptc1_addr_space, .user = OCP_USER_MPU, }; /* l3 main -> tpcc2 */ -static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { - { - .pa_start = 0x49a00000, - .pa_end = 0x49a00000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_tptc2_hwmod, .clk = "l3_gclk", - .addr = am33xx_tptc2_addr_space, .user = OCP_USER_MPU, }; @@ -513,38 +403,18 @@ struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { }; /* l3 main -> sha0 HIB2 */ -static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { - { - .pa_start = 0x53100000, - .pa_end = 0x53100000 + SZ_512 - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_sha0_hwmod, .clk = "sha0_fck", - .addr = am33xx_sha0_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* l3 main -> AES0 HIB2 */ -static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { - { - .pa_start = 0x53500000, - .pa_end = 0x53500000 + SZ_1M - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_aes0_hwmod, .clk = "aes0_fck", - .addr = am33xx_aes0_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index de06a1d5ffab..4bcf9f3e1544 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -778,9 +778,9 @@ struct omap_hwmod am33xx_mcasp1_hwmod = { /* 'mmc' class */ static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { - .rev_offs = 0x1fc, - .sysc_offs = 0x10, - .syss_offs = 0x14, + .rev_offs = 0x2fc, + .sysc_offs = 0x110, + .syss_offs = 0x114, .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 6dc51a774a26..4d16b15bb0cf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -320,20 +320,11 @@ static struct omap_hwmod am33xx_usbss_hwmod = { * Interfaces */ -static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { - { - .pa_start = 0x4c000000, - .pa_end = 0x4c000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; /* l3 main -> emif */ static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_emif_hwmod, .clk = "dpll_core_m4_ck", - .addr = am33xx_emif_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -370,20 +361,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { }; /* l3_main -> debugss */ -static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { - { - .pa_start = 0x4b000000, - .pa_end = 0x4b000000 + SZ_16M - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_debugss_hwmod, .clk = "dpll_core_m4_ck", - .addr = am33xx_debugss_addrs, .user = OCP_USER_MPU, }; @@ -428,20 +409,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { }; /* L4 WKUP -> ADC_TSC */ -static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = { - { - .pa_start = 0x44E0D000, - .pa_end = 0x44E0D000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_adc_tsc_hwmod, .clk = "dpll_core_m4_div2_ck", - .addr = am33xx_adc_tsc_addrs, .user = OCP_USER_MPU, }; @@ -452,20 +423,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { - { - .pa_start = 0x4830E000, - .pa_end = 0x4830E000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { .master = &am33xx_l3_main_hwmod, .slave = &am33xx_lcdc_hwmod, .clk = "dpll_core_m4_ck", - .addr = am33xx_lcdc_addr_space, .user = OCP_USER_MPU, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c3276436b0ae..d2106ae4410a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -565,12 +565,6 @@ static struct omap_hwmod_class i2c_class = { .reset = &omap_i2c_reset, }; -static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { - { .name = "dispc", .dma_req = 5 }, - { .name = "dsi1", .dma_req = 74 }, - { .dma_req = -1, }, -}; - /* dss */ static struct omap_hwmod_opt_clk dss_opt_clks[] = { /* @@ -587,7 +581,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { .name = "dss_core", .class = &omap2_dss_hwmod_class, .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .sdma_reqs = omap3xxx_dss_sdma_chs, .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -607,7 +600,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .class = &omap2_dss_hwmod_class, .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ - .sdma_reqs = omap3xxx_dss_sdma_chs, .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -647,7 +639,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = { static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap3_dispc_hwmod_class, - .mpu_irqs = omap2_dispc_irqs, .main_clk = "dss1_alwon_fck", .prcm = { .omap2 = { @@ -1017,7 +1008,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { static struct omap_hwmod omap3xxx_dma_system_hwmod = { .name = "dma", .class = &omap3xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, .main_clk = "core_l3_ick", .prcm = { .omap2 = { @@ -2108,20 +2098,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { }; /* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { - { - .pa_start = OMAP34XX_SR1_BASE, - .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { }, -}; - static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap34xx_sr1_hwmod, .clk = "sr_l4_ick", - .addr = omap3_sr1_addr_space, .user = OCP_USER_MPU, }; @@ -2129,25 +2109,15 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap36xx_sr1_hwmod, .clk = "sr_l4_ick", - .addr = omap3_sr1_addr_space, .user = OCP_USER_MPU, }; -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { - { - .pa_start = OMAP34XX_SR2_BASE, - .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { }, -}; +/* L4 CORE -> SR2 interface */ static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap34xx_sr2_hwmod, .clk = "sr_l4_ick", - .addr = omap3_sr2_addr_space, .user = OCP_USER_MPU, }; @@ -2155,7 +2125,6 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap36xx_sr2_hwmod, .clk = "sr_l4_ick", - .addr = omap3_sr2_addr_space, .user = OCP_USER_MPU, }; @@ -2524,21 +2493,11 @@ static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { - { - .pa_start = 0x48056000, - .pa_end = 0x48056fff, - .flags = ADDR_TYPE_RT, - }, - { }, -}; - /* l4_cfg -> dma_system */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap3xxx_dma_system_hwmod, .clk = "core_l4_ick", - .addr = omap3xxx_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -3148,7 +3107,7 @@ int __init omap3xxx_hwmod_init(void) int r; struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL; struct omap_hwmod_ocp_if **h_aes = NULL; - struct device_node *bus = NULL; + struct device_node *bus; unsigned int rev; omap_hwmod_init(); @@ -3208,18 +3167,14 @@ int __init omap3xxx_hwmod_init(void) if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) { r = omap_hwmod_register_links(h_sham); - if (r < 0) { - of_node_put(bus); - return r; - } + if (r < 0) + goto put_node; } if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) { r = omap_hwmod_register_links(h_aes); - if (r < 0) { - of_node_put(bus); - return r; - } + if (r < 0) + goto put_node; } of_node_put(bus); @@ -3270,4 +3225,8 @@ int __init omap3xxx_hwmod_init(void) r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); return r; + +put_node: + of_node_put(bus); + return r; } diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 3e2d792fd9df..c47709659a54 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -465,20 +465,10 @@ static struct omap_dma_dev_attr dma_dev_attr = { }; /* dma_system */ -static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { - { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, - { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, - { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, - { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap44xx_dma_system_hwmod = { .name = "dma_system", .class = &omap44xx_dma_hwmod_class, .clkdm_name = "l3_dma_clkdm", - .mpu_irqs = omap44xx_dma_system_irqs, - .xlate_irq = omap4_xlate_irq, .main_clk = "l3_div_ck", .prcm = { .omap4 = { @@ -620,16 +610,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { }; /* dss_dispc */ -static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { - { .irq = 25 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { - { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { .manager_count = 3, .has_framedonetv_irq = 1 @@ -639,9 +619,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap44xx_dispc_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .mpu_irqs = omap44xx_dss_dispc_irqs, - .xlate_irq = omap4_xlate_irq, - .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, .main_clk = "dss_dss_clk", .prcm = { .omap4 = { @@ -675,16 +652,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { }; /* dss_dsi1 */ -static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { - { .irq = 53 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { - { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -693,9 +660,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { .name = "dss_dsi1", .class = &omap44xx_dsi_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .mpu_irqs = omap44xx_dss_dsi1_irqs, - .xlate_irq = omap4_xlate_irq, - .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, .main_clk = "dss_dss_clk", .prcm = { .omap4 = { @@ -709,16 +673,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { }; /* dss_dsi2 */ -static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { - { .irq = 84 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { - { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -727,9 +681,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { .name = "dss_dsi2", .class = &omap44xx_dsi_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .mpu_irqs = omap44xx_dss_dsi2_irqs, - .xlate_irq = omap4_xlate_irq, - .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, .main_clk = "dss_dss_clk", .prcm = { .omap4 = { @@ -763,16 +714,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { }; /* dss_hdmi */ -static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { - { .irq = 101 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - -static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { - { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, @@ -787,9 +728,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { * set idle mode by software. */ .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED, - .mpu_irqs = omap44xx_dss_hdmi_irqs, - .xlate_irq = omap4_xlate_irq, - .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, .main_clk = "dss_48mhz_clk", .prcm = { .omap4 = { @@ -823,11 +761,6 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { }; /* dss_rfbi */ -static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { - { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "l3_div_ck" }, }; @@ -836,7 +769,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { .name = "dss_rfbi", .class = &omap44xx_rfbi_hwmod_class, .clkdm_name = "l3_dss_clkdm", - .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, .main_clk = "dss_dss_clk", .prcm = { .omap4 = { @@ -1936,19 +1868,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { }; /* mcspi1 */ -static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { - { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, - { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, - { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, - { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, - { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, - { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, - { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, - { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - -/* mcspi1 dev_attr */ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { .num_chipselect = 4, }; @@ -1957,7 +1876,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .name = "mcspi1", .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", - .sdma_reqs = omap44xx_mcspi1_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -1970,15 +1888,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { }; /* mcspi2 */ -static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { - { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, - { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, - { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, - { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - -/* mcspi2 dev_attr */ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { .num_chipselect = 2, }; @@ -1987,7 +1896,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .name = "mcspi2", .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", - .sdma_reqs = omap44xx_mcspi2_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -2000,15 +1908,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { }; /* mcspi3 */ -static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { - { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, - { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, - { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, - { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - -/* mcspi3 dev_attr */ static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { .num_chipselect = 2, }; @@ -2017,7 +1916,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .name = "mcspi3", .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", - .sdma_reqs = omap44xx_mcspi3_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -2030,13 +1928,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { }; /* mcspi4 */ -static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { - { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, - { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - -/* mcspi4 dev_attr */ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { .num_chipselect = 1, }; @@ -2045,7 +1936,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .name = "mcspi4", .class = &omap44xx_mcspi_hwmod_class, .clkdm_name = "l4_per_clkdm", - .sdma_reqs = omap44xx_mcspi4_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -2080,13 +1970,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { }; /* mmc1 */ -static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { - { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - -/* mmc1 dev_attr */ static struct omap_hsmmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; @@ -2095,7 +1978,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { .name = "mmc1", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l3_init_clkdm", - .sdma_reqs = omap44xx_mmc1_sdma_reqs, .main_clk = "hsmmc1_fclk", .prcm = { .omap4 = { @@ -2108,17 +1990,10 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { }; /* mmc2 */ -static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { - { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_mmc2_hwmod = { .name = "mmc2", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l3_init_clkdm", - .sdma_reqs = omap44xx_mmc2_sdma_reqs, .main_clk = "hsmmc2_fclk", .prcm = { .omap4 = { @@ -2130,17 +2005,10 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { }; /* mmc3 */ -static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { - { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_mmc3_hwmod = { .name = "mmc3", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", - .sdma_reqs = omap44xx_mmc3_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -2152,17 +2020,10 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { }; /* mmc4 */ -static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { - { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_mmc4_hwmod = { .name = "mmc4", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", - .sdma_reqs = omap44xx_mmc4_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -2174,17 +2035,10 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { }; /* mmc5 */ -static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { - { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, - { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod omap44xx_mmc5_hwmod = { .name = "mmc5", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", - .sdma_reqs = omap44xx_mmc5_sdma_reqs, .main_clk = "func_48m_fclk", .prcm = { .omap4 = { @@ -3538,81 +3392,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { - { - .name = "dmem", - .pa_start = 0x40180000, - .pa_end = 0x4018ffff - }, - { - .name = "cmem", - .pa_start = 0x401a0000, - .pa_end = 0x401a1fff - }, - { - .name = "smem", - .pa_start = 0x401c0000, - .pa_end = 0x401c5fff - }, - { - .name = "pmem", - .pa_start = 0x401e0000, - .pa_end = 0x401e1fff - }, - { - .name = "mpu", - .pa_start = 0x401f1000, - .pa_end = 0x401f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> aess */ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_aess_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { - { - .name = "dmem_dma", - .pa_start = 0x49080000, - .pa_end = 0x4908ffff - }, - { - .name = "cmem_dma", - .pa_start = 0x490a0000, - .pa_end = 0x490a1fff - }, - { - .name = "smem_dma", - .pa_start = 0x490c0000, - .pa_end = 0x490c5fff - }, - { - .name = "pmem_dma", - .pa_start = 0x490e0000, - .pa_end = 0x490e1fff - }, - { - .name = "dma", - .pa_start = 0x490f1000, - .pa_end = 0x490f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> aess (dma) */ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_aess_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_dma_addrs, .user = OCP_USER_SDMA, }; @@ -3632,75 +3424,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { - { - .pa_start = 0x4a002000, - .pa_end = 0x4a0027ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> ctrl_module_core */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_ctrl_module_core_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_ctrl_module_core_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { - { - .pa_start = 0x4a100000, - .pa_end = 0x4a1007ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> ctrl_module_pad_core */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_ctrl_module_pad_core_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_ctrl_module_pad_core_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { - { - .pa_start = 0x4a30c000, - .pa_end = 0x4a30c7ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> ctrl_module_wkup */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_ctrl_module_wkup_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_ctrl_module_wkup_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { - { - .pa_start = 0x4a31e000, - .pa_end = 0x4a31e7ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_wkup -> ctrl_module_pad_wkup */ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_ctrl_module_pad_wkup_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -3712,21 +3464,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { - { - .pa_start = 0x4a056000, - .pa_end = 0x4a056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> dma_system */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_dma_system_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -3762,255 +3504,115 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { - { - .pa_start = 0x58000000, - .pa_end = 0x5800007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> dss */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_dss_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { - { - .pa_start = 0x48040000, - .pa_end = 0x4804007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> dss */ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_dss_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_dss_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { - { - .pa_start = 0x58001000, - .pa_end = 0x58001fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> dss_dispc */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_dispc_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_dss_dispc_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { - { - .pa_start = 0x48041000, - .pa_end = 0x48041fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> dss_dispc */ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_dss_dispc_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_dss_dispc_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { - { - .pa_start = 0x58004000, - .pa_end = 0x580041ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> dss_dsi1 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_dsi1_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_dss_dsi1_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { - { - .pa_start = 0x48044000, - .pa_end = 0x480441ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> dss_dsi1 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_dss_dsi1_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi1_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { - { - .pa_start = 0x58005000, - .pa_end = 0x580051ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> dss_dsi2 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_dsi2_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_dss_dsi2_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { - { - .pa_start = 0x48045000, - .pa_end = 0x480451ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> dss_dsi2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_dss_dsi2_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi2_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { - { - .pa_start = 0x58006000, - .pa_end = 0x58006fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> dss_hdmi */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_hdmi_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_dss_hdmi_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { - { - .pa_start = 0x48046000, - .pa_end = 0x48046fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> dss_hdmi */ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_dss_hdmi_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_dss_hdmi_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { - { - .pa_start = 0x58002000, - .pa_end = 0x580020ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> dss_rfbi */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_rfbi_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_dss_rfbi_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { - { - .pa_start = 0x48042000, - .pa_end = 0x480420ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> dss_rfbi */ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_dss_rfbi_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_dss_rfbi_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { - { - .pa_start = 0x58003000, - .pa_end = 0x580030ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> dss_venc */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_dss_venc_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_dss_venc_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { - { - .pa_start = 0x48043000, - .pa_end = 0x480430ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> dss_venc */ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_dss_venc_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_dss_venc_addrs, .user = OCP_USER_MPU, }; @@ -4030,21 +3632,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { - { - .pa_start = 0x4a10a000, - .pa_end = 0x4a10a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> fdif */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_fdif_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_fdif_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -4104,57 +3696,27 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { - { - .pa_start = 0x56000000, - .pa_end = 0x5600ffff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> gpu */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_gpu_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_gpu_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { - { - .pa_start = 0x480b2000, - .pa_end = 0x480b201f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> hdq1w */ static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_hdq1w_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_hdq1w_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { - { - .pa_start = 0x4a058000, - .pa_end = 0x4a05bfff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> hsi */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_hsi_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_hsi_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -4198,21 +3760,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { - { - .pa_start = 0x52000000, - .pa_end = 0x520000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l3_main_2 -> iss */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_iss_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_iss_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -4248,39 +3800,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { - { - .pa_start = 0x40128000, - .pa_end = 0x401283ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcasp */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcasp_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcasp_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { - { - .pa_start = 0x49028000, - .pa_end = 0x490283ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> mcasp (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_mcasp_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_mcasp_dma_addrs, .user = OCP_USER_SDMA, }; @@ -4460,111 +3992,51 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { - { - .pa_start = 0x4012c000, - .pa_end = 0x4012c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> slimbus1 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_slimbus1_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_slimbus1_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { - { - .pa_start = 0x4902c000, - .pa_end = 0x4902c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> slimbus1 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_slimbus1_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_slimbus1_dma_addrs, .user = OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { - { - .pa_start = 0x48076000, - .pa_end = 0x480763ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per -> slimbus2 */ static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_slimbus2_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_slimbus2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { - { - .pa_start = 0x4a0dd000, - .pa_end = 0x4a0dd03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> smartreflex_core */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_smartreflex_core_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_core_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { - { - .pa_start = 0x4a0db000, - .pa_end = 0x4a0db03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> smartreflex_iva */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_smartreflex_iva_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_iva_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { - { - .pa_start = 0x4a0d9000, - .pa_end = 0x4a0d903f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> smartreflex_mpu */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_smartreflex_mpu_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_mpu_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -4736,39 +4208,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { - { - .pa_start = 0x40130000, - .pa_end = 0x4013007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> wd_timer3 */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_wd_timer3_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { - { - .pa_start = 0x49030000, - .pa_end = 0x4903007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_abe -> wd_timer3 (dma) */ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { .master = &omap44xx_l4_abe_hwmod, .slave = &omap44xx_wd_timer3_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_dma_addrs, .user = OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 9a67f013ebad..988e7eaa1330 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -275,20 +275,10 @@ static struct omap_dma_dev_attr dma_dev_attr = { }; /* dma_system */ -static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = { - { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START }, - { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START }, - { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START }, - { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START }, - { .irq = -1 } -}; - static struct omap_hwmod omap54xx_dma_system_hwmod = { .name = "dma_system", .class = &omap54xx_dma_hwmod_class, .clkdm_name = "dma_clkdm", - .mpu_irqs = omap54xx_dma_system_irqs, - .xlate_irq = omap4_xlate_irq, .main_clk = "l3_iclk_div", .prcm = { .omap4 = { @@ -2255,21 +2245,11 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = { - { - .pa_start = 0x4a056000, - .pa_end = 0x4a056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> dma_system */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = { .master = &omap54xx_l4_cfg_hwmod, .slave = &omap54xx_dma_system_hwmod, .clk = "l4_root_clk_div", - .addr = omap54xx_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 2f4f7002f38d..d05e553d6346 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -572,11 +572,6 @@ static struct omap_hwmod_class dra7xx_dss_hwmod_class = { }; /* dss */ -static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = { - { .dma_req = 75 + DRA7XX_DMA_REQ_START }, - { .dma_req = -1 } -}; - static struct omap_hwmod_opt_clk dss_opt_clks[] = { { .role = "dss_clk", .clk = "dss_dss_clk" }, { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" }, @@ -592,7 +587,6 @@ static struct omap_hwmod dra7xx_dss_hwmod = { .class = &dra7xx_dss_hwmod_class, .clkdm_name = "dss_clkdm", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .sdma_reqs = dra7xx_dss_sdma_reqs, .main_clk = "dss_dss_clk", .prcm = { .omap4 = { @@ -2995,21 +2989,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = { - { - .pa_start = 0x4a056000, - .pa_end = 0x4a056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> dma_system */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = { .master = &dra7xx_l4_cfg_hwmod, .slave = &dra7xx_dma_system_hwmod, .clk = "l3_iclk_div", - .addr = dra7xx_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -3253,21 +3237,11 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = { - { - .pa_start = 0x480b2000, - .pa_end = 0x480b201f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_per1 -> hdq1w */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = { .master = &dra7xx_l4_per1_hwmod, .slave = &dra7xx_hdq1w_hwmod, .clk = "l3_iclk_div", - .addr = dra7xx_hdq1w_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -3551,58 +3525,27 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { - { - .name = "sysc", - .pa_start = 0x4a141100, - .pa_end = 0x4a141107, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> sata */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { .master = &dra7xx_l4_cfg_hwmod, .slave = &dra7xx_sata_hwmod, .clk = "l3_iclk_div", - .addr = dra7xx_sata_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = { - { - .pa_start = 0x4a0dd000, - .pa_end = 0x4a0dd07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> smartreflex_core */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = { .master = &dra7xx_l4_cfg_hwmod, .slave = &dra7xx_smartreflex_core_hwmod, .clk = "l4_root_clk_div", - .addr = dra7xx_smartreflex_core_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = { - { - .pa_start = 0x4a0d9000, - .pa_end = 0x4a0d907f, - .flags = ADDR_TYPE_RT - }, - { } -}; - /* l4_cfg -> smartreflex_mpu */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = { .master = &dra7xx_l4_cfg_hwmod, .slave = &dra7xx_smartreflex_mpu_hwmod, .clk = "l4_root_clk_div", - .addr = dra7xx_smartreflex_mpu_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 310afe474ec4..77a515b11ec2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -1260,15 +1260,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = { - { - .pa_start = 0x49800000, - .pa_end = 0x49800000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { }, -}; - static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { .name = "tptc0", }; @@ -1290,7 +1281,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { .master = &dm81xx_alwon_l3_fast_hwmod, .slave = &dm81xx_tptc0_hwmod, .clk = "sysclk4_ck", - .addr = dm81xx_tptc0_addr_space, .user = OCP_USER_MPU, }; @@ -1298,19 +1288,9 @@ static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { .master = &dm81xx_tptc0_hwmod, .slave = &dm81xx_alwon_l3_fast_hwmod, .clk = "sysclk4_ck", - .addr = dm81xx_tptc0_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = { - { - .pa_start = 0x49900000, - .pa_end = 0x49900000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { }, -}; - static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { .name = "tptc1", }; @@ -1332,7 +1312,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { .master = &dm81xx_alwon_l3_fast_hwmod, .slave = &dm81xx_tptc1_hwmod, .clk = "sysclk4_ck", - .addr = dm81xx_tptc1_addr_space, .user = OCP_USER_MPU, }; @@ -1340,19 +1319,9 @@ static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { .master = &dm81xx_tptc1_hwmod, .slave = &dm81xx_alwon_l3_fast_hwmod, .clk = "sysclk4_ck", - .addr = dm81xx_tptc1_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = { - { - .pa_start = 0x49a00000, - .pa_end = 0x49a00000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { }, -}; - static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { .name = "tptc2", }; @@ -1374,7 +1343,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { .master = &dm81xx_alwon_l3_fast_hwmod, .slave = &dm81xx_tptc2_hwmod, .clk = "sysclk4_ck", - .addr = dm81xx_tptc2_addr_space, .user = OCP_USER_MPU, }; @@ -1382,19 +1350,9 @@ static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { .master = &dm81xx_tptc2_hwmod, .slave = &dm81xx_alwon_l3_fast_hwmod, .clk = "sysclk4_ck", - .addr = dm81xx_tptc2_addr_space, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = { - { - .pa_start = 0x49b00000, - .pa_end = 0x49b00000 + SZ_8K - 1, - .flags = ADDR_TYPE_RT, - }, - { }, -}; - static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { .name = "tptc3", }; @@ -1416,7 +1374,6 @@ static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { .master = &dm81xx_alwon_l3_fast_hwmod, .slave = &dm81xx_tptc3_hwmod, .clk = "sysclk4_ck", - .addr = dm81xx_tptc3_addr_space, .user = OCP_USER_MPU, }; @@ -1424,7 +1381,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { .master = &dm81xx_tptc3_hwmod, .slave = &dm81xx_alwon_l3_fast_hwmod, .clk = "sysclk4_ck", - .addr = dm81xx_tptc3_addr_space, .user = OCP_USER_MPU, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index f22e9cb39f4a..29a52df2de26 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -18,9 +18,6 @@ #include "common.h" #include "display.h" -/* Common address space across OMAP2xxx/3xxx */ -extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; - /* Common IP block data across OMAP2xxx */ extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; extern struct omap_hwmod omap2xxx_l3_main_hwmod; @@ -89,44 +86,6 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham; extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes; -/* Common IP block data */ -extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; -extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[]; -extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[]; -extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[]; -extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[]; -extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[]; -extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[]; -extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[]; -extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[]; - -/* Common IP block data on OMAP2430/OMAP3 */ -extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[]; - -/* Common IP block data across OMAP2/3 */ -extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_dispc_irqs[]; -extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_dma_system_irqs[]; -extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[]; -extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; -extern struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[]; - /* OMAP hwmod classes - forward declarations */ extern struct omap_hwmod_class l3_hwmod_class; extern struct omap_hwmod_class l4_hwmod_class; diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index ee7041d523cf..0592b23902c6 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -506,7 +506,6 @@ struct omap_prcm_irq_setup { u8 nr_irqs; const struct omap_prcm_irq *irqs; int irq; - unsigned int (*xlate_irq)(unsigned int); void (*read_pending_irqs)(unsigned long *events); void (*ocp_barrier)(void); void (*save_and_clear_irqen)(u32 *saved_mask); diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 94dc3565add8..f0fb50871055 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -29,11 +29,9 @@ int omap2_prcm_base_init(void); * * PRM_HAS_IO_WAKEUP: has IO wakeup capability * PRM_HAS_VOLTAGE: has voltage domains - * PRM_IRQ_DEFAULT: use default irq number for PRM irq */ #define PRM_HAS_IO_WAKEUP BIT(0) #define PRM_HAS_VOLTAGE BIT(1) -#define PRM_IRQ_DEFAULT BIT(2) /* * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index a2dd13217c89..05858f966f7d 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -704,12 +704,18 @@ static int omap3xxx_prm_late_init(void) omap3430_pre_es3_1_reconfigure_io_chain; np = of_find_matching_node(NULL, omap3_prm_dt_match_table); - if (np) { - irq_num = of_irq_get(np, 0); - if (irq_num > 0) - omap3_prcm_irq_setup.irq = irq_num; + if (!np) { + pr_err("PRM: no device tree node for interrupt?\n"); + + return -ENODEV; } + irq_num = of_irq_get(np, 0); + if (irq_num == -EPROBE_DEFER) + return irq_num; + + omap3_prcm_irq_setup.irq = irq_num; + omap3xxx_prm_enable_io_wakeup(); return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 1c0c1663f078..acb95936dfe7 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -50,8 +50,6 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { .nr_regs = 2, .irqs = omap4_prcm_irqs, .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), - .irq = 11 + OMAP44XX_IRQ_GIC_START, - .xlate_irq = omap4_xlate_irq, .read_pending_irqs = &omap44xx_prm_read_pending_irqs, .ocp_barrier = &omap44xx_prm_ocp_barrier, .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, @@ -743,23 +741,10 @@ static int omap44xx_prm_late_init(void) return 0; irq_num = of_irq_get(prm_init_data->np, 0); - /* - * Already have OMAP4 IRQ num. For all other platforms, we need - * IRQ numbers from DT - */ - if (irq_num <= 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) { - if (irq_num == -EPROBE_DEFER) - return irq_num; - - /* Have nothing to do */ - return 0; - } + if (irq_num == -EPROBE_DEFER) + return irq_num; - /* Once OMAP4 DT is filled as well */ - if (irq_num > 0) { - omap4_prcm_irq_setup.irq = irq_num; - omap4_prcm_irq_setup.xlate_irq = NULL; - } + omap4_prcm_irq_setup.irq = irq_num; omap44xx_prm_enable_io_wakeup(); diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 09180a59b1c9..021b5a8b9c0a 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -218,10 +218,7 @@ void omap_prcm_irq_cleanup(void) kfree(prcm_irq_setup->priority_mask); prcm_irq_setup->priority_mask = NULL; - if (prcm_irq_setup->xlate_irq) - irq = prcm_irq_setup->xlate_irq(prcm_irq_setup->irq); - else - irq = prcm_irq_setup->irq; + irq = prcm_irq_setup->irq; irq_set_chained_handler(irq, NULL); if (prcm_irq_setup->base_irq > 0) @@ -307,10 +304,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) 1 << (offset & 0x1f); } - if (irq_setup->xlate_irq) - irq = irq_setup->xlate_irq(irq_setup->irq); - else - irq = irq_setup->irq; + irq = irq_setup->irq; irq_set_chained_handler(irq, omap_prcm_irq_handler); irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32, @@ -671,7 +665,7 @@ static struct omap_prcm_init_data omap4_prm_data __initdata = { .index = TI_CLKM_PRM, .init = omap44xx_prm_init, .device_inst_offset = OMAP4430_PRM_DEVICE_INST, - .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT, + .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE, }; #endif diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 754cd0fc0e7b..28fa1f8d8363 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -395,8 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430) #define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8)) #define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8)) #define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8)) -#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8)) #define DRA722_REV_ES2_0 (DRA7XX_CLASS | (0x22 << 16) | (0x20 << 8)) +#define DRA722_REV_ES2_1 (DRA7XX_CLASS | (0x22 << 16) | (0x21 << 8)) void omap2xxx_check_revision(void); void omap3xxx_check_revision(void); diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c index b7970f1fa3d5..d5f1f06e4811 100644 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c +++ b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c @@ -206,7 +206,7 @@ static int calc_tacc(unsigned int cyc, int nwait_en, } /** - * s3c2410_calc_bank - calculate bank timing infromation + * s3c2410_calc_bank - calculate bank timing information * @cfg: The configuration we need to calculate for. * @bt: The bank timing information. * @@ -453,11 +453,9 @@ int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, s3c_freq_iodbg("%s: bank %d: con %08lx\n", __func__, bank, bankcon); - bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL); - if (!bt) { - printk(KERN_ERR "%s: no memory for bank\n", __func__); + bt = kzalloc(sizeof(*bt), GFP_KERNEL); + if (!bt) return -ENOMEM; - } /* find out in nWait is enabled for bank. */ diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c index 28b13951de87..c5b12f6b02b5 100644 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c +++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c @@ -35,7 +35,7 @@ #define print_ns(x) ((x) / 10), ((x) % 10) /** - * s3c2412_print_timing - print timing infromation via printk. + * s3c2412_print_timing - print timing information via printk. * @pfx: The prefix to print each line with. * @iot: The IO timing information */ @@ -242,11 +242,9 @@ int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, if (!bank_is_io(bank, bankcfg)) continue; - bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL); - if (!bt) { - printk(KERN_ERR "%s: no memory for bank\n", __func__); + bt = kzalloc(sizeof(*bt), GFP_KERNEL); + if (!bt) return -ENOMEM; - } timings->bank[bank].io_2412 = bt; s3c2412_iotiming_getbank(cfg, bt, bank); diff --git a/arch/arm/mach-s3c64xx/dev-backlight.c b/arch/arm/mach-s3c64xx/dev-backlight.c index e62e789f9aee..7ef8b9019344 100644 --- a/arch/arm/mach-s3c64xx/dev-backlight.c +++ b/arch/arm/mach-s3c64xx/dev-backlight.c @@ -94,17 +94,14 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, samsung_bl_device = kmemdup(&samsung_dfl_bl_device, sizeof(struct platform_device), GFP_KERNEL); - if (!samsung_bl_device) { - printk(KERN_ERR "%s: no memory for platform dev\n", __func__); + if (!samsung_bl_device) return; - } samsung_bl_drvdata = kmemdup(&samsung_dfl_bl_data, sizeof(samsung_dfl_bl_data), GFP_KERNEL); - if (!samsung_bl_drvdata) { - printk(KERN_ERR "%s: no memory for platform dev\n", __func__); + if (!samsung_bl_drvdata) goto err_data; - } + samsung_bl_device->dev.platform_data = &samsung_bl_drvdata->plat_data; samsung_bl_drvdata->gpio_info = gpio_info; samsung_bl_data = &samsung_bl_drvdata->plat_data; @@ -144,5 +141,4 @@ err_plat_reg2: kfree(samsung_bl_data); err_data: kfree(samsung_bl_device); - return; } diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index e16b81ec4b07..1939f521579c 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -23,6 +23,7 @@ cpu-y := platsmp.o headsmp.o # Shared SoC family objects obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y) CFLAGS_setup-rcar-gen2.o += -march=armv7-a +obj-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h index f8fcd799d677..a8fa4f7e1f60 100644 --- a/arch/arm/mach-shmobile/common.h +++ b/arch/arm/mach-shmobile/common.h @@ -2,6 +2,7 @@ #ifndef __ARCH_MACH_COMMON_H #define __ARCH_MACH_COMMON_H +extern void shmobile_init_cntvoff(void); extern void shmobile_init_delay(void); extern void shmobile_boot_vector(void); extern unsigned long shmobile_boot_fn; @@ -12,6 +13,7 @@ extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg); extern bool shmobile_smp_cpu_can_disable(unsigned int cpu); extern bool shmobile_smp_init_fallback_ops(void); +extern void shmobile_boot_apmu(void); extern void shmobile_boot_scu(void); extern void shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys, unsigned int max_cpus); diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S b/arch/arm/mach-shmobile/headsmp-apmu.S new file mode 100644 index 000000000000..5672b5849401 --- /dev/null +++ b/arch/arm/mach-shmobile/headsmp-apmu.S @@ -0,0 +1,39 @@ +/* + * SMP support for APMU based systems with Cortex A7/A15 + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +ENTRY(shmobile_init_cntvoff) + /* + * CNTVOFF has to be initialized either from non-secure Hypervisor + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled + * then it should be handled by the secure code + */ + cps #MON_MODE + mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */ + orr r0, r1, #1 + mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ + instr_sync + mov r0, #0 + mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */ + instr_sync + mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */ + instr_sync + cps #SVC_MODE + ret lr +ENDPROC(shmobile_init_cntvoff) + +#ifdef CONFIG_SMP +ENTRY(shmobile_boot_apmu) + bl shmobile_init_cntvoff + b secondary_startup +ENDPROC(shmobile_boot_apmu) +#endif diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 3ca2c13346f0..4422b615a6ee 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -204,7 +204,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) { /* For this particular CPU register boot vector */ - shmobile_smp_hook(cpu, __pa_symbol(secondary_startup), 0); + shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0); return apmu_wrap(cpu, apmu_power_on); } diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 7ab1690fab82..5561dbed7a33 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -70,28 +70,12 @@ void __init rcar_gen2_timer_init(void) void __iomem *base; u32 freq; + shmobile_init_cntvoff(); + if (of_machine_is_compatible("renesas,r8a7745") || of_machine_is_compatible("renesas,r8a7792") || of_machine_is_compatible("renesas,r8a7794")) { freq = 260000000 / 8; /* ZS / 8 */ - /* CNTVOFF has to be initialized either from non-secure - * Hypervisor mode or secure Monitor mode with SCR.NS==1. - * If TrustZone is enabled then it should be handled by the - * secure code. - */ - asm volatile( - " cps 0x16\n" - " mrc p15, 0, r1, c1, c1, 0\n" - " orr r0, r1, #1\n" - " mcr p15, 0, r0, c1, c1, 0\n" - " isb\n" - " mov r0, #0\n" - " mcrr p15, 4, r0, r0, c14\n" - " isb\n" - " mcr p15, 0, r1, c1, c1, 0\n" - " isb\n" - " cps 0x13\n" - : : : "r0", "r1"); } else { /* At Linux boot time the r8a7790 arch timer comes up * with the counter disabled. Moreover, it may also report diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 7ab353fb25f2..5e9602ce1573 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -65,6 +65,7 @@ static const char * const sun8i_board_dt_compat[] = { "allwinner,sun8i-a83t", "allwinner,sun8i-h2-plus", "allwinner,sun8i-h3", + "allwinner,sun8i-r40", "allwinner,sun8i-v3s", NULL, }; diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c index fe488523694c..21c064267af5 100644 --- a/arch/arm/mach-vexpress/spc.c +++ b/arch/arm/mach-vexpress/spc.c @@ -451,10 +451,8 @@ int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq) { int ret; info = kzalloc(sizeof(*info), GFP_KERNEL); - if (!info) { - pr_err(SPCLOG "unable to allocate mem\n"); + if (!info) return -ENOMEM; - } info->baseaddr = baseaddr; info->a15_clusid = a15_clusid; @@ -535,10 +533,8 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev) struct clk_spc *spc; spc = kzalloc(sizeof(*spc), GFP_KERNEL); - if (!spc) { - pr_err("could not allocate spc clk\n"); + if (!spc) return ERR_PTR(-ENOMEM); - } spc->hw.init = &init; spc->cluster = topology_physical_package_id(cpu_dev->id); diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 1e460b4ee3b9..d4012d6c0dcb 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1316,16 +1316,14 @@ static int omap_system_dma_probe(struct platform_device *pdev) enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count, - sizeof(struct omap_dma_lch), GFP_KERNEL); - if (!dma_chan) { - dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__); + sizeof(*dma_chan), GFP_KERNEL); + if (!dma_chan) return -ENOMEM; - } - if (dma_omap2plus()) { - dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * - dma_lch_count, GFP_KERNEL); + dma_linked_lch = kcalloc(dma_lch_count, + sizeof(*dma_linked_lch), + GFP_KERNEL); if (!dma_linked_lch) { ret = -ENOMEM; goto exit_dma_lch_fail; diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 7a327bd32521..d443e481c3e9 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -254,8 +254,8 @@ static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) if (cap == (t->capability & cap)) { /* * If timer is not NULL, we have already found - * one timer but it was not an exact match - * because it had more capabilites that what + * one timer. But it was not an exact match + * because it had more capabilities than what * was required. Therefore, unreserve the last * timer found and see if this one is a better * match. @@ -857,11 +857,9 @@ static int omap_dm_timer_probe(struct platform_device *pdev) return -ENODEV; } - timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL); - if (!timer) { - dev_err(dev, "%s: memory alloc failed!\n", __func__); + timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); + if (!timer) return -ENOMEM; - } timer->fclk = ERR_PTR(-ENODEV); timer->io_base = devm_ioremap_resource(dev, mem); diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index daf3db9f0058..e9de9e92ce01 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -238,11 +238,9 @@ struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, if (!pdev) return ERR_PTR(-EINVAL); - client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL); - if (!client) { - dev_err(&pdev->dev, "no memory for adc client\n"); + client = kzalloc(sizeof(*client), GFP_KERNEL); + if (!client) return ERR_PTR(-ENOMEM); - } client->pdev = pdev; client->is_ts = is_ts; @@ -344,11 +342,9 @@ static int s3c_adc_probe(struct platform_device *pdev) int ret; unsigned tmp; - adc = devm_kzalloc(dev, sizeof(struct adc_device), GFP_KERNEL); - if (adc == NULL) { - dev_err(dev, "failed to allocate adc_device\n"); + adc = devm_kzalloc(dev, sizeof(*adc), GFP_KERNEL); + if (!adc) return -ENOMEM; - } spin_lock_init(&adc->lock); diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index dc269d9143bc..5668e4eb03df 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -339,8 +339,7 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) pd->bus_num = 0; } - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c0); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c0); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c0_cfg_gpio; @@ -368,8 +367,7 @@ void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) pd->bus_num = 1; } - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c1); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c1); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c1_cfg_gpio; @@ -398,8 +396,7 @@ void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) pd->bus_num = 2; } - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c2); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c2); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c2_cfg_gpio; @@ -428,8 +425,7 @@ void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd) pd->bus_num = 3; } - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c3); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c3); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c3_cfg_gpio; @@ -458,8 +454,7 @@ void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd) pd->bus_num = 4; } - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c4); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c4); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c4_cfg_gpio; @@ -488,8 +483,7 @@ void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd) pd->bus_num = 5; } - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c5); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c5); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c5_cfg_gpio; @@ -518,8 +512,7 @@ void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd) pd->bus_num = 6; } - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c6); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c6); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c6_cfg_gpio; @@ -548,8 +541,7 @@ void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd) pd->bus_num = 7; } - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c7); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c7); if (!npd->cfg_gpio) npd->cfg_gpio = s3c_i2c7_cfg_gpio; @@ -615,8 +607,7 @@ void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd) { struct samsung_keypad_platdata *npd; - npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata), - &samsung_device_keypad); + npd = s3c_set_platdata(pd, sizeof(*npd), &samsung_device_keypad); if (!npd->cfg_gpio) npd->cfg_gpio = samsung_keypad_cfg_gpio; @@ -721,8 +712,7 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand) * time then there is little chance the system is going to run. */ - npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand), - &s3c_device_nand); + npd = s3c_set_platdata(nand, sizeof(*npd), &s3c_device_nand); if (!npd) return; @@ -1022,8 +1012,7 @@ void __init dwc2_hsotg_set_platdata(struct dwc2_hsotg_plat *pd) { struct dwc2_hsotg_plat *npd; - npd = s3c_set_platdata(pd, sizeof(struct dwc2_hsotg_plat), - &s3c_device_usb_hsotg); + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_usb_hsotg); if (!npd->phy_init) npd->phy_init = s5p_usb_phy_init; diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c index b430e9946287..6cf52ee7eeec 100644 --- a/arch/arm/plat-samsung/platformdata.c +++ b/arch/arm/plat-samsung/platformdata.c @@ -29,10 +29,8 @@ void __init *s3c_set_platdata(void *pd, size_t pdsize, } npd = kmemdup(pd, pdsize, GFP_KERNEL); - if (!npd) { - printk(KERN_ERR "%s: cannot clone platform data\n", pdev->name); + if (!npd) return NULL; - } pdev->dev.platform_data = npd; return npd; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 34480e9af2e7..6356c6da34ea 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -51,6 +51,8 @@ CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_RENESAS=y CONFIG_ARCH_R8A7795=y CONFIG_ARCH_R8A7796=y +CONFIG_ARCH_R8A77970=y +CONFIG_ARCH_R8A77995=y CONFIG_ARCH_STRATIX10=y CONFIG_ARCH_TEGRA=y CONFIG_ARCH_SPRD=y @@ -72,10 +74,13 @@ CONFIG_PCIE_QCOM=y CONFIG_PCIE_KIRIN=y CONFIG_PCIE_ARMADA_8K=y CONFIG_PCI_AARDVARK=y +CONFIG_PCI_TEGRA=y CONFIG_PCIE_RCAR=y CONFIG_PCIE_ROCKCHIP=m CONFIG_PCI_HOST_GENERIC=y CONFIG_PCI_XGENE=y +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_ARM64_VA_BITS_48=y CONFIG_SCHED_MC=y CONFIG_NUMA=y @@ -156,6 +161,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_PXA3xx=y CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m @@ -188,6 +194,7 @@ CONFIG_VIRTIO_NET=y CONFIG_AMD_XGBE=y CONFIG_NET_XGENE=y CONFIG_MACB=y +CONFIG_THUNDER_NIC_PF=y CONFIG_HNS_DSAF=y CONFIG_HNS_ENET=y CONFIG_E1000E=y @@ -204,6 +211,7 @@ CONFIG_STMMAC_ETH=m CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_AT803X_PHY=m CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m CONFIG_MESON_GXL_PHY=m CONFIG_MICREL_PHY=y CONFIG_REALTEK_PHY=m @@ -297,6 +305,7 @@ CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y +CONFIG_GPIO_UNIPHIER=y CONFIG_GPIO_XGENE=y CONFIG_GPIO_XGENE_SB=y CONFIG_GPIO_PCA953X=y @@ -315,6 +324,7 @@ CONFIG_CPU_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_BRCMSTB_THERMAL=m CONFIG_EXYNOS_THERMAL=y +CONFIG_RCAR_GEN3_THERMAL=y CONFIG_ROCKCHIP_THERMAL=m CONFIG_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y @@ -386,6 +396,7 @@ CONFIG_DRM_TEGRA=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_VC4=m +CONFIG_DRM_HISI_HIBMC=m CONFIG_DRM_HISI_KIRIN=m CONFIG_DRM_MESON=m CONFIG_FB=y @@ -423,6 +434,7 @@ CONFIG_USB_DWC2=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_ULPI=y CONFIG_USB_ISP1760=y CONFIG_USB_HSIC_USB3503=y CONFIG_NOP_USB_XCEIV=y @@ -431,6 +443,7 @@ CONFIG_USB_QCOM_8X16_PHY=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_ULPI_BUS=y CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -470,6 +483,7 @@ CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_S3C=y CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_DRV_ARMADA38X=y CONFIG_RTC_DRV_TEGRA=y CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y @@ -510,6 +524,7 @@ CONFIG_HI6220_MBOX=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_ARM_SMMU=y CONFIG_ARM_SMMU_V3=y +CONFIG_QCOM_IOMMU=y CONFIG_RPMSG_QCOM_SMD=y CONFIG_RASPBERRYPI_POWER=y CONFIG_QCOM_SMEM=y @@ -533,7 +548,9 @@ CONFIG_PWM_SAMSUNG=y CONFIG_PWM_TEGRA=m CONFIG_PHY_RCAR_GEN3_USB2=y CONFIG_PHY_HI6220_USB=y +CONFIG_PHY_QCOM_USB_HS=y CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_MVEBU_CP110_COMPHY=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_EMMC=y CONFIG_PHY_ROCKCHIP_PCIE=m diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 3e66f4cc1a59..fa94a85bf410 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -158,6 +158,13 @@ config TEGRA_GMI Driver for the Tegra Generic Memory Interface bus which can be used to attach devices such as NOR, UART, FPGA and more. +config TI_SYSC + bool "TI sysc interconnect target module driver" + depends on ARCH_OMAP2PLUS + help + Generic driver for Texas Instruments interconnect target module + found on many TI SoCs. + config UNIPHIER_SYSTEM_BUS tristate "UniPhier System Bus driver" depends on ARCH_UNIPHIER && OF diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 3ae96cffabd5..94a079008cbe 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o +obj-$(CONFIG_TI_SYSC) += ti-sysc.o obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c new file mode 100644 index 000000000000..c3c76a1ea8a8 --- /dev/null +++ b/drivers/bus/ti-sysc.c @@ -0,0 +1,583 @@ +/* + * ti-sysc.c - Texas Instruments sysc interconnect target driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> + +enum sysc_registers { + SYSC_REVISION, + SYSC_SYSCONFIG, + SYSC_SYSSTATUS, + SYSC_MAX_REGS, +}; + +static const char * const reg_names[] = { "rev", "sysc", "syss", }; + +enum sysc_clocks { + SYSC_FCK, + SYSC_ICK, + SYSC_MAX_CLOCKS, +}; + +static const char * const clock_names[] = { "fck", "ick", }; + +/** + * struct sysc - TI sysc interconnect target module registers and capabilities + * @dev: struct device pointer + * @module_pa: physical address of the interconnect target module + * @module_size: size of the interconnect target module + * @module_va: virtual address of the interconnect target module + * @offsets: register offsets from module base + * @clocks: clocks used by the interconnect target module + * @legacy_mode: configured for legacy mode if set + */ +struct sysc { + struct device *dev; + u64 module_pa; + u32 module_size; + void __iomem *module_va; + int offsets[SYSC_MAX_REGS]; + struct clk *clocks[SYSC_MAX_CLOCKS]; + const char *legacy_mode; +}; + +static u32 sysc_read_revision(struct sysc *ddata) +{ + return readl_relaxed(ddata->module_va + + ddata->offsets[SYSC_REVISION]); +} + +static int sysc_get_one_clock(struct sysc *ddata, + enum sysc_clocks index) +{ + const char *name; + int error; + + switch (index) { + case SYSC_FCK: + break; + case SYSC_ICK: + break; + default: + return -EINVAL; + } + name = clock_names[index]; + + ddata->clocks[index] = devm_clk_get(ddata->dev, name); + if (IS_ERR(ddata->clocks[index])) { + if (PTR_ERR(ddata->clocks[index]) == -ENOENT) + return 0; + + dev_err(ddata->dev, "clock get error for %s: %li\n", + name, PTR_ERR(ddata->clocks[index])); + + return PTR_ERR(ddata->clocks[index]); + } + + error = clk_prepare(ddata->clocks[index]); + if (error) { + dev_err(ddata->dev, "clock prepare error for %s: %i\n", + name, error); + + return error; + } + + return 0; +} + +static int sysc_get_clocks(struct sysc *ddata) +{ + int i, error; + + if (ddata->legacy_mode) + return 0; + + for (i = 0; i < SYSC_MAX_CLOCKS; i++) { + error = sysc_get_one_clock(ddata, i); + if (error && error != -ENOENT) + return error; + } + + return 0; +} + +/** + * sysc_parse_and_check_child_range - parses module IO region from ranges + * @ddata: device driver data + * + * In general we only need rev, syss, and sysc registers and not the whole + * module range. But we do want the offsets for these registers from the + * module base. This allows us to check them against the legacy hwmod + * platform data. Let's also check the ranges are configured properly. + */ +static int sysc_parse_and_check_child_range(struct sysc *ddata) +{ + struct device_node *np = ddata->dev->of_node; + const __be32 *ranges; + u32 nr_addr, nr_size; + int len, error; + + ranges = of_get_property(np, "ranges", &len); + if (!ranges) { + dev_err(ddata->dev, "missing ranges for %pOF\n", np); + + return -ENOENT; + } + + len /= sizeof(*ranges); + + if (len < 3) { + dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); + + return -EINVAL; + } + + error = of_property_read_u32(np, "#address-cells", &nr_addr); + if (error) + return -ENOENT; + + error = of_property_read_u32(np, "#size-cells", &nr_size); + if (error) + return -ENOENT; + + if (nr_addr != 1 || nr_size != 1) { + dev_err(ddata->dev, "invalid ranges for %pOF\n", np); + + return -EINVAL; + } + + ranges++; + ddata->module_pa = of_translate_address(np, ranges++); + ddata->module_size = be32_to_cpup(ranges); + + dev_dbg(ddata->dev, "interconnect target 0x%llx size 0x%x for %pOF\n", + ddata->module_pa, ddata->module_size, np); + + return 0; +} + +/** + * sysc_check_one_child - check child configuration + * @ddata: device driver data + * @np: child device node + * + * Let's avoid messy situations where we have new interconnect target + * node but children have "ti,hwmods". These belong to the interconnect + * target node and are managed by this driver. + */ +static int sysc_check_one_child(struct sysc *ddata, + struct device_node *np) +{ + const char *name; + + name = of_get_property(np, "ti,hwmods", NULL); + if (name) + dev_warn(ddata->dev, "really a child ti,hwmods property?"); + + return 0; +} + +static int sysc_check_children(struct sysc *ddata) +{ + struct device_node *child; + int error; + + for_each_child_of_node(ddata->dev->of_node, child) { + error = sysc_check_one_child(ddata, child); + if (error) + return error; + } + + return 0; +} + +/** + * sysc_parse_one - parses the interconnect target module registers + * @ddata: device driver data + * @reg: register to parse + */ +static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) +{ + struct resource *res; + const char *name; + + switch (reg) { + case SYSC_REVISION: + case SYSC_SYSCONFIG: + case SYSC_SYSSTATUS: + name = reg_names[reg]; + break; + default: + return -EINVAL; + } + + res = platform_get_resource_byname(to_platform_device(ddata->dev), + IORESOURCE_MEM, name); + if (!res) { + dev_dbg(ddata->dev, "has no %s register\n", name); + ddata->offsets[reg] = -ENODEV; + + return 0; + } + + ddata->offsets[reg] = res->start - ddata->module_pa; + + return 0; +} + +static int sysc_parse_registers(struct sysc *ddata) +{ + int i, error; + + for (i = 0; i < SYSC_MAX_REGS; i++) { + error = sysc_parse_one(ddata, i); + if (error) + return error; + } + + return 0; +} + +/** + * sysc_check_registers - check for misconfigured register overlaps + * @ddata: device driver data + */ +static int sysc_check_registers(struct sysc *ddata) +{ + int i, j, nr_regs = 0, nr_matches = 0; + + for (i = 0; i < SYSC_MAX_REGS; i++) { + if (ddata->offsets[i] < 0) + continue; + + if (ddata->offsets[i] > (ddata->module_size - 4)) { + dev_err(ddata->dev, "register outside module range"); + + return -EINVAL; + } + + for (j = 0; j < SYSC_MAX_REGS; j++) { + if (ddata->offsets[j] < 0) + continue; + + if (ddata->offsets[i] == ddata->offsets[j]) + nr_matches++; + } + nr_regs++; + } + + if (nr_regs < 1) { + dev_err(ddata->dev, "missing registers\n"); + + return -EINVAL; + } + + if (nr_matches > nr_regs) { + dev_err(ddata->dev, "overlapping registers: (%i/%i)", + nr_regs, nr_matches); + + return -EINVAL; + } + + return 0; +} + +/** + * syc_ioremap - ioremap register space for the interconnect target module + * @ddata: deviec driver data + * + * Note that the interconnect target module registers can be anywhere + * within the first child device address space. For example, SGX has + * them at offset 0x1fc00 in the 32MB module address space. We just + * what we need around the interconnect target module registers. + */ +static int sysc_ioremap(struct sysc *ddata) +{ + u32 size = 0; + + if (ddata->offsets[SYSC_SYSSTATUS] >= 0) + size = ddata->offsets[SYSC_SYSSTATUS]; + else if (ddata->offsets[SYSC_SYSCONFIG] >= 0) + size = ddata->offsets[SYSC_SYSCONFIG]; + else if (ddata->offsets[SYSC_REVISION] >= 0) + size = ddata->offsets[SYSC_REVISION]; + else + return -EINVAL; + + size &= 0xfff00; + size += SZ_256; + + ddata->module_va = devm_ioremap(ddata->dev, + ddata->module_pa, + size); + if (!ddata->module_va) + return -EIO; + + return 0; +} + +/** + * sysc_map_and_check_registers - ioremap and check device registers + * @ddata: device driver data + */ +static int sysc_map_and_check_registers(struct sysc *ddata) +{ + int error; + + error = sysc_parse_and_check_child_range(ddata); + if (error) + return error; + + error = sysc_check_children(ddata); + if (error) + return error; + + error = sysc_parse_registers(ddata); + if (error) + return error; + + error = sysc_ioremap(ddata); + if (error) + return error; + + error = sysc_check_registers(ddata); + if (error) + return error; + + return 0; +} + +/** + * sysc_show_rev - read and show interconnect target module revision + * @bufp: buffer to print the information to + * @ddata: device driver data + */ +static int sysc_show_rev(char *bufp, struct sysc *ddata) +{ + int error, len; + + if (ddata->offsets[SYSC_REVISION] < 0) + return sprintf(bufp, ":NA"); + + error = pm_runtime_get_sync(ddata->dev); + if (error < 0) { + pm_runtime_put_noidle(ddata->dev); + + return 0; + } + + len = sprintf(bufp, ":%08x", sysc_read_revision(ddata)); + + pm_runtime_mark_last_busy(ddata->dev); + pm_runtime_put_autosuspend(ddata->dev); + + return len; +} + +static int sysc_show_reg(struct sysc *ddata, + char *bufp, enum sysc_registers reg) +{ + if (ddata->offsets[reg] < 0) + return sprintf(bufp, ":NA"); + + return sprintf(bufp, ":%x", ddata->offsets[reg]); +} + +/** + * sysc_show_registers - show information about interconnect target module + * @ddata: device driver data + */ +static void sysc_show_registers(struct sysc *ddata) +{ + char buf[128]; + char *bufp = buf; + int i; + + for (i = 0; i < SYSC_MAX_REGS; i++) + bufp += sysc_show_reg(ddata, bufp, i); + + bufp += sysc_show_rev(bufp, ddata); + + dev_dbg(ddata->dev, "%llx:%x%s\n", + ddata->module_pa, ddata->module_size, + buf); +} + +static int __maybe_unused sysc_runtime_suspend(struct device *dev) +{ + struct sysc *ddata; + int i; + + ddata = dev_get_drvdata(dev); + + if (ddata->legacy_mode) + return 0; + + for (i = 0; i < SYSC_MAX_CLOCKS; i++) { + if (IS_ERR_OR_NULL(ddata->clocks[i])) + continue; + clk_disable(ddata->clocks[i]); + } + + return 0; +} + +static int __maybe_unused sysc_runtime_resume(struct device *dev) +{ + struct sysc *ddata; + int i, error; + + ddata = dev_get_drvdata(dev); + + if (ddata->legacy_mode) + return 0; + + for (i = 0; i < SYSC_MAX_CLOCKS; i++) { + if (IS_ERR_OR_NULL(ddata->clocks[i])) + continue; + error = clk_enable(ddata->clocks[i]); + if (error) + return error; + } + + return 0; +} + +static const struct dev_pm_ops sysc_pm_ops = { + SET_RUNTIME_PM_OPS(sysc_runtime_suspend, + sysc_runtime_resume, + NULL) +}; + +static void sysc_unprepare(struct sysc *ddata) +{ + int i; + + for (i = 0; i < SYSC_MAX_CLOCKS; i++) { + if (!IS_ERR_OR_NULL(ddata->clocks[i])) + clk_unprepare(ddata->clocks[i]); + } +} + +static int sysc_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct sysc *ddata; + int error; + + ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->dev = &pdev->dev; + ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); + + error = sysc_get_clocks(ddata); + if (error) + return error; + + error = sysc_map_and_check_registers(ddata); + if (error) + goto unprepare; + + platform_set_drvdata(pdev, ddata); + + pm_runtime_enable(ddata->dev); + error = pm_runtime_get_sync(ddata->dev); + if (error < 0) { + pm_runtime_put_noidle(ddata->dev); + pm_runtime_disable(ddata->dev); + goto unprepare; + } + + pm_runtime_use_autosuspend(ddata->dev); + + sysc_show_registers(ddata); + + error = of_platform_populate(ddata->dev->of_node, + NULL, NULL, ddata->dev); + if (error) + goto err; + + pm_runtime_mark_last_busy(ddata->dev); + pm_runtime_put_autosuspend(ddata->dev); + + return 0; + +err: + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); +unprepare: + sysc_unprepare(ddata); + + return error; +} + +static int sysc_remove(struct platform_device *pdev) +{ + struct sysc *ddata = platform_get_drvdata(pdev); + int error; + + error = pm_runtime_get_sync(ddata->dev); + if (error < 0) { + pm_runtime_put_noidle(ddata->dev); + pm_runtime_disable(ddata->dev); + goto unprepare; + } + + of_platform_depopulate(&pdev->dev); + + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + +unprepare: + sysc_unprepare(ddata); + + return 0; +} + +static const struct of_device_id sysc_match[] = { + { .compatible = "ti,sysc-omap2" }, + { .compatible = "ti,sysc-omap4" }, + { .compatible = "ti,sysc-omap4-simple" }, + { .compatible = "ti,sysc-omap3430-sr" }, + { .compatible = "ti,sysc-omap3630-sr" }, + { .compatible = "ti,sysc-omap4-sr" }, + { .compatible = "ti,sysc-omap3-sham" }, + { .compatible = "ti,sysc-omap-aes" }, + { .compatible = "ti,sysc-mcasp" }, + { .compatible = "ti,sysc-usb-host-fs" }, + { }, +}; +MODULE_DEVICE_TABLE(of, sysc_match); + +static struct platform_driver sysc_driver = { + .probe = sysc_probe, + .remove = sysc_remove, + .driver = { + .name = "ti-sysc", + .of_match_table = sysc_match, + .pm = &sysc_pm_ops, + }, +}; +module_platform_driver(sysc_driver); + +MODULE_DESCRIPTION("TI sysc interconnect target driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/bcm/clk-bcm2835-aux.c b/drivers/clk/bcm/clk-bcm2835-aux.c index bd750cf2238d..77e276d61702 100644 --- a/drivers/clk/bcm/clk-bcm2835-aux.c +++ b/drivers/clk/bcm/clk-bcm2835-aux.c @@ -14,7 +14,6 @@ #include <linux/clk.h> #include <linux/clk-provider.h> -#include <linux/clk/bcm2835.h> #include <linux/module.h> #include <linux/platform_device.h> #include <dt-bindings/clock/bcm2835-aux.h> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 58ce6af8452d..44301a3d9963 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -37,7 +37,6 @@ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk.h> -#include <linux/clk/bcm2835.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/module.h> @@ -416,35 +415,6 @@ static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, return regdump ? 0 : -ENOMEM; } -/* - * These are fixed clocks. They're probably not all root clocks and it may - * be possible to turn them on and off but until this is mapped out better - * it's the only way they can be used. - */ -void __init bcm2835_init_clocks(void) -{ - struct clk_hw *hw; - int ret; - - hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); - if (IS_ERR(hw)) - pr_err("apb_pclk not registered\n"); - - hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); - if (IS_ERR(hw)) - pr_err("uart0_pclk not registered\n"); - ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart"); - if (ret) - pr_err("uart0_pclk alias not registered\n"); - - hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); - if (IS_ERR(hw)) - pr_err("uart1_pclk not registered\n"); - ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart"); - if (ret) - pr_err("uart1_pclk alias not registered\n"); -} - struct bcm2835_pll_data { const char *name; u32 cm_ctrl_reg; diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c index dc8c1e3eafe7..667b9e14b032 100644 --- a/drivers/irqchip/irq-bcm2836.c +++ b/drivers/irqchip/irq-bcm2836.c @@ -19,62 +19,9 @@ #include <linux/of_irq.h> #include <linux/irqchip.h> #include <linux/irqdomain.h> -#include <asm/exception.h> - -#define LOCAL_CONTROL 0x000 -#define LOCAL_PRESCALER 0x008 +#include <linux/irqchip/irq-bcm2836.h> -/* - * The low 2 bits identify the CPU that the GPU IRQ goes to, and the - * next 2 bits identify the CPU that the GPU FIQ goes to. - */ -#define LOCAL_GPU_ROUTING 0x00c -/* When setting bits 0-3, enables PMU interrupts on that CPU. */ -#define LOCAL_PM_ROUTING_SET 0x010 -/* When setting bits 0-3, disables PMU interrupts on that CPU. */ -#define LOCAL_PM_ROUTING_CLR 0x014 -/* - * The low 4 bits of this are the CPU's timer IRQ enables, and the - * next 4 bits are the CPU's timer FIQ enables (which override the IRQ - * bits). - */ -#define LOCAL_TIMER_INT_CONTROL0 0x040 -/* - * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and - * the next 4 bits are the CPU's per-mailbox FIQ enables (which - * override the IRQ bits). - */ -#define LOCAL_MAILBOX_INT_CONTROL0 0x050 -/* - * The CPU's interrupt status register. Bits are defined by the the - * LOCAL_IRQ_* bits below. - */ -#define LOCAL_IRQ_PENDING0 0x060 -/* Same status bits as above, but for FIQ. */ -#define LOCAL_FIQ_PENDING0 0x070 -/* - * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and - * these bits are organized by mailbox number and then CPU number. We - * use mailbox 0 for IPIs. The mailbox's interrupt is raised while - * any bit is set. - */ -#define LOCAL_MAILBOX0_SET0 0x080 -#define LOCAL_MAILBOX3_SET0 0x08c -/* Mailbox write-to-clear bits. */ -#define LOCAL_MAILBOX0_CLR0 0x0c0 -#define LOCAL_MAILBOX3_CLR0 0x0cc - -#define LOCAL_IRQ_CNTPSIRQ 0 -#define LOCAL_IRQ_CNTPNSIRQ 1 -#define LOCAL_IRQ_CNTHPIRQ 2 -#define LOCAL_IRQ_CNTVIRQ 3 -#define LOCAL_IRQ_MAILBOX0 4 -#define LOCAL_IRQ_MAILBOX1 5 -#define LOCAL_IRQ_MAILBOX2 6 -#define LOCAL_IRQ_MAILBOX3 7 -#define LOCAL_IRQ_GPU_FAST 8 -#define LOCAL_IRQ_PMU_FAST 9 -#define LAST_IRQ LOCAL_IRQ_PMU_FAST +#include <asm/exception.h> struct bcm2836_arm_irqchip_intc { struct irq_domain *domain; @@ -215,24 +162,6 @@ static int bcm2836_cpu_dying(unsigned int cpu) cpu); return 0; } - -#ifdef CONFIG_ARM -static int __init bcm2836_smp_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - unsigned long secondary_startup_phys = - (unsigned long)virt_to_phys((void *)secondary_startup); - - writel(secondary_startup_phys, - intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu); - - return 0; -} - -static const struct smp_operations bcm2836_smp_ops __initconst = { - .smp_boot_secondary = bcm2836_smp_boot_secondary, -}; -#endif #endif static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = { @@ -249,10 +178,6 @@ bcm2836_arm_irqchip_smp_init(void) bcm2836_cpu_dying); set_smp_cross_call(bcm2836_arm_irqchip_send_ipi); - -#ifdef CONFIG_ARM - smp_set_ops(&bcm2836_smp_ops); -#endif #endif } diff --git a/include/linux/clk/bcm2835.h b/include/linux/clk/bcm2835.h deleted file mode 100644 index aa937f6c17da..000000000000 --- a/include/linux/clk/bcm2835.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2010 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __LINUX_CLK_BCM2835_H_ -#define __LINUX_CLK_BCM2835_H_ - -void __init bcm2835_init_clocks(void); - -#endif diff --git a/include/linux/irqchip/irq-bcm2836.h b/include/linux/irqchip/irq-bcm2836.h new file mode 100644 index 000000000000..218a6e1b18d8 --- /dev/null +++ b/include/linux/irqchip/irq-bcm2836.h @@ -0,0 +1,70 @@ +/* + * Root interrupt controller for the BCM2836 (Raspberry Pi 2). + * + * Copyright 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define LOCAL_CONTROL 0x000 +#define LOCAL_PRESCALER 0x008 + +/* + * The low 2 bits identify the CPU that the GPU IRQ goes to, and the + * next 2 bits identify the CPU that the GPU FIQ goes to. + */ +#define LOCAL_GPU_ROUTING 0x00c +/* When setting bits 0-3, enables PMU interrupts on that CPU. */ +#define LOCAL_PM_ROUTING_SET 0x010 +/* When setting bits 0-3, disables PMU interrupts on that CPU. */ +#define LOCAL_PM_ROUTING_CLR 0x014 +/* + * The low 4 bits of this are the CPU's timer IRQ enables, and the + * next 4 bits are the CPU's timer FIQ enables (which override the IRQ + * bits). + */ +#define LOCAL_TIMER_INT_CONTROL0 0x040 +/* + * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and + * the next 4 bits are the CPU's per-mailbox FIQ enables (which + * override the IRQ bits). + */ +#define LOCAL_MAILBOX_INT_CONTROL0 0x050 +/* + * The CPU's interrupt status register. Bits are defined by the the + * LOCAL_IRQ_* bits below. + */ +#define LOCAL_IRQ_PENDING0 0x060 +/* Same status bits as above, but for FIQ. */ +#define LOCAL_FIQ_PENDING0 0x070 +/* + * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and + * these bits are organized by mailbox number and then CPU number. We + * use mailbox 0 for IPIs. The mailbox's interrupt is raised while + * any bit is set. + */ +#define LOCAL_MAILBOX0_SET0 0x080 +#define LOCAL_MAILBOX3_SET0 0x08c +/* Mailbox write-to-clear bits. */ +#define LOCAL_MAILBOX0_CLR0 0x0c0 +#define LOCAL_MAILBOX3_CLR0 0x0cc + +#define LOCAL_IRQ_CNTPSIRQ 0 +#define LOCAL_IRQ_CNTPNSIRQ 1 +#define LOCAL_IRQ_CNTHPIRQ 2 +#define LOCAL_IRQ_CNTVIRQ 3 +#define LOCAL_IRQ_MAILBOX0 4 +#define LOCAL_IRQ_MAILBOX1 5 +#define LOCAL_IRQ_MAILBOX2 6 +#define LOCAL_IRQ_MAILBOX3 7 +#define LOCAL_IRQ_GPU_FAST 8 +#define LOCAL_IRQ_PMU_FAST 9 +#define LAST_IRQ LOCAL_IRQ_PMU_FAST |