diff options
Diffstat (limited to 'arch/mips/sibyte/sb1250')
| -rw-r--r-- | arch/mips/sibyte/sb1250/irq.c | 17 | ||||
| -rw-r--r-- | arch/mips/sibyte/sb1250/setup.c | 15 |
2 files changed, 23 insertions, 9 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 5e7f2016cceb..12ac04a658ee 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -22,7 +22,6 @@ #include <linux/spinlock.h> #include <linux/smp.h> #include <linux/mm.h> -#include <linux/slab.h> #include <linux/kernel_stat.h> #include <asm/errno.h> @@ -72,20 +71,20 @@ static struct irq_chip sb1250_irq_type = { /* Store the CPU id (not the logical number) */ int sb1250_irq_owner[SB1250_NR_IRQS]; -DEFINE_SPINLOCK(sb1250_imr_lock); +static DEFINE_RAW_SPINLOCK(sb1250_imr_lock); void sb1250_mask_irq(int cpu, int irq) { unsigned long flags; u64 cur_ints; - spin_lock_irqsave(&sb1250_imr_lock, flags); + raw_spin_lock_irqsave(&sb1250_imr_lock, flags); cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); cur_ints |= (((u64) 1) << irq); ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); - spin_unlock_irqrestore(&sb1250_imr_lock, flags); + raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags); } void sb1250_unmask_irq(int cpu, int irq) @@ -93,13 +92,13 @@ void sb1250_unmask_irq(int cpu, int irq) unsigned long flags; u64 cur_ints; - spin_lock_irqsave(&sb1250_imr_lock, flags); + raw_spin_lock_irqsave(&sb1250_imr_lock, flags); cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); cur_ints &= ~(((u64) 1) << irq); ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); - spin_unlock_irqrestore(&sb1250_imr_lock, flags); + raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags); } #ifdef CONFIG_SMP @@ -115,7 +114,7 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) cpu = cpu_logical_map(i); /* Protect against other affinity changers and IMR manipulation */ - spin_lock_irqsave(&sb1250_imr_lock, flags); + raw_spin_lock_irqsave(&sb1250_imr_lock, flags); /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = sb1250_irq_owner[irq]; @@ -137,7 +136,7 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); } - spin_unlock_irqrestore(&sb1250_imr_lock, flags); + raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags); return 0; } @@ -237,7 +236,7 @@ void __init init_sb1250_irqs(void) * On the second cpu, everything is set to IP5, which is * ignored, EXCEPT the mailbox interrupt. That one is * set to IP[2] so it is handled. This is needed so we - * can do cross-cpu function calls, as requred by SMP + * can do cross-cpu function calls, as required by SMP */ #define IMR_IP2_VAL K_INT_MAP_I0 diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index 0444da1e23c2..92da3155ce07 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -87,6 +87,21 @@ static int __init setup_bcm1250(void) return ret; } +int sb1250_m3_workaround_needed(void) +{ + switch (soc_type) { + case K_SYS_SOC_TYPE_BCM1250: + case K_SYS_SOC_TYPE_BCM1250_ALT: + case K_SYS_SOC_TYPE_BCM1250_ALT2: + case K_SYS_SOC_TYPE_BCM1125: + case K_SYS_SOC_TYPE_BCM1125H: + return soc_pass < K_SYS_REVISION_BCM1250_C0; + + default: + return 0; + } +} + static int __init setup_bcm112x(void) { int ret = 0; |