diff options
Diffstat (limited to 'arch/mn10300/boot/compressed/head.S')
| -rw-r--r-- | arch/mn10300/boot/compressed/head.S | 69 |
1 files changed, 67 insertions, 2 deletions
diff --git a/arch/mn10300/boot/compressed/head.S b/arch/mn10300/boot/compressed/head.S index 502e1eb56709..7b50345b9e84 100644 --- a/arch/mn10300/boot/compressed/head.S +++ b/arch/mn10300/boot/compressed/head.S @@ -14,10 +14,29 @@ #include <linux/linkage.h> #include <asm/cpu-regs.h> +#include <asm/cache.h> +#ifdef CONFIG_SMP +#include <proc/smp-regs.h> +#endif .globl startup_32 startup_32: - # first save off parameters from bootloader +#ifdef CONFIG_SMP + # + # Secondary CPUs jump directly to the kernel entry point + # + # Must save primary CPU's D0-D2 registers as they hold boot parameters + # + mov (CPUID), d3 + and CPUID_MASK,d3 + beq startup_primary + mov CONFIG_KERNEL_TEXT_ADDRESS,a0 + jmp (a0) + +startup_primary: +#endif /* CONFIG_SMP */ + + # first save parameters from bootloader mov param_save_area,a0 mov d0,(a0) mov d1,(4,a0) @@ -37,8 +56,15 @@ startup_32: mov (a0),d0 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy lne - mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD,d0 # writethru dcache + +#ifdef CONFIG_MN10300_CACHE_ENABLED +#ifdef CONFIG_MN10300_CACHE_WBACK + mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 +#else + mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 +#endif /* WBACK */ movhu d0,(a0) # enable +#endif /* !ENABLED */ # clear the BSS area mov __bss_start,a0 @@ -54,6 +80,9 @@ bssclear_end: # decompress the kernel call decompress_kernel[],0 +#ifdef CONFIG_MN10300_CACHE_WBACK + call mn10300_dcache_flush_inv[],0 +#endif # disable caches again mov CHCTR,a0 @@ -69,10 +98,46 @@ bssclear_end: mov (4,a0),d1 mov (8,a0),d2 + # jump to the kernel proper entry point mov a3,sp mov CONFIG_KERNEL_TEXT_ADDRESS,a0 jmp (a0) + +############################################################################### +# +# Cache flush routines +# +############################################################################### +#ifdef CONFIG_MN10300_CACHE_WBACK +mn10300_dcache_flush_inv: + movhu (CHCTR),d0 + btst CHCTR_DCEN,d0 + beq mn10300_dcache_flush_inv_end + + mov L1_CACHE_NENTRIES,d1 + clr a1 + +mn10300_dcache_flush_inv_loop: + mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge + mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge + mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge + mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge + + add L1_CACHE_BYTES,a1 + add -1,d1 + bne mn10300_dcache_flush_inv_loop + +mn10300_dcache_flush_inv_end: + ret [],0 +#endif /* CONFIG_MN10300_CACHE_WBACK */ + + +############################################################################### +# +# Data areas +# +############################################################################### .data .align 4 param_save_area: |