diff options
Diffstat (limited to 'arch/powerpc/boot/dts')
22 files changed, 1731 insertions, 1338 deletions
diff --git a/arch/powerpc/boot/dts/ep8248e.dts b/arch/powerpc/boot/dts/ep8248e.dts index 5d2fb76a72c1..756758fb5b7b 100644 --- a/arch/powerpc/boot/dts/ep8248e.dts +++ b/arch/powerpc/boot/dts/ep8248e.dts @@ -121,8 +121,7 @@ data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 0x1100 0x1140 - 0xec0 0x9800 0x800>; + reg = <0 0x2000 0x9800 0x800>; }; }; @@ -138,7 +137,7 @@ device_type = "serial"; compatible = "fsl,mpc8248-smc-uart", "fsl,cpm2-smc-uart"; - reg = <0x11a80 0x20 0x1100 0x40>; + reg = <0x11a80 0x20 0x87fc 2>; interrupts = <4 8>; interrupt-parent = <&PIC>; fsl,cpm-brg = <7>; diff --git a/arch/powerpc/boot/dts/ep88xc.dts b/arch/powerpc/boot/dts/ep88xc.dts index 02705f299790..ae57d6240120 100644 --- a/arch/powerpc/boot/dts/ep88xc.dts +++ b/arch/powerpc/boot/dts/ep88xc.dts @@ -2,7 +2,7 @@ * EP88xC Device Tree Source * * Copyright 2006 MontaVista Software, Inc. - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007,2008 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -10,6 +10,7 @@ * option) any later version. */ +/dts-v1/; / { model = "EP88xC"; @@ -23,44 +24,44 @@ PowerPC,885@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <d#16>; - i-cache-line-size = <d#16>; - d-cache-size = <d#8192>; - i-cache-size = <d#8192>; + reg = <0x0>; + d-cache-line-size = <16>; + i-cache-line-size = <16>; + d-cache-size = <8192>; + i-cache-size = <8192>; timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - interrupts = <f 2>; // decrementer interrupt + interrupts = <15 2>; // decrementer interrupt interrupt-parent = <&PIC>; }; }; memory { device_type = "memory"; - reg = <0 0>; + reg = <0x0 0x0>; }; localbus@fa200100 { compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus"; #address-cells = <2>; #size-cells = <1>; - reg = <fa200100 40>; + reg = <0xfa200100 0x40>; ranges = < - 0 0 fc000000 04000000 - 3 0 fa000000 01000000 + 0x0 0x0 0xfc000000 0x4000000 + 0x3 0x0 0xfa000000 0x1000000 >; flash@0,2000000 { compatible = "cfi-flash"; - reg = <0 2000000 2000000>; + reg = <0x0 0x2000000 0x2000000>; bank-width = <4>; device-width = <2>; }; board-control@3,400000 { - reg = <3 400000 10>; + reg = <0x3 0x400000 0x10>; compatible = "fsl,ep88xc-bcsr"; }; }; @@ -70,25 +71,25 @@ #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <0 fa200000 00004000>; + ranges = <0x0 0xfa200000 0x4000>; bus-frequency = <0>; // Temporary -- will go away once kernel uses ranges for get_immrbase(). - reg = <fa200000 4000>; + reg = <0xfa200000 0x4000>; mdio@e00 { compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio"; - reg = <e00 188>; + reg = <0xe00 0x188>; #address-cells = <1>; #size-cells = <0>; PHY0: ethernet-phy@0 { - reg = <0>; + reg = <0x0>; device_type = "ethernet-phy"; }; PHY1: ethernet-phy@1 { - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; }; @@ -97,7 +98,7 @@ device_type = "network"; compatible = "fsl,mpc885-fec-enet", "fsl,pq1-fec-enet"; - reg = <e00 188>; + reg = <0xe00 0x188>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <3 1>; interrupt-parent = <&PIC>; @@ -109,7 +110,7 @@ device_type = "network"; compatible = "fsl,mpc885-fec-enet", "fsl,pq1-fec-enet"; - reg = <1e00 188>; + reg = <0x1e00 0x188>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <7 1>; interrupt-parent = <&PIC>; @@ -120,7 +121,7 @@ PIC: interrupt-controller@0 { interrupt-controller; #interrupt-cells = <2>; - reg = <0 24>; + reg = <0x0 0x24>; compatible = "fsl,mpc885-pic", "fsl,pq1-pic"; }; @@ -130,29 +131,29 @@ #size-cells = <2>; compatible = "fsl,pq-pcmcia"; device_type = "pcmcia"; - reg = <80 80>; + reg = <0x80 0x80>; interrupt-parent = <&PIC>; - interrupts = <d 1>; + interrupts = <13 1>; }; cpm@9c0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc885-cpm", "fsl,cpm1"; - command-proc = <9c0>; + command-proc = <0x9c0>; interrupts = <0>; // cpm error interrupt interrupt-parent = <&CPM_PIC>; - reg = <9c0 40>; + reg = <0x9c0 0x40>; ranges; muram@2000 { #address-cells = <1>; #size-cells = <1>; - ranges = <0 2000 2000>; + ranges = <0x0 0x2000 0x2000>; data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 1c00>; + reg = <0x0 0x1c00>; }; }; @@ -160,7 +161,7 @@ compatible = "fsl,mpc885-brg", "fsl,cpm1-brg", "fsl,cpm-brg"; - reg = <9f0 10>; + reg = <0x9f0 0x10>; }; CPM_PIC: interrupt-controller@930 { @@ -168,7 +169,7 @@ #interrupt-cells = <1>; interrupts = <5 2 0 2>; interrupt-parent = <&PIC>; - reg = <930 20>; + reg = <0x930 0x20>; compatible = "fsl,mpc885-cpm-pic", "fsl,cpm1-pic"; }; @@ -178,11 +179,11 @@ device_type = "serial"; compatible = "fsl,mpc885-smc-uart", "fsl,cpm1-smc-uart"; - reg = <a80 10 3e80 40>; + reg = <0xa80 0x10 0x3e80 0x40>; interrupts = <4>; interrupt-parent = <&CPM_PIC>; fsl,cpm-brg = <1>; - fsl,cpm-command = <0090>; + fsl,cpm-command = <0x90>; linux,planetcore-label = "SMC1"; }; @@ -191,11 +192,11 @@ device_type = "serial"; compatible = "fsl,mpc885-scc-uart", "fsl,cpm1-scc-uart"; - reg = <a20 20 3d00 80>; - interrupts = <1d>; + reg = <0xa20 0x20 0x3d00 0x80>; + interrupts = <29>; interrupt-parent = <&CPM_PIC>; fsl,cpm-brg = <2>; - fsl,cpm-command = <0040>; + fsl,cpm-command = <0x40>; linux,planetcore-label = "SCC2"; }; @@ -204,9 +205,9 @@ #size-cells = <0>; compatible = "fsl,mpc885-usb", "fsl,cpm1-usb"; - reg = <a00 18 1c00 80>; + reg = <0xa00 0x18 0x1c00 0x80>; interrupt-parent = <&CPM_PIC>; - interrupts = <1e>; + interrupts = <30>; fsl,cpm-command = <0000>; }; }; diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts index 446958854519..2e5a1a1812b6 100644 --- a/arch/powerpc/boot/dts/kuroboxHD.dts +++ b/arch/powerpc/boot/dts/kuroboxHD.dts @@ -7,6 +7,7 @@ * Based on sandpoint.dts * * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de> + * Copyright 2008 Freescale Semiconductor, Inc. * * This file is licensed under * the terms of the GNU General Public License version 2. This program @@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ?? */ +/dts-v1/; + / { model = "KuroboxHD"; compatible = "linkstation"; @@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ?? PowerPC,603e { /* Really 8241 */ device_type = "cpu"; - reg = <0>; - clock-frequency = <bebc200>; /* Fixed by bootloader */ - timebase-frequency = <1743000>; /* Fixed by bootloader */ + reg = <0x0>; + clock-frequency = <200000000>; /* Fixed by bootloader */ + timebase-frequency = <24391680>; /* Fixed by bootloader */ bus-frequency = <0>; /* Fixed by bootloader */ /* Following required by dtc but not used */ - i-cache-size = <4000>; - d-cache-size = <4000>; + i-cache-size = <0x4000>; + d-cache-size = <0x4000>; }; }; memory { device_type = "memory"; - reg = <00000000 04000000>; + reg = <0x0 0x4000000>; }; soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ @@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ?? device_type = "soc"; compatible = "mpc10x"; store-gathering = <0>; /* 0 == off, !0 == on */ - reg = <80000000 00100000>; - ranges = <80000000 80000000 70000000 /* pci mem space */ - fc000000 fc000000 00100000 /* EUMB */ - fe000000 fe000000 00c00000 /* pci i/o space */ - fec00000 fec00000 00300000 /* pci cfg regs */ - fef00000 fef00000 00100000>; /* pci iack */ + reg = <0x80000000 0x100000>; + ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */ + 0xfc000000 0xfc000000 0x100000 /* EUMB */ + 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */ + 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */ + 0xfef00000 0xfef00000 0x100000>; /* pci iack */ i2c@80003000 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <80003000 1000>; + reg = <0x80003000 0x1000>; interrupts = <5 2>; interrupt-parent = <&mpic>; rtc@32 { device_type = "rtc"; compatible = "ricoh,rs5c372a"; - reg = <32>; + reg = <0x32>; }; }; @@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ?? cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <80004500 8>; - clock-frequency = <5d08d88>; - current-speed = <2580>; + reg = <0x80004500 0x8>; + clock-frequency = <97553800>; + current-speed = <9600>; interrupts = <9 0>; interrupt-parent = <&mpic>; }; @@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ?? cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <80004600 8>; - clock-frequency = <5d08d88>; - current-speed = <e100>; - interrupts = <a 0>; + reg = <0x80004600 0x8>; + clock-frequency = <97553800>; + current-speed = <57600>; + interrupts = <10 0>; interrupt-parent = <&mpic>; }; @@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ?? device_type = "open-pic"; compatible = "chrp,open-pic"; interrupt-controller; - reg = <80040000 40000>; + reg = <0x80040000 0x40000>; }; pci0: pci@fec00000 { @@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ?? #interrupt-cells = <1>; device_type = "pci"; compatible = "mpc10x-pci"; - reg = <fec00000 400000>; - ranges = <01000000 0 0 fe000000 0 00c00000 - 02000000 0 80000000 80000000 0 70000000>; - bus-range = <0 ff>; - clock-frequency = <7f28155>; + reg = <0xfec00000 0x400000>; + ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000 + 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>; + bus-range = <0 255>; + clock-frequency = <133333333>; interrupt-parent = <&mpic>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 11 - IRQ0 ETH */ - 5800 0 0 1 &mpic 0 1 - 5800 0 0 2 &mpic 1 1 - 5800 0 0 3 &mpic 2 1 - 5800 0 0 4 &mpic 3 1 + 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 12 - IRQ1 IDE0 */ - 6000 0 0 1 &mpic 1 1 - 6000 0 0 2 &mpic 2 1 - 6000 0 0 3 &mpic 3 1 - 6000 0 0 4 &mpic 0 1 + 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1 /* IDSEL 14 - IRQ3 USB2.0 */ - 7000 0 0 1 &mpic 3 1 - 7000 0 0 2 &mpic 3 1 - 7000 0 0 3 &mpic 3 1 - 7000 0 0 4 &mpic 3 1 + 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1 >; }; }; diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts index 8443c85b7b30..e4916e69ad31 100644 --- a/arch/powerpc/boot/dts/kuroboxHG.dts +++ b/arch/powerpc/boot/dts/kuroboxHG.dts @@ -7,6 +7,7 @@ * Based on sandpoint.dts * * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de> + * Copyright 2008 Freescale Semiconductor, Inc. * * This file is licensed under * the terms of the GNU General Public License version 2. This program @@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ?? */ +/dts-v1/; + / { model = "KuroboxHG"; compatible = "linkstation"; @@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ?? PowerPC,603e { /* Really 8241 */ device_type = "cpu"; - reg = <0>; - clock-frequency = <fdad680>; /* Fixed by bootloader */ - timebase-frequency = <1F04000>; /* Fixed by bootloader */ + reg = <0x0>; + clock-frequency = <266000000>; /* Fixed by bootloader */ + timebase-frequency = <32522240>; /* Fixed by bootloader */ bus-frequency = <0>; /* Fixed by bootloader */ /* Following required by dtc but not used */ - i-cache-size = <4000>; - d-cache-size = <4000>; + i-cache-size = <0x4000>; + d-cache-size = <0x4000>; }; }; memory { device_type = "memory"; - reg = <00000000 08000000>; + reg = <0x0 0x8000000>; }; soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ @@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ?? device_type = "soc"; compatible = "mpc10x"; store-gathering = <0>; /* 0 == off, !0 == on */ - reg = <80000000 00100000>; - ranges = <80000000 80000000 70000000 /* pci mem space */ - fc000000 fc000000 00100000 /* EUMB */ - fe000000 fe000000 00c00000 /* pci i/o space */ - fec00000 fec00000 00300000 /* pci cfg regs */ - fef00000 fef00000 00100000>; /* pci iack */ + reg = <0x80000000 0x100000>; + ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */ + 0xfc000000 0xfc000000 0x100000 /* EUMB */ + 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */ + 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */ + 0xfef00000 0xfef00000 0x100000>; /* pci iack */ i2c@80003000 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <80003000 1000>; + reg = <0x80003000 0x1000>; interrupts = <5 2>; interrupt-parent = <&mpic>; rtc@32 { device_type = "rtc"; compatible = "ricoh,rs5c372a"; - reg = <32>; + reg = <0x32>; }; }; @@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ?? cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <80004500 8>; - clock-frequency = <7c044a8>; - current-speed = <2580>; + reg = <0x80004500 0x8>; + clock-frequency = <130041000>; + current-speed = <9600>; interrupts = <9 0>; interrupt-parent = <&mpic>; }; @@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ?? cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <80004600 8>; - clock-frequency = <7c044a8>; - current-speed = <e100>; - interrupts = <a 0>; + reg = <0x80004600 0x8>; + clock-frequency = <130041000>; + current-speed = <57600>; + interrupts = <10 0>; interrupt-parent = <&mpic>; }; @@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ?? device_type = "open-pic"; compatible = "chrp,open-pic"; interrupt-controller; - reg = <80040000 40000>; + reg = <0x80040000 0x40000>; }; pci0: pci@fec00000 { @@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ?? #interrupt-cells = <1>; device_type = "pci"; compatible = "mpc10x-pci"; - reg = <fec00000 400000>; - ranges = <01000000 0 0 fe000000 0 00c00000 - 02000000 0 80000000 80000000 0 70000000>; - bus-range = <0 ff>; - clock-frequency = <7f28155>; + reg = <0xfec00000 0x400000>; + ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000 + 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>; + bus-range = <0 255>; + clock-frequency = <133333333>; interrupt-parent = <&mpic>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 11 - IRQ0 ETH */ - 5800 0 0 1 &mpic 0 1 - 5800 0 0 2 &mpic 1 1 - 5800 0 0 3 &mpic 2 1 - 5800 0 0 4 &mpic 3 1 + 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 12 - IRQ1 IDE0 */ - 6000 0 0 1 &mpic 1 1 - 6000 0 0 2 &mpic 2 1 - 6000 0 0 3 &mpic 3 1 - 6000 0 0 4 &mpic 0 1 + 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1 /* IDSEL 14 - IRQ3 USB2.0 */ - 7000 0 0 1 &mpic 3 1 - 7000 0 0 2 &mpic 3 1 - 7000 0 0 3 &mpic 3 1 - 7000 0 0 4 &mpic 3 1 + 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1 >; }; }; diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts index 8fb542387436..4936349b87cd 100644 --- a/arch/powerpc/boot/dts/mpc7448hpc2.dts +++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts @@ -1,7 +1,7 @@ /* * MPC7448HPC2 (Taiga) board Device Tree Source * - * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2006, 2008 Freescale Semiconductor Inc. * 2006 Roy Zang <Roy Zang at freescale.com>. * * This program is free software; you can redistribute it and/or modify it @@ -10,6 +10,7 @@ * option) any later version. */ +/dts-v1/; / { model = "mpc7448hpc2"; @@ -23,11 +24,11 @@ PowerPC,7448@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K bytes - i-cache-size = <8000>; // L1, 32K bytes + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K bytes + i-cache-size = <0x8000>; // L1, 32K bytes timebase-frequency = <0>; // 33 MHz, from uboot clock-frequency = <0>; // From U-Boot bus-frequency = <0>; // From U-Boot @@ -36,7 +37,7 @@ memory { device_type = "memory"; - reg = <00000000 20000000 // DDR2 512M at 0 + reg = <0x0 0x20000000 // DDR2 512M at 0 >; }; @@ -44,14 +45,14 @@ #address-cells = <1>; #size-cells = <1>; device_type = "tsi-bridge"; - ranges = <00000000 c0000000 00010000>; - reg = <c0000000 00010000>; + ranges = <0x0 0xc0000000 0x10000>; + reg = <0xc0000000 0x10000>; bus-frequency = <0>; i2c@7000 { interrupt-parent = <&mpic>; - interrupts = <E 0>; - reg = <7000 400>; + interrupts = <14 0>; + reg = <0x7000 0x400>; device_type = "i2c"; compatible = "tsi108-i2c"; }; @@ -59,20 +60,20 @@ MDIO: mdio@6000 { device_type = "mdio"; compatible = "tsi108-mdio"; - reg = <6000 50>; + reg = <0x6000 0x50>; #address-cells = <1>; #size-cells = <0>; phy8: ethernet-phy@8 { interrupt-parent = <&mpic>; interrupts = <2 1>; - reg = <8>; + reg = <0x8>; }; phy9: ethernet-phy@9 { interrupt-parent = <&mpic>; interrupts = <2 1>; - reg = <9>; + reg = <0x9>; }; }; @@ -82,9 +83,9 @@ #size-cells = <0>; device_type = "network"; compatible = "tsi108-ethernet"; - reg = <6000 200>; + reg = <0x6000 0x200>; address = [ 00 06 D2 00 00 01 ]; - interrupts = <10 2>; + interrupts = <16 2>; interrupt-parent = <&mpic>; mdio-handle = <&MDIO>; phy-handle = <&phy8>; @@ -96,9 +97,9 @@ #size-cells = <0>; device_type = "network"; compatible = "tsi108-ethernet"; - reg = <6400 200>; + reg = <0x6400 0x200>; address = [ 00 06 D2 00 00 02 ]; - interrupts = <11 2>; + interrupts = <17 2>; interrupt-parent = <&mpic>; mdio-handle = <&MDIO>; phy-handle = <&phy9>; @@ -107,18 +108,18 @@ serial@7808 { device_type = "serial"; compatible = "ns16550"; - reg = <7808 200>; - clock-frequency = <3f6b5a00>; - interrupts = <c 0>; + reg = <0x7808 0x200>; + clock-frequency = <1064000000>; + interrupts = <12 0>; interrupt-parent = <&mpic>; }; serial@7c08 { device_type = "serial"; compatible = "ns16550"; - reg = <7c08 200>; - clock-frequency = <3f6b5a00>; - interrupts = <d 0>; + reg = <0x7c08 0x200>; + clock-frequency = <1064000000>; + interrupts = <13 0>; interrupt-parent = <&mpic>; }; @@ -127,7 +128,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <7400 400>; + reg = <0x7400 0x400>; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -138,39 +139,39 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <1000 1000>; + reg = <0x1000 0x1000>; bus-range = <0 0>; - ranges = <02000000 0 e0000000 e0000000 0 1A000000 - 01000000 0 00000000 fa000000 0 00010000>; - clock-frequency = <7f28154>; + ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000 + 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>; + clock-frequency = <133333332>; interrupt-parent = <&mpic>; - interrupts = <17 2>; - interrupt-map-mask = <f800 0 0 7>; + interrupts = <23 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x11 */ - 0800 0 0 1 &RT0 24 0 - 0800 0 0 2 &RT0 25 0 - 0800 0 0 3 &RT0 26 0 - 0800 0 0 4 &RT0 27 0 + 0x800 0x0 0x0 0x1 &RT0 0x24 0x0 + 0x800 0x0 0x0 0x2 &RT0 0x25 0x0 + 0x800 0x0 0x0 0x3 &RT0 0x26 0x0 + 0x800 0x0 0x0 0x4 &RT0 0x27 0x0 /* IDSEL 0x12 */ - 1000 0 0 1 &RT0 25 0 - 1000 0 0 2 &RT0 26 0 - 1000 0 0 3 &RT0 27 0 - 1000 0 0 4 &RT0 24 0 + 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0 + 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0 + 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0 + 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0 /* IDSEL 0x13 */ - 1800 0 0 1 &RT0 26 0 - 1800 0 0 2 &RT0 27 0 - 1800 0 0 3 &RT0 24 0 - 1800 0 0 4 &RT0 25 0 + 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0 + 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0 + 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0 + 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0 /* IDSEL 0x14 */ - 2000 0 0 1 &RT0 27 0 - 2000 0 0 2 &RT0 24 0 - 2000 0 0 3 &RT0 25 0 - 2000 0 0 4 &RT0 26 0 + 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0 + 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0 + 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0 + 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0 >; RT0: router@1180 { @@ -180,7 +181,7 @@ #address-cells = <0>; #interrupt-cells = <2>; big-endian; - interrupts = <17 2>; + interrupts = <23 2>; interrupt-parent = <&mpic>; }; }; diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts index 7285ca1325fd..46e2da30c3dd 100644 --- a/arch/powerpc/boot/dts/mpc8272ads.dts +++ b/arch/powerpc/boot/dts/mpc8272ads.dts @@ -1,7 +1,7 @@ /* * MPC8272 ADS Device Tree Source * - * Copyright 2005 Freescale Semiconductor Inc. + * Copyright 2005,2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,8 @@ * option) any later version. */ +/dts-v1/; + / { model = "MPC8272ADS"; compatible = "fsl,mpc8272ads"; @@ -21,11 +23,11 @@ PowerPC,8272@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <d#32>; - i-cache-line-size = <d#32>; - d-cache-size = <d#16384>; - i-cache-size = <d#16384>; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <16384>; + i-cache-size = <16384>; timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; @@ -34,7 +36,7 @@ memory { device_type = "memory"; - reg = <0 0>; + reg = <0x0 0x0>; }; localbus@f0010100 { @@ -42,21 +44,21 @@ "fsl,pq2-localbus"; #address-cells = <2>; #size-cells = <1>; - reg = <f0010100 40>; + reg = <0xf0010100 0x40>; - ranges = <0 0 fe000000 02000000 - 1 0 f4500000 00008000 - 3 0 f8200000 00008000>; + ranges = <0x0 0x0 0xfe000000 0x2000000 + 0x1 0x0 0xf4500000 0x8000 + 0x3 0x0 0xf8200000 0x8000>; flash@0,0 { compatible = "jedec-flash"; - reg = <0 0 2000000>; + reg = <0x0 0x0 0x2000000>; bank-width = <4>; device-width = <1>; }; board-control@1,0 { - reg = <1 0 20>; + reg = <0x1 0x0 0x20>; compatible = "fsl,mpc8272ads-bcsr"; }; @@ -65,46 +67,46 @@ "fsl,pq2ads-pci-pic"; #interrupt-cells = <1>; interrupt-controller; - reg = <3 0 8>; + reg = <0x3 0x0 0x8>; interrupt-parent = <&PIC>; - interrupts = <14 8>; + interrupts = <20 8>; }; }; pci@f0010800 { device_type = "pci"; - reg = <f0010800 10c f00101ac 8 f00101c4 8>; + reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; compatible = "fsl,mpc8272-pci", "fsl,pq2-pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - clock-frequency = <d#66666666>; - interrupt-map-mask = <f800 0 0 7>; + clock-frequency = <66666666>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x16 */ - b000 0 0 1 &PCI_PIC 0 - b000 0 0 2 &PCI_PIC 1 - b000 0 0 3 &PCI_PIC 2 - b000 0 0 4 &PCI_PIC 3 + 0xb000 0x0 0x0 0x1 &PCI_PIC 0 + 0xb000 0x0 0x0 0x2 &PCI_PIC 1 + 0xb000 0x0 0x0 0x3 &PCI_PIC 2 + 0xb000 0x0 0x0 0x4 &PCI_PIC 3 /* IDSEL 0x17 */ - b800 0 0 1 &PCI_PIC 4 - b800 0 0 2 &PCI_PIC 5 - b800 0 0 3 &PCI_PIC 6 - b800 0 0 4 &PCI_PIC 7 + 0xb800 0x0 0x0 0x1 &PCI_PIC 4 + 0xb800 0x0 0x0 0x2 &PCI_PIC 5 + 0xb800 0x0 0x0 0x3 &PCI_PIC 6 + 0xb800 0x0 0x0 0x4 &PCI_PIC 7 /* IDSEL 0x18 */ - c000 0 0 1 &PCI_PIC 8 - c000 0 0 2 &PCI_PIC 9 - c000 0 0 3 &PCI_PIC a - c000 0 0 4 &PCI_PIC b>; + 0xc000 0x0 0x0 0x1 &PCI_PIC 8 + 0xc000 0x0 0x0 0x2 &PCI_PIC 9 + 0xc000 0x0 0x0 0x3 &PCI_PIC 10 + 0xc000 0x0 0x0 0x4 &PCI_PIC 11>; interrupt-parent = <&PIC>; - interrupts = <12 8>; - ranges = <42000000 0 80000000 80000000 0 20000000 - 02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 f6000000 0 02000000>; + interrupts = <18 8>; + ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>; }; soc@f0000000 { @@ -112,26 +114,26 @@ #size-cells = <1>; device_type = "soc"; compatible = "fsl,mpc8272", "fsl,pq2-soc"; - ranges = <00000000 f0000000 00053000>; + ranges = <0x0 0xf0000000 0x53000>; // Temporary -- will go away once kernel uses ranges for get_immrbase(). - reg = <f0000000 00053000>; + reg = <0xf0000000 0x53000>; cpm@119c0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; - reg = <119c0 30>; + reg = <0x119c0 0x30>; ranges; muram@0 { #address-cells = <1>; #size-cells = <1>; - ranges = <0 0 10000>; + ranges = <0x0 0x0 0x10000>; data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 2000 9800 800>; + reg = <0x0 0x2000 0x9800 0x800>; }; }; @@ -139,29 +141,29 @@ compatible = "fsl,mpc8272-brg", "fsl,cpm2-brg", "fsl,cpm-brg"; - reg = <119f0 10 115f0 10>; + reg = <0x119f0 0x10 0x115f0 0x10>; }; serial@11a00 { device_type = "serial"; compatible = "fsl,mpc8272-scc-uart", "fsl,cpm2-scc-uart"; - reg = <11a00 20 8000 100>; - interrupts = <28 8>; + reg = <0x11a00 0x20 0x8000 0x100>; + interrupts = <40 8>; interrupt-parent = <&PIC>; fsl,cpm-brg = <1>; - fsl,cpm-command = <00800000>; + fsl,cpm-command = <0x800000>; }; serial@11a60 { device_type = "serial"; compatible = "fsl,mpc8272-scc-uart", "fsl,cpm2-scc-uart"; - reg = <11a60 20 8300 100>; - interrupts = <2b 8>; + reg = <0x11a60 0x20 0x8300 0x100>; + interrupts = <43 8>; interrupt-parent = <&PIC>; fsl,cpm-brg = <4>; - fsl,cpm-command = <0ce00000>; + fsl,cpm-command = <0xce00000>; }; mdio@10d40 { @@ -169,23 +171,23 @@ compatible = "fsl,mpc8272ads-mdio-bitbang", "fsl,mpc8272-mdio-bitbang", "fsl,cpm2-mdio-bitbang"; - reg = <10d40 14>; + reg = <0x10d40 0x14>; #address-cells = <1>; #size-cells = <0>; - fsl,mdio-pin = <12>; - fsl,mdc-pin = <13>; + fsl,mdio-pin = <18>; + fsl,mdc-pin = <19>; PHY0: ethernet-phy@0 { interrupt-parent = <&PIC>; - interrupts = <17 8>; - reg = <0>; + interrupts = <23 8>; + reg = <0x0>; device_type = "ethernet-phy"; }; PHY1: ethernet-phy@1 { interrupt-parent = <&PIC>; - interrupts = <17 8>; - reg = <3>; + interrupts = <23 8>; + reg = <0x3>; device_type = "ethernet-phy"; }; }; @@ -194,33 +196,33 @@ device_type = "network"; compatible = "fsl,mpc8272-fcc-enet", "fsl,cpm2-fcc-enet"; - reg = <11300 20 8400 100 11390 1>; + reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <20 8>; + interrupts = <32 8>; interrupt-parent = <&PIC>; phy-handle = <&PHY0>; linux,network-index = <0>; - fsl,cpm-command = <12000300>; + fsl,cpm-command = <0x12000300>; }; ethernet@11320 { device_type = "network"; compatible = "fsl,mpc8272-fcc-enet", "fsl,cpm2-fcc-enet"; - reg = <11320 20 8500 100 113b0 1>; + reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <21 8>; + interrupts = <33 8>; interrupt-parent = <&PIC>; phy-handle = <&PHY1>; linux,network-index = <1>; - fsl,cpm-command = <16200300>; + fsl,cpm-command = <0x16200300>; }; }; PIC: interrupt-controller@10c00 { #interrupt-cells = <2>; interrupt-controller; - reg = <10c00 80>; + reg = <0x10c00 0x80>; compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic"; }; @@ -232,14 +234,14 @@ "fsl,talitos-sec2", "fsl,talitos", "talitos"; - reg = <30000 10000>; - interrupts = <b 8>; + reg = <0x30000 0x10000>; + interrupts = <11 8>; interrupt-parent = <&PIC>; num-channels = <4>; - channel-fifo-len = <18>; - exec-units-mask = <0000007e>; + channel-fifo-len = <24>; + exec-units-mask = <0x7e>; /* desc mask is for rev1.x, we need runtime fixup for >=2.x */ - descriptor-types-mask = <01010ebf>; + descriptor-types-mask = <0x1010ebf>; }; }; diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts index 9bb408371bcd..539e02fb3526 100644 --- a/arch/powerpc/boot/dts/mpc832x_mds.dts +++ b/arch/powerpc/boot/dts/mpc832x_mds.dts @@ -255,9 +255,7 @@ enet0: ucc@2200 { device_type = "network"; compatible = "ucc_geth"; - model = "UCC"; cell-index = <3>; - device-id = <3>; reg = <0x2200 0x200>; interrupts = <34>; interrupt-parent = <&qeic>; @@ -271,9 +269,7 @@ enet1: ucc@3200 { device_type = "network"; compatible = "ucc_geth"; - model = "UCC"; cell-index = <4>; - device-id = <4>; reg = <0x3200 0x200>; interrupts = <35>; interrupt-parent = <&qeic>; @@ -287,8 +283,7 @@ ucc@2400 { device_type = "serial"; compatible = "ucc_uart"; - model = "UCC"; - device-id = <5>; /* The UCC number, 1-7*/ + cell-index = <5>; /* The UCC number, 1-7*/ port-number = <0>; /* Which ttyQEx device */ soft-uart; /* We need Soft-UART */ reg = <0x2400 0x200>; diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts index 94f93d209de8..179c81c6a7ac 100644 --- a/arch/powerpc/boot/dts/mpc832x_rdb.dts +++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts @@ -208,9 +208,7 @@ enet0: ucc@3000 { device_type = "network"; compatible = "ucc_geth"; - model = "UCC"; cell-index = <2>; - device-id = <2>; reg = <0x3000 0x200>; interrupts = <33>; interrupt-parent = <&qeic>; @@ -224,9 +222,7 @@ enet1: ucc@2200 { device_type = "network"; compatible = "ucc_geth"; - model = "UCC"; cell-index = <3>; - device-id = <3>; reg = <0x2200 0x200>; interrupts = <34>; interrupt-parent = <&qeic>; diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts index 55f03e8dc97f..8160ff24e87e 100644 --- a/arch/powerpc/boot/dts/mpc836x_mds.dts +++ b/arch/powerpc/boot/dts/mpc836x_mds.dts @@ -257,9 +257,7 @@ enet0: ucc@2000 { device_type = "network"; compatible = "ucc_geth"; - model = "UCC"; cell-index = <1>; - device-id = <1>; reg = <0x2000 0x200>; interrupts = <32>; interrupt-parent = <&qeic>; @@ -274,9 +272,7 @@ enet1: ucc@3000 { device_type = "network"; compatible = "ucc_geth"; - model = "UCC"; cell-index = <2>; - device-id = <2>; reg = <0x3000 0x200>; interrupts = <33>; interrupt-parent = <&qeic>; diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts index 975248491b7b..18033ed0b535 100644 --- a/arch/powerpc/boot/dts/mpc8540ads.dts +++ b/arch/powerpc/boot/dts/mpc8540ads.dts @@ -1,7 +1,7 @@ /* * MPC8540 ADS Device Tree Source * - * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2006, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,7 @@ * option) any later version. */ +/dts-v1/; / { model = "MPC8540ADS"; @@ -31,11 +32,11 @@ PowerPC,8540@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot @@ -44,31 +45,31 @@ memory { device_type = "memory"; - reg = <00000000 08000000>; // 128M at 0x0 + reg = <0x0 0x8000000>; // 128M at 0x0 }; soc8540@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = <e0000000 00100000>; // CCSRBAR 1M + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x100000>; // CCSRBAR 1M bus-frequency = <0>; memory-controller@2000 { compatible = "fsl,8540-memory-controller"; - reg = <2000 1000>; + reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <40000>; // L2, 256K + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x40000>; // L2, 256K interrupt-parent = <&mpic>; - interrupts = <10 2>; + interrupts = <16 2>; }; i2c@3000 { @@ -76,8 +77,8 @@ #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; + reg = <0x3000 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -86,24 +87,24 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; - reg = <24520 20>; + reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <0>; + reg = <0x0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; phy3: ethernet-phy@3 { interrupt-parent = <&mpic>; interrupts = <7 1>; - reg = <3>; + reg = <0x3>; device_type = "ethernet-phy"; }; }; @@ -113,9 +114,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <24000 1000>; + reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1d 2 1e 2 22 2>; + interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; }; @@ -125,9 +126,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <25000 1000>; + reg = <0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <23 2 24 2 28 2>; + interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; phy-handle = <&phy1>; }; @@ -137,9 +138,9 @@ device_type = "network"; model = "FEC"; compatible = "gianfar"; - reg = <26000 1000>; + reg = <0x26000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <29 2>; + interrupts = <41 2>; interrupt-parent = <&mpic>; phy-handle = <&phy3>; }; @@ -148,9 +149,9 @@ cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size + reg = <0x4500 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -158,9 +159,9 @@ cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; // reg base, size + reg = <0x4600 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; mpic: pic@40000 { @@ -168,7 +169,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; + reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -177,90 +178,90 @@ pci0: pci@e0008000 { cell-index = <0>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x02 */ - 1000 0 0 1 &mpic 1 1 - 1000 0 0 2 &mpic 2 1 - 1000 0 0 3 &mpic 3 1 - 1000 0 0 4 &mpic 4 1 + 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1 /* IDSEL 0x03 */ - 1800 0 0 1 &mpic 4 1 - 1800 0 0 2 &mpic 1 1 - 1800 0 0 3 &mpic 2 1 - 1800 0 0 4 &mpic 3 1 + 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x04 */ - 2000 0 0 1 &mpic 3 1 - 2000 0 0 2 &mpic 4 1 - 2000 0 0 3 &mpic 1 1 - 2000 0 0 4 &mpic 2 1 + 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x05 */ - 2800 0 0 1 &mpic 2 1 - 2800 0 0 2 &mpic 3 1 - 2800 0 0 3 &mpic 4 1 - 2800 0 0 4 &mpic 1 1 + 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x0c */ - 6000 0 0 1 &mpic 1 1 - 6000 0 0 2 &mpic 2 1 - 6000 0 0 3 &mpic 3 1 - 6000 0 0 4 &mpic 4 1 + 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1 /* IDSEL 0x0d */ - 6800 0 0 1 &mpic 4 1 - 6800 0 0 2 &mpic 1 1 - 6800 0 0 3 &mpic 2 1 - 6800 0 0 4 &mpic 3 1 + 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x0e */ - 7000 0 0 1 &mpic 3 1 - 7000 0 0 2 &mpic 4 1 - 7000 0 0 3 &mpic 1 1 - 7000 0 0 4 &mpic 2 1 + 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x0f */ - 7800 0 0 1 &mpic 2 1 - 7800 0 0 2 &mpic 3 1 - 7800 0 0 3 &mpic 4 1 - 7800 0 0 4 &mpic 1 1 + 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x12 */ - 9000 0 0 1 &mpic 1 1 - 9000 0 0 2 &mpic 2 1 - 9000 0 0 3 &mpic 3 1 - 9000 0 0 4 &mpic 4 1 + 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 /* IDSEL 0x13 */ - 9800 0 0 1 &mpic 4 1 - 9800 0 0 2 &mpic 1 1 - 9800 0 0 3 &mpic 2 1 - 9800 0 0 4 &mpic 3 1 + 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x14 */ - a000 0 0 1 &mpic 3 1 - a000 0 0 2 &mpic 4 1 - a000 0 0 3 &mpic 1 1 - a000 0 0 4 &mpic 2 1 + 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1 + 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1 + 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x15 */ - a800 0 0 1 &mpic 2 1 - a800 0 0 2 &mpic 3 1 - a800 0 0 3 &mpic 4 1 - a800 0 0 4 &mpic 1 1>; + 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1 + 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1 + 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>; interrupt-parent = <&mpic>; - interrupts = <18 2>; + interrupts = <24 2>; bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0008000 1000>; + reg = <0xe0008000 0x1000>; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index fa8d9aaad157..663c7c50ca45 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -1,7 +1,7 @@ /* * MPC8541 CDS Device Tree Source * - * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2006, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,7 @@ * option) any later version. */ +/dts-v1/; / { model = "MPC8541CDS"; @@ -31,11 +32,11 @@ PowerPC,8541@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot @@ -44,31 +45,31 @@ memory { device_type = "memory"; - reg = <00000000 08000000>; // 128M at 0x0 + reg = <0x0 0x8000000>; // 128M at 0x0 }; soc8541@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = <e0000000 00001000>; // CCSRBAR 1M + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; memory-controller@2000 { compatible = "fsl,8541-memory-controller"; - reg = <2000 1000>; + reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; l2-cache-controller@20000 { compatible = "fsl,8541-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <40000>; // L2, 256K + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x40000>; // L2, 256K interrupt-parent = <&mpic>; - interrupts = <10 2>; + interrupts = <16 2>; }; i2c@3000 { @@ -76,8 +77,8 @@ #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; + reg = <0x3000 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -86,18 +87,18 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; - reg = <24520 20>; + reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <0>; + reg = <0x0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; }; @@ -107,9 +108,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <24000 1000>; + reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1d 2 1e 2 22 2>; + interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; }; @@ -119,9 +120,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <25000 1000>; + reg = <0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <23 2 24 2 28 2>; + interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; phy-handle = <&phy1>; }; @@ -130,9 +131,9 @@ cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size + reg = <0x4500 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -140,9 +141,9 @@ cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; // reg base, size + reg = <0x4600 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -151,7 +152,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; + reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -161,17 +162,17 @@ #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; - reg = <919c0 30>; + reg = <0x919c0 0x30>; ranges; muram@80000 { #address-cells = <1>; #size-cells = <1>; - ranges = <0 80000 10000>; + ranges = <0x0 0x80000 0x10000>; data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 2000 9000 1000>; + reg = <0x0 0x2000 0x9000 0x1000>; }; }; @@ -179,16 +180,16 @@ compatible = "fsl,mpc8541-brg", "fsl,cpm2-brg", "fsl,cpm-brg"; - reg = <919f0 10 915f0 10>; + reg = <0x919f0 0x10 0x915f0 0x10>; }; cpmpic: pic@90c00 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - interrupts = <2e 2>; + interrupts = <46 2>; interrupt-parent = <&mpic>; - reg = <90c00 80>; + reg = <0x90c00 0x80>; compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; }; }; @@ -196,68 +197,68 @@ pci0: pci@e0008000 { cell-index = <0>; - interrupt-map-mask = <1f800 0 0 7>; + interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 */ - 08000 0 0 1 &mpic 0 1 - 08000 0 0 2 &mpic 1 1 - 08000 0 0 3 &mpic 2 1 - 08000 0 0 4 &mpic 3 1 + 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x11 */ - 08800 0 0 1 &mpic 0 1 - 08800 0 0 2 &mpic 1 1 - 08800 0 0 3 &mpic 2 1 - 08800 0 0 4 &mpic 3 1 + 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x12 (Slot 1) */ - 09000 0 0 1 &mpic 0 1 - 09000 0 0 2 &mpic 1 1 - 09000 0 0 3 &mpic 2 1 - 09000 0 0 4 &mpic 3 1 + 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x13 (Slot 2) */ - 09800 0 0 1 &mpic 1 1 - 09800 0 0 2 &mpic 2 1 - 09800 0 0 3 &mpic 3 1 - 09800 0 0 4 &mpic 0 1 + 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 /* IDSEL 0x14 (Slot 3) */ - 0a000 0 0 1 &mpic 2 1 - 0a000 0 0 2 &mpic 3 1 - 0a000 0 0 3 &mpic 0 1 - 0a000 0 0 4 &mpic 1 1 + 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 + 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 + 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 + 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x15 (Slot 4) */ - 0a800 0 0 1 &mpic 3 1 - 0a800 0 0 2 &mpic 0 1 - 0a800 0 0 3 &mpic 1 1 - 0a800 0 0 4 &mpic 2 1 + 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 + 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 + 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 + 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 /* Bus 1 (Tundra Bridge) */ /* IDSEL 0x12 (ISA bridge) */ - 19000 0 0 1 &mpic 0 1 - 19000 0 0 2 &mpic 1 1 - 19000 0 0 3 &mpic 2 1 - 19000 0 0 4 &mpic 3 1>; + 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; interrupt-parent = <&mpic>; - interrupts = <18 2>; + interrupts = <24 2>; bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0008000 1000>; + reg = <0xe0008000 0x1000>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; i8259@19000 { interrupt-controller; device_type = "interrupt-controller"; - reg = <19000 0 0 0 1>; + reg = <0x19000 0x0 0x0 0x0 0x1>; #address-cells = <0>; #interrupt-cells = <2>; compatible = "chrp,iic"; @@ -268,24 +269,24 @@ pci1: pci@e0009000 { cell-index = <1>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x15 */ - a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic b 1 - a800 0 0 3 &mpic b 1 - a800 0 0 4 &mpic b 1>; + 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 + 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 + 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 + 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; interrupt-parent = <&mpic>; - interrupts = <19 2>; + interrupts = <25 2>; bus-range = <0 0>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 00100000>; - clock-frequency = <3f940aa>; + ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0009000 1000>; + reg = <0xe0009000 0x1000>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 688af9d06382..6a0d8db96d97 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -1,7 +1,7 @@ /* * MPC8544 DS Device Tree Source * - * Copyright 2007 Freescale Semiconductor Inc. + * Copyright 2007, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,7 @@ * option) any later version. */ +/dts-v1/; / { model = "MPC8544DS"; compatible = "MPC8544DS", "MPC85xxDS"; @@ -27,17 +28,16 @@ }; cpus { - #cpus = <1>; #address-cells = <1>; #size-cells = <0>; PowerPC,8544@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; @@ -46,7 +46,7 @@ memory { device_type = "memory"; - reg = <00000000 00000000>; // Filled by U-Boot + reg = <0x0 0x0>; // Filled by U-Boot }; soc8544@e0000000 { @@ -54,24 +54,24 @@ #size-cells = <1>; device_type = "soc"; - ranges = <00000000 e0000000 00100000>; - reg = <e0000000 00001000>; // CCSRBAR 1M + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; // Filled out by uboot. memory-controller@2000 { compatible = "fsl,8544-memory-controller"; - reg = <2000 1000>; + reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; l2-cache-controller@20000 { compatible = "fsl,8544-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <40000>; // L2, 256K + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x40000>; // L2, 256K interrupt-parent = <&mpic>; - interrupts = <10 2>; + interrupts = <16 2>; }; i2c@3000 { @@ -79,8 +79,8 @@ #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; + reg = <0x3000 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -90,8 +90,8 @@ #size-cells = <0>; cell-index = <1>; compatible = "fsl-i2c"; - reg = <3100 100>; - interrupts = <2b 2>; + reg = <0x3100 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -100,30 +100,71 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; - reg = <24520 20>; + reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; - interrupts = <a 1>; - reg = <0>; + interrupts = <10 1>; + reg = <0x0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; - interrupts = <a 1>; - reg = <1>; + interrupts = <10 1>; + reg = <0x1>; device_type = "ethernet-phy"; }; }; + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8544-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8544-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8544-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8544-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + enet0: ethernet@24000 { cell-index = <0>; device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <24000 1000>; + reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1d 2 1e 2 22 2>; + interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; phy-connection-type = "rgmii-id"; @@ -134,9 +175,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <26000 1000>; + reg = <0x26000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1f 2 20 2 21 2>; + interrupts = <31 2 32 2 33 2>; interrupt-parent = <&mpic>; phy-handle = <&phy1>; phy-connection-type = "rgmii-id"; @@ -146,9 +187,9 @@ cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; + reg = <0x4500 0x100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -156,15 +197,15 @@ cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; + reg = <0x4600 0x100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; global-utilities@e0000 { //global utilities block compatible = "fsl,mpc8548-guts"; - reg = <e0000 1000>; + reg = <0xe0000 0x1000>; fsl,has-rstcr; }; @@ -173,7 +214,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; + reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -184,32 +225,32 @@ cell-index = <0>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x11 J17 Slot 1 */ - 8800 0 0 1 &mpic 2 1 - 8800 0 0 2 &mpic 3 1 - 8800 0 0 3 &mpic 4 1 - 8800 0 0 4 &mpic 1 1 + 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x12 J16 Slot 2 */ - 9000 0 0 1 &mpic 3 1 - 9000 0 0 2 &mpic 4 1 - 9000 0 0 3 &mpic 2 1 - 9000 0 0 4 &mpic 1 1>; + 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>; interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 ff>; - ranges = <02000000 0 c0000000 c0000000 0 20000000 - 01000000 0 00000000 e1000000 0 00010000>; - clock-frequency = <3f940aa>; + interrupts = <24 2>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0008000 1000>; + reg = <0xe0008000 0x1000>; }; pci1: pcie@e0009000 { @@ -219,33 +260,33 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0009000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e1010000 0 00010000>; - clock-frequency = <1fca055>; + reg = <0xe0009000 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>; + clock-frequency = <33333333>; interrupt-parent = <&mpic>; - interrupts = <1a 2>; - interrupt-map-mask = <f800 0 0 7>; + interrupts = <26 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 4 1 - 0000 0 0 2 &mpic 5 1 - 0000 0 0 3 &mpic 6 1 - 0000 0 0 4 &mpic 7 1 + 0000 0x0 0x0 0x1 &mpic 0x4 0x1 + 0000 0x0 0x0 0x2 &mpic 0x5 0x1 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 >; pcie@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <02000000 0 80000000 - 02000000 0 80000000 - 0 20000000 + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00010000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x10000>; }; }; @@ -256,33 +297,33 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e000a000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 e1020000 0 00010000>; - clock-frequency = <1fca055>; + reg = <0xe000a000 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 + 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>; + clock-frequency = <33333333>; interrupt-parent = <&mpic>; - interrupts = <19 2>; - interrupt-map-mask = <f800 0 0 7>; + interrupts = <25 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 0 1 - 0000 0 0 2 &mpic 1 1 - 0000 0 0 3 &mpic 2 1 - 0000 0 0 4 &mpic 3 1 + 0000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0000 0x0 0x0 0x4 &mpic 0x3 0x1 >; pcie@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <02000000 0 a0000000 - 02000000 0 a0000000 - 0 10000000 + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x10000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00010000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x10000>; }; }; @@ -293,72 +334,72 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e000b000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 b0000000 b0000000 0 00100000 - 01000000 0 00000000 b0100000 0 00100000>; - clock-frequency = <1fca055>; + reg = <0xe000b000 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000 + 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>; + clock-frequency = <33333333>; interrupt-parent = <&mpic>; - interrupts = <1b 2>; - interrupt-map-mask = <ff00 0 0 1>; + interrupts = <27 2>; + interrupt-map-mask = <0xff00 0x0 0x0 0x1>; interrupt-map = < // IDSEL 0x1c USB - e000 0 0 1 &i8259 c 2 - e100 0 0 2 &i8259 9 2 - e200 0 0 3 &i8259 a 2 - e300 0 0 4 &i8259 b 2 + 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2 + 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2 + 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2 + 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2 // IDSEL 0x1d Audio - e800 0 0 1 &i8259 6 2 + 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 // IDSEL 0x1e Legacy - f000 0 0 1 &i8259 7 2 - f100 0 0 1 &i8259 7 2 + 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 + 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 // IDSEL 0x1f IDE/SATA - f800 0 0 1 &i8259 e 2 - f900 0 0 1 &i8259 5 2 + 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 + 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 >; pcie@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <02000000 0 b0000000 - 02000000 0 b0000000 - 0 00100000 + ranges = <0x2000000 0x0 0xb0000000 + 0x2000000 0x0 0xb0000000 + 0x0 0x100000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00100000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; uli1575@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; - ranges = <02000000 0 b0000000 - 02000000 0 b0000000 - 0 00100000 + ranges = <0x2000000 0x0 0xb0000000 + 0x2000000 0x0 0xb0000000 + 0x0 0x100000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00100000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; isa@1e { device_type = "isa"; #interrupt-cells = <2>; #size-cells = <1>; #address-cells = <2>; - reg = <f000 0 0 0 0>; - ranges = <1 0 - 01000000 0 0 - 00001000>; + reg = <0xf000 0x0 0x0 0x0 0x0>; + ranges = <0x1 0x0 + 0x1000000 0x0 0x0 + 0x1000>; interrupt-parent = <&i8259>; i8259: interrupt-controller@20 { - reg = <1 20 2 - 1 a0 2 - 1 4d0 2>; + reg = <0x1 0x20 0x2 + 0x1 0xa0 0x2 + 0x1 0x4d0 0x2>; interrupt-controller; device_type = "interrupt-controller"; #address-cells = <0>; @@ -371,28 +412,28 @@ i8042@60 { #size-cells = <0>; #address-cells = <1>; - reg = <1 60 1 1 64 1>; - interrupts = <1 3 c 3>; + reg = <0x1 0x60 0x1 0x1 0x64 0x1>; + interrupts = <1 3 12 3>; interrupt-parent = <&i8259>; keyboard@0 { - reg = <0>; + reg = <0x0>; compatible = "pnpPNP,303"; }; mouse@1 { - reg = <1>; + reg = <0x1>; compatible = "pnpPNP,f03"; }; }; rtc@70 { compatible = "pnpPNP,b00"; - reg = <1 70 2>; + reg = <0x1 0x70 0x2>; }; gpio@400 { - reg = <1 400 80>; + reg = <0x1 0x400 0x80>; }; }; }; diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index 1f470c6a1c63..fa298a8c81cc 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -1,7 +1,7 @@ /* * MPC8548 CDS Device Tree Source * - * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2006, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,7 @@ * option) any later version. */ +/dts-v1/; / { model = "MPC8548CDS"; @@ -36,11 +37,11 @@ PowerPC,8548@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot @@ -49,31 +50,31 @@ memory { device_type = "memory"; - reg = <00000000 08000000>; // 128M at 0x0 + reg = <0x0 0x8000000>; // 128M at 0x0 }; soc8548@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <00000000 e0000000 00100000>; - reg = <e0000000 00001000>; // CCSRBAR + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x1000>; // CCSRBAR bus-frequency = <0>; memory-controller@2000 { compatible = "fsl,8548-memory-controller"; - reg = <2000 1000>; + reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; l2-cache-controller@20000 { compatible = "fsl,8548-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <80000>; // L2, 512K + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K interrupt-parent = <&mpic>; - interrupts = <10 2>; + interrupts = <16 2>; }; i2c@3000 { @@ -81,8 +82,8 @@ #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; + reg = <0x3000 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -92,8 +93,8 @@ #size-cells = <0>; cell-index = <1>; compatible = "fsl-i2c"; - reg = <3100 100>; - interrupts = <2b 2>; + reg = <0x3100 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -102,30 +103,30 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; - reg = <24520 20>; + reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <0>; + reg = <0x0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; phy2: ethernet-phy@2 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <2>; + reg = <0x2>; device_type = "ethernet-phy"; }; phy3: ethernet-phy@3 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <3>; + reg = <0x3>; device_type = "ethernet-phy"; }; }; @@ -135,9 +136,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <24000 1000>; + reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1d 2 1e 2 22 2>; + interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; }; @@ -147,9 +148,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <25000 1000>; + reg = <0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <23 2 24 2 28 2>; + interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; phy-handle = <&phy1>; }; @@ -160,9 +161,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <26000 1000>; + reg = <0x26000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1f 2 20 2 21 2>; + interrupts = <31 2 32 2 33 2>; interrupt-parent = <&mpic>; phy-handle = <&phy2>; }; @@ -172,9 +173,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <27000 1000>; + reg = <0x27000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <25 2 26 2 27 2>; + interrupts = <37 2 38 2 39 2>; interrupt-parent = <&mpic>; phy-handle = <&phy3>; }; @@ -184,9 +185,9 @@ cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size + reg = <0x4500 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -194,15 +195,15 @@ cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; // reg base, size + reg = <0x4600 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; global-utilities@e0000 { //global utilities reg compatible = "fsl,mpc8548-guts"; - reg = <e0000 1000>; + reg = <0xe0000 0x1000>; fsl,has-rstcr; }; @@ -211,7 +212,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; + reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -220,139 +221,139 @@ pci0: pci@e0008000 { cell-index = <0>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x4 (PCIX Slot 2) */ - 02000 0 0 1 &mpic 0 1 - 02000 0 0 2 &mpic 1 1 - 02000 0 0 3 &mpic 2 1 - 02000 0 0 4 &mpic 3 1 + 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x5 (PCIX Slot 3) */ - 02800 0 0 1 &mpic 1 1 - 02800 0 0 2 &mpic 2 1 - 02800 0 0 3 &mpic 3 1 - 02800 0 0 4 &mpic 0 1 + 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 /* IDSEL 0x6 (PCIX Slot 4) */ - 03000 0 0 1 &mpic 2 1 - 03000 0 0 2 &mpic 3 1 - 03000 0 0 3 &mpic 0 1 - 03000 0 0 4 &mpic 1 1 + 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 + 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x8 (PCIX Slot 5) */ - 04000 0 0 1 &mpic 0 1 - 04000 0 0 2 &mpic 1 1 - 04000 0 0 3 &mpic 2 1 - 04000 0 0 4 &mpic 3 1 + 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0xC (Tsi310 bridge) */ - 06000 0 0 1 &mpic 0 1 - 06000 0 0 2 &mpic 1 1 - 06000 0 0 3 &mpic 2 1 - 06000 0 0 4 &mpic 3 1 + 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x14 (Slot 2) */ - 0a000 0 0 1 &mpic 0 1 - 0a000 0 0 2 &mpic 1 1 - 0a000 0 0 3 &mpic 2 1 - 0a000 0 0 4 &mpic 3 1 + 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x15 (Slot 3) */ - 0a800 0 0 1 &mpic 1 1 - 0a800 0 0 2 &mpic 2 1 - 0a800 0 0 3 &mpic 3 1 - 0a800 0 0 4 &mpic 0 1 + 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 + 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 + 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 + 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 /* IDSEL 0x16 (Slot 4) */ - 0b000 0 0 1 &mpic 2 1 - 0b000 0 0 2 &mpic 3 1 - 0b000 0 0 3 &mpic 0 1 - 0b000 0 0 4 &mpic 1 1 + 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 + 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 + 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 + 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x18 (Slot 5) */ - 0c000 0 0 1 &mpic 0 1 - 0c000 0 0 2 &mpic 1 1 - 0c000 0 0 3 &mpic 2 1 - 0c000 0 0 4 &mpic 3 1 + 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ - 0E000 0 0 1 &mpic 0 1 - 0E000 0 0 2 &mpic 1 1 - 0E000 0 0 3 &mpic 2 1 - 0E000 0 0 4 &mpic 3 1>; + 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>; interrupt-parent = <&mpic>; - interrupts = <18 2>; + interrupts = <24 2>; bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 10000000 - 01000000 0 00000000 e2000000 0 00800000>; - clock-frequency = <3f940aa>; + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000 + 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0008000 1000>; + reg = <0xe0008000 0x1000>; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; pci_bridge@1c { - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x00 (PrPMC Site) */ - 0000 0 0 1 &mpic 0 1 - 0000 0 0 2 &mpic 1 1 - 0000 0 0 3 &mpic 2 1 - 0000 0 0 4 &mpic 3 1 + 0000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x04 (VIA chip) */ - 2000 0 0 1 &mpic 0 1 - 2000 0 0 2 &mpic 1 1 - 2000 0 0 3 &mpic 2 1 - 2000 0 0 4 &mpic 3 1 + 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x05 (8139) */ - 2800 0 0 1 &mpic 1 1 + 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 /* IDSEL 0x06 (Slot 6) */ - 3000 0 0 1 &mpic 2 1 - 3000 0 0 2 &mpic 3 1 - 3000 0 0 3 &mpic 0 1 - 3000 0 0 4 &mpic 1 1 + 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 + 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDESL 0x07 (Slot 7) */ - 3800 0 0 1 &mpic 3 1 - 3800 0 0 2 &mpic 0 1 - 3800 0 0 3 &mpic 1 1 - 3800 0 0 4 &mpic 2 1>; + 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 + 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>; - reg = <e000 0 0 0 0>; + reg = <0xe000 0x0 0x0 0x0 0x0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - ranges = <02000000 0 80000000 - 02000000 0 80000000 - 0 20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00080000>; - clock-frequency = <1fca055>; + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x80000>; + clock-frequency = <33333333>; isa@4 { device_type = "isa"; #interrupt-cells = <2>; #size-cells = <1>; #address-cells = <2>; - reg = <2000 0 0 0 0>; - ranges = <1 0 01000000 0 0 00001000>; + reg = <0x2000 0x0 0x0 0x0 0x0>; + ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>; interrupt-parent = <&i8259>; i8259: interrupt-controller@20 { interrupt-controller; device_type = "interrupt-controller"; - reg = <1 20 2 - 1 a0 2 - 1 4d0 2>; + reg = <0x1 0x20 0x2 + 0x1 0xa0 0x2 + 0x1 0x4d0 0x2>; #address-cells = <0>; #interrupt-cells = <2>; compatible = "chrp,iic"; @@ -362,7 +363,7 @@ rtc@70 { compatible = "pnpPNP,b00"; - reg = <1 70 2>; + reg = <0x1 0x70 0x2>; }; }; }; @@ -370,64 +371,64 @@ pci1: pci@e0009000 { cell-index = <1>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x15 */ - a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic 1 1 - a800 0 0 3 &mpic 2 1 - a800 0 0 4 &mpic 3 1>; + 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 + 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>; interrupt-parent = <&mpic>; - interrupts = <19 2>; + interrupts = <25 2>; bus-range = <0 0>; - ranges = <02000000 0 90000000 90000000 0 10000000 - 01000000 0 00000000 e2800000 0 00800000>; - clock-frequency = <3f940aa>; + ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000 + 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0009000 1000>; + reg = <0xe0009000 0x1000>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; pci2: pcie@e000a000 { cell-index = <2>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 (PEX) */ - 00000 0 0 1 &mpic 0 1 - 00000 0 0 2 &mpic 1 1 - 00000 0 0 3 &mpic 2 1 - 00000 0 0 4 &mpic 3 1>; + 00000 0x0 0x0 0x1 &mpic 0x0 0x1 + 00000 0x0 0x0 0x2 &mpic 0x1 0x1 + 00000 0x0 0x0 0x3 &mpic 0x2 0x1 + 00000 0x0 0x0 0x4 &mpic 0x3 0x1>; interrupt-parent = <&mpic>; - interrupts = <1a 2>; - bus-range = <0 ff>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 08000000>; - clock-frequency = <1fca055>; + interrupts = <26 2>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>; + clock-frequency = <33333333>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e000a000 1000>; + reg = <0xe000a000 0x1000>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; pcie@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <02000000 0 a0000000 - 02000000 0 a0000000 - 0 20000000 + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 08000000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x8000000>; }; }; }; diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts index 4538f3c38862..b025c566c10d 100644 --- a/arch/powerpc/boot/dts/mpc8555cds.dts +++ b/arch/powerpc/boot/dts/mpc8555cds.dts @@ -1,7 +1,7 @@ /* * MPC8555 CDS Device Tree Source * - * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2006, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,7 @@ * option) any later version. */ +/dts-v1/; / { model = "MPC8555CDS"; @@ -31,11 +32,11 @@ PowerPC,8555@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot @@ -44,31 +45,31 @@ memory { device_type = "memory"; - reg = <00000000 08000000>; // 128M at 0x0 + reg = <0x0 0x8000000>; // 128M at 0x0 }; soc8555@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = <e0000000 00001000>; // CCSRBAR 1M + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x1000>; // CCSRBAR 1M bus-frequency = <0>; memory-controller@2000 { compatible = "fsl,8555-memory-controller"; - reg = <2000 1000>; + reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; l2-cache-controller@20000 { compatible = "fsl,8555-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <40000>; // L2, 256K + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x40000>; // L2, 256K interrupt-parent = <&mpic>; - interrupts = <10 2>; + interrupts = <16 2>; }; i2c@3000 { @@ -76,8 +77,8 @@ #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; + reg = <0x3000 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -86,18 +87,18 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; - reg = <24520 20>; + reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <0>; + reg = <0x0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; }; @@ -107,9 +108,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <24000 1000>; + reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1d 2 1e 2 22 2>; + interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; }; @@ -119,9 +120,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <25000 1000>; + reg = <0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <23 2 24 2 28 2>; + interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; phy-handle = <&phy1>; }; @@ -130,9 +131,9 @@ cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size + reg = <0x4500 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -140,9 +141,9 @@ cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; // reg base, size + reg = <0x4600 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -151,7 +152,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; + reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -161,17 +162,17 @@ #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; - reg = <919c0 30>; + reg = <0x919c0 0x30>; ranges; muram@80000 { #address-cells = <1>; #size-cells = <1>; - ranges = <0 80000 10000>; + ranges = <0x0 0x80000 0x10000>; data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 2000 9000 1000>; + reg = <0x0 0x2000 0x9000 0x1000>; }; }; @@ -179,16 +180,16 @@ compatible = "fsl,mpc8555-brg", "fsl,cpm2-brg", "fsl,cpm-brg"; - reg = <919f0 10 915f0 10>; + reg = <0x919f0 0x10 0x915f0 0x10>; }; cpmpic: pic@90c00 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - interrupts = <2e 2>; + interrupts = <46 2>; interrupt-parent = <&mpic>; - reg = <90c00 80>; + reg = <0x90c00 0x80>; compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; }; }; @@ -196,68 +197,68 @@ pci0: pci@e0008000 { cell-index = <0>; - interrupt-map-mask = <1f800 0 0 7>; + interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 */ - 08000 0 0 1 &mpic 0 1 - 08000 0 0 2 &mpic 1 1 - 08000 0 0 3 &mpic 2 1 - 08000 0 0 4 &mpic 3 1 + 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x11 */ - 08800 0 0 1 &mpic 0 1 - 08800 0 0 2 &mpic 1 1 - 08800 0 0 3 &mpic 2 1 - 08800 0 0 4 &mpic 3 1 + 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x12 (Slot 1) */ - 09000 0 0 1 &mpic 0 1 - 09000 0 0 2 &mpic 1 1 - 09000 0 0 3 &mpic 2 1 - 09000 0 0 4 &mpic 3 1 + 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x13 (Slot 2) */ - 09800 0 0 1 &mpic 1 1 - 09800 0 0 2 &mpic 2 1 - 09800 0 0 3 &mpic 3 1 - 09800 0 0 4 &mpic 0 1 + 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 /* IDSEL 0x14 (Slot 3) */ - 0a000 0 0 1 &mpic 2 1 - 0a000 0 0 2 &mpic 3 1 - 0a000 0 0 3 &mpic 0 1 - 0a000 0 0 4 &mpic 1 1 + 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 + 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 + 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 + 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x15 (Slot 4) */ - 0a800 0 0 1 &mpic 3 1 - 0a800 0 0 2 &mpic 0 1 - 0a800 0 0 3 &mpic 1 1 - 0a800 0 0 4 &mpic 2 1 + 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 + 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 + 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 + 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 /* Bus 1 (Tundra Bridge) */ /* IDSEL 0x12 (ISA bridge) */ - 19000 0 0 1 &mpic 0 1 - 19000 0 0 2 &mpic 1 1 - 19000 0 0 3 &mpic 2 1 - 19000 0 0 4 &mpic 3 1>; + 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; interrupt-parent = <&mpic>; - interrupts = <18 2>; + interrupts = <24 2>; bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0008000 1000>; + reg = <0xe0008000 0x1000>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; i8259@19000 { interrupt-controller; device_type = "interrupt-controller"; - reg = <19000 0 0 0 1>; + reg = <0x19000 0x0 0x0 0x0 0x1>; #address-cells = <0>; #interrupt-cells = <2>; compatible = "chrp,iic"; @@ -268,24 +269,24 @@ pci1: pci@e0009000 { cell-index = <1>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x15 */ - a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic b 1 - a800 0 0 3 &mpic b 1 - a800 0 0 4 &mpic b 1>; + 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 + 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 + 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 + 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; interrupt-parent = <&mpic>; - interrupts = <19 2>; + interrupts = <25 2>; bus-range = <0 0>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 00100000>; - clock-frequency = <3f940aa>; + ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0009000 1000>; + reg = <0xe0009000 0x1000>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index 639ce8a709a6..0cc16ab305d1 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -1,7 +1,7 @@ /* * MPC8560 ADS Device Tree Source * - * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2006, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,7 @@ * option) any later version. */ +/dts-v1/; / { model = "MPC8560ADS"; @@ -32,74 +33,74 @@ PowerPC,8560@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K - timebase-frequency = <04ead9a0>; - bus-frequency = <13ab6680>; - clock-frequency = <312c8040>; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <82500000>; + bus-frequency = <330000000>; + clock-frequency = <825000000>; }; }; memory { device_type = "memory"; - reg = <00000000 10000000>; + reg = <0x0 0x10000000>; }; soc8560@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = <e0000000 00000200>; - bus-frequency = <13ab6680>; + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x200>; + bus-frequency = <330000000>; memory-controller@2000 { compatible = "fsl,8540-memory-controller"; - reg = <2000 1000>; + reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; l2-cache-controller@20000 { compatible = "fsl,8540-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <40000>; // L2, 256K + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x40000>; // L2, 256K interrupt-parent = <&mpic>; - interrupts = <10 2>; + interrupts = <16 2>; }; mdio@24520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; - reg = <24520 20>; + reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <0>; + reg = <0x0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; interrupts = <5 1>; - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; phy2: ethernet-phy@2 { interrupt-parent = <&mpic>; interrupts = <7 1>; - reg = <2>; + reg = <0x2>; device_type = "ethernet-phy"; }; phy3: ethernet-phy@3 { interrupt-parent = <&mpic>; interrupts = <7 1>; - reg = <3>; + reg = <0x3>; device_type = "ethernet-phy"; }; }; @@ -109,9 +110,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <24000 1000>; + reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1d 2 1e 2 22 2>; + interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; }; @@ -121,9 +122,9 @@ device_type = "network"; model = "TSEC"; compatible = "gianfar"; - reg = <25000 1000>; + reg = <0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <23 2 24 2 28 2>; + interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; phy-handle = <&phy1>; }; @@ -132,7 +133,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; + reg = <0x40000 0x40000>; device_type = "open-pic"; }; @@ -140,17 +141,17 @@ #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8560-cpm", "fsl,cpm2"; - reg = <919c0 30>; + reg = <0x919c0 0x30>; ranges; muram@80000 { #address-cells = <1>; #size-cells = <1>; - ranges = <0 80000 10000>; + ranges = <0x0 0x80000 0x10000>; data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 4000 9000 2000>; + reg = <0x0 0x4000 0x9000 0x2000>; }; }; @@ -158,17 +159,17 @@ compatible = "fsl,mpc8560-brg", "fsl,cpm2-brg", "fsl,cpm-brg"; - reg = <919f0 10 915f0 10>; - clock-frequency = <d#165000000>; + reg = <0x919f0 0x10 0x915f0 0x10>; + clock-frequency = <165000000>; }; cpmpic: pic@90c00 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - interrupts = <2e 2>; + interrupts = <46 2>; interrupt-parent = <&mpic>; - reg = <90c00 80>; + reg = <0x90c00 0x80>; compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; }; @@ -176,11 +177,11 @@ device_type = "serial"; compatible = "fsl,mpc8560-scc-uart", "fsl,cpm2-scc-uart"; - reg = <91a00 20 88000 100>; + reg = <0x91a00 0x20 0x88000 0x100>; fsl,cpm-brg = <1>; - fsl,cpm-command = <00800000>; - current-speed = <1c200>; - interrupts = <28 8>; + fsl,cpm-command = <0x800000>; + current-speed = <115200>; + interrupts = <40 8>; interrupt-parent = <&cpmpic>; }; @@ -188,11 +189,11 @@ device_type = "serial"; compatible = "fsl,mpc8560-scc-uart", "fsl,cpm2-scc-uart"; - reg = <91a20 20 88100 100>; + reg = <0x91a20 0x20 0x88100 0x100>; fsl,cpm-brg = <2>; - fsl,cpm-command = <04a00000>; - current-speed = <1c200>; - interrupts = <29 8>; + fsl,cpm-command = <0x4a00000>; + current-speed = <115200>; + interrupts = <41 8>; interrupt-parent = <&cpmpic>; }; @@ -200,10 +201,10 @@ device_type = "network"; compatible = "fsl,mpc8560-fcc-enet", "fsl,cpm2-fcc-enet"; - reg = <91320 20 88500 100 913b0 1>; + reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>; local-mac-address = [ 00 00 00 00 00 00 ]; - fsl,cpm-command = <16200300>; - interrupts = <21 8>; + fsl,cpm-command = <0x16200300>; + interrupts = <33 8>; interrupt-parent = <&cpmpic>; phy-handle = <&phy2>; }; @@ -212,10 +213,10 @@ device_type = "network"; compatible = "fsl,mpc8560-fcc-enet", "fsl,cpm2-fcc-enet"; - reg = <91340 20 88600 100 913d0 1>; + reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>; local-mac-address = [ 00 00 00 00 00 00 ]; - fsl,cpm-command = <1a400300>; - interrupts = <22 8>; + fsl,cpm-command = <0x1a400300>; + interrupts = <34 8>; interrupt-parent = <&cpmpic>; phy-handle = <&phy3>; }; @@ -229,87 +230,87 @@ #address-cells = <3>; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; device_type = "pci"; - reg = <e0008000 1000>; - clock-frequency = <3f940aa>; - interrupt-map-mask = <f800 0 0 7>; + reg = <0xe0008000 0x1000>; + clock-frequency = <66666666>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x2 */ - 1000 0 0 1 &mpic 1 1 - 1000 0 0 2 &mpic 2 1 - 1000 0 0 3 &mpic 3 1 - 1000 0 0 4 &mpic 4 1 + 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1 /* IDSEL 0x3 */ - 1800 0 0 1 &mpic 4 1 - 1800 0 0 2 &mpic 1 1 - 1800 0 0 3 &mpic 2 1 - 1800 0 0 4 &mpic 3 1 + 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x4 */ - 2000 0 0 1 &mpic 3 1 - 2000 0 0 2 &mpic 4 1 - 2000 0 0 3 &mpic 1 1 - 2000 0 0 4 &mpic 2 1 + 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x5 */ - 2800 0 0 1 &mpic 2 1 - 2800 0 0 2 &mpic 3 1 - 2800 0 0 3 &mpic 4 1 - 2800 0 0 4 &mpic 1 1 + 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 12 */ - 6000 0 0 1 &mpic 1 1 - 6000 0 0 2 &mpic 2 1 - 6000 0 0 3 &mpic 3 1 - 6000 0 0 4 &mpic 4 1 + 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1 /* IDSEL 13 */ - 6800 0 0 1 &mpic 4 1 - 6800 0 0 2 &mpic 1 1 - 6800 0 0 3 &mpic 2 1 - 6800 0 0 4 &mpic 3 1 + 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 14*/ - 7000 0 0 1 &mpic 3 1 - 7000 0 0 2 &mpic 4 1 - 7000 0 0 3 &mpic 1 1 - 7000 0 0 4 &mpic 2 1 + 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 15 */ - 7800 0 0 1 &mpic 2 1 - 7800 0 0 2 &mpic 3 1 - 7800 0 0 3 &mpic 4 1 - 7800 0 0 4 &mpic 1 1 + 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 18 */ - 9000 0 0 1 &mpic 1 1 - 9000 0 0 2 &mpic 2 1 - 9000 0 0 3 &mpic 3 1 - 9000 0 0 4 &mpic 4 1 + 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1 + 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1 + 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1 + 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 /* IDSEL 19 */ - 9800 0 0 1 &mpic 4 1 - 9800 0 0 2 &mpic 1 1 - 9800 0 0 3 &mpic 2 1 - 9800 0 0 4 &mpic 3 1 + 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1 + 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1 + 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1 + 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 20 */ - a000 0 0 1 &mpic 3 1 - a000 0 0 2 &mpic 4 1 - a000 0 0 3 &mpic 1 1 - a000 0 0 4 &mpic 2 1 + 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1 + 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1 + 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 21 */ - a800 0 0 1 &mpic 2 1 - a800 0 0 2 &mpic 3 1 - a800 0 0 3 &mpic 4 1 - a800 0 0 4 &mpic 1 1>; + 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1 + 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1 + 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>; interrupt-parent = <&mpic>; - interrupts = <18 2>; + interrupts = <24 2>; bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 01000000>; + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>; }; }; diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts index 97bc048f2158..a025a8ededc5 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -1,7 +1,7 @@ /* * MPC8568E MDS Device Tree Source * - * Copyright 2007 Freescale Semiconductor Inc. + * Copyright 2007, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,10 +9,7 @@ * option) any later version. */ - -/* -/memreserve/ 00000000 1000000; -*/ +/dts-v1/; / { model = "MPC8568EMDS"; @@ -37,11 +34,11 @@ PowerPC,8568@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; @@ -50,36 +47,36 @@ memory { device_type = "memory"; - reg = <00000000 10000000>; + reg = <0x0 0x10000000>; }; bcsr@f8000000 { device_type = "board-control"; - reg = <f8000000 8000>; + reg = <0xf8000000 0x8000>; }; soc8568@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = <e0000000 00001000>; + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x1000>; bus-frequency = <0>; memory-controller@2000 { compatible = "fsl,8568-memory-controller"; - reg = <2000 1000>; + reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; l2-cache-controller@20000 { compatible = "fsl,8568-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <80000>; // L2, 512K + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K interrupt-parent = <&mpic>; - interrupts = <10 2>; + interrupts = <16 2>; }; i2c@3000 { @@ -87,14 +84,14 @@ #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; + reg = <0x3000 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; rtc@68 { compatible = "dallas,ds1374"; - reg = <68>; + reg = <0x68>; }; }; @@ -103,8 +100,8 @@ #size-cells = <0>; cell-index = <1>; compatible = "fsl-i2c"; - reg = <3100 100>; - interrupts = <2b 2>; + reg = <0x3100 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -113,30 +110,30 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; - reg = <24520 20>; + reg = <0x24520 0x20>; phy0: ethernet-phy@7 { interrupt-parent = <&mpic>; interrupts = <1 1>; - reg = <7>; + reg = <0x7>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; interrupts = <2 1>; - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; phy2: ethernet-phy@2 { interrupt-parent = <&mpic>; interrupts = <1 1>; - reg = <2>; + reg = <0x2>; device_type = "ethernet-phy"; }; phy3: ethernet-phy@3 { interrupt-parent = <&mpic>; interrupts = <2 1>; - reg = <3>; + reg = <0x3>; device_type = "ethernet-phy"; }; }; @@ -146,9 +143,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <24000 1000>; + reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1d 2 1e 2 22 2>; + interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; phy-handle = <&phy2>; }; @@ -158,9 +155,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <25000 1000>; + reg = <0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <23 2 24 2 28 2>; + interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; phy-handle = <&phy3>; }; @@ -169,15 +166,15 @@ cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; + reg = <0x4500 0x100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; global-utilities@e0000 { //global utilities block compatible = "fsl,mpc8548-guts"; - reg = <e0000 1000>; + reg = <0xe0000 0x1000>; fsl,has-rstcr; }; @@ -185,9 +182,9 @@ cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; + reg = <0x4600 0x100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -195,13 +192,13 @@ device_type = "crypto"; model = "SEC2"; compatible = "talitos"; - reg = <30000 f000>; - interrupts = <2d 2>; + reg = <0x30000 0xf000>; + interrupts = <45 2>; interrupt-parent = <&mpic>; num-channels = <4>; - channel-fifo-len = <18>; - exec-units-mask = <000000fe>; - descriptor-types-mask = <012b0ebf>; + channel-fifo-len = <24>; + exec-units-mask = <0xfe>; + descriptor-types-mask = <0x12b0ebf>; }; mpic: pic@40000 { @@ -209,73 +206,73 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; + reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; }; par_io@e0100 { - reg = <e0100 100>; + reg = <0xe0100 0x100>; device_type = "par_io"; num-ports = <7>; pio1: ucc_pin@01 { pio-map = < /* port pin dir open_drain assignment has_irq */ - 4 0a 1 0 2 0 /* TxD0 */ - 4 09 1 0 2 0 /* TxD1 */ - 4 08 1 0 2 0 /* TxD2 */ - 4 07 1 0 2 0 /* TxD3 */ - 4 17 1 0 2 0 /* TxD4 */ - 4 16 1 0 2 0 /* TxD5 */ - 4 15 1 0 2 0 /* TxD6 */ - 4 14 1 0 2 0 /* TxD7 */ - 4 0f 2 0 2 0 /* RxD0 */ - 4 0e 2 0 2 0 /* RxD1 */ - 4 0d 2 0 2 0 /* RxD2 */ - 4 0c 2 0 2 0 /* RxD3 */ - 4 1d 2 0 2 0 /* RxD4 */ - 4 1c 2 0 2 0 /* RxD5 */ - 4 1b 2 0 2 0 /* RxD6 */ - 4 1a 2 0 2 0 /* RxD7 */ - 4 0b 1 0 2 0 /* TX_EN */ - 4 18 1 0 2 0 /* TX_ER */ - 4 10 2 0 2 0 /* RX_DV */ - 4 1e 2 0 2 0 /* RX_ER */ - 4 11 2 0 2 0 /* RX_CLK */ - 4 13 1 0 2 0 /* GTX_CLK */ - 1 1f 2 0 3 0>; /* GTX125 */ + 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */ + 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */ + 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */ + 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */ + 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */ + 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */ + 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */ + 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */ + 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */ + 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */ + 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */ + 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */ + 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */ + 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */ + 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */ + 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */ + 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */ + 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */ + 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */ + 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */ + 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */ + 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */ + 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */ }; pio2: ucc_pin@02 { pio-map = < /* port pin dir open_drain assignment has_irq */ - 5 0a 1 0 2 0 /* TxD0 */ - 5 09 1 0 2 0 /* TxD1 */ - 5 08 1 0 2 0 /* TxD2 */ - 5 07 1 0 2 0 /* TxD3 */ - 5 17 1 0 2 0 /* TxD4 */ - 5 16 1 0 2 0 /* TxD5 */ - 5 15 1 0 2 0 /* TxD6 */ - 5 14 1 0 2 0 /* TxD7 */ - 5 0f 2 0 2 0 /* RxD0 */ - 5 0e 2 0 2 0 /* RxD1 */ - 5 0d 2 0 2 0 /* RxD2 */ - 5 0c 2 0 2 0 /* RxD3 */ - 5 1d 2 0 2 0 /* RxD4 */ - 5 1c 2 0 2 0 /* RxD5 */ - 5 1b 2 0 2 0 /* RxD6 */ - 5 1a 2 0 2 0 /* RxD7 */ - 5 0b 1 0 2 0 /* TX_EN */ - 5 18 1 0 2 0 /* TX_ER */ - 5 10 2 0 2 0 /* RX_DV */ - 5 1e 2 0 2 0 /* RX_ER */ - 5 11 2 0 2 0 /* RX_CLK */ - 5 13 1 0 2 0 /* GTX_CLK */ - 1 1f 2 0 3 0 /* GTX125 */ - 4 06 3 0 2 0 /* MDIO */ - 4 05 1 0 2 0>; /* MDC */ + 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */ + 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */ + 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */ + 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */ + 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */ + 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */ + 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */ + 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */ + 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */ + 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */ + 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */ + 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */ + 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */ + 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */ + 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */ + 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */ + 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */ + 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */ + 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */ + 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */ + 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */ + 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */ + 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */ + 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */ + 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */ }; }; }; @@ -285,28 +282,28 @@ #size-cells = <1>; device_type = "qe"; compatible = "fsl,qe"; - ranges = <0 e0080000 00040000>; - reg = <e0080000 480>; + ranges = <0x0 0xe0080000 0x40000>; + reg = <0xe0080000 0x480>; brg-frequency = <0>; - bus-frequency = <179A7B00>; + bus-frequency = <396000000>; muram@10000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,qe-muram", "fsl,cpm-muram"; - ranges = <0 00010000 0000c000>; + ranges = <0x0 0x10000 0x10000>; data-only@0 { compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data"; - reg = <0 c000>; + reg = <0x0 0x10000>; }; }; spi@4c0 { cell-index = <0>; compatible = "fsl,spi"; - reg = <4c0 40>; + reg = <0x4c0 0x40>; interrupts = <2>; interrupt-parent = <&qeic>; mode = "cpu"; @@ -315,7 +312,7 @@ spi@500 { cell-index = <1>; compatible = "fsl,spi"; - reg = <500 40>; + reg = <0x500 0x40>; interrupts = <1>; interrupt-parent = <&qeic>; mode = "cpu"; @@ -324,11 +321,9 @@ enet2: ucc@2000 { device_type = "network"; compatible = "ucc_geth"; - model = "UCC"; cell-index = <1>; - device-id = <1>; - reg = <2000 200>; - interrupts = <20>; + reg = <0x2000 0x200>; + interrupts = <32>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; @@ -341,11 +336,9 @@ enet3: ucc@3000 { device_type = "network"; compatible = "ucc_geth"; - model = "UCC"; cell-index = <2>; - device-id = <2>; - reg = <3000 200>; - interrupts = <21>; + reg = <0x3000 0x200>; + interrupts = <33>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; @@ -358,7 +351,7 @@ mdio@2120 { #address-cells = <1>; #size-cells = <0>; - reg = <2120 18>; + reg = <0x2120 0x18>; compatible = "fsl,ucc-mdio"; /* These are the same PHYs as on @@ -366,25 +359,25 @@ qe_phy0: ethernet-phy@07 { interrupt-parent = <&mpic>; interrupts = <1 1>; - reg = <7>; + reg = <0x7>; device_type = "ethernet-phy"; }; qe_phy1: ethernet-phy@01 { interrupt-parent = <&mpic>; interrupts = <2 1>; - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; qe_phy2: ethernet-phy@02 { interrupt-parent = <&mpic>; interrupts = <1 1>; - reg = <2>; + reg = <0x2>; device_type = "ethernet-phy"; }; qe_phy3: ethernet-phy@03 { interrupt-parent = <&mpic>; interrupts = <2 1>; - reg = <3>; + reg = <0x3>; device_type = "ethernet-phy"; }; }; @@ -394,9 +387,9 @@ compatible = "fsl,qe-ic"; #address-cells = <0>; #interrupt-cells = <1>; - reg = <80 80>; + reg = <0x80 0x80>; big-endian; - interrupts = <2e 2 2e 2>; //high:30 low:30 + interrupts = <46 2 46 2>; //high:30 low:30 interrupt-parent = <&mpic>; }; @@ -404,30 +397,30 @@ pci0: pci@e0008000 { cell-index = <0>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x12 AD18 */ - 9000 0 0 1 &mpic 5 1 - 9000 0 0 2 &mpic 6 1 - 9000 0 0 3 &mpic 7 1 - 9000 0 0 4 &mpic 4 1 + 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 + 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 + 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 + 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 /* IDSEL 0x13 AD19 */ - 9800 0 0 1 &mpic 6 1 - 9800 0 0 2 &mpic 7 1 - 9800 0 0 3 &mpic 4 1 - 9800 0 0 4 &mpic 5 1>; + 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 + 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 + 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>; interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 ff>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00800000>; - clock-frequency = <3f940aa>; + interrupts = <24 2>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>; + clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e0008000 1000>; + reg = <0xe0008000 0x1000>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; @@ -435,39 +428,39 @@ /* PCI Express */ pci1: pcie@e000a000 { cell-index = <2>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 (PEX) */ - 00000 0 0 1 &mpic 0 1 - 00000 0 0 2 &mpic 1 1 - 00000 0 0 3 &mpic 2 1 - 00000 0 0 4 &mpic 3 1>; + 00000 0x0 0x0 0x1 &mpic 0x0 0x1 + 00000 0x0 0x0 0x2 &mpic 0x1 0x1 + 00000 0x0 0x0 0x3 &mpic 0x2 0x1 + 00000 0x0 0x0 0x4 &mpic 0x3 0x1>; interrupt-parent = <&mpic>; - interrupts = <1a 2>; - bus-range = <0 ff>; - ranges = <02000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 e2800000 0 00800000>; - clock-frequency = <1fca055>; + interrupts = <26 2>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 + 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>; + clock-frequency = <33333333>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <e000a000 1000>; + reg = <0xe000a000 0x1000>; compatible = "fsl,mpc8548-pcie"; device_type = "pci"; pcie@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <02000000 0 a0000000 - 02000000 0 a0000000 - 0 10000000 + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x10000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00800000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x800000>; }; }; }; diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index db37214aee37..66f27ab613a2 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -1,7 +1,7 @@ /* * MPC8572 DS Device Tree Source * - * Copyright 2007 Freescale Semiconductor Inc. + * Copyright 2007, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,7 @@ * option) any later version. */ +/dts-v1/; / { model = "fsl,MPC8572DS"; compatible = "fsl,MPC8572DS"; @@ -33,11 +34,11 @@ PowerPC,8572@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; @@ -45,11 +46,11 @@ PowerPC,8572@1 { device_type = "cpu"; - reg = <1>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K + reg = <0x1>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; @@ -58,38 +59,38 @@ memory { device_type = "memory"; - reg = <00000000 00000000>; // Filled by U-Boot + reg = <0x0 0x0>; // Filled by U-Boot }; soc8572@ffe00000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <00000000 ffe00000 00100000>; - reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed + ranges = <0x0 0xffe00000 0x100000>; + reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed bus-frequency = <0>; // Filled out by uboot. memory-controller@2000 { compatible = "fsl,mpc8572-memory-controller"; - reg = <2000 1000>; + reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; memory-controller@6000 { compatible = "fsl,mpc8572-memory-controller"; - reg = <6000 1000>; + reg = <0x6000 0x1000>; interrupt-parent = <&mpic>; - interrupts = <12 2>; + interrupts = <18 2>; }; l2-cache-controller@20000 { compatible = "fsl,mpc8572-l2-cache-controller"; - reg = <20000 1000>; - cache-line-size = <20>; // 32 bytes - cache-size = <80000>; // L2, 512K + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K interrupt-parent = <&mpic>; - interrupts = <10 2>; + interrupts = <16 2>; }; i2c@3000 { @@ -97,8 +98,8 @@ #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; + reg = <0x3000 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -108,8 +109,8 @@ #size-cells = <0>; cell-index = <1>; compatible = "fsl-i2c"; - reg = <3100 100>; - interrupts = <2b 2>; + reg = <0x3100 0x100>; + interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; @@ -118,27 +119,27 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; - reg = <24520 20>; + reg = <0x24520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; - interrupts = <a 1>; - reg = <0>; + interrupts = <10 1>; + reg = <0x0>; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; - interrupts = <a 1>; - reg = <1>; + interrupts = <10 1>; + reg = <0x1>; }; phy2: ethernet-phy@2 { interrupt-parent = <&mpic>; - interrupts = <a 1>; - reg = <2>; + interrupts = <10 1>; + reg = <0x2>; }; phy3: ethernet-phy@3 { interrupt-parent = <&mpic>; - interrupts = <a 1>; - reg = <3>; + interrupts = <10 1>; + reg = <0x3>; }; }; @@ -147,9 +148,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <24000 1000>; + reg = <0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1d 2 1e 2 22 2>; + interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; phy-connection-type = "rgmii-id"; @@ -160,9 +161,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <25000 1000>; + reg = <0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <23 2 24 2 28 2>; + interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; phy-handle = <&phy1>; phy-connection-type = "rgmii-id"; @@ -173,9 +174,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <26000 1000>; + reg = <0x26000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1f 2 20 2 21 2>; + interrupts = <31 2 32 2 33 2>; interrupt-parent = <&mpic>; phy-handle = <&phy2>; phy-connection-type = "rgmii-id"; @@ -186,9 +187,9 @@ device_type = "network"; model = "eTSEC"; compatible = "gianfar"; - reg = <27000 1000>; + reg = <0x27000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <25 2 26 2 27 2>; + interrupts = <37 2 38 2 39 2>; interrupt-parent = <&mpic>; phy-handle = <&phy3>; phy-connection-type = "rgmii-id"; @@ -198,9 +199,9 @@ cell-index = <0>; device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; + reg = <0x4500 0x100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -208,15 +209,15 @@ cell-index = <1>; device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; + reg = <0x4600 0x100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; global-utilities@e0000 { //global utilities block compatible = "fsl,mpc8572-guts"; - reg = <e0000 1000>; + reg = <0xe0000 0x1000>; fsl,has-rstcr; }; @@ -225,7 +226,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; + reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; @@ -239,167 +240,167 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <ffe08000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 ffc00000 0 00010000>; - clock-frequency = <1fca055>; + reg = <0xffe08000 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>; + clock-frequency = <33333333>; interrupt-parent = <&mpic>; - interrupts = <18 2>; - interrupt-map-mask = <ff00 0 0 7>; + interrupts = <24 2>; + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x11 func 0 - PCI slot 1 */ - 8800 0 0 1 &mpic 2 1 - 8800 0 0 2 &mpic 3 1 - 8800 0 0 3 &mpic 4 1 - 8800 0 0 4 &mpic 1 1 + 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 1 - PCI slot 1 */ - 8900 0 0 1 &mpic 2 1 - 8900 0 0 2 &mpic 3 1 - 8900 0 0 3 &mpic 4 1 - 8900 0 0 4 &mpic 1 1 + 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 2 - PCI slot 1 */ - 8a00 0 0 1 &mpic 2 1 - 8a00 0 0 2 &mpic 3 1 - 8a00 0 0 3 &mpic 4 1 - 8a00 0 0 4 &mpic 1 1 + 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 3 - PCI slot 1 */ - 8b00 0 0 1 &mpic 2 1 - 8b00 0 0 2 &mpic 3 1 - 8b00 0 0 3 &mpic 4 1 - 8b00 0 0 4 &mpic 1 1 + 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 4 - PCI slot 1 */ - 8c00 0 0 1 &mpic 2 1 - 8c00 0 0 2 &mpic 3 1 - 8c00 0 0 3 &mpic 4 1 - 8c00 0 0 4 &mpic 1 1 + 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 5 - PCI slot 1 */ - 8d00 0 0 1 &mpic 2 1 - 8d00 0 0 2 &mpic 3 1 - 8d00 0 0 3 &mpic 4 1 - 8d00 0 0 4 &mpic 1 1 + 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 6 - PCI slot 1 */ - 8e00 0 0 1 &mpic 2 1 - 8e00 0 0 2 &mpic 3 1 - 8e00 0 0 3 &mpic 4 1 - 8e00 0 0 4 &mpic 1 1 + 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x11 func 7 - PCI slot 1 */ - 8f00 0 0 1 &mpic 2 1 - 8f00 0 0 2 &mpic 3 1 - 8f00 0 0 3 &mpic 4 1 - 8f00 0 0 4 &mpic 1 1 + 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 + 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 + 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 + 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x12 func 0 - PCI slot 2 */ - 9000 0 0 1 &mpic 3 1 - 9000 0 0 2 &mpic 4 1 - 9000 0 0 3 &mpic 1 1 - 9000 0 0 4 &mpic 2 1 + 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 1 - PCI slot 2 */ - 9100 0 0 1 &mpic 3 1 - 9100 0 0 2 &mpic 4 1 - 9100 0 0 3 &mpic 1 1 - 9100 0 0 4 &mpic 2 1 + 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 2 - PCI slot 2 */ - 9200 0 0 1 &mpic 3 1 - 9200 0 0 2 &mpic 4 1 - 9200 0 0 3 &mpic 1 1 - 9200 0 0 4 &mpic 2 1 + 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 3 - PCI slot 2 */ - 9300 0 0 1 &mpic 3 1 - 9300 0 0 2 &mpic 4 1 - 9300 0 0 3 &mpic 1 1 - 9300 0 0 4 &mpic 2 1 + 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 4 - PCI slot 2 */ - 9400 0 0 1 &mpic 3 1 - 9400 0 0 2 &mpic 4 1 - 9400 0 0 3 &mpic 1 1 - 9400 0 0 4 &mpic 2 1 + 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 5 - PCI slot 2 */ - 9500 0 0 1 &mpic 3 1 - 9500 0 0 2 &mpic 4 1 - 9500 0 0 3 &mpic 1 1 - 9500 0 0 4 &mpic 2 1 + 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 6 - PCI slot 2 */ - 9600 0 0 1 &mpic 3 1 - 9600 0 0 2 &mpic 4 1 - 9600 0 0 3 &mpic 1 1 - 9600 0 0 4 &mpic 2 1 + 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 /* IDSEL 0x12 func 7 - PCI slot 2 */ - 9700 0 0 1 &mpic 3 1 - 9700 0 0 2 &mpic 4 1 - 9700 0 0 3 &mpic 1 1 - 9700 0 0 4 &mpic 2 1 + 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 + 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 + 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 + 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 // IDSEL 0x1c USB - e000 0 0 1 &i8259 c 2 - e100 0 0 2 &i8259 9 2 - e200 0 0 3 &i8259 a 2 - e300 0 0 4 &i8259 b 2 + 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2 + 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2 + 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2 + 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2 // IDSEL 0x1d Audio - e800 0 0 1 &i8259 6 2 + 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2 // IDSEL 0x1e Legacy - f000 0 0 1 &i8259 7 2 - f100 0 0 1 &i8259 7 2 + 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2 + 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2 // IDSEL 0x1f IDE/SATA - f800 0 0 1 &i8259 e 2 - f900 0 0 1 &i8259 5 2 + 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2 + 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2 >; pcie@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <02000000 0 80000000 - 02000000 0 80000000 - 0 20000000 + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00100000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; uli1575@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; - ranges = <02000000 0 80000000 - 02000000 0 80000000 - 0 20000000 + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00100000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; isa@1e { device_type = "isa"; #interrupt-cells = <2>; #size-cells = <1>; #address-cells = <2>; - reg = <f000 0 0 0 0>; - ranges = <1 0 01000000 0 0 - 00001000>; + reg = <0xf000 0x0 0x0 0x0 0x0>; + ranges = <0x1 0x0 0x1000000 0x0 0x0 + 0x1000>; interrupt-parent = <&i8259>; i8259: interrupt-controller@20 { - reg = <1 20 2 - 1 a0 2 - 1 4d0 2>; + reg = <0x1 0x20 0x2 + 0x1 0xa0 0x2 + 0x1 0x4d0 0x2>; interrupt-controller; device_type = "interrupt-controller"; #address-cells = <0>; @@ -412,29 +413,29 @@ i8042@60 { #size-cells = <0>; #address-cells = <1>; - reg = <1 60 1 1 64 1>; - interrupts = <1 3 c 3>; + reg = <0x1 0x60 0x1 0x1 0x64 0x1>; + interrupts = <1 3 12 3>; interrupt-parent = <&i8259>; keyboard@0 { - reg = <0>; + reg = <0x0>; compatible = "pnpPNP,303"; }; mouse@1 { - reg = <1>; + reg = <0x1>; compatible = "pnpPNP,f03"; }; }; rtc@70 { compatible = "pnpPNP,b00"; - reg = <1 70 2>; + reg = <0x1 0x70 0x2>; }; gpio@400 { - reg = <1 400 80>; + reg = <0x1 0x400 0x80>; }; }; }; @@ -449,33 +450,33 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <ffe09000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 ffc10000 0 00010000>; - clock-frequency = <1fca055>; + reg = <0xffe09000 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>; + clock-frequency = <33333333>; interrupt-parent = <&mpic>; - interrupts = <1a 2>; - interrupt-map-mask = <f800 0 0 7>; + interrupts = <26 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 4 1 - 0000 0 0 2 &mpic 5 1 - 0000 0 0 3 &mpic 6 1 - 0000 0 0 4 &mpic 7 1 + 0000 0x0 0x0 0x1 &mpic 0x4 0x1 + 0000 0x0 0x0 0x2 &mpic 0x5 0x1 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 >; pcie@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <02000000 0 a0000000 - 02000000 0 a0000000 - 0 20000000 + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00100000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; }; }; @@ -486,33 +487,33 @@ #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - reg = <ffe0a000 1000>; - bus-range = <0 ff>; - ranges = <02000000 0 c0000000 c0000000 0 20000000 - 01000000 0 00000000 ffc20000 0 00010000>; - clock-frequency = <1fca055>; + reg = <0xffe0a000 0x1000>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>; + clock-frequency = <33333333>; interrupt-parent = <&mpic>; - interrupts = <1b 2>; - interrupt-map-mask = <f800 0 0 7>; + interrupts = <27 2>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 */ - 0000 0 0 1 &mpic 0 1 - 0000 0 0 2 &mpic 1 1 - 0000 0 0 3 &mpic 2 1 - 0000 0 0 4 &mpic 3 1 + 0000 0x0 0x0 0x1 &mpic 0x0 0x1 + 0000 0x0 0x0 0x2 &mpic 0x1 0x1 + 0000 0x0 0x0 0x3 &mpic 0x2 0x1 + 0000 0x0 0x0 0x4 &mpic 0x3 0x1 >; pcie@0 { - reg = <0 0 0 0 0>; + reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; - ranges = <02000000 0 c0000000 - 02000000 0 c0000000 - 0 20000000 + ranges = <0x2000000 0x0 0xc0000000 + 0x2000000 0x0 0xc0000000 + 0x0 0x20000000 - 01000000 0 00000000 - 01000000 0 00000000 - 0 00100000>; + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; }; }; }; diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts index 79385bcd5c5f..7f9b999843ce 100644 --- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts +++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts @@ -13,7 +13,7 @@ / { model = "MPC8641HPCN"; - compatible = "mpc86xx"; + compatible = "fsl,mpc8641hpcn"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts index daf9433e906b..765e43c997da 100644 --- a/arch/powerpc/boot/dts/mpc866ads.dts +++ b/arch/powerpc/boot/dts/mpc866ads.dts @@ -2,6 +2,7 @@ * MPC866 ADS Device Tree Source * * Copyright 2006 MontaVista Software, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +10,7 @@ * option) any later version. */ +/dts-v1/; / { model = "MPC866ADS"; @@ -22,37 +24,37 @@ PowerPC,866@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <10>; // 16 bytes - i-cache-line-size = <10>; // 16 bytes - d-cache-size = <2000>; // L1, 8K - i-cache-size = <4000>; // L1, 16K + reg = <0x0>; + d-cache-line-size = <16>; // 16 bytes + i-cache-line-size = <16>; // 16 bytes + d-cache-size = <0x2000>; // L1, 8K + i-cache-size = <0x4000>; // L1, 16K timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - interrupts = <f 2>; // decrementer interrupt + interrupts = <15 2>; // decrementer interrupt interrupt-parent = <&PIC>; }; }; memory { device_type = "memory"; - reg = <00000000 800000>; + reg = <0x0 0x800000>; }; localbus@ff000100 { compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus"; #address-cells = <2>; #size-cells = <1>; - reg = <ff000100 40>; + reg = <0xff000100 0x40>; ranges = < - 1 0 ff080000 00008000 - 5 0 ff0a0000 00008000 + 0x1 0x0 0xff080000 0x8000 + 0x5 0x0 0xff0a0000 0x8000 >; board-control@1,0 { - reg = <1 0 20 5 300 4>; + reg = <0x1 0x0 0x20 0x5 0x300 0x4>; compatible = "fsl,mpc866ads-bcsr"; }; }; @@ -61,17 +63,17 @@ #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <0 ff000000 00100000>; - reg = <ff000000 00000200>; + ranges = <0x0 0xff000000 0x100000>; + reg = <0xff000000 0x200>; bus-frequency = <0>; mdio@e00 { compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio"; - reg = <e00 188>; + reg = <0xe00 0x188>; #address-cells = <1>; #size-cells = <0>; PHY: ethernet-phy@f { - reg = <f>; + reg = <0xf>; device_type = "ethernet-phy"; }; }; @@ -80,7 +82,7 @@ device_type = "network"; compatible = "fsl,mpc866-fec-enet", "fsl,pq1-fec-enet"; - reg = <e00 188>; + reg = <0xe00 0x188>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <3 1>; interrupt-parent = <&PIC>; @@ -91,7 +93,7 @@ PIC: pic@0 { interrupt-controller; #interrupt-cells = <2>; - reg = <0 24>; + reg = <0x0 0x24>; compatible = "fsl,mpc866-pic", "fsl,pq1-pic"; }; @@ -100,7 +102,7 @@ #size-cells = <1>; compatible = "fsl,mpc866-cpm", "fsl,cpm1"; ranges; - reg = <9c0 40>; + reg = <0x9c0 0x40>; brg-frequency = <0>; interrupts = <0 2>; // cpm error interrupt interrupt-parent = <&CPM_PIC>; @@ -108,11 +110,11 @@ muram@2000 { #address-cells = <1>; #size-cells = <1>; - ranges = <0 2000 2000>; + ranges = <0x0 0x2000 0x2000>; data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 1c00>; + reg = <0x0 0x1c00>; }; }; @@ -120,7 +122,7 @@ compatible = "fsl,mpc866-brg", "fsl,cpm1-brg", "fsl,cpm-brg"; - reg = <9f0 10>; + reg = <0x9f0 0x10>; clock-frequency = <0>; }; @@ -130,7 +132,7 @@ #interrupt-cells = <1>; interrupts = <5 2 0 2>; interrupt-parent = <&PIC>; - reg = <930 20>; + reg = <0x930 0x20>; compatible = "fsl,mpc866-cpm-pic", "fsl,cpm1-pic"; }; @@ -140,31 +142,31 @@ device_type = "serial"; compatible = "fsl,mpc866-smc-uart", "fsl,cpm1-smc-uart"; - reg = <a80 10 3e80 40>; + reg = <0xa80 0x10 0x3e80 0x40>; interrupts = <4>; interrupt-parent = <&CPM_PIC>; fsl,cpm-brg = <1>; - fsl,cpm-command = <0090>; + fsl,cpm-command = <0x90>; }; serial@a90 { device_type = "serial"; compatible = "fsl,mpc866-smc-uart", "fsl,cpm1-smc-uart"; - reg = <a90 10 3f80 40>; + reg = <0xa90 0x10 0x3f80 0x40>; interrupts = <3>; interrupt-parent = <&CPM_PIC>; fsl,cpm-brg = <2>; - fsl,cpm-command = <00d0>; + fsl,cpm-command = <0xd0>; }; ethernet@a00 { device_type = "network"; compatible = "fsl,mpc866-scc-enet", "fsl,cpm1-scc-enet"; - reg = <a00 18 3c00 100>; + reg = <0xa00 0x18 0x3c00 0x100>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1e>; + interrupts = <30>; interrupt-parent = <&CPM_PIC>; fsl,cpm-command = <0000>; linux,network-index = <1>; diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts index d84a012c2aaf..9895043722b9 100644 --- a/arch/powerpc/boot/dts/mpc885ads.dts +++ b/arch/powerpc/boot/dts/mpc885ads.dts @@ -2,7 +2,7 @@ * MPC885 ADS Device Tree Source * * Copyright 2006 MontaVista Software, Inc. - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007,2008 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -10,6 +10,7 @@ * option) any later version. */ +/dts-v1/; / { model = "MPC885ADS"; @@ -23,45 +24,45 @@ PowerPC,885@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <d#16>; - i-cache-line-size = <d#16>; - d-cache-size = <d#8192>; - i-cache-size = <d#8192>; + reg = <0x0>; + d-cache-line-size = <16>; + i-cache-line-size = <16>; + d-cache-size = <8192>; + i-cache-size = <8192>; timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; - interrupts = <f 2>; // decrementer interrupt + interrupts = <15 2>; // decrementer interrupt interrupt-parent = <&PIC>; }; }; memory { device_type = "memory"; - reg = <0 0>; + reg = <0x0 0x0>; }; localbus@ff000100 { compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus"; #address-cells = <2>; #size-cells = <1>; - reg = <ff000100 40>; + reg = <0xff000100 0x40>; ranges = < - 0 0 fe000000 00800000 - 1 0 ff080000 00008000 - 5 0 ff0a0000 00008000 + 0x0 0x0 0xfe000000 0x800000 + 0x1 0x0 0xff080000 0x8000 + 0x5 0x0 0xff0a0000 0x8000 >; flash@0,0 { compatible = "jedec-flash"; - reg = <0 0 800000>; + reg = <0x0 0x0 0x800000>; bank-width = <4>; device-width = <1>; }; board-control@1,0 { - reg = <1 0 20 5 300 4>; + reg = <0x1 0x0 0x20 0x5 0x300 0x4>; compatible = "fsl,mpc885ads-bcsr"; }; }; @@ -71,30 +72,30 @@ #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - ranges = <0 ff000000 00004000>; + ranges = <0x0 0xff000000 0x4000>; bus-frequency = <0>; // Temporary -- will go away once kernel uses ranges for get_immrbase(). - reg = <ff000000 4000>; + reg = <0xff000000 0x4000>; mdio@e00 { compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio"; - reg = <e00 188>; + reg = <0xe00 0x188>; #address-cells = <1>; #size-cells = <0>; PHY0: ethernet-phy@0 { - reg = <0>; + reg = <0x0>; device_type = "ethernet-phy"; }; PHY1: ethernet-phy@1 { - reg = <1>; + reg = <0x1>; device_type = "ethernet-phy"; }; PHY2: ethernet-phy@2 { - reg = <2>; + reg = <0x2>; device_type = "ethernet-phy"; }; }; @@ -103,7 +104,7 @@ device_type = "network"; compatible = "fsl,mpc885-fec-enet", "fsl,pq1-fec-enet"; - reg = <e00 188>; + reg = <0xe00 0x188>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <3 1>; interrupt-parent = <&PIC>; @@ -115,7 +116,7 @@ device_type = "network"; compatible = "fsl,mpc885-fec-enet", "fsl,pq1-fec-enet"; - reg = <1e00 188>; + reg = <0x1e00 0x188>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <7 1>; interrupt-parent = <&PIC>; @@ -126,7 +127,7 @@ PIC: interrupt-controller@0 { interrupt-controller; #interrupt-cells = <2>; - reg = <0 24>; + reg = <0x0 0x24>; compatible = "fsl,mpc885-pic", "fsl,pq1-pic"; }; @@ -136,29 +137,29 @@ #size-cells = <2>; compatible = "fsl,pq-pcmcia"; device_type = "pcmcia"; - reg = <80 80>; + reg = <0x80 0x80>; interrupt-parent = <&PIC>; - interrupts = <d 1>; + interrupts = <13 1>; }; cpm@9c0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc885-cpm", "fsl,cpm1"; - command-proc = <9c0>; + command-proc = <0x9c0>; interrupts = <0>; // cpm error interrupt interrupt-parent = <&CPM_PIC>; - reg = <9c0 40>; + reg = <0x9c0 0x40>; ranges; muram@2000 { #address-cells = <1>; #size-cells = <1>; - ranges = <0 2000 2000>; + ranges = <0x0 0x2000 0x2000>; data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 1c00>; + reg = <0x0 0x1c00>; }; }; @@ -167,7 +168,7 @@ "fsl,cpm1-brg", "fsl,cpm-brg"; clock-frequency = <0>; - reg = <9f0 10>; + reg = <0x9f0 0x10>; }; CPM_PIC: interrupt-controller@930 { @@ -175,7 +176,7 @@ #interrupt-cells = <1>; interrupts = <5 2 0 2>; interrupt-parent = <&PIC>; - reg = <930 20>; + reg = <0x930 0x20>; compatible = "fsl,mpc885-cpm-pic", "fsl,cpm1-pic"; }; @@ -184,34 +185,34 @@ device_type = "serial"; compatible = "fsl,mpc885-smc-uart", "fsl,cpm1-smc-uart"; - reg = <a80 10 3e80 40>; + reg = <0xa80 0x10 0x3e80 0x40>; interrupts = <4>; interrupt-parent = <&CPM_PIC>; fsl,cpm-brg = <1>; - fsl,cpm-command = <0090>; + fsl,cpm-command = <0x90>; }; serial@a90 { device_type = "serial"; compatible = "fsl,mpc885-smc-uart", "fsl,cpm1-smc-uart"; - reg = <a90 10 3f80 40>; + reg = <0xa90 0x10 0x3f80 0x40>; interrupts = <3>; interrupt-parent = <&CPM_PIC>; fsl,cpm-brg = <2>; - fsl,cpm-command = <00d0>; + fsl,cpm-command = <0xd0>; }; ethernet@a40 { device_type = "network"; compatible = "fsl,mpc885-scc-enet", "fsl,cpm1-scc-enet"; - reg = <a40 18 3e00 100>; + reg = <0xa40 0x18 0x3e00 0x100>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <1c>; + interrupts = <28>; interrupt-parent = <&CPM_PIC>; phy-handle = <&PHY2>; - fsl,cpm-command = <0080>; + fsl,cpm-command = <0x80>; linux,network-index = <2>; }; }; diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts index 2d564921897a..b2d61091b36d 100644 --- a/arch/powerpc/boot/dts/pq2fads.dts +++ b/arch/powerpc/boot/dts/pq2fads.dts @@ -1,7 +1,7 @@ /* * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip. * - * Copyright 2007 Freescale Semiconductor Inc. + * Copyright 2007,2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -9,6 +9,8 @@ * option) any later version. */ +/dts-v1/; + / { model = "pq2fads"; compatible = "fsl,pq2fads"; @@ -21,11 +23,11 @@ cpu@0 { device_type = "cpu"; - reg = <0>; - d-cache-line-size = <d#32>; - i-cache-line-size = <d#32>; - d-cache-size = <d#16384>; - i-cache-size = <d#16384>; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <16384>; + i-cache-size = <16384>; timebase-frequency = <0>; clock-frequency = <0>; }; @@ -33,7 +35,7 @@ memory { device_type = "memory"; - reg = <0 0>; + reg = <0x0 0x0>; }; localbus@f0010100 { @@ -41,67 +43,67 @@ "fsl,pq2-localbus"; #address-cells = <2>; #size-cells = <1>; - reg = <f0010100 60>; + reg = <0xf0010100 0x60>; - ranges = <0 0 fe000000 00800000 - 1 0 f4500000 00008000 - 8 0 f8200000 00008000>; + ranges = <0x0 0x0 0xfe000000 0x800000 + 0x1 0x0 0xf4500000 0x8000 + 0x8 0x0 0xf8200000 0x8000>; flash@0,0 { compatible = "jedec-flash"; - reg = <0 0 800000>; + reg = <0x0 0x0 0x800000>; bank-width = <4>; device-width = <1>; }; bcsr@1,0 { - reg = <1 0 20>; + reg = <0x1 0x0 0x20>; compatible = "fsl,pq2fads-bcsr"; }; PCI_PIC: pic@8,0 { #interrupt-cells = <1>; interrupt-controller; - reg = <8 0 8>; + reg = <0x8 0x0 0x8>; compatible = "fsl,pq2ads-pci-pic"; interrupt-parent = <&PIC>; - interrupts = <18 8>; + interrupts = <24 8>; }; }; pci@f0010800 { device_type = "pci"; - reg = <f0010800 10c f00101ac 8 f00101c4 8>; + reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; - clock-frequency = <d#66000000>; - interrupt-map-mask = <f800 0 0 7>; + clock-frequency = <66000000>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x16 */ - b000 0 0 1 &PCI_PIC 0 - b000 0 0 2 &PCI_PIC 1 - b000 0 0 3 &PCI_PIC 2 - b000 0 0 4 &PCI_PIC 3 + 0xb000 0x0 0x0 0x1 &PCI_PIC 0 + 0xb000 0x0 0x0 0x2 &PCI_PIC 1 + 0xb000 0x0 0x0 0x3 &PCI_PIC 2 + 0xb000 0x0 0x0 0x4 &PCI_PIC 3 /* IDSEL 0x17 */ - b800 0 0 1 &PCI_PIC 4 - b800 0 0 2 &PCI_PIC 5 - b800 0 0 3 &PCI_PIC 6 - b800 0 0 4 &PCI_PIC 7 + 0xb800 0x0 0x0 0x1 &PCI_PIC 4 + 0xb800 0x0 0x0 0x2 &PCI_PIC 5 + 0xb800 0x0 0x0 0x3 &PCI_PIC 6 + 0xb800 0x0 0x0 0x4 &PCI_PIC 7 /* IDSEL 0x18 */ - c000 0 0 1 &PCI_PIC 8 - c000 0 0 2 &PCI_PIC 9 - c000 0 0 3 &PCI_PIC a - c000 0 0 4 &PCI_PIC b>; + 0xc000 0x0 0x0 0x1 &PCI_PIC 8 + 0xc000 0x0 0x0 0x2 &PCI_PIC 9 + 0xc000 0x0 0x0 0x3 &PCI_PIC 10 + 0xc000 0x0 0x0 0x4 &PCI_PIC 11>; interrupt-parent = <&PIC>; - interrupts = <12 8>; - ranges = <42000000 0 80000000 80000000 0 20000000 - 02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 f6000000 0 02000000>; + interrupts = <18 8>; + ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>; }; soc@f0000000 { @@ -109,27 +111,27 @@ #size-cells = <1>; device_type = "soc"; compatible = "fsl,mpc8280", "fsl,pq2-soc"; - ranges = <00000000 f0000000 00053000>; + ranges = <0x0 0xf0000000 0x53000>; // Temporary -- will go away once kernel uses ranges for get_immrbase(). - reg = <f0000000 00053000>; + reg = <0xf0000000 0x53000>; cpm@119c0 { #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <2>; compatible = "fsl,mpc8280-cpm", "fsl,cpm2"; - reg = <119c0 30>; + reg = <0x119c0 0x30>; ranges; muram@0 { #address-cells = <1>; #size-cells = <1>; - ranges = <0 0 10000>; + ranges = <0x0 0x0 0x10000>; data@0 { compatible = "fsl,cpm-muram-data"; - reg = <0 2000 9800 800>; + reg = <0x0 0x2000 0x9800 0x800>; }; }; @@ -137,53 +139,53 @@ compatible = "fsl,mpc8280-brg", "fsl,cpm2-brg", "fsl,cpm-brg"; - reg = <119f0 10 115f0 10>; + reg = <0x119f0 0x10 0x115f0 0x10>; }; serial@11a00 { device_type = "serial"; compatible = "fsl,mpc8280-scc-uart", "fsl,cpm2-scc-uart"; - reg = <11a00 20 8000 100>; - interrupts = <28 8>; + reg = <0x11a00 0x20 0x8000 0x100>; + interrupts = <40 8>; interrupt-parent = <&PIC>; fsl,cpm-brg = <1>; - fsl,cpm-command = <00800000>; + fsl,cpm-command = <0x800000>; }; serial@11a20 { device_type = "serial"; compatible = "fsl,mpc8280-scc-uart", "fsl,cpm2-scc-uart"; - reg = <11a20 20 8100 100>; - interrupts = <29 8>; + reg = <0x11a20 0x20 0x8100 0x100>; + interrupts = <41 8>; interrupt-parent = <&PIC>; fsl,cpm-brg = <2>; - fsl,cpm-command = <04a00000>; + fsl,cpm-command = <0x4a00000>; }; ethernet@11320 { device_type = "network"; compatible = "fsl,mpc8280-fcc-enet", "fsl,cpm2-fcc-enet"; - reg = <11320 20 8500 100 113b0 1>; - interrupts = <21 8>; + reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>; + interrupts = <33 8>; interrupt-parent = <&PIC>; phy-handle = <&PHY0>; linux,network-index = <0>; - fsl,cpm-command = <16200300>; + fsl,cpm-command = <0x16200300>; }; ethernet@11340 { device_type = "network"; compatible = "fsl,mpc8280-fcc-enet", "fsl,cpm2-fcc-enet"; - reg = <11340 20 8600 100 113d0 1>; - interrupts = <22 8>; + reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>; + interrupts = <34 8>; interrupt-parent = <&PIC>; phy-handle = <&PHY1>; linux,network-index = <1>; - fsl,cpm-command = <1a400300>; + fsl,cpm-command = <0x1a400300>; local-mac-address = [00 e0 0c 00 79 01]; }; @@ -194,21 +196,21 @@ "fsl,cpm2-mdio-bitbang"; #address-cells = <1>; #size-cells = <0>; - reg = <10d40 14>; + reg = <0x10d40 0x14>; fsl,mdio-pin = <9>; - fsl,mdc-pin = <a>; + fsl,mdc-pin = <10>; PHY0: ethernet-phy@0 { interrupt-parent = <&PIC>; - interrupts = <19 2>; - reg = <0>; + interrupts = <25 2>; + reg = <0x0>; device_type = "ethernet-phy"; }; PHY1: ethernet-phy@1 { interrupt-parent = <&PIC>; - interrupts = <19 2>; - reg = <3>; + interrupts = <25 2>; + reg = <0x3>; device_type = "ethernet-phy"; }; }; @@ -218,17 +220,17 @@ #size-cells = <0>; compatible = "fsl,mpc8280-usb", "fsl,cpm2-usb"; - reg = <11b60 18 8b00 100>; + reg = <0x11b60 0x18 0x8b00 0x100>; interrupt-parent = <&PIC>; - interrupts = <b 8>; - fsl,cpm-command = <2e600000>; + interrupts = <11 8>; + fsl,cpm-command = <0x2e600000>; }; }; PIC: interrupt-controller@10c00 { #interrupt-cells = <2>; interrupt-controller; - reg = <10c00 80>; + reg = <0x10c00 0x80>; compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic"; }; diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts new file mode 100644 index 000000000000..3eebeec157b3 --- /dev/null +++ b/arch/powerpc/boot/dts/sbc8641d.dts @@ -0,0 +1,352 @@ +/* + * SBC8641D Device Tree Source + * + * Copyright 2008 Wind River Systems Inc. + * + * Paul Gortmaker (see MAINTAINERS for contact information) + * + * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "SBC8641D"; + compatible = "wind,sbc8641"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8641@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; // L1 + i-cache-size = <32768>; // L1 + timebase-frequency = <0>; // From uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + }; + PowerPC,8641@1 { + device_type = "cpu"; + reg = <1>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + timebase-frequency = <0>; // From uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; // 512M at 0x0 + }; + + localbus@f8005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8641-localbus", "simple-bus"; + reg = <0xf8005000 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + + ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash + 1 0 0xf0000000 0x00010000 // 64KB EEPROM + 2 0 0xf1000000 0x00100000 // EPLD (1MB) + 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3) + 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4) + 6 0 0xf4000000 0x00100000 // LCD display (1MB) + 7 0 0xe8000000 0x04000000>; // 64MB OneNAND + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x01000000>; + bank-width = <2>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "dtb"; + reg = <0x00000000 0x00100000>; + read-only; + }; + partition@300000 { + label = "kernel"; + reg = <0x00100000 0x00400000>; + read-only; + }; + partition@400000 { + label = "fs"; + reg = <0x00500000 0x00a00000>; + }; + partition@700000 { + label = "firmware"; + reg = <0x00f00000 0x00100000>; + read-only; + }; + }; + + epld@2,0 { + compatible = "wrs,epld-localbus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <2 0 0x100000>; + ranges = <0 0 5 0 1 // User switches + 1 0 5 1 1 // Board ID/Rev + 3 0 5 3 1>; // LEDs + }; + }; + + soc@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x00000000 0xf8000000 0x00100000>; + reg = <0xf8000000 0x00001000>; // CCSRBAR + bus-frequency = <0>; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + + phy0: ethernet-phy@1f { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <0x1f>; + device_type = "ethernet-phy"; + }; + phy1: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <0>; + device_type = "ethernet-phy"; + }; + phy2: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <1>; + device_type = "ethernet-phy"; + }; + phy3: ethernet-phy@2 { + interrupt-parent = <&mpic>; + interrupts = <10 1>; + reg = <2>; + device_type = "ethernet-phy"; + }; + }; + + enet0: ethernet@24000 { + cell-index = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ethernet@25000 { + cell-index = <1>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 36 2 40 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; + + enet2: ethernet@26000 { + cell-index = <2>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-id"; + }; + + enet3: ethernet@27000 { + cell-index = <3>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 38 2 39 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy3>; + phy-connection-type = "rgmii-id"; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <28 2>; + interrupt-parent = <&mpic>; + }; + + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + + global-utilities@e0000 { + compatible = "fsl,mpc8641-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + }; + + pci0: pcie@f8008000 { + cell-index = <0>; + compatible = "fsl,mpc8641-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xf8008000 0x1000>; + bus-range = <0x0 0xff>; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <24 2>; + interrupt-map-mask = <0xff00 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0000 0 0 1 &mpic 0 1 + 0x0000 0 0 2 &mpic 1 1 + 0x0000 0 0 3 &mpic 2 1 + 0x0000 0 0 4 &mpic 3 1 + >; + + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x80000000 + 0x02000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x01000000 0x0 0x00000000 + 0x01000000 0x0 0x00000000 + 0x0 0x00100000>; + }; + + }; + + pci1: pcie@f8009000 { + cell-index = <1>; + compatible = "fsl,mpc8641-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xf8009000 0x1000>; + bus-range = <0 0xff>; + ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; + clock-frequency = <33333333>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0x0000 0 0 1 &mpic 4 1 + 0x0000 0 0 2 &mpic 5 1 + 0x0000 0 0 3 &mpic 6 1 + 0x0000 0 0 4 &mpic 7 1 + >; + + pcie@0 { + reg = <0 0 0 0 0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x02000000 0x0 0xa0000000 + 0x02000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x01000000 0x0 0x00000000 + 0x01000000 0x0 0x00000000 + 0x0 0x00100000>; + }; + }; +}; |