diff options
Diffstat (limited to 'arch/ppc/syslib')
25 files changed, 1263 insertions, 207 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index 220a65ab0a51..8b9b226005d1 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -43,8 +43,6 @@ obj-$(CONFIG_PPC_PMAC) += open_pic.o indirect_pci.o obj-$(CONFIG_POWER4) += open_pic2.o obj-$(CONFIG_PPC_CHRP) += open_pic.o indirect_pci.o i8259.o obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o -obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \ - todc_time.o obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o @@ -52,16 +50,10 @@ obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o obj-$(CONFIG_GEMINI) += open_pic.o indirect_pci.o obj-$(CONFIG_GT64260) += gt64260_pic.o -obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \ - pci_auto.o obj-$(CONFIG_LOPEC) += i8259.o pci_auto.o todc_time.o obj-$(CONFIG_HDPU) += pci_auto.o obj-$(CONFIG_LUAN) += indirect_pci.o pci_auto.o todc_time.o obj-$(CONFIG_KATANA) += pci_auto.o -obj-$(CONFIG_MCPN765) += todc_time.o indirect_pci.o pci_auto.o \ - open_pic.o i8259.o hawk_common.o -obj-$(CONFIG_MENF1) += todc_time.o i8259.o mpc10x_common.o \ - pci_auto.o indirect_pci.o obj-$(CONFIG_MV64360) += mv64360_pic.o obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o indirect_pci.o obj-$(CONFIG_MVME5100) += open_pic.o todc_time.o indirect_pci.o \ @@ -69,7 +61,6 @@ obj-$(CONFIG_MVME5100) += open_pic.o todc_time.o indirect_pci.o \ obj-$(CONFIG_MVME5100_IPMC761_PRESENT) += i8259.o obj-$(CONFIG_OCOTEA) += indirect_pci.o pci_auto.o todc_time.o obj-$(CONFIG_PAL4) += cpc700_pic.o -obj-$(CONFIG_PCORE) += todc_time.o i8259.o pci_auto.o obj-$(CONFIG_POWERPMC250) += pci_auto.o obj-$(CONFIG_PPLUS) += hawk_common.o open_pic.o i8259.o \ indirect_pci.o todc_time.o pci_auto.o @@ -82,7 +73,8 @@ obj-$(CONFIG_SANDPOINT) += i8259.o pci_auto.o todc_time.o obj-$(CONFIG_SBC82xx) += todc_time.o obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \ todc_time.o -obj-$(CONFIG_8260) += m8260_setup.o +obj-$(CONFIG_8260) += m8260_setup.o pq2_devices.o pq2_sys.o \ + ppc_sys.o obj-$(CONFIG_PCI_8260) += m82xx_pci.o indirect_pci.o pci_auto.o obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o diff --git a/arch/ppc/syslib/cpc700_pic.c b/arch/ppc/syslib/cpc700_pic.c index 774709807538..75fe8eb10693 100644 --- a/arch/ppc/syslib/cpc700_pic.c +++ b/arch/ppc/syslib/cpc700_pic.c @@ -90,14 +90,10 @@ cpc700_mask_and_ack_irq(unsigned int irq) } static struct hw_interrupt_type cpc700_pic = { - "CPC700 PIC", - NULL, - NULL, - cpc700_unmask_irq, - cpc700_mask_irq, - cpc700_mask_and_ack_irq, - NULL, - NULL + .typename = "CPC700 PIC", + .enable = cpc700_unmask_irq, + .disable = cpc700_mask_irq, + .ack = cpc700_mask_and_ack_irq, }; __init static void diff --git a/arch/ppc/syslib/i8259.c b/arch/ppc/syslib/i8259.c index b9391e650141..5c7908c20e43 100644 --- a/arch/ppc/syslib/i8259.c +++ b/arch/ppc/syslib/i8259.c @@ -129,14 +129,11 @@ static void i8259_end_irq(unsigned int irq) } struct hw_interrupt_type i8259_pic = { - " i8259 ", - NULL, - NULL, - i8259_unmask_irq, - i8259_mask_irq, - i8259_mask_and_ack_irq, - i8259_end_irq, - NULL + .typename = " i8259 ", + .enable = i8259_unmask_irq, + .disable = i8259_mask_irq, + .ack = i8259_mask_and_ack_irq, + .end = i8259_end_irq, }; static struct resource pic1_iores = { diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c index d4776af6a3ca..0bb919859b8b 100644 --- a/arch/ppc/syslib/ibm440gx_common.c +++ b/arch/ppc/syslib/ibm440gx_common.c @@ -236,9 +236,10 @@ void __init ibm440gx_l2c_setup(struct ibm44x_clocks* p) /* Disable L2C on rev.A, rev.B and 800MHz version of rev.C, enable it on all other revisions */ - u32 pvr = mfspr(SPRN_PVR); - if (pvr == PVR_440GX_RA || pvr == PVR_440GX_RB || - (pvr == PVR_440GX_RC && p->cpu > 667000000)) + if (strcmp(cur_cpu_spec[0]->cpu_name, "440GX Rev. A") == 0 || + strcmp(cur_cpu_spec[0]->cpu_name, "440GX Rev. B") == 0 + || (strcmp(cur_cpu_spec[0]->cpu_name, "440GX Rev. C") + == 0 && p->cpu > 667000000)) ibm440gx_l2c_disable(); else ibm440gx_l2c_enable(); diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c index a3702cfe8f7c..4c888da89b3c 100644 --- a/arch/ppc/syslib/m8xx_setup.c +++ b/arch/ppc/syslib/m8xx_setup.c @@ -57,7 +57,7 @@ unsigned char __res[sizeof(bd_t)]; extern void m8xx_ide_init(void); extern unsigned long find_available_memory(void); -extern void m8xx_cpm_reset(); +extern void m8xx_cpm_reset(void); extern void m8xx_wdt_handler_install(bd_t *bp); extern void rpxfb_alloc_pages(void); extern void cpm_interrupt_init(void); @@ -266,8 +266,8 @@ m8xx_show_percpuinfo(struct seq_file *m, int i) bp = (bd_t *)__res; - seq_printf(m, "clock\t\t: %ldMHz\n" - "bus clock\t: %ldMHz\n", + seq_printf(m, "clock\t\t: %uMHz\n" + "bus clock\t: %uMHz\n", bp->bi_intfreq / 1000000, bp->bi_busfreq / 1000000); diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c index 87065e2e4c5f..3e039706bdbc 100644 --- a/arch/ppc/syslib/mpc10x_common.c +++ b/arch/ppc/syslib/mpc10x_common.c @@ -140,12 +140,12 @@ struct platform_device ppc_sys_platform_devices[] = { }, [MPC10X_UART0] = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev.platform_data = serial_plat_uart0, }, [MPC10X_UART1] = { .name = "serial8250", - .id = 1, + .id = PLAT8250_DEV_PLATFORM1, .dev.platform_data = serial_plat_uart1, }, diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c index 5aaf0e58e1f9..95b3b8a7f0ba 100644 --- a/arch/ppc/syslib/mpc83xx_devices.c +++ b/arch/ppc/syslib/mpc83xx_devices.c @@ -165,7 +165,7 @@ struct platform_device ppc_sys_platform_devices[] = { }, [MPC83xx_DUART] = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev.platform_data = serial_platform_data, }, [MPC83xx_SEC2] = { diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c index 8af322dd476a..bbc5ac0de878 100644 --- a/arch/ppc/syslib/mpc85xx_devices.c +++ b/arch/ppc/syslib/mpc85xx_devices.c @@ -282,7 +282,7 @@ struct platform_device ppc_sys_platform_devices[] = { }, [MPC85xx_DUART] = { .name = "serial8250", - .id = 0, + .id = PLAT8250_DEV_PLATFORM, .dev.platform_data = serial_platform_data, }, [MPC85xx_PERFMON] = { diff --git a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c index 74d8996418e9..8356da4678a2 100644 --- a/arch/ppc/syslib/mv64360_pic.c +++ b/arch/ppc/syslib/mv64360_pic.c @@ -366,10 +366,16 @@ mv64360_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs) return IRQ_HANDLED; } +/* + * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of + * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as + * well. IOW, don't set bit 0. + */ +#define MV64360_PCI0_ERR_MASK_VAL 0x00a50c24 + static int __init mv64360_register_hdlrs(void) { - u32 mask; int rc; /* Clear old errors and register CPU interface error intr handler */ @@ -387,17 +393,6 @@ mv64360_register_hdlrs(void) mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0))) printk(KERN_WARNING "Can't register SRAM error handler: %d",rc); - /* - * Bit 0 reserved on 64360 and erratum FEr PCI-#11 (PCI internal - * data parity error set incorrectly) on rev 0 & 1 of 64460 requires - * bit 0 to be cleared. - */ - mask = 0x00a50c24; - - if ((mv64x60_get_bridge_type() == MV64x60_TYPE_MV64460) && - (mv64x60_get_bridge_rev() > 1)) - mask |= 0x1; /* enable DPErr on 64460 */ - /* Clear old errors and register PCI 0 error intr handler */ mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0); if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base, @@ -407,7 +402,11 @@ mv64360_register_hdlrs(void) rc); mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0); - mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, mask); + mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL); + + /* Erratum FEr PCI-#16 says to clear bit 0 of PCI SERRn Mask reg. */ + mv64x60_write(&bh, MV64x60_PCI0_ERR_SERR_MASK, + mv64x60_read(&bh, MV64x60_PCI0_ERR_SERR_MASK) & ~0x1UL); /* Clear old errors and register PCI 1 error intr handler */ mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0); @@ -418,7 +417,11 @@ mv64360_register_hdlrs(void) rc); mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0); - mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, mask); + mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL); + + /* Erratum FEr PCI-#16 says to clear bit 0 of PCI Intr Mask reg. */ + mv64x60_write(&bh, MV64x60_PCI1_ERR_SERR_MASK, + mv64x60_read(&bh, MV64x60_PCI1_ERR_SERR_MASK) & ~0x1UL); return 0; } diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c index cc77177fa1c6..839f8872826f 100644 --- a/arch/ppc/syslib/mv64x60.c +++ b/arch/ppc/syslib/mv64x60.c @@ -30,13 +30,16 @@ #include <asm/mv64x60.h> -u8 mv64x60_pci_exclude_bridge = 1; -spinlock_t mv64x60_lock = SPIN_LOCK_UNLOCKED; +u8 mv64x60_pci_exclude_bridge = 1; +DEFINE_SPINLOCK(mv64x60_lock); -static phys_addr_t mv64x60_bridge_pbase = 0; -static void *mv64x60_bridge_vbase = 0; +static phys_addr_t mv64x60_bridge_pbase; +static void *mv64x60_bridge_vbase; static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID; -static u32 mv64x60_bridge_rev = 0; +static u32 mv64x60_bridge_rev; +#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) +static struct pci_controller sysfs_hose_a; +#endif static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits); static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits); @@ -432,6 +435,20 @@ static struct platform_device i2c_device = { }; #endif +#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) +static struct mv64xxx_pdata mv64xxx_pdata = { + .hs_reg_valid = 0, +}; + +static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */ + .name = MV64XXX_DEV_NAME, + .id = 0, + .dev = { + .platform_data = &mv64xxx_pdata, + }, +}; +#endif + static struct platform_device *mv64x60_pd_devs[] __initdata = { #ifdef CONFIG_SERIAL_MPSC &mpsc_shared_device, @@ -453,6 +470,9 @@ static struct platform_device *mv64x60_pd_devs[] __initdata = { #ifdef CONFIG_I2C_MV64XXX &i2c_device, #endif +#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) + &mv64xxx_device, +#endif }; /* @@ -574,6 +594,11 @@ mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si) bh->hose_a = &hose_a; bh->hose_b = &hose_b; +#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) + /* Save a copy of hose_a for sysfs functions -- hack */ + memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a)); +#endif + mv64x60_set_bus(bh, 0, 0); mv64x60_set_bus(bh, 1, 0); @@ -590,8 +615,6 @@ mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si) mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff); mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff); - - return; } /* @@ -628,19 +651,15 @@ mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, val = mv64x60_read(bh, size_reg); val = get_from_field(val, size_bits); *size = bh->ci->untranslate_size(*base, val, size_bits); - } - else + } else *size = 0; - } - else { + } else { *base = 0; *size = 0; } pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n", window, *base, *size); - - return; } /* @@ -677,8 +696,6 @@ mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, (void)mv64x60_read(bh, base_reg); /* Flush FIFO */ } - - return; } /* @@ -712,11 +729,9 @@ mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, val = get_from_field(val, size_bits); *size = bh->ci->untranslate_size(*base_lo, val, size_bits); - } - else + } else *size = 0; - } - else { + } else { *base_hi = 0; *base_lo = 0; *size = 0; @@ -724,8 +739,6 @@ mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, " "size: 0x%x\n", window, *base_hi, *base_lo, *size); - - return; } /* @@ -766,8 +779,6 @@ mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */ } - - return; } /* @@ -1008,8 +1019,6 @@ mv64x60_get_mem_windows(struct mv64x60_handle *bh, mem_windows[i][0] = 0; mem_windows[i][1] = 0; } - - return; } /* @@ -1077,8 +1086,6 @@ mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, } } - - return; } /* @@ -1112,8 +1119,7 @@ mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, mv64x60_set_32bit_window(bh, remap_tab[bus][0], pi->pci_io.pci_base_lo, 0, 0); bh->ci->enable_window_32bit(bh, win_tab[bus][0]); - } - else /* Actually, the window should already be disabled */ + } else /* Actually, the window should already be disabled */ bh->ci->disable_window_32bit(bh, win_tab[bus][0]); for (i=0; i<3; i++) @@ -1125,11 +1131,8 @@ mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, pi->pci_mem[i].pci_base_hi, pi->pci_mem[i].pci_base_lo, 0, 0); bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]); - } - else /* Actually, the window should already be disabled */ + } else /* Actually, the window should already be disabled */ bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]); - - return; } /* @@ -1206,8 +1209,6 @@ mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, MV64x60_PCI0_BAR_ENABLE : MV64x60_PCI1_BAR_ENABLE), (1 << i)); } - - return; } /* @@ -1229,7 +1230,6 @@ mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data, *hose = pcibios_alloc_controller(); setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr, bh->v_base + cfg_data); - return; } /* @@ -1272,7 +1272,6 @@ mv64x60_config_resources(struct pci_controller *hose, pi->pci_mem[0].size - 1; hose->pci_mem_offset = pi->pci_mem[0].cpu_base - pi->pci_mem[0].pci_base_lo; - return; } /* @@ -1309,7 +1308,6 @@ mv64x60_config_pci_params(struct pci_controller *hose, early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val); mv64x60_pci_exclude_bridge = save_exclude; - return; } /* @@ -1336,8 +1334,7 @@ mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus) p2p_cfg = MV64x60_PCI0_P2P_CONFIG; pci_cfg_offset = 0x64; hose = bh->hose_a; - } - else { + } else { pci_mode = bh->pci_mode_b; p2p_cfg = MV64x60_PCI1_P2P_CONFIG; pci_cfg_offset = 0xe4; @@ -1352,8 +1349,7 @@ mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus) val |= (child_bus << 16) | 0xff; mv64x60_write(bh, p2p_cfg, val); (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */ - } - else { /* PCI-X */ + } else { /* PCI-X */ /* * Need to use the current bus/dev number (that's in the * P2P CONFIG reg) to access the bridge's pci config space. @@ -1365,8 +1361,6 @@ mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus) pci_cfg_offset, child_bus << 8); mv64x60_pci_exclude_bridge = save_exclude; } - - return; } /* @@ -1423,8 +1417,6 @@ mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[], j++; } } - - return; } /* @@ -1498,8 +1490,6 @@ gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window, early_write_config_dword(hose, 0, PCI_DEVFN(0, 0), gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8); mv64x60_pci_exclude_bridge = save_exclude; - - return; } /* @@ -1523,8 +1513,6 @@ gt64260_set_pci2regs_window(struct mv64x60_handle *bh, early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus], (base << 16)); mv64x60_pci_exclude_bridge = save_exclude; - - return; } /* @@ -1561,7 +1549,6 @@ static void __init gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window) { pr_debug("enable 32bit window: %d\n", window); - return; } /* @@ -1584,8 +1571,6 @@ gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window) mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff); mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0); } - - return; } /* @@ -1599,7 +1584,6 @@ static void __init gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window) { pr_debug("enable 64bit window: %d\n", window); - return; /* Enabled when window configured (i.e., when top >= base) */ } /* @@ -1624,8 +1608,6 @@ gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window) mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0); mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0); } - - return; } /* @@ -1712,8 +1694,6 @@ gt64260_disable_all_windows(struct mv64x60_handle *bh, mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0); mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0); mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0); - - return; } /* @@ -1781,14 +1761,11 @@ gt64260a_chip_specific_init(struct mv64x60_handle *bh, mv64x60_mpsc1_pdata.cache_mgmt = 1; if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0)) - != NULL) { - + != NULL) { r->start = MV64x60_IRQ_SDMA_0; r->end = MV64x60_IRQ_SDMA_0; } #endif - - return; } /* @@ -1861,14 +1838,11 @@ gt64260b_chip_specific_init(struct mv64x60_handle *bh, mv64x60_mpsc1_pdata.cache_mgmt = 1; if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0)) - != NULL) { - + != NULL) { r->start = MV64x60_IRQ_SDMA_0; r->end = MV64x60_IRQ_SDMA_0; } #endif - - return; } /* @@ -1945,8 +1919,6 @@ mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window, mv64360_reg_addrs[bus][window].base_lo_bar, mv64x60_mask(base,20) | 0xc); mv64x60_pci_exclude_bridge = save_exclude; - - return; } /* @@ -1972,8 +1944,6 @@ mv64360_set_pci2regs_window(struct mv64x60_handle *bh, early_write_config_dword(hose, 0, PCI_DEVFN(0,0), mv64360_offset[bus][1], 0); mv64x60_pci_exclude_bridge = save_exclude; - - return; } /* @@ -2082,8 +2052,6 @@ mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window) "32bit table corrupted"); } } - - return; } /* @@ -2139,8 +2107,6 @@ mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window) "32bit table corrupted"); } } - - return; } /* @@ -2158,8 +2124,7 @@ mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window) (mv64360_64bit_windows[window].size_reg != 0)) { if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK) - == MV64x60_EXTRA_PCIACC_ENAB) - + == MV64x60_EXTRA_PCIACC_ENAB) mv64x60_set_bits(bh, mv64360_64bit_windows[window].base_lo_reg, (1 << (mv64360_64bit_windows[window].extra & @@ -2168,8 +2133,6 @@ mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window) printk(KERN_ERR "mv64360_enable: %s\n", "64bit table corrupted"); } - - return; } /* @@ -2186,11 +2149,9 @@ mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window) mv64360_64bit_windows[window].size_reg); if ((mv64360_64bit_windows[window].base_lo_reg != 0) && - (mv64360_64bit_windows[window].size_reg != 0)) { - + (mv64360_64bit_windows[window].size_reg != 0)) { if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK) - == MV64x60_EXTRA_PCIACC_ENAB) - + == MV64x60_EXTRA_PCIACC_ENAB) mv64x60_clr_bits(bh, mv64360_64bit_windows[window].base_lo_reg, (1 << (mv64360_64bit_windows[window].extra & @@ -2199,8 +2160,6 @@ mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window) printk(KERN_ERR "mv64360_disable: %s\n", "64bit table corrupted"); } - - return; } /* @@ -2241,8 +2200,6 @@ mv64360_disable_all_windows(struct mv64x60_handle *bh, /* Disable all PCI-><whatever> windows */ mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff); mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff); - - return; } /* @@ -2335,8 +2292,6 @@ mv64360_config_io2mem_windows(struct mv64x60_handle *bh, mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3, (0x3 << (i << 1))); } - - return; } /* @@ -2350,42 +2305,145 @@ static void __init mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base) { pr_debug("set mpsc->internal regs, base: 0x%x\n", base); - mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000); - return; } /* * mv64360_chip_specific_init() * - * No errata work arounds for the MV64360 implemented at this point. + * Implement errata work arounds for the MV64360. */ static void __init mv64360_chip_specific_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si) { +#if !defined(CONFIG_NOT_COHERENT_CACHE) + mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24)); +#endif #ifdef CONFIG_SERIAL_MPSC mv64x60_mpsc0_pdata.brg_can_tune = 1; mv64x60_mpsc0_pdata.cache_mgmt = 1; mv64x60_mpsc1_pdata.brg_can_tune = 1; mv64x60_mpsc1_pdata.cache_mgmt = 1; #endif - - return; } /* * mv64460_chip_specific_init() * - * No errata work arounds for the MV64460 implemented at this point. + * Implement errata work arounds for the MV64460. */ static void __init mv64460_chip_specific_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si) { +#if !defined(CONFIG_NOT_COHERENT_CACHE) + mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25)); + mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4)); +#endif #ifdef CONFIG_SERIAL_MPSC mv64x60_mpsc0_pdata.brg_can_tune = 1; + mv64x60_mpsc0_pdata.cache_mgmt = 1; mv64x60_mpsc1_pdata.brg_can_tune = 1; + mv64x60_mpsc1_pdata.cache_mgmt = 1; #endif - return; } + + +#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) +/* Export the hotswap register via sysfs for enum event monitoring */ +#define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */ + +DECLARE_MUTEX(mv64xxx_hs_lock); + +static ssize_t +mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count) +{ + u32 v; + u8 save_exclude; + + if (off > 0) + return 0; + if (count < VAL_LEN_MAX) + return -EINVAL; + + if (down_interruptible(&mv64xxx_hs_lock)) + return -ERESTARTSYS; + save_exclude = mv64x60_pci_exclude_bridge; + mv64x60_pci_exclude_bridge = 0; + early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, &v); + mv64x60_pci_exclude_bridge = save_exclude; + up(&mv64xxx_hs_lock); + + return sprintf(buf, "0x%08x\n", v); +} + +static ssize_t +mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count) +{ + u32 v; + u8 save_exclude; + + if (off > 0) + return 0; + if (count <= 0) + return -EINVAL; + + if (sscanf(buf, "%i", &v) == 1) { + if (down_interruptible(&mv64xxx_hs_lock)) + return -ERESTARTSYS; + save_exclude = mv64x60_pci_exclude_bridge; + mv64x60_pci_exclude_bridge = 0; + early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0), + MV64360_PCICFG_CPCI_HOTSWAP, v); + mv64x60_pci_exclude_bridge = save_exclude; + up(&mv64xxx_hs_lock); + } + else + count = -EINVAL; + + return count; +} + +static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */ + .attr = { + .name = "hs_reg", + .mode = S_IRUGO | S_IWUSR, + .owner = THIS_MODULE, + }, + .size = VAL_LEN_MAX, + .read = mv64xxx_hs_reg_read, + .write = mv64xxx_hs_reg_write, +}; + +/* Provide sysfs file indicating if this platform supports the hs_reg */ +static ssize_t +mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev; + struct mv64xxx_pdata *pdp; + u32 v; + + pdev = container_of(dev, struct platform_device, dev); + pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data; + + if (down_interruptible(&mv64xxx_hs_lock)) + return -ERESTARTSYS; + v = pdp->hs_reg_valid; + up(&mv64xxx_hs_lock); + + return sprintf(buf, "%i\n", v); +} +static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL); + +static int __init +mv64xxx_sysfs_init(void) +{ + sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr); + sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr); + return 0; +} +subsys_initcall(mv64xxx_sysfs_init); +#endif diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c index e5fd2ae503ea..9ccce438bd7a 100644 --- a/arch/ppc/syslib/ocp.c +++ b/arch/ppc/syslib/ocp.c @@ -165,7 +165,7 @@ ocp_device_remove(struct device *dev) } static int -ocp_device_suspend(struct device *dev, u32 state) +ocp_device_suspend(struct device *dev, pm_message_t state) { struct ocp_device *ocp_dev = to_ocp_dev(dev); struct ocp_driver *ocp_drv = to_ocp_drv(dev->driver); diff --git a/arch/ppc/syslib/of_device.c b/arch/ppc/syslib/of_device.c index 1eb4f726ca9f..da8a0f2128dc 100644 --- a/arch/ppc/syslib/of_device.c +++ b/arch/ppc/syslib/of_device.c @@ -105,7 +105,7 @@ static int of_device_remove(struct device *dev) return 0; } -static int of_device_suspend(struct device *dev, u32 state) +static int of_device_suspend(struct device *dev, pm_message_t state) { struct of_device * of_dev = to_of_device(dev); struct of_platform_driver * drv = to_of_platform_driver(dev->driver); diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c index ad39b86ca92c..53da58523e39 100644 --- a/arch/ppc/syslib/open_pic.c +++ b/arch/ppc/syslib/open_pic.c @@ -948,7 +948,7 @@ static void openpic_cached_disable_irq(u_int irq) * we need something better to deal with that... Maybe switch to S1 for * cpufreq changes */ -int openpic_suspend(struct sys_device *sysdev, u32 state) +int openpic_suspend(struct sys_device *sysdev, pm_message_t state) { int i; unsigned long flags; diff --git a/arch/ppc/syslib/open_pic2.c b/arch/ppc/syslib/open_pic2.c index 7e272c51a497..2e0ea92144f6 100644 --- a/arch/ppc/syslib/open_pic2.c +++ b/arch/ppc/syslib/open_pic2.c @@ -82,13 +82,11 @@ static void openpic2_end_irq(unsigned int irq_nr); static void openpic2_ack_irq(unsigned int irq_nr); struct hw_interrupt_type open_pic2 = { - " OpenPIC2 ", - NULL, - NULL, - openpic2_enable_irq, - openpic2_disable_irq, - openpic2_ack_irq, - openpic2_end_irq, + .typename = " OpenPIC2 ", + .enable = openpic2_enable_irq, + .disable = openpic2_disable_irq, + .ack = openpic2_ack_irq, + .end = openpic2_end_irq, }; /* diff --git a/arch/ppc/syslib/ppc403_pic.c b/arch/ppc/syslib/ppc403_pic.c index 06cb0af2a58d..ce4d1deb86e9 100644 --- a/arch/ppc/syslib/ppc403_pic.c +++ b/arch/ppc/syslib/ppc403_pic.c @@ -34,13 +34,10 @@ static void ppc403_aic_disable(unsigned int irq); static void ppc403_aic_disable_and_ack(unsigned int irq); static struct hw_interrupt_type ppc403_aic = { - "403GC AIC", - NULL, - NULL, - ppc403_aic_enable, - ppc403_aic_disable, - ppc403_aic_disable_and_ack, - 0 + .typename = "403GC AIC", + .enable = ppc403_aic_enable, + .disable = ppc403_aic_disable, + .ack = ppc403_aic_disable_and_ack, }; int diff --git a/arch/ppc/syslib/ppc4xx_setup.c b/arch/ppc/syslib/ppc4xx_setup.c index e170aebeb69b..b843c4fef25e 100644 --- a/arch/ppc/syslib/ppc4xx_setup.c +++ b/arch/ppc/syslib/ppc4xx_setup.c @@ -48,10 +48,6 @@ extern void abort(void); extern void ppc4xx_find_bridges(void); -extern void ppc4xx_wdt_heartbeat(void); -extern int wdt_enable; -extern unsigned long wdt_period; - /* Global Variables */ bd_t __res; @@ -171,7 +167,7 @@ ppc4xx_calibrate_decr(void) unsigned int freq; bd_t *bip = &__res; -#if defined(CONFIG_WALNUT) || defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE) +#if defined(CONFIG_WALNUT) || defined(CONFIG_SYCAMORE) /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */ mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE); #endif @@ -257,22 +253,6 @@ ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, *(char *) (r7 + KERNELBASE) = 0; strcpy(cmd_line, (char *) (r6 + KERNELBASE)); } -#if defined(CONFIG_PPC405_WDT) -/* Look for wdt= option on command line */ - if (strstr(cmd_line, "wdt=")) { - int valid_wdt = 0; - char *p, *q; - for (q = cmd_line; (p = strstr(q, "wdt=")) != 0;) { - q = p + 4; - if (p > cmd_line && p[-1] != ' ') - continue; - wdt_period = simple_strtoul(q, &q, 0); - valid_wdt = 1; - ++q; - } - wdt_enable = valid_wdt; - } -#endif /* Initialize machine-dependent vectors */ @@ -287,11 +267,6 @@ ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.calibrate_decr = ppc4xx_calibrate_decr; -#ifdef CONFIG_PPC405_WDT - ppc_md.heartbeat = ppc4xx_wdt_heartbeat; -#endif - ppc_md.heartbeat_count = 0; - ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory; ppc_md.setup_io_mappings = ppc4xx_map_io; diff --git a/arch/ppc/syslib/ppc83xx_pci.h b/arch/ppc/syslib/ppc83xx_pci.h new file mode 100644 index 000000000000..ec691640f6be --- /dev/null +++ b/arch/ppc/syslib/ppc83xx_pci.h @@ -0,0 +1,151 @@ +/* Created by Tony Li <tony.li@freescale.com> + * Copyright (c) 2005 freescale semiconductor + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __PPC_SYSLIB_PPC83XX_PCI_H +#define __PPC_SYSLIB_PPC83XX_PCI_H + +typedef struct immr_clk { + u32 spmr; /* system PLL mode Register */ + u32 occr; /* output clock control Register */ + u32 sccr; /* system clock control Register */ + u8 res0[0xF4]; +} immr_clk_t; + +/* + * Sequencer + */ +typedef struct immr_ios { + u32 potar0; + u8 res0[4]; + u32 pobar0; + u8 res1[4]; + u32 pocmr0; + u8 res2[4]; + u32 potar1; + u8 res3[4]; + u32 pobar1; + u8 res4[4]; + u32 pocmr1; + u8 res5[4]; + u32 potar2; + u8 res6[4]; + u32 pobar2; + u8 res7[4]; + u32 pocmr2; + u8 res8[4]; + u32 potar3; + u8 res9[4]; + u32 pobar3; + u8 res10[4]; + u32 pocmr3; + u8 res11[4]; + u32 potar4; + u8 res12[4]; + u32 pobar4; + u8 res13[4]; + u32 pocmr4; + u8 res14[4]; + u32 potar5; + u8 res15[4]; + u32 pobar5; + u8 res16[4]; + u32 pocmr5; + u8 res17[4]; + u8 res18[0x60]; + u32 pmcr; + u8 res19[4]; + u32 dtcr; + u8 res20[4]; +} immr_ios_t; +#define POTAR_TA_MASK 0x000fffff +#define POBAR_BA_MASK 0x000fffff +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ +#define POCMR_SE 0x20000000 /* streaming enable */ +#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ +#define POCMR_CM_MASK 0x000fffff + +/* + * PCI Controller Control and Status Registers + */ +typedef struct immr_pcictrl { + u32 esr; + u32 ecdr; + u32 eer; + u32 eatcr; + u32 eacr; + u32 eeacr; + u32 edlcr; + u32 edhcr; + u32 gcr; + u32 ecr; + u32 gsr; + u8 res0[12]; + u32 pitar2; + u8 res1[4]; + u32 pibar2; + u32 piebar2; + u32 piwar2; + u8 res2[4]; + u32 pitar1; + u8 res3[4]; + u32 pibar1; + u32 piebar1; + u32 piwar1; + u8 res4[4]; + u32 pitar0; + u8 res5[4]; + u32 pibar0; + u8 res6[4]; + u32 piwar0; + u8 res7[132]; +} immr_pcictrl_t; +#define PITAR_TA_MASK 0x000fffff +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E + +#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */ diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c index 602a86891f7f..890484e576e7 100644 --- a/arch/ppc/syslib/ppc83xx_setup.c +++ b/arch/ppc/syslib/ppc83xx_setup.c @@ -11,6 +11,17 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Added PCI support -- Tony Li <tony.li@freescale.com> */ #include <linux/config.h> @@ -31,6 +42,10 @@ #include <asm/delay.h> #include <syslib/ppc83xx_setup.h> +#if defined(CONFIG_PCI) +#include <asm/delay.h> +#include <syslib/ppc83xx_pci.h> +#endif phys_addr_t immrbar; @@ -162,4 +177,237 @@ mpc83xx_halt(void) for(;;); } -/* PCI SUPPORT DOES NOT EXIT, MODEL after ppc85xx_setup.c */ +#if defined(CONFIG_PCI) +void __init +mpc83xx_setup_pci1(struct pci_controller *hose) +{ + u16 reg16; + volatile immr_pcictrl_t * pci_ctrl; + volatile immr_ios_t * ios; + bd_t *binfo = (bd_t *) __res; + + pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t)); + ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); + + /* + * Configure PCI Outbound Translation Windows + */ + ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK; + ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK; + ios->pocmr0 = POCMR_EN | + (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM - + MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK); + + /* mapped to PCI1 IO space */ + ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK; + ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK; + ios->pocmr1 = POCMR_EN | POCMR_IO | + (((0xffffffff - (MPC83xx_PCI1_UPPER_IO - + MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl->pitar1 = 0x0; + pci_ctrl->pibar1 = 0x0; + pci_ctrl->piebar1 = 0x0; + pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; + + /* + * Release PCI RST signal + */ + pci_ctrl->gcr = 0; + udelay(2000); + pci_ctrl->gcr = 1; + udelay(2000); + + reg16 = 0xff; + early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); + early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); + + iounmap(pci_ctrl); + iounmap(ios); +} + +void __init +mpc83xx_setup_pci2(struct pci_controller *hose) +{ + u16 reg16; + volatile immr_pcictrl_t * pci_ctrl; + volatile immr_ios_t * ios; + bd_t *binfo = (bd_t *) __res; + + pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t)); + ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); + + /* + * Configure PCI Outbound Translation Windows + */ + ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK; + ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK; + ios->pocmr3 = POCMR_EN | POCMR_DST | + (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM - + MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK); + + /* mapped to PCI2 IO space */ + ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK; + ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK; + ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO | + (((0xffffffff - (MPC83xx_PCI2_UPPER_IO - + MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl->pitar1 = 0x0; + pci_ctrl->pibar1 = 0x0; + pci_ctrl->piebar1 = 0x0; + pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; + + /* + * Release PCI RST signal + */ + pci_ctrl->gcr = 0; + udelay(2000); + pci_ctrl->gcr = 1; + udelay(2000); + + reg16 = 0xff; + early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); + early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); + + iounmap(pci_ctrl); + iounmap(ios); +} + +/* + * PCI buses can be enabled only if SYS board combinates with PIB + * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses + * and 3 PCI slots, so people must configure the routes between them before + * enable PCI bus. This routes are under the control of PCA9555PW device which + * can be accessed via I2C bus 2 and are configured by firmware. Refer to + * Freescale to get more information about firmware configuration. + */ + +extern int mpc83xx_exclude_device(u_char bus, u_char devfn); +extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, + unsigned char pin); +void __init +mpc83xx_setup_hose(void) +{ + u32 val32; + volatile immr_clk_t * clk; + struct pci_controller * hose1; +#ifdef CONFIG_MPC83xx_PCI2 + struct pci_controller * hose2; +#endif + bd_t * binfo = (bd_t *)__res; + + clk = ioremap(binfo->bi_immr_base + 0xA00, + sizeof(immr_clk_t)); + + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + val32 = clk->occr; + udelay(2000); + clk->occr = 0xff000000; + udelay(2000); + + iounmap(clk); + + hose1 = pcibios_alloc_controller(); + if(!hose1) + return; + + ppc_md.pci_swizzle = common_swizzle; + ppc_md.pci_map_irq = mpc83xx_map_irq; + + hose1->bus_offset = 0; + hose1->first_busno = 0; + hose1->last_busno = 0xff; + + setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, + binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); + hose1->set_cfg_type = 1; + + mpc83xx_setup_pci1(hose1); + + hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; + hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; + hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; + + hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; + hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; + hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; +#ifdef CONFIG_MPC83xx_PCI2 + isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, + MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); +#else + isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, + MPC83xx_PCI1_IO_SIZE); +#endif /* CONFIG_MPC83xx_PCI2 */ + hose1->io_base_virt = (void *)isa_io_base; + /* setup resources */ + pci_init_resource(&hose1->io_resource, + MPC83xx_PCI1_LOWER_IO, + MPC83xx_PCI1_UPPER_IO, + IORESOURCE_IO, "PCI host bridge 1"); + pci_init_resource(&hose1->mem_resources[0], + MPC83xx_PCI1_LOWER_MEM, + MPC83xx_PCI1_UPPER_MEM, + IORESOURCE_MEM, "PCI host bridge 1"); + + ppc_md.pci_exclude_device = mpc83xx_exclude_device; + hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); + +#ifdef CONFIG_MPC83xx_PCI2 + hose2 = pcibios_alloc_controller(); + if(!hose2) + return; + + hose2->bus_offset = hose1->last_busno + 1; + hose2->first_busno = hose1->last_busno + 1; + hose2->last_busno = 0xff; + setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, + binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); + hose2->set_cfg_type = 1; + + mpc83xx_setup_pci2(hose2); + + hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; + hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; + hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; + + hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; + hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; + hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; + hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); + /* setup resources */ + pci_init_resource(&hose2->io_resource, + MPC83xx_PCI2_LOWER_IO, + MPC83xx_PCI2_UPPER_IO, + IORESOURCE_IO, "PCI host bridge 2"); + pci_init_resource(&hose2->mem_resources[0], + MPC83xx_PCI2_LOWER_MEM, + MPC83xx_PCI2_UPPER_MEM, + IORESOURCE_MEM, "PCI host bridge 2"); + + hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); +#endif /* CONFIG_MPC83xx_PCI2 */ +} +#endif /*CONFIG_PCI*/ diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h index 683f179b746c..c766c1a5f786 100644 --- a/arch/ppc/syslib/ppc83xx_setup.h +++ b/arch/ppc/syslib/ppc83xx_setup.h @@ -12,6 +12,14 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __PPC_SYSLIB_PPC83XX_SETUP_H @@ -19,7 +27,6 @@ #include <linux/config.h> #include <linux/init.h> -#include <asm/ppcboot.h> extern unsigned long mpc83xx_find_end_of_memory(void) __init; extern long mpc83xx_time_init(void) __init; @@ -31,13 +38,11 @@ extern void mpc83xx_halt(void); extern void mpc83xx_setup_hose(void) __init; /* PCI config */ -#if 0 -#define PCI1_CFG_ADDR_OFFSET (FIXME) -#define PCI1_CFG_DATA_OFFSET (FIXME) +#define PCI1_CFG_ADDR_OFFSET (0x8300) +#define PCI1_CFG_DATA_OFFSET (0x8304) -#define PCI2_CFG_ADDR_OFFSET (FIXME) -#define PCI2_CFG_DATA_OFFSET (FIXME) -#endif +#define PCI2_CFG_ADDR_OFFSET (0x8380) +#define PCI2_CFG_DATA_OFFSET (0x8384) /* Serial Config */ #ifdef CONFIG_SERIAL_MANY_PORTS diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c index 879202352560..52ba0c68078d 100644 --- a/arch/ppc/syslib/ppc_sys.c +++ b/arch/ppc/syslib/ppc_sys.c @@ -6,6 +6,7 @@ * Maintainer: Kumar Gala <kumar.gala@freescale.com> * * Copyright 2005 Freescale Semiconductor Inc. + * Copyright 2005 MontaVista, Inc. by Vitaly Bordug <vbordug@ru.mvista.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -35,10 +36,59 @@ void __init identify_ppc_sys_by_id(u32 id) void __init identify_ppc_sys_by_name(char *name) { - /* TODO */ + unsigned int i = 0; + while (ppc_sys_specs[i].ppc_sys_name[0]) + { + if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name)) + break; + i++; + } + cur_ppc_sys_spec = &ppc_sys_specs[i]; return; } +static int __init count_sys_specs(void) +{ + int i = 0; + while (ppc_sys_specs[i].ppc_sys_name[0]) + i++; + return i; +} + +static int __init find_chip_by_name_and_id(char *name, u32 id) +{ + int ret = -1; + unsigned int i = 0; + unsigned int j = 0; + unsigned int dups = 0; + + unsigned char matched[count_sys_specs()]; + + while (ppc_sys_specs[i].ppc_sys_name[0]) { + if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name)) + matched[j++] = i; + i++; + } + if (j != 0) { + for (i = 0; i < j; i++) { + if ((ppc_sys_specs[matched[i]].mask & id) == + ppc_sys_specs[matched[i]].value) { + ret = matched[i]; + dups++; + } + } + ret = (dups == 1) ? ret : (-1 * dups); + } + return ret; +} + +void __init identify_ppc_sys_by_name_and_id(char *name, u32 id) +{ + int i = find_chip_by_name_and_id(name, id); + BUG_ON(i < 0); + cur_ppc_sys_spec = &ppc_sys_specs[i]; +} + /* Update all memory resources by paddr, call before platform_device_register */ void __init ppc_sys_fixup_mem_resource(struct platform_device *pdev, phys_addr_t paddr) diff --git a/arch/ppc/syslib/pq2_devices.c b/arch/ppc/syslib/pq2_devices.c new file mode 100644 index 000000000000..1d3869768f96 --- /dev/null +++ b/arch/ppc/syslib/pq2_devices.c @@ -0,0 +1,389 @@ +/* + * arch/ppc/syslib/pq2_devices.c + * + * PQ2 Device descriptions + * + * Maintainer: Kumar Gala <kumar.gala@freescale.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/ioport.h> +#include <asm/cpm2.h> +#include <asm/irq.h> +#include <asm/ppc_sys.h> + +struct platform_device ppc_sys_platform_devices[] = { + [MPC82xx_CPM_FCC1] = { + .name = "fsl-cpm-fcc", + .id = 1, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "fcc_regs", + .start = 0x11300, + .end = 0x1131f, + .flags = IORESOURCE_MEM, + }, + { + .name = "fcc_pram", + .start = 0x8400, + .end = 0x84ff, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_FCC1, + .end = SIU_INT_FCC1, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_FCC2] = { + .name = "fsl-cpm-fcc", + .id = 2, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "fcc_regs", + .start = 0x11320, + .end = 0x1133f, + .flags = IORESOURCE_MEM, + }, + { + .name = "fcc_pram", + .start = 0x8500, + .end = 0x85ff, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_FCC2, + .end = SIU_INT_FCC2, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_FCC3] = { + .name = "fsl-cpm-fcc", + .id = 3, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "fcc_regs", + .start = 0x11340, + .end = 0x1135f, + .flags = IORESOURCE_MEM, + }, + { + .name = "fcc_pram", + .start = 0x8600, + .end = 0x86ff, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_FCC3, + .end = SIU_INT_FCC3, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_I2C] = { + .name = "fsl-cpm-i2c", + .id = 1, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "i2c_mem", + .start = 0x11860, + .end = 0x118BF, + .flags = IORESOURCE_MEM, + }, + { + .name = "i2c_pram", + .start = 0x8afc, + .end = 0x8afd, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_I2C, + .end = SIU_INT_I2C, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_SCC1] = { + .name = "fsl-cpm-scc", + .id = 1, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "scc_mem", + .start = 0x11A00, + .end = 0x11A1F, + .flags = IORESOURCE_MEM, + }, + { + .name = "scc_pram", + .start = 0x8000, + .end = 0x80ff, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_SCC1, + .end = SIU_INT_SCC1, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_SCC2] = { + .name = "fsl-cpm-scc", + .id = 2, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "scc_mem", + .start = 0x11A20, + .end = 0x11A3F, + .flags = IORESOURCE_MEM, + }, + { + .name = "scc_pram", + .start = 0x8100, + .end = 0x81ff, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_SCC2, + .end = SIU_INT_SCC2, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_SCC3] = { + .name = "fsl-cpm-scc", + .id = 3, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "scc_mem", + .start = 0x11A40, + .end = 0x11A5F, + .flags = IORESOURCE_MEM, + }, + { + .name = "scc_pram", + .start = 0x8200, + .end = 0x82ff, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_SCC3, + .end = SIU_INT_SCC3, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_SCC4] = { + .name = "fsl-cpm-scc", + .id = 4, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "scc_mem", + .start = 0x11A60, + .end = 0x11A7F, + .flags = IORESOURCE_MEM, + }, + { + .name = "scc_pram", + .start = 0x8300, + .end = 0x83ff, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_SCC4, + .end = SIU_INT_SCC4, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_SPI] = { + .name = "fsl-cpm-spi", + .id = 1, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "spi_mem", + .start = 0x11AA0, + .end = 0x11AFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "spi_pram", + .start = 0x89fc, + .end = 0x89fd, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_SPI, + .end = SIU_INT_SPI, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_MCC1] = { + .name = "fsl-cpm-mcc", + .id = 1, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "mcc_mem", + .start = 0x11B30, + .end = 0x11B3F, + .flags = IORESOURCE_MEM, + }, + { + .name = "mcc_pram", + .start = 0x8700, + .end = 0x877f, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_MCC1, + .end = SIU_INT_MCC1, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_MCC2] = { + .name = "fsl-cpm-mcc", + .id = 2, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "mcc_mem", + .start = 0x11B50, + .end = 0x11B5F, + .flags = IORESOURCE_MEM, + }, + { + .name = "mcc_pram", + .start = 0x8800, + .end = 0x887f, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_MCC2, + .end = SIU_INT_MCC2, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_SMC1] = { + .name = "fsl-cpm-smc", + .id = 1, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "smc_mem", + .start = 0x11A80, + .end = 0x11A8F, + .flags = IORESOURCE_MEM, + }, + { + .name = "smc_pram", + .start = 0x87fc, + .end = 0x87fd, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_SMC1, + .end = SIU_INT_SMC1, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_SMC2] = { + .name = "fsl-cpm-smc", + .id = 2, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "smc_mem", + .start = 0x11A90, + .end = 0x11A9F, + .flags = IORESOURCE_MEM, + }, + { + .name = "smc_pram", + .start = 0x88fc, + .end = 0x88fd, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_SMC2, + .end = SIU_INT_SMC2, + .flags = IORESOURCE_IRQ, + }, + }, + }, + [MPC82xx_CPM_USB] = { + .name = "fsl-cpm-usb", + .id = 1, + .num_resources = 3, + .resource = (struct resource[]) { + { + .name = "usb_mem", + .start = 0x11b60, + .end = 0x11b78, + .flags = IORESOURCE_MEM, + }, + { + .name = "usb_pram", + .start = 0x8b00, + .end = 0x8bff, + .flags = IORESOURCE_MEM, + }, + { + .start = SIU_INT_USB, + .end = SIU_INT_USB, + .flags = IORESOURCE_IRQ, + }, + + }, + }, + [MPC82xx_SEC1] = { + .name = "fsl-sec", + .id = 1, + .num_resources = 1, + .resource = (struct resource[]) { + { + .name = "sec_mem", + .start = 0x40000, + .end = 0x52fff, + .flags = IORESOURCE_MEM, + }, + }, + }, +}; + +static int __init mach_mpc82xx_fixup(struct platform_device *pdev) +{ + ppc_sys_fixup_mem_resource(pdev, CPM_MAP_ADDR); + return 0; +} + +static int __init mach_mpc82xx_init(void) +{ + if (ppc_md.progress) + ppc_md.progress("mach_mpc82xx_init:enter", 0); + ppc_sys_device_fixup = mach_mpc82xx_fixup; + return 0; +} + +postcore_initcall(mach_mpc82xx_init); diff --git a/arch/ppc/syslib/pq2_sys.c b/arch/ppc/syslib/pq2_sys.c new file mode 100644 index 000000000000..7b6c9ebdb9e3 --- /dev/null +++ b/arch/ppc/syslib/pq2_sys.c @@ -0,0 +1,200 @@ +/* + * arch/ppc/syslib/pq2_devices.c + * + * PQ2 System descriptions + * + * Maintainer: Kumar Gala <kumar.gala@freescale.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> + +#include <asm/ppc_sys.h> + +struct ppc_sys_spec *cur_ppc_sys_spec; +struct ppc_sys_spec ppc_sys_specs[] = { + /* below is a list of the 8260 family of processors */ + { + .ppc_sys_name = "8250", + .mask = 0x0000ff00, + .value = 0x00000000, + .num_devices = 12, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, + MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + } + }, + { + .ppc_sys_name = "8255", + .mask = 0x0000ff00, + .value = 0x00000000, + .num_devices = 11, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, + MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4, + MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, + MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + } + }, + { + .ppc_sys_name = "8260", + .mask = 0x0000ff00, + .value = 0x00000000, + .num_devices = 12, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, + MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + } + }, + { + .ppc_sys_name = "8264", + .mask = 0x0000ff00, + .value = 0x00000000, + .num_devices = 12, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, + MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + } + }, + { + .ppc_sys_name = "8265", + .mask = 0x0000ff00, + .value = 0x00000000, + .num_devices = 12, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, + MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + } + }, + { + .ppc_sys_name = "8266", + .mask = 0x0000ff00, + .value = 0x00000000, + .num_devices = 12, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, + MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + } + }, + /* below is a list of the 8272 family of processors */ + { + .ppc_sys_name = "8247", + .mask = 0x0000ff00, + .value = 0x00000d00, + .num_devices = 10, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, + MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + MPC82xx_CPM_USB, + }, + }, + { + .ppc_sys_name = "8248", + .mask = 0x0000ff00, + .value = 0x00000c00, + .num_devices = 11, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, + MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + MPC82xx_CPM_USB, MPC82xx_SEC1, + }, + }, + { + .ppc_sys_name = "8271", + .mask = 0x0000ff00, + .value = 0x00000d00, + .num_devices = 10, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, + MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + MPC82xx_CPM_USB, + }, + }, + { + .ppc_sys_name = "8272", + .mask = 0x0000ff00, + .value = 0x00000c00, + .num_devices = 11, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1, + MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + MPC82xx_CPM_USB, MPC82xx_SEC1, + }, + }, + /* below is a list of the 8280 family of processors */ + { + .ppc_sys_name = "8270", + .mask = 0x0000ff00, + .value = 0x00000a00, + .num_devices = 12, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, + MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + }, + }, + { + .ppc_sys_name = "8275", + .mask = 0x0000ff00, + .value = 0x00000a00, + .num_devices = 12, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, + MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_SMC1, + MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, MPC82xx_CPM_I2C, + }, + }, + { + .ppc_sys_name = "8280", + .mask = 0x0000ff00, + .value = 0x00000a00, + .num_devices = 13, + .device_list = (enum ppc_sys_devices[]) + { + MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_FCC3, + MPC82xx_CPM_SCC1, MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, + MPC82xx_CPM_SCC4, MPC82xx_CPM_MCC1, MPC82xx_CPM_MCC2, + MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI, + MPC82xx_CPM_I2C, + }, + }, + { + /* default match */ + .ppc_sys_name = "", + .mask = 0x00000000, + .value = 0x00000000, + }, +}; diff --git a/arch/ppc/syslib/prep_nvram.c b/arch/ppc/syslib/prep_nvram.c index 2bcf8a16d1c9..8599850ca772 100644 --- a/arch/ppc/syslib/prep_nvram.c +++ b/arch/ppc/syslib/prep_nvram.c @@ -15,7 +15,6 @@ #include <linux/ioport.h> #include <asm/sections.h> -#include <asm/segment.h> #include <asm/io.h> #include <asm/machdep.h> #include <asm/prep_nvram.h> diff --git a/arch/ppc/syslib/qspan_pci.c b/arch/ppc/syslib/qspan_pci.c index 57f4ed5e5ae1..0970b5d30391 100644 --- a/arch/ppc/syslib/qspan_pci.c +++ b/arch/ppc/syslib/qspan_pci.c @@ -94,7 +94,7 @@ #define mk_config_type1(bus, dev, offset) \ mk_config_addr(bus, dev, offset) | 1; -static spinlock_t pcibios_lock = SPIN_LOCK_UNLOCKED; +static DEFINE_SPINLOCK(pcibios_lock); int qspan_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned char *val) diff --git a/arch/ppc/syslib/xilinx_pic.c b/arch/ppc/syslib/xilinx_pic.c index e0bd66f0847a..2cbcad278cef 100644 --- a/arch/ppc/syslib/xilinx_pic.c +++ b/arch/ppc/syslib/xilinx_pic.c @@ -79,14 +79,11 @@ xilinx_intc_end(unsigned int irq) } static struct hw_interrupt_type xilinx_intc = { - "Xilinx Interrupt Controller", - NULL, - NULL, - xilinx_intc_enable, - xilinx_intc_disable, - xilinx_intc_disable_and_ack, - xilinx_intc_end, - 0 + .typename = "Xilinx Interrupt Controller", + .enable = xilinx_intc_enable, + .disable = xilinx_intc_disable, + .ack = xilinx_intc_disable_and_ack, + .end = xilinx_intc_end, }; int |