diff options
Diffstat (limited to 'arch')
470 files changed, 8840 insertions, 20932 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 56a4df952fb0..22e58a99f38b 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -477,7 +477,7 @@ config ALPHA_BROKEN_IRQ_MASK config VGA_HOSE bool - depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI + depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI) default y help Support VGA on an arbitrary hose; needed for several platforms diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h index f62251e82ffa..3bb7ffeae3bc 100644 --- a/arch/alpha/include/asm/atomic.h +++ b/arch/alpha/include/asm/atomic.h @@ -3,6 +3,7 @@ #include <linux/types.h> #include <asm/barrier.h> +#include <asm/cmpxchg.h> /* * Atomic operations that C can't guarantee us. Useful for @@ -168,73 +169,6 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) return result; } -/* - * Atomic exchange routines. - */ - -#define __ASM__MB -#define ____xchg(type, args...) __xchg ## type ## _local(args) -#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args) -#include <asm/xchg.h> - -#define xchg_local(ptr,x) \ - ({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \ - sizeof(*(ptr))); \ - }) - -#define cmpxchg_local(ptr, o, n) \ - ({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \ - (unsigned long)_n_, \ - sizeof(*(ptr))); \ - }) - -#define cmpxchg64_local(ptr, o, n) \ - ({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg_local((ptr), (o), (n)); \ - }) - -#ifdef CONFIG_SMP -#undef __ASM__MB -#define __ASM__MB "\tmb\n" -#endif -#undef ____xchg -#undef ____cmpxchg -#define ____xchg(type, args...) __xchg ##type(args) -#define ____cmpxchg(type, args...) __cmpxchg ##type(args) -#include <asm/xchg.h> - -#define xchg(ptr,x) \ - ({ \ - __typeof__(*(ptr)) _x_ = (x); \ - (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \ - sizeof(*(ptr))); \ - }) - -#define cmpxchg(ptr, o, n) \ - ({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ - (unsigned long)_n_, sizeof(*(ptr)));\ - }) - -#define cmpxchg64(ptr, o, n) \ - ({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg((ptr), (o), (n)); \ - }) - -#undef __ASM__MB -#undef ____cmpxchg - -#define __HAVE_ARCH_CMPXCHG 1 - #define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new)) #define atomic64_xchg(v, new) (xchg(&((v)->counter), new)) diff --git a/arch/alpha/include/asm/cmpxchg.h b/arch/alpha/include/asm/cmpxchg.h new file mode 100644 index 000000000000..429e8cd0d78e --- /dev/null +++ b/arch/alpha/include/asm/cmpxchg.h @@ -0,0 +1,71 @@ +#ifndef _ALPHA_CMPXCHG_H +#define _ALPHA_CMPXCHG_H + +/* + * Atomic exchange routines. + */ + +#define __ASM__MB +#define ____xchg(type, args...) __xchg ## type ## _local(args) +#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args) +#include <asm/xchg.h> + +#define xchg_local(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \ + sizeof(*(ptr))); \ +}) + +#define cmpxchg_local(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, \ + sizeof(*(ptr))); \ +}) + +#define cmpxchg64_local(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg_local((ptr), (o), (n)); \ +}) + +#ifdef CONFIG_SMP +#undef __ASM__MB +#define __ASM__MB "\tmb\n" +#endif +#undef ____xchg +#undef ____cmpxchg +#define ____xchg(type, args...) __xchg ##type(args) +#define ____cmpxchg(type, args...) __cmpxchg ##type(args) +#include <asm/xchg.h> + +#define xchg(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \ + sizeof(*(ptr))); \ +}) + +#define cmpxchg(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, sizeof(*(ptr)));\ +}) + +#define cmpxchg64(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg((ptr), (o), (n)); \ +}) + +#undef __ASM__MB +#undef ____cmpxchg + +#define __HAVE_ARCH_CMPXCHG 1 + +#endif /* _ALPHA_CMPXCHG_H */ diff --git a/arch/alpha/include/asm/rtc.h b/arch/alpha/include/asm/rtc.h index 1f7fba671ae6..d70408d36677 100644 --- a/arch/alpha/include/asm/rtc.h +++ b/arch/alpha/include/asm/rtc.h @@ -1,14 +1,10 @@ #ifndef _ALPHA_RTC_H #define _ALPHA_RTC_H -#if defined(CONFIG_ALPHA_GENERIC) +#if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) \ + || defined(CONFIG_ALPHA_GENERIC) # define get_rtc_time alpha_mv.rtc_get_time # define set_rtc_time alpha_mv.rtc_set_time -#else -# if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) -# define get_rtc_time marvel_get_rtc_time -# define set_rtc_time marvel_set_rtc_time -# endif #endif #include <asm-generic/rtc.h> diff --git a/arch/alpha/include/asm/xchg.h b/arch/alpha/include/asm/xchg.h index 1d1b436fbff2..0ca9724597c1 100644 --- a/arch/alpha/include/asm/xchg.h +++ b/arch/alpha/include/asm/xchg.h @@ -1,10 +1,10 @@ -#ifndef _ALPHA_ATOMIC_H +#ifndef _ALPHA_CMPXCHG_H #error Do not include xchg.h directly! #else /* * xchg/xchg_local and cmpxchg/cmpxchg_local share the same code * except that local version do not have the expensive memory barrier. - * So this file is included twice from asm/system.h. + * So this file is included twice from asm/cmpxchg.h. */ /* diff --git a/arch/alpha/kernel/core_tsunami.c b/arch/alpha/kernel/core_tsunami.c index 5e7c28f92f19..61893d7bdda5 100644 --- a/arch/alpha/kernel/core_tsunami.c +++ b/arch/alpha/kernel/core_tsunami.c @@ -11,6 +11,7 @@ #include <asm/core_tsunami.h> #undef __EXTERN_INLINE +#include <linux/module.h> #include <linux/types.h> #include <linux/pci.h> #include <linux/sched.h> diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index 14a4b6a7cf59..407accc80877 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c @@ -317,7 +317,7 @@ marvel_init_irq(void) } static int -marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { struct pci_controller *hose = dev->sysdata; struct io7_port *io7_port = hose->sysdata; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cf006d40342c..cece19202c6b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -340,8 +340,8 @@ config ARCH_AT91 select IRQ_DOMAIN select NEED_MACH_IO_H if PCCARD help - This enables support for systems based on the Atmel AT91RM9200, - AT91SAM9 processors. + This enables support for systems based on Atmel + AT91RM9200 and AT91SAM9* processors. config ARCH_BCMRING bool "Broadcom BCMRING" @@ -528,28 +528,6 @@ config ARCH_IOP33X help Support for Intel's IOP33X (XScale) family of processors. -config ARCH_IXP23XX - bool "IXP23XX-based" - depends on MMU - select CPU_XSC3 - select PCI - select ARCH_USES_GETTIMEOFFSET - select NEED_MACH_IO_H - select NEED_MACH_MEMORY_H - help - Support for Intel's IXP23xx (XScale) family of processors. - -config ARCH_IXP2000 - bool "IXP2400/2800-based" - depends on MMU - select CPU_XSCALE - select PCI - select ARCH_USES_GETTIMEOFFSET - select NEED_MACH_IO_H - select NEED_MACH_MEMORY_H - help - Support for Intel's IXP2400/2800 (XScale) family of processors. - config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU @@ -1046,10 +1024,6 @@ source "arch/arm/mach-iop13xx/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" -source "arch/arm/mach-ixp2000/Kconfig" - -source "arch/arm/mach-ixp23xx/Kconfig" - source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/mach-ks8695/Kconfig" @@ -1186,6 +1160,15 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config ARM_ERRATA_326103 + bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" + depends on CPU_V6 + help + Executing a SWP instruction to read-only memory does not set bit 11 + of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to + treat the access as a read, preventing a COW from occurring and + causing the faulting task to livelock. + config ARM_ERRATA_411920 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" depends on CPU_V6 || CPU_V6K diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 047a20780fc1..a0c40a0986cd 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -149,8 +149,6 @@ machine-$(CONFIG_ARCH_INTEGRATOR) := integrator machine-$(CONFIG_ARCH_IOP13XX) := iop13xx machine-$(CONFIG_ARCH_IOP32X) := iop32x machine-$(CONFIG_ARCH_IOP33X) := iop33x -machine-$(CONFIG_ARCH_IXP2000) := ixp2000 -machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood machine-$(CONFIG_ARCH_KS8695) := ks8695 diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c index 6ce11c481178..797f04bedb47 100644 --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c @@ -77,6 +77,8 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space) } else if (atag->hdr.tag == ATAG_MEM) { if (memcount >= sizeof(mem_reg_property)/4) continue; + if (!atag->u.mem.size) + continue; mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start); mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size); } else if (atag->hdr.tag == ATAG_INITRD2) { diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index aa5ee49c5c5a..6ab0599c02dd 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S @@ -32,10 +32,3 @@ __XScale_start: bic r0, r0, #0x1000 @ clear Icache mcr p15, 0, r0, c1, c0, 0 -#ifdef CONFIG_ARCH_IXP2000 - mov r1, #-1 - mov r0, #0xd6000000 - str r1, [r0, #0x14] - str r1, [r0, #0x18] -#endif - diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 5f6045f1766c..dc7e8ce8e6be 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -273,7 +273,7 @@ restart: adr r0, LC0 add r0, r0, #0x100 mov r1, r6 sub r2, sp, r6 - blne atags_to_fdt + bleq atags_to_fdt ldmfd sp!, {r0-r3, ip, lr} sub sp, sp, #0x10000 diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 799ad1889b51..773ef484037a 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -55,7 +55,6 @@ #interrupt-cells = <2>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; - interrupt-parent; reg = <0xfffff000 0x200>; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 9e6eb6ecea0e..c8042147eaa2 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -56,7 +56,6 @@ #interrupt-cells = <2>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; - interrupt-parent; reg = <0xfffff000 0x200>; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 70ab3a4e026f..dd4ed748469a 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -54,7 +54,6 @@ #interrupt-cells = <2>; compatible = "atmel,at91rm9200-aic"; interrupt-controller; - interrupt-parent; reg = <0xfffff000 0x200>; }; diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index d73dce645667..14bc30705099 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -24,7 +24,6 @@ #interrupt-cells = <3>; #address-cells = <1>; interrupt-controller; - interrupt-parent; reg = <0xa0411000 0x1000>, <0xa0410100 0x100>; }; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 37c0ff9c8b90..83e72294aefb 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -89,7 +89,6 @@ #size-cells = <0>; #address-cells = <1>; interrupt-controller; - interrupt-parent; reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; }; diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 15ded0deaa79..45bc4bb04e57 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -10,7 +10,7 @@ intc: interrupt-controller@02080000 { compatible = "qcom,msm-8660-qgic"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <3>; reg = < 0x02080000 0x1000 >, < 0x02081000 0x1000 >; }; @@ -19,6 +19,6 @@ compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <195>; + interrupts = <0 195 0x0>; }; }; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index 0b32925f2147..e2fe3195c0d1 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -173,7 +173,7 @@ mmc@5000 { compatible = "arm,primecell"; reg = < 0x5000 0x1000>; - interrupts = <22>; + interrupts = <22 34>; }; kmi@6000 { compatible = "arm,pl050", "arm,primecell"; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index 166461073b78..7e8175269064 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -41,7 +41,7 @@ mmc@b000 { compatible = "arm,primecell"; reg = <0xb000 0x1000>; - interrupts = <23>; + interrupts = <23 34>; }; }; }; diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 215816f1775f..e8a4e58f1b82 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -11,7 +11,5 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o obj-$(CONFIG_SHARP_SCOOP) += scoop.o -obj-$(CONFIG_ARCH_IXP2000) += uengine.o -obj-$(CONFIG_ARCH_IXP23XX) += uengine.o obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c deleted file mode 100644 index bef408f3d76c..000000000000 --- a/arch/arm/common/uengine.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Generic library functions for the microengines found on the Intel - * IXP2000 series of network processors. - * - * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> - * Dedicated to Marija Kulikova. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2.1 of the - * License, or (at your option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/hardware/uengine.h> - -#if defined(CONFIG_ARCH_IXP2000) -#define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE -#define IXP_PRODUCT_ID IXP2000_PRODUCT_ID -#define IXP_MISC_CONTROL IXP2000_MISC_CONTROL -#define IXP_RESET1 IXP2000_RESET1 -#else -#if defined(CONFIG_ARCH_IXP23XX) -#define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE -#define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID -#define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL -#define IXP_RESET1 IXP23XX_RESET1 -#else -#error unknown platform -#endif -#endif - -#define USTORE_ADDRESS 0x000 -#define USTORE_DATA_LOWER 0x004 -#define USTORE_DATA_UPPER 0x008 -#define CTX_ENABLES 0x018 -#define CC_ENABLE 0x01c -#define CSR_CTX_POINTER 0x020 -#define INDIRECT_CTX_STS 0x040 -#define ACTIVE_CTX_STS 0x044 -#define INDIRECT_CTX_SIG_EVENTS 0x048 -#define INDIRECT_CTX_WAKEUP_EVENTS 0x050 -#define NN_PUT 0x080 -#define NN_GET 0x084 -#define TIMESTAMP_LOW 0x0c0 -#define TIMESTAMP_HIGH 0x0c4 -#define T_INDEX_BYTE_INDEX 0x0f4 -#define LOCAL_CSR_STATUS 0x180 - -u32 ixp2000_uengine_mask; - -static void *ixp2000_uengine_csr_area(int uengine) -{ - return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10); -} - -/* - * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR - * space means that the microengine we tried to access was also trying - * to access its own CSR space on the same clock cycle as we did. When - * this happens, we lose the arbitration process by default, and the - * read or write we tried to do was not actually performed, so we try - * again until it succeeds. - */ -u32 ixp2000_uengine_csr_read(int uengine, int offset) -{ - void *uebase; - u32 *local_csr_status; - u32 *reg; - u32 value; - - uebase = ixp2000_uengine_csr_area(uengine); - - local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS); - reg = (u32 *)(uebase + offset); - do { - value = ixp2000_reg_read(reg); - } while (ixp2000_reg_read(local_csr_status) & 1); - - return value; -} -EXPORT_SYMBOL(ixp2000_uengine_csr_read); - -void ixp2000_uengine_csr_write(int uengine, int offset, u32 value) -{ - void *uebase; - u32 *local_csr_status; - u32 *reg; - - uebase = ixp2000_uengine_csr_area(uengine); - - local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS); - reg = (u32 *)(uebase + offset); - do { - ixp2000_reg_write(reg, value); - } while (ixp2000_reg_read(local_csr_status) & 1); -} -EXPORT_SYMBOL(ixp2000_uengine_csr_write); - -void ixp2000_uengine_reset(u32 uengine_mask) -{ - u32 value; - - value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask; - - uengine_mask &= ixp2000_uengine_mask; - ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask); - ixp2000_reg_wrb(IXP_RESET1, value); -} -EXPORT_SYMBOL(ixp2000_uengine_reset); - -void ixp2000_uengine_set_mode(int uengine, u32 mode) -{ - /* - * CTL_STR_PAR_EN: unconditionally enable parity checking on - * control store. - */ - mode |= 0x10000000; - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode); - - /* - * Enable updating of condition codes. - */ - ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000); - - /* - * Initialise other per-microengine registers. - */ - ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00); - ixp2000_uengine_csr_write(uengine, NN_GET, 0x00); - ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0); -} -EXPORT_SYMBOL(ixp2000_uengine_set_mode); - -static int make_even_parity(u32 x) -{ - return hweight32(x) & 1; -} - -static void ustore_write(int uengine, u64 insn) -{ - /* - * Generate even parity for top and bottom 20 bits. - */ - insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41; - insn |= (u64)make_even_parity(insn & 0x000fffff) << 40; - - /* - * Write to microstore. The second write auto-increments - * the USTORE_ADDRESS index register. - */ - ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn); - ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32)); -} - -void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns) -{ - int i; - - /* - * Start writing to microstore at address 0. - */ - ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000); - for (i = 0; i < insns; i++) { - u64 insn; - - insn = (((u64)ucode[0]) << 32) | - (((u64)ucode[1]) << 24) | - (((u64)ucode[2]) << 16) | - (((u64)ucode[3]) << 8) | - ((u64)ucode[4]); - ucode += 5; - - ustore_write(uengine, insn); - } - - /* - * Pad with a few NOPs at the end (to avoid the microengine - * aborting as it prefetches beyond the last instruction), unless - * we run off the end of the instruction store first, at which - * point the address register will wrap back to zero. - */ - for (i = 0; i < 4; i++) { - u32 addr; - - addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS); - if (addr == 0x80000000) - break; - ustore_write(uengine, 0xf0000c0300ULL); - } - - /* - * End programming. - */ - ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000); -} -EXPORT_SYMBOL(ixp2000_uengine_load_microcode); - -void ixp2000_uengine_init_context(int uengine, int context, int pc) -{ - /* - * Select the right context for indirect access. - */ - ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context); - - /* - * Initialise signal masks to immediately go to Ready state. - */ - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1); - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1); - - /* - * Set program counter. - */ - ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc); -} -EXPORT_SYMBOL(ixp2000_uengine_init_context); - -void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask) -{ - u32 mask; - - /* - * Enable the specified context to go to Executing state. - */ - mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES); - mask |= ctx_mask << 8; - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask); -} -EXPORT_SYMBOL(ixp2000_uengine_start_contexts); - -void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask) -{ - u32 mask; - - /* - * Disable the Ready->Executing transition. Note that this - * does not stop the context until it voluntarily yields. - */ - mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES); - mask &= ~(ctx_mask << 8); - ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask); -} -EXPORT_SYMBOL(ixp2000_uengine_stop_contexts); - -static int check_ixp_type(struct ixp2000_uengine_code *c) -{ - u32 product_id; - u32 rev; - - product_id = ixp2000_reg_read(IXP_PRODUCT_ID); - if (((product_id >> 16) & 0x1f) != 0) - return 0; - - switch ((product_id >> 8) & 0xff) { -#ifdef CONFIG_ARCH_IXP2000 - case 0: /* IXP2800 */ - if (!(c->cpu_model_bitmask & 4)) - return 0; - break; - - case 1: /* IXP2850 */ - if (!(c->cpu_model_bitmask & 8)) - return 0; - break; - - case 2: /* IXP2400 */ - if (!(c->cpu_model_bitmask & 2)) - return 0; - break; -#endif - -#ifdef CONFIG_ARCH_IXP23XX - case 4: /* IXP23xx */ - if (!(c->cpu_model_bitmask & 0x3f0)) - return 0; - break; -#endif - - default: - return 0; - } - - rev = product_id & 0xff; - if (rev < c->cpu_min_revision || rev > c->cpu_max_revision) - return 0; - - return 1; -} - -static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) -{ - int offset; - int i; - - offset = 0; - - for (i = 0; i < 128; i++) { - u8 b3; - u8 b2; - u8 b1; - u8 b0; - - b3 = (gpr_a[i] >> 24) & 0xff; - b2 = (gpr_a[i] >> 16) & 0xff; - b1 = (gpr_a[i] >> 8) & 0xff; - b0 = gpr_a[i] & 0xff; - - /* immed[@ai, (b1 << 8) | b0] */ - /* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */ - ucode[offset++] = 0xf0; - ucode[offset++] = (b1 >> 4); - ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6); - ucode[offset++] = (b0 << 2); - ucode[offset++] = 0x80 | i; - - /* immed_w1[@ai, (b3 << 8) | b2] */ - /* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */ - ucode[offset++] = 0xf4; - ucode[offset++] = 0x40 | (b3 >> 4); - ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6); - ucode[offset++] = (b2 << 2); - ucode[offset++] = 0x80 | i; - } - - for (i = 0; i < 128; i++) { - u8 b3; - u8 b2; - u8 b1; - u8 b0; - - b3 = (gpr_b[i] >> 24) & 0xff; - b2 = (gpr_b[i] >> 16) & 0xff; - b1 = (gpr_b[i] >> 8) & 0xff; - b0 = gpr_b[i] & 0xff; - - /* immed[@bi, (b1 << 8) | b0] */ - /* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */ - ucode[offset++] = 0xf0; - ucode[offset++] = (b1 >> 4); - ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6); - ucode[offset++] = (i << 2) | 0x03; - ucode[offset++] = b0; - - /* immed_w1[@bi, (b3 << 8) | b2] */ - /* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */ - ucode[offset++] = 0xf4; - ucode[offset++] = 0x40 | (b3 >> 4); - ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6); - ucode[offset++] = (i << 2) | 0x03; - ucode[offset++] = b2; - } - - /* ctx_arb[kill] */ - ucode[offset++] = 0xe0; - ucode[offset++] = 0x00; - ucode[offset++] = 0x01; - ucode[offset++] = 0x00; - ucode[offset++] = 0x00; -} - -static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c) -{ - int per_ctx_regs; - u32 *gpr_a; - u32 *gpr_b; - u8 *ucode; - int i; - - gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL); - gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL); - ucode = kmalloc(513 * 5, GFP_KERNEL); - if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) { - kfree(ucode); - kfree(gpr_b); - kfree(gpr_a); - return 1; - } - - per_ctx_regs = 16; - if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS) - per_ctx_regs = 32; - - for (i = 0; i < 256; i++) { - struct ixp2000_reg_value *r = c->initial_reg_values + i; - u32 *bank; - int inc; - int j; - - if (r->reg == -1) - break; - - bank = (r->reg & 0x400) ? gpr_b : gpr_a; - inc = (r->reg & 0x80) ? 128 : per_ctx_regs; - - j = r->reg & 0x7f; - while (j < 128) { - bank[j] = r->value; - j += inc; - } - } - - generate_ucode(ucode, gpr_a, gpr_b); - ixp2000_uengine_load_microcode(uengine, ucode, 513); - ixp2000_uengine_init_context(uengine, 0, 0); - ixp2000_uengine_start_contexts(uengine, 0x01); - for (i = 0; i < 100; i++) { - u32 status; - - status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS); - if (!(status & 0x80000000)) - break; - } - ixp2000_uengine_stop_contexts(uengine, 0x01); - - kfree(ucode); - kfree(gpr_b); - kfree(gpr_a); - - return !!(i == 100); -} - -int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c) -{ - int ctx; - - if (!check_ixp_type(c)) - return 1; - - if (!(ixp2000_uengine_mask & (1 << uengine))) - return 1; - - ixp2000_uengine_reset(1 << uengine); - ixp2000_uengine_set_mode(uengine, c->uengine_parameters); - if (set_initial_registers(uengine, c)) - return 1; - ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns); - - for (ctx = 0; ctx < 8; ctx++) - ixp2000_uengine_init_context(uengine, ctx, 0); - - return 0; -} -EXPORT_SYMBOL(ixp2000_uengine_load); - - -static int __init ixp2000_uengine_init(void) -{ - int uengine; - u32 value; - - /* - * Determine number of microengines present. - */ - switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) { -#ifdef CONFIG_ARCH_IXP2000 - case 0: /* IXP2800 */ - case 1: /* IXP2850 */ - ixp2000_uengine_mask = 0x00ff00ff; - break; - - case 2: /* IXP2400 */ - ixp2000_uengine_mask = 0x000f000f; - break; -#endif - -#ifdef CONFIG_ARCH_IXP23XX - case 4: /* IXP23xx */ - ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf; - break; -#endif - - default: - printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n", - (unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID)); - ixp2000_uengine_mask = 0x00000000; - break; - } - - /* - * Reset microengines. - */ - ixp2000_uengine_reset(ixp2000_uengine_mask); - - /* - * Synchronise timestamp counters across all microengines. - */ - value = ixp2000_reg_read(IXP_MISC_CONTROL); - ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80); - for (uengine = 0; uengine < 32; uengine++) { - if (ixp2000_uengine_mask & (1 << uengine)) { - ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0); - ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0); - } - } - ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80); - - return 0; -} - -subsys_initcall(ixp2000_uengine_init); diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 7a66311f3066..7e288f96cedf 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -427,19 +427,18 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent) /* * Handle each interrupt in a single VIC. Returns non-zero if we've - * handled at least one interrupt. This does a single read of the - * status register and handles all interrupts in order from LSB first. + * handled at least one interrupt. This reads the status register + * before handling each interrupt, which is necessary given that + * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. */ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) { u32 stat, irq; int handled = 0; - stat = readl_relaxed(vic->base + VIC_IRQ_STATUS); - while (stat) { + while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { irq = ffs(stat) - 1; handle_IRQ(irq_find_mapping(vic->domain, irq), regs); - stat &= ~(1 << irq); handled = 1; } diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig new file mode 100644 index 000000000000..67bc571ed0c3 --- /dev/null +++ b/arch/arm/configs/at91_dt_defconfig @@ -0,0 +1,196 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_AT91=y +CONFIG_SOC_AT91SAM9260=y +CONFIG_SOC_AT91SAM9263=y +CONFIG_SOC_AT91SAM9G45=y +CONFIG_SOC_AT91SAM9X5=y +CONFIG_MACH_AT91SAM_DT=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_AT91_TIMER_HZ=128 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" +CONFIG_KEXEC=y +CONFIG_AUTO_ZRELADDR=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT_6RD=y +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_ATMEL_PWM=y +CONFIG_ATMEL_TCLIB=y +CONFIG_EEPROM_93CX6=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_MACB=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_DAVICOM_PHY=y +CONFIG_MICREL_PHY=y +# CONFIG_WLAN is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_SERIO is not set +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_SPI=y +CONFIG_SPI_ATMEL=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_AT91SAM9X_WATCHDOG=y +CONFIG_SSB=m +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_ATMEL=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_ATMEL_LCDC=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_FONT_MINI_4x6=y +CONFIG_LOGO=y +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_GADGET=y +CONFIG_USB_AT91=m +CONFIG_USB_ATMEL_USBA=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_RTC_DRV_AT91SAM9=y +CONFIG_DMADEVICES=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +CONFIG_FANOTIFY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_CCITT=m +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m +CONFIG_AVERAGE=y diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig index bbe4e1a1f5d8..d54e2acd3ab1 100644 --- a/arch/arm/configs/at91rm9200_defconfig +++ b/arch/arm/configs/at91rm9200_defconfig @@ -14,6 +14,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_CFQ is not set CONFIG_ARCH_AT91=y +CONFIG_ARCH_AT91RM9200=y CONFIG_MACH_ONEARM=y CONFIG_ARCH_AT91RM9200DK=y CONFIG_MACH_AT91RM9200EK=y diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index b5ac644e12af..6b31cb60daab 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -112,6 +112,7 @@ CONFIG_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_MFD_MC13XXX=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_FB=y diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig deleted file mode 100644 index 8405aded97a3..000000000000 --- a/arch/arm/configs/ixp2000_defconfig +++ /dev/null @@ -1,99 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_HOTPLUG is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_ARCH_IXP2000=y -CONFIG_ARCH_ENP2611=y -CONFIG_ARCH_IXDP2400=y -CONFIG_ARCH_IXDP2800=y -CONFIG_ARCH_IXDP2401=y -CONFIG_ARCH_IXDP2801=y -# CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO is not set -# CONFIG_ARM_THUMB is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0" -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_SYN_COOKIES=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_IXP2000=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_EEPROM_LEGACY=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_CS89x0=y -CONFIG_E100=y -CONFIG_ENP2611_MSF_NET=y -CONFIG_WAN=y -CONFIG_HDLC=y -CONFIG_HDLC_RAW=y -CONFIG_HDLC_CISCO=y -CONFIG_HDLC_FR=y -CONFIG_HDLC_PPP=y -CONFIG_DLCI=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=3 -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IXP2000=y -CONFIG_WATCHDOG=y -CONFIG_IXP2000_WATCHDOG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_INOTIFY=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig deleted file mode 100644 index 688717612e91..000000000000 --- a/arch/arm/configs/ixp23xx_defconfig +++ /dev/null @@ -1,105 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_ARCH_IXP23XX=y -CONFIG_MACH_ESPRESSO=y -CONFIG_MACH_IXDP2351=y -CONFIG_MACH_ROADRUNNER=y -# CONFIG_ARM_THUMB is not set -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp" -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_SYN_COOKIES=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_EEPROM_LEGACY=y -CONFIG_IDE=y -CONFIG_BLK_DEV_SIIMAGE=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_E100=y -CONFIG_E1000=y -CONFIG_WAN=y -CONFIG_HDLC=y -CONFIG_HDLC_RAW=y -CONFIG_HDLC_CISCO=y -CONFIG_HDLC_FR=y -CONFIG_HDLC_PPP=y -CONFIG_DLCI=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_WATCHDOG=y -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_INOTIFY=y -CONFIG_MSDOS_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 42da9183acc8..082175c54e7c 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_BLK_DEV_INTEGRITY=y CONFIG_ARCH_S3C24XX=y +# CONFIG_CPU_S3C2410 is not set +CONFIG_CPU_S3C2440=y CONFIG_S3C_ADC=y CONFIG_S3C24XX_PWM=y CONFIG_MACH_MINI2440=y diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 889d73ac1ae1..7e84f453e8a6 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_U8500=y -CONFIG_UX500_SOC_DB5500=y -CONFIG_UX500_SOC_DB8500=y CONFIG_MACH_HREFV60=y CONFIG_MACH_SNOWBALL=y CONFIG_MACH_U5500=y @@ -39,7 +37,6 @@ CONFIG_CAIF=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_MISC_DEVICES=y CONFIG_AB8500_PWM=y CONFIG_SENSORS_BH1780=y CONFIG_NETDEVICES=y @@ -65,16 +62,18 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_NOMADIK=y -CONFIG_I2C=y -CONFIG_I2C_NOMADIK=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_TC3589X=y +CONFIG_POWER_SUPPLY=y +CONFIG_AB8500_BM=y +CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y CONFIG_MFD_STMPE=y CONFIG_MFD_TC3589X=y CONFIG_AB5500_CORE=y CONFIG_AB8500_CORE=y +CONFIG_REGULATOR=y CONFIG_REGULATOR_AB8500=y # CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y diff --git a/arch/arm/include/asm/hardware/clps7111.h b/arch/arm/include/asm/hardware/clps7111.h index 44477225aed6..78e2856b06dc 100644 --- a/arch/arm/include/asm/hardware/clps7111.h +++ b/arch/arm/include/asm/hardware/clps7111.h @@ -23,16 +23,7 @@ #ifndef __ASM_HARDWARE_CLPS7111_H #define __ASM_HARDWARE_CLPS7111_H -#define CLPS7111_PHYS_BASE (0x80000000) - -#ifndef __ASSEMBLY__ -#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) -#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off)) -#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) -#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) -#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off)) -#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) -#endif +#define CLPS711X_PHYS_BASE (0x80000000) #define PADR (0x0000) #define PBDR (0x0001) diff --git a/arch/arm/include/asm/hardware/ep7211.h b/arch/arm/include/asm/hardware/ep7211.h index 654d5f625c49..4b3f86bf1bfc 100644 --- a/arch/arm/include/asm/hardware/ep7211.h +++ b/arch/arm/include/asm/hardware/ep7211.h @@ -23,15 +23,6 @@ #ifndef __ASM_HARDWARE_EP7211_H #define __ASM_HARDWARE_EP7211_H -#include <asm/hardware/clps7111.h> - -/* - * define EP7211_BASE to be the base address of the region - * you want to access. - */ - -#define EP7211_PHYS_BASE (0x80000000) - /* * XXX miket@bluemug.com: need to introduce EP7211 registers (those not * present in 7212) here. diff --git a/arch/arm/include/asm/hardware/ep7212.h b/arch/arm/include/asm/hardware/ep7212.h index 3b43bbeaf1db..aad07f77dcff 100644 --- a/arch/arm/include/asm/hardware/ep7212.h +++ b/arch/arm/include/asm/hardware/ep7212.h @@ -24,18 +24,6 @@ #define __ASM_HARDWARE_EP7212_H /* - * define EP7212_BASE to be the base address of the region - * you want to access. - */ - -#define EP7212_PHYS_BASE (0x80000000) - -#ifndef __ASSEMBLY__ -#define ep_readl(off) __raw_readl(EP7212_BASE + (off)) -#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off)) -#endif - -/* * These registers are specific to the EP7212 only */ #define DAIR 0x2000 diff --git a/arch/arm/include/asm/hardware/uengine.h b/arch/arm/include/asm/hardware/uengine.h deleted file mode 100644 index b442d65c6593..000000000000 --- a/arch/arm/include/asm/hardware/uengine.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Generic library functions for the microengines found on the Intel - * IXP2000 series of network processors. - * - * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org> - * Dedicated to Marija Kulikova. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as - * published by the Free Software Foundation; either version 2.1 of the - * License, or (at your option) any later version. - */ - -#ifndef __IXP2000_UENGINE_H -#define __IXP2000_UENGINE_H - -extern u32 ixp2000_uengine_mask; - -struct ixp2000_uengine_code -{ - u32 cpu_model_bitmask; - u8 cpu_min_revision; - u8 cpu_max_revision; - - u32 uengine_parameters; - - struct ixp2000_reg_value { - int reg; - u32 value; - } *initial_reg_values; - - int num_insns; - u8 *insns; -}; - -u32 ixp2000_uengine_csr_read(int uengine, int offset); -void ixp2000_uengine_csr_write(int uengine, int offset, u32 value); -void ixp2000_uengine_reset(u32 uengine_mask); -void ixp2000_uengine_set_mode(int uengine, u32 mode); -void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns); -void ixp2000_uengine_init_context(int uengine, int context, int pc); -void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask); -void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask); -int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c); - -#define IXP2000_UENGINE_8_CONTEXTS 0x00000000 -#define IXP2000_UENGINE_4_CONTEXTS 0x80000000 -#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000 -#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000 -#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000 -#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000 -#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000 -#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000 -#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000 -#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000 -#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000 - - -#endif diff --git a/arch/arm/include/asm/jump_label.h b/arch/arm/include/asm/jump_label.h index 5c5ca2ea62b0..bfc198c75913 100644 --- a/arch/arm/include/asm/jump_label.h +++ b/arch/arm/include/asm/jump_label.h @@ -14,7 +14,7 @@ #define JUMP_LABEL_NOP "nop" #endif -static __always_inline bool arch_static_branch(struct jump_label_key *key) +static __always_inline bool arch_static_branch(struct static_key *key) { asm goto("1:\n\t" JUMP_LABEL_NOP "\n\t" diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index d4c24d412a8d..0f04d84582e1 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *); extern void vfp_sync_hwstate(struct thread_info *); extern void vfp_flush_hwstate(struct thread_info *); +struct user_vfp; +struct user_vfp_exc; + +extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *, + struct user_vfp_exc __user *); +extern int vfp_restore_user_hwstate(struct user_vfp __user *, + struct user_vfp_exc __user *); #endif /* diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index 60843eb0f61c..73409e6c0251 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -7,6 +7,8 @@ .macro set_tls_v6k, tp, tmp1, tmp2 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register + mov \tmp1, #0 + mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register .endm .macro set_tls_v6, tp, tmp1, tmp2 @@ -15,6 +17,8 @@ mov \tmp2, #0xffff0fff tst \tmp1, #HWCAP_TLS @ hardware TLS available? mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register + movne \tmp1, #0 + mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 .endm diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 71ccdbfed662..8349d4e97e2b 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc) } c = irq_data_get_irq_chip(d); - if (c->irq_set_affinity) - c->irq_set_affinity(d, affinity, true); - else + if (!c->irq_set_affinity) pr_debug("IRQ%u: unable to set affinity\n", d->irq); + else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret) + cpumask_copy(d->affinity, affinity); return ret; } diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index b91411371ae1..ebfac782593f 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -523,7 +523,21 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size) */ size -= start & ~PAGE_MASK; bank->start = PAGE_ALIGN(start); - bank->size = size & PAGE_MASK; + +#ifndef CONFIG_LPAE + if (bank->start + size < bank->start) { + printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " + "32-bit physical address space\n", (long long)start); + /* + * To ensure bank->start + bank->size is representable in + * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB. + * This means we lose a page after masking. + */ + size = ULONG_MAX - bank->start; + } +#endif + + bank->size = size & PAGE_MASK; /* * Check whether this memory region has non-zero size or diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 7cb532fc8aa4..d68d1b694680 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame) static int preserve_vfp_context(struct vfp_sigframe __user *frame) { - struct thread_info *thread = current_thread_info(); - struct vfp_hard_struct *h = &thread->vfpstate.hard; const unsigned long magic = VFP_MAGIC; const unsigned long size = VFP_STORAGE_SIZE; int err = 0; - vfp_sync_hwstate(thread); __put_user_error(magic, &frame->magic, err); __put_user_error(size, &frame->size, err); - /* - * Copy the floating point registers. There can be unused - * registers see asm/hwcap.h for details. - */ - err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs, - sizeof(h->fpregs)); - /* - * Copy the status and control register. - */ - __put_user_error(h->fpscr, &frame->ufp.fpscr, err); - - /* - * Copy the exception registers. - */ - __put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err); - __put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); - __put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); + if (err) + return -EFAULT; - return err ? -EFAULT : 0; + return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc); } static int restore_vfp_context(struct vfp_sigframe __user *frame) { - struct thread_info *thread = current_thread_info(); - struct vfp_hard_struct *h = &thread->vfpstate.hard; unsigned long magic; unsigned long size; - unsigned long fpexc; int err = 0; __get_user_error(magic, &frame->magic, err); @@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame) if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) return -EINVAL; - vfp_flush_hwstate(thread); - - /* - * Copy the floating point registers. There can be unused - * registers see asm/hwcap.h for details. - */ - err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs, - sizeof(h->fpregs)); - /* - * Copy the status and control register. - */ - __get_user_error(h->fpscr, &frame->ufp.fpscr, err); - - /* - * Sanitise and restore the exception registers. - */ - __get_user_error(fpexc, &frame->ufp_exc.fpexc, err); - /* Ensure the VFP is enabled. */ - fpexc |= FPEXC_EN; - /* Ensure FPINST2 is invalid and the exception flag is cleared. */ - fpexc &= ~(FPEXC_EX | FPEXC_FP2V); - h->fpexc = fpexc; - - __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err); - __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err); - - return err ? -EFAULT : 0; + return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc); } #endif diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index addbbe8028c2..f6a4d32b0421 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -510,10 +510,6 @@ static void ipi_cpu_stop(unsigned int cpu) local_fiq_disable(); local_irq_disable(); -#ifdef CONFIG_HOTPLUG_CPU - platform_cpu_kill(cpu); -#endif - while (1) cpu_relax(); } @@ -576,17 +572,25 @@ void smp_send_reschedule(int cpu) smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); } +#ifdef CONFIG_HOTPLUG_CPU +static void smp_kill_cpus(cpumask_t *mask) +{ + unsigned int cpu; + for_each_cpu(cpu, mask) + platform_cpu_kill(cpu); +} +#else +static void smp_kill_cpus(cpumask_t *mask) { } +#endif + void smp_send_stop(void) { unsigned long timeout; + struct cpumask mask; - if (num_online_cpus() > 1) { - struct cpumask mask; - cpumask_copy(&mask, cpu_online_mask); - cpumask_clear_cpu(smp_processor_id(), &mask); - - smp_cross_call(&mask, IPI_CPU_STOP); - } + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(smp_processor_id(), &mask); + smp_cross_call(&mask, IPI_CPU_STOP); /* Wait up to one second for other CPUs to stop */ timeout = USEC_PER_SEC; @@ -595,6 +599,8 @@ void smp_send_stop(void) if (num_online_cpus() > 1) pr_warning("SMP: failed to stop secondary CPUs\n"); + + smp_kill_cpus(&mask); } /* diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 45db05d8d94c..98a42f3472d5 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -9,15 +9,6 @@ config HAVE_AT91_DBGU0 config HAVE_AT91_DBGU1 bool -config HAVE_AT91_USART3 - bool - -config HAVE_AT91_USART4 - bool - -config HAVE_AT91_USART5 - bool - config AT91_SAM9_ALT_RESET bool default !ARCH_AT91X40 @@ -26,87 +17,121 @@ config AT91_SAM9G45_RESET bool default !ARCH_AT91X40 +config SOC_AT91SAM9 + bool + select GENERIC_CLOCKEVENTS + select CPU_ARM926T + menu "Atmel AT91 System-on-Chip" -choice - prompt "Atmel AT91 Processor" +comment "Atmel AT91 Processor" -config ARCH_AT91RM9200 +config SOC_AT91SAM9 + bool + select CPU_ARM926T + select AT91_SAM9_TIME + select AT91_SAM9_SMC + +config SOC_AT91RM9200 bool "AT91RM9200" select CPU_ARM920T select GENERIC_CLOCKEVENTS select HAVE_AT91_DBGU0 - select HAVE_AT91_USART3 -config ARCH_AT91SAM9260 - bool "AT91SAM9260 or AT91SAM9XE" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS +config SOC_AT91SAM9260 + bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 - select HAVE_AT91_USART3 - select HAVE_AT91_USART4 - select HAVE_AT91_USART5 select HAVE_NET_MACB + help + Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE + or AT91SAM9G20 SoC. -config ARCH_AT91SAM9261 - bool "AT91SAM9261" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS +config SOC_AT91SAM9261 + bool "AT91SAM9261 or AT91SAM9G10" + select SOC_AT91SAM9 + select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL + help + Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. + +config SOC_AT91SAM9263 + bool "AT91SAM9263" + select SOC_AT91SAM9 + select HAVE_AT91_DBGU1 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + +config SOC_AT91SAM9RL + bool "AT91SAM9RL" + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 + select HAVE_FB_ATMEL -config ARCH_AT91SAM9G10 - bool "AT91SAM9G10" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS +config SOC_AT91SAM9G45 + bool "AT91SAM9G45 or AT91SAM9M10 families" + select SOC_AT91SAM9 + select HAVE_AT91_DBGU1 + select HAVE_FB_ATMEL + select HAVE_NET_MACB + help + Select this if you are using one of Atmel's AT91SAM9G45 family SoC. + This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. + +config SOC_AT91SAM9X5 + bool "AT91SAM9x5 family" + select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL + select HAVE_NET_MACB + help + Select this if you are using one of Atmel's AT91SAM9x5 family SoC. + This means that your SAM9 name finishes with a '5' (except if it is + AT91SAM9G45!). + This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35 + and AT91SAM9X35. + +choice + prompt "Atmel AT91 Processor Devices for non DT boards" + +config ARCH_AT91_NONE + bool "None" + +config ARCH_AT91RM9200 + bool "AT91RM9200" + select SOC_AT91RM9200 + +config ARCH_AT91SAM9260 + bool "AT91SAM9260 or AT91SAM9XE" + select SOC_AT91SAM9260 + +config ARCH_AT91SAM9261 + bool "AT91SAM9261" + select SOC_AT91SAM9261 + +config ARCH_AT91SAM9G10 + bool "AT91SAM9G10" + select SOC_AT91SAM9261 config ARCH_AT91SAM9263 bool "AT91SAM9263" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_FB_ATMEL - select HAVE_NET_MACB - select HAVE_AT91_DBGU1 + select SOC_AT91SAM9263 config ARCH_AT91SAM9RL bool "AT91SAM9RL" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_AT91_USART3 - select HAVE_FB_ATMEL - select HAVE_AT91_DBGU0 + select SOC_AT91SAM9RL config ARCH_AT91SAM9G20 bool "AT91SAM9G20" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_AT91_DBGU0 - select HAVE_AT91_USART3 - select HAVE_AT91_USART4 - select HAVE_AT91_USART5 - select HAVE_NET_MACB + select SOC_AT91SAM9260 config ARCH_AT91SAM9G45 bool "AT91SAM9G45" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_AT91_USART3 - select HAVE_FB_ATMEL - select HAVE_NET_MACB - select HAVE_AT91_DBGU1 - -config ARCH_AT91SAM9X5 - bool "AT91SAM9x5 family" - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select HAVE_FB_ATMEL - select HAVE_NET_MACB - select HAVE_AT91_DBGU0 + select SOC_AT91SAM9G45 config ARCH_AT91X40 bool "AT91x40" + depends on !MMU select ARCH_USES_GETTIMEOFFSET endchoice @@ -364,6 +389,7 @@ config MACH_AT91SAM9G20EK_2MMC Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and onwards. + <http://www.atmel.com/tools/SAM9G20-EK.aspx> config MACH_CPU9G20 bool "Eukrea CPU9G20 board" @@ -433,9 +459,10 @@ comment "AT91SAM9G45 Board Type" config MACH_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" help - Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. - "ES" at the end of the name means that this board is an - Engineering Sample. + Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. + Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 + families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. + <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx> endif @@ -515,41 +542,6 @@ config AT91_TIMER_HZ system clock (of at least several MHz), rounding is less of a problem so it can be safer to use a decimal values like 100. -choice - prompt "Select a UART for early kernel messages" - -config AT91_EARLY_DBGU0 - bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl" - depends on HAVE_AT91_DBGU0 - -config AT91_EARLY_DBGU1 - bool "DBGU on 9263 and 9g45" - depends on HAVE_AT91_DBGU1 - -config AT91_EARLY_USART0 - bool "USART0" - -config AT91_EARLY_USART1 - bool "USART1" - -config AT91_EARLY_USART2 - bool "USART2" - depends on ! ARCH_AT91X40 - -config AT91_EARLY_USART3 - bool "USART3" - depends on HAVE_AT91_USART3 - -config AT91_EARLY_USART4 - bool "USART4" - depends on HAVE_AT91_USART4 - -config AT91_EARLY_USART5 - bool "USART5" - depends on HAVE_AT91_USART5 - -endchoice - endmenu endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 8512e53bed93..79d0f60af0b2 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -10,17 +10,25 @@ obj- := obj-$(CONFIG_AT91_PMC_UNIT) += clock.o obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o +obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o # CPU-specific support -obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o sam9_smc.o +obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o +obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o +obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o +obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o +obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o +obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o +obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o + +obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261_devices.o +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260_devices.o +obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 364c19357e60..d50da1a9d0bf 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -258,18 +258,6 @@ static void __init at91rm9200_register_clocks(void) clk_register(&pck3); } -static struct clk_lookup console_clock_lookup; - -void __init at91rm9200_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 99ce5c955e39..99affb5d0563 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -1152,14 +1152,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91rm9200_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1168,14 +1160,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else -void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index dd7f782b0b91..104ca40d8d18 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -23,6 +23,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/clockchips.h> +#include <linux/export.h> #include <asm/mach/time.h> @@ -176,6 +177,7 @@ static struct clock_event_device clkevt = { }; void __iomem *at91_st_base; +EXPORT_SYMBOL_GPL(at91_st_base); void __init at91rm9200_ioremap_st(u32 addr) { diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 46f774233298..a27bbec50ca3 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -268,18 +268,6 @@ static void __init at91sam9260_register_clocks(void) clk_register(&pck1); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9260_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 5652dde4bbe2..ad00fe91d37d 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -1229,14 +1229,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9260_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1245,13 +1237,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 7de81e6222f1..c77d503d09d1 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -239,18 +239,6 @@ static void __init at91sam9261_register_clocks(void) clk_register(&hck1); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9261_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 4db961a93085..9295e90b08ff 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -1051,14 +1051,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9261_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1067,13 +1059,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index ef301be66575..7fae36502fbb 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -255,18 +255,6 @@ static void __init at91sam9263_register_clocks(void) clk_register(&pck3); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9263_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index fe99206de880..dfe5bc006d5e 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -1461,14 +1461,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9263_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1477,13 +1469,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index d222f8333dab..f2054495a655 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -288,18 +288,6 @@ static void __init at91sam9g45_register_clocks(void) clk_register(&pck1); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9g45_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 6b008aee1dff..db2f88c246ff 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -1741,14 +1741,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9g45_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1757,13 +1749,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index d9f2774f385e..e420085a57ef 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -232,18 +232,6 @@ static void __init at91sam9rl_register_clocks(void) clk_register(&pck1); } -static struct clk_lookup console_clock_lookup; - -void __init at91sam9rl_set_console_clock(int id) -{ - if (id >= ARRAY_SIZE(usart_clocks_lookups)) - return; - - console_clock_lookup.con_id = "usart"; - console_clock_lookup.clk = usart_clocks_lookups[id].clk; - clkdev_add(&console_clock_lookup); -} - /* -------------------------------------------------------------------- * GPIO * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index fe4ae22e8561..9c0b1481a9a7 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -1192,14 +1192,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } -void __init at91_set_serial_console(unsigned portnr) -{ - if (portnr < ATMEL_MAX_UART) { - atmel_default_console_device = at91_uarts[portnr]; - at91sam9rl_set_console_clock(at91_uarts[portnr]->id); - } -} - void __init at91_add_device_serial(void) { int i; @@ -1208,13 +1200,9 @@ void __init at91_add_device_serial(void) if (at91_uarts[i]) platform_device_register(at91_uarts[i]); } - - if (!atmel_default_console_device) - printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} -void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} #endif diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c index 2628384aaae1..271f994314a4 100644 --- a/arch/arm/mach-at91/board-1arm.c +++ b/arch/arm/mach-at91/board-1arm.c @@ -47,20 +47,6 @@ static void __init onearm_init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata onearm_eth_data = { @@ -82,6 +68,16 @@ static struct at91_udc_data __initdata onearm_udc_data = { static void __init onearm_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&onearm_eth_data); diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index 161efbaa1029..b7d8aa7b81e6 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c @@ -52,22 +52,6 @@ static void __init afeb9260_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR - | ATMEL_UART_DCD | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -183,6 +167,18 @@ static struct at91_cf_data afeb9260_cf_data = { static void __init afeb9260_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR + | ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&afeb9260_usbh_data); diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index c6d44ee0c77e..29d3ef0a50fb 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -49,12 +49,6 @@ static void __init cam60_init_early(void) { /* Initialize processor: 10 MHz crystal */ at91_initialize(10000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -175,6 +169,8 @@ static void __init cam60_add_device_nand(void) static void __init cam60_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* SPI */ at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices)); diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index 59d9cf997537..44328a6d4609 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -44,17 +44,6 @@ static void __init carmeva_init_early(void) { /* Initialize processor: 20.000 MHz crystal */ at91_initialize(20000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata carmeva_eth_data = { @@ -139,6 +128,13 @@ static struct gpio_led carmeva_leds[] = { static void __init carmeva_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&carmeva_eth_data); diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c index 5f3680e7c883..69951ec7dbf3 100644 --- a/arch/arm/mach-at91/board-cpu9krea.c +++ b/arch/arm/mach-at91/board-cpu9krea.c @@ -52,34 +52,6 @@ static void __init cpu9krea_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DGBU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | - ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | - ATMEL_UART_DCD | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | - ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | - ATMEL_UART_RTS); - - /* USART3 on ttyS4. (Rx, Tx) */ - at91_register_uart(AT91SAM9260_ID_US3, 4, 0); - - /* USART4 on ttyS5. (Rx, Tx) */ - at91_register_uart(AT91SAM9260_ID_US4, 5, 0); - - /* USART5 on ttyS6. (Rx, Tx) */ - at91_register_uart(AT91SAM9260_ID_US5, 6, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -352,6 +324,30 @@ static void __init cpu9krea_board_init(void) /* NOR */ cpu9krea_add_device_nor(); /* Serial */ + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | + ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | + ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | + ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | + ATMEL_UART_RTS); + + /* USART3 on ttyS4. (Rx, Tx) */ + at91_register_uart(AT91SAM9260_ID_US3, 4, 0); + + /* USART4 on ttyS5. (Rx, Tx) */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + + /* USART5 on ttyS6. (Rx, Tx) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&cpu9krea_usbh_data); diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c index e094cc81fe25..895cf2dba612 100644 --- a/arch/arm/mach-at91/board-cpuat91.c +++ b/arch/arm/mach-at91/board-cpuat91.c @@ -59,28 +59,6 @@ static void __init cpuat91_init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | - ATMEL_UART_RTS); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | - ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | - ATMEL_UART_DCD | ATMEL_UART_RI); - - /* USART2 on ttyS3 (Rx, Tx) */ - at91_register_uart(AT91RM9200_ID_US2, 3, 0); - - /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | - ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata cpuat91_eth_data = { @@ -161,6 +139,24 @@ static struct platform_device *platform_devices[] __initdata = { static void __init cpuat91_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | + ATMEL_UART_RTS); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | + ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | + ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART2 on ttyS3 (Rx, Tx) */ + at91_register_uart(AT91RM9200_ID_US2, 3, 0); + + /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | + ATMEL_UART_RTS); at91_add_device_serial(); /* LEDs. */ at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds)); diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index 1a1547b1ce4e..cd813361cd26 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c @@ -47,15 +47,6 @@ static void __init csb337_init_early(void) { /* Initialize processor: 3.6864 MHz crystal */ at91_initialize(3686400); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); - - /* DBGU on ttyS0 */ - at91_register_uart(0, 0, 0); - - /* make console=ttyS0 the default */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata csb337_eth_data = { @@ -228,7 +219,11 @@ static struct gpio_led csb_leds[] = { static void __init csb337_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); /* Serial */ + /* DBGU on ttyS0 */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&csb337_eth_data); diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index f650bf39455d..7c8b05a57d7f 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c @@ -44,12 +44,6 @@ static void __init csb637_init_early(void) { /* Initialize processor: 3.6864 MHz crystal */ at91_initialize(3686400); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* make console=ttyS0 (ie, DBGU) the default */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata csb637_eth_data = { @@ -118,6 +112,8 @@ static void __init csb637_board_init(void) /* LED(s) */ at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds)); /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&csb637_eth_data); diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c index c18d4d307801..a1fce05aa7a5 100644 --- a/arch/arm/mach-at91/board-dt.c +++ b/arch/arm/mach-at91/board-dt.c @@ -1,10 +1,6 @@ /* * Setup code for AT91SAM Evaluation Kits with Device Tree support * - * Covers: * AT91SAM9G45-EKES board - * * AT91SAM9M10-EKES board - * * AT91SAM9M10G45-EK board - * * Copyright (C) 2011 Atmel, * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> * @@ -49,9 +45,7 @@ static void __init at91_dt_device_init(void) } static const char *at91_dt_board_compat[] __initdata = { - "atmel,at91sam9m10g45ek", - "atmel,at91sam9x5ek", - "calao,usb-a9g20", + "atmel,at91sam9", NULL }; diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c index d302ca3eeb64..bd1017297989 100644 --- a/arch/arm/mach-at91/board-eb9200.c +++ b/arch/arm/mach-at91/board-eb9200.c @@ -44,20 +44,6 @@ static void __init eb9200_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART2 on ttyS2. (Rx, Tx) - IRDA */ - at91_register_uart(AT91RM9200_ID_US2, 2, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata eb9200_eth_data = { @@ -101,6 +87,16 @@ static struct i2c_board_info __initdata eb9200_i2c_devices[] = { static void __init eb9200_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART2 on ttyS2. (Rx, Tx) - IRDA */ + at91_register_uart(AT91RM9200_ID_US2, 2, 0); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&eb9200_eth_data); diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c index 69966ce4d776..89cc3726a9ce 100644 --- a/arch/arm/mach-at91/board-ecbat91.c +++ b/arch/arm/mach-at91/board-ecbat91.c @@ -50,18 +50,6 @@ static void __init ecb_at91init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx & Tx only) */ - at91_register_uart(AT91RM9200_ID_US0, 1, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata ecb_at91eth_data = { @@ -151,7 +139,15 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = { static void __init ecb_at91board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx & Tx only) */ + at91_register_uart(AT91RM9200_ID_US0, 1, 0); at91_add_device_serial(); /* Ethernet */ diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c index f23aabef8551..558546cf63f4 100644 --- a/arch/arm/mach-at91/board-eco920.c +++ b/arch/arm/mach-at91/board-eco920.c @@ -37,15 +37,6 @@ static void __init eco920_init_early(void) at91rm9200_set_type(ARCH_REVISON_9200_PQFP); at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); - - /* DBGU on ttyS0. (Rx & Tx only */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata eco920_eth_data = { @@ -103,6 +94,10 @@ static struct spi_board_info eco920_spi_devices[] = { static void __init eco920_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1); + /* DBGU on ttyS0. (Rx & Tx only */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); at91_add_device_eth(&eco920_eth_data); at91_add_device_usbh(&eco920_usbh_data); diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c index 1815152001f7..47658f78105d 100644 --- a/arch/arm/mach-at91/board-flexibity.c +++ b/arch/arm/mach-at91/board-flexibity.c @@ -41,12 +41,6 @@ static void __init flexibity_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* USB Host port */ @@ -143,6 +137,8 @@ static struct gpio_led flexibity_leds[] = { static void __init flexibity_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&flexibity_usbh_data); diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c index caf017f0f4ee..33411e6ecb1f 100644 --- a/arch/arm/mach-at91/board-foxg20.c +++ b/arch/arm/mach-at91/board-foxg20.c @@ -61,44 +61,6 @@ static void __init foxg20_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS - | ATMEL_UART_RTS - | ATMEL_UART_DTR - | ATMEL_UART_DSR - | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS - | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx & Tx only) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, 0); - - /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US3, 4, - ATMEL_UART_CTS - | ATMEL_UART_RTS); - - /* USART4 on ttyS5. (Rx & Tx only) */ - at91_register_uart(AT91SAM9260_ID_US4, 5, 0); - - /* USART5 on ttyS6. (Rx & Tx only) */ - at91_register_uart(AT91SAM9260_ID_US5, 6, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); - - /* Set the internal pull-up resistor on DRXD */ - at91_set_A_periph(AT91_PIN_PB14, 1); - } /* @@ -241,6 +203,39 @@ static struct i2c_board_info __initdata foxg20_i2c_devices[] = { static void __init foxg20_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS + | ATMEL_UART_RTS + | ATMEL_UART_DTR + | ATMEL_UART_DSR + | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, 0); + + /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US3, 4, + ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART4 on ttyS5. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + + /* USART5 on ttyS6. (Rx & Tx only) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); + + /* Set the internal pull-up resistor on DRXD */ + at91_set_A_periph(AT91_PIN_PB14, 1); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&foxg20_usbh_data); diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index 230e71969fb7..3e0dfa643a86 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c @@ -41,38 +41,6 @@ static void __init gsia18s_init_early(void) { stamp9g20_init_early(); - - /* - * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI). - * Used for Internal Analog Modem. - */ - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS | ATMEL_UART_RTS | - ATMEL_UART_DTR | ATMEL_UART_DSR | - ATMEL_UART_DCD | ATMEL_UART_RI); - /* - * USART1 on ttyS2 (Rx, Tx, CTS, RTS). - * Used for GPS or WiFi or Data stream. - */ - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS | ATMEL_UART_RTS); - /* - * USART2 on ttyS3 (Rx, Tx, CTS, RTS). - * Used for External Modem. - */ - at91_register_uart(AT91SAM9260_ID_US2, 3, - ATMEL_UART_CTS | ATMEL_UART_RTS); - /* - * USART3 on ttyS4 (Rx, Tx, RTS). - * Used for RS-485. - */ - at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS); - - /* - * USART4 on ttyS5 (Rx, Tx). - * Used for TRX433 Radio Module. - */ - at91_register_uart(AT91SAM9260_ID_US4, 5, 0); } /* @@ -558,6 +526,37 @@ static int __init gsia18s_power_off_init(void) static void __init gsia18s_board_init(void) { + /* + * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI). + * Used for Internal Analog Modem. + */ + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS | + ATMEL_UART_DTR | ATMEL_UART_DSR | + ATMEL_UART_DCD | ATMEL_UART_RI); + /* + * USART1 on ttyS2 (Rx, Tx, CTS, RTS). + * Used for GPS or WiFi or Data stream. + */ + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); + /* + * USART2 on ttyS3 (Rx, Tx, CTS, RTS). + * Used for External Modem. + */ + at91_register_uart(AT91SAM9260_ID_US2, 3, + ATMEL_UART_CTS | ATMEL_UART_RTS); + /* + * USART3 on ttyS4 (Rx, Tx, RTS). + * Used for RS-485. + */ + at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS); + + /* + * USART4 on ttyS5 (Rx, Tx). + * Used for TRX433 Radio Module. + */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); stamp9g20_board_init(); at91_add_device_usbh(&usbh_data); at91_add_device_udc(&udc_data); diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c index efde1b2327c8..f260657f32bc 100644 --- a/arch/arm/mach-at91/board-kafa.c +++ b/arch/arm/mach-at91/board-kafa.c @@ -47,18 +47,6 @@ static void __init kafa_init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Set up the LEDs */ - at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata kafa_eth_data = { @@ -79,7 +67,15 @@ static struct at91_udc_data __initdata kafa_udc_data = { static void __init kafa_board_init(void) { + /* Set up the LEDs */ + at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&kafa_eth_data); diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index 59b92aab9bcf..ba39db5482b9 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c @@ -50,24 +50,6 @@ static void __init kb9202_init_early(void) /* Initialize processor: 10 MHz crystal */ at91_initialize(10000000); - - /* Set up the LEDs */ - at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1 (Rx & Tx only) */ - at91_register_uart(AT91RM9200_ID_US0, 1, 0); - - /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */ - at91_register_uart(AT91RM9200_ID_US1, 2, 0); - - /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */ - at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata kb9202_eth_data = { @@ -115,7 +97,21 @@ static struct atmel_nand_data __initdata kb9202_nand_data = { static void __init kb9202_board_init(void) { + /* Set up the LEDs */ + at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1 (Rx & Tx only) */ + at91_register_uart(AT91RM9200_ID_US0, 1, 0); + + /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */ + at91_register_uart(AT91RM9200_ID_US1, 2, 0); + + /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */ + at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&kb9202_eth_data); diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c index 57d5f6a4726a..d2f4cc161766 100644 --- a/arch/arm/mach-at91/board-neocore926.c +++ b/arch/arm/mach-at91/board-neocore926.c @@ -55,15 +55,6 @@ static void __init neocore926_init_early(void) { /* Initialize processor: 20 MHz crystal */ at91_initialize(20000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -341,6 +332,11 @@ static struct ac97c_platform_data neocore926_ac97_data = { static void __init neocore926_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index b4a12fc184c8..7fe638342421 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c @@ -40,17 +40,6 @@ static void __init pcontrol_g20_init_early(void) { stamp9g20_init_early(); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS - | ATMEL_UART_RTS); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS - | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ - at91_register_uart(AT91SAM9260_ID_US4, 3, 0); } static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { { @@ -199,6 +188,16 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = { static void __init pcontrol_g20_board_init(void) { + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS + | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */ + at91_register_uart(AT91SAM9260_ID_US4, 3, 0); stamp9g20_board_init(); at91_add_device_usbh(&usbh_data); at91_add_device_eth(&macb_data); diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c index 59e35dd14863..b45c0a5d5ca7 100644 --- a/arch/arm/mach-at91/board-picotux200.c +++ b/arch/arm/mach-at91/board-picotux200.c @@ -48,17 +48,6 @@ static void __init picotux200_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata picotux200_eth_data = { @@ -106,6 +95,13 @@ static struct platform_device picotux200_flash = { static void __init picotux200_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&picotux200_eth_data); diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c index b6ed5ed7081a..0c61bf0d272c 100644 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ b/arch/arm/mach-at91/board-qil-a9260.c @@ -52,24 +52,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ at91_initialize(12000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS1 (ie, USART0) */ - at91_set_serial_console(1); - } /* @@ -235,6 +217,19 @@ static struct gpio_led ek_leds[] = { static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c index 01332aa538b2..afd7a4713766 100644 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ b/arch/arm/mach-at91/board-rm9200dk.c @@ -50,20 +50,6 @@ static void __init dk_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata dk_eth_data = { @@ -190,7 +176,17 @@ static struct gpio_led dk_leds[] = { static void __init dk_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&dk_eth_data); diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index 11cbaa8946fe..2b15b8adec4c 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c @@ -50,20 +50,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } static struct macb_platform_data __initdata ek_eth_data = { @@ -117,7 +103,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = { }; #define EK_FLASH_BASE AT91_CHIPSELECT_0 -#define EK_FLASH_SIZE SZ_2M +#define EK_FLASH_SIZE SZ_8M static struct physmap_flash_data ek_flash_data = { .width = 2, @@ -161,7 +147,17 @@ static struct gpio_led ek_leds[] = { static void __init ek_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&ek_eth_data); diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c index af0750fafa29..24ab9be7510f 100644 --- a/arch/arm/mach-at91/board-rsi-ews.c +++ b/arch/arm/mach-at91/board-rsi-ews.c @@ -35,26 +35,6 @@ static void __init rsi_ews_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9); - - /* DBGU on ttyS0. (Rx & Tx only) */ - /* This one is for debugging */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - /* Dialin/-out modem interface */ - at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART3 on ttyS4. (Rx, Tx, RTS) */ - /* RS485 communication */ - at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -204,7 +184,23 @@ static struct platform_device rsiews_nor_flash = { */ static void __init rsi_ews_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + /* This one is for debugging */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + /* Dialin/-out modem interface */ + at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART3 on ttyS4. (Rx, Tx, RTS) */ + /* RS485 communication */ + at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS); at91_add_device_serial(); at91_set_gpio_output(AT91_PIN_PA21, 0); /* Ethernet */ diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index e8b116b6cba6..cdd21f2595d2 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c @@ -48,23 +48,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -184,7 +167,20 @@ static struct at91_mmc_data __initdata ek_mmc_data = { static void __init ek_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index d5aec55b0eb4..7b3c3913551a 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -54,20 +54,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -320,6 +306,16 @@ static void __init ek_add_device_buttons(void) {} static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index c3f994462864..2736453821b0 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -58,15 +58,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs */ - at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -85,8 +76,6 @@ static struct resource dm9000_resource[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = AT91_PIN_PC11, - .end = AT91_PIN_PC11, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE, } @@ -130,6 +119,8 @@ static struct sam9_smc_config __initdata dm9000_smc_config = { static void __init ek_add_device_dm9000(void) { + struct resource *r = &dm9000_resource[2]; + /* Configure chip-select 2 (DM9000) */ sam9_smc_configure(0, 2, &dm9000_smc_config); @@ -139,6 +130,7 @@ static void __init ek_add_device_dm9000(void) /* Configure Interrupt pin as input, no pull-up */ at91_set_gpio_input(AT91_PIN_PC11, 0); + r->start = r->end = gpio_to_irq(AT91_PIN_PC11); platform_device_register(&dm9000_device); } #else @@ -576,7 +568,12 @@ static struct gpio_led ek_leds[] = { static void __init ek_board_init(void) { + /* Setup the LEDs */ + at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 2ffe50f3a9e9..983cb98d2465 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -57,15 +57,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 16.367 MHz crystal */ at91_initialize(16367660); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -412,6 +403,11 @@ static struct at91_can_data ek_can_data = { static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 8923ec9f5831..3d615532ae5c 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -65,20 +65,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -372,6 +358,16 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = { static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index c88e908ddd82..9a87f0b072f8 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -53,16 +53,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ at91_initialize(12000000); - - /* DGBU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 not connected on the -EK board */ - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -457,6 +447,12 @@ static struct platform_device *devices[] __initdata = { static void __init ek_board_init(void) { /* Serial */ + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 not connected on the -EK board */ + /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ + at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB HS Host */ at91_add_device_usbh_ohci(&ek_usbh_hs_data); diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index b109ce2ba864..be3239f13daa 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -42,15 +42,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.000 MHz crystal */ at91_initialize(12000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -296,6 +287,11 @@ static void __init ek_add_device_buttons(void) {} static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB HS */ at91_add_device_usba(&ek_usba_udc_data); diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index ebc9d01ce742..9d446f1bb45f 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -43,16 +43,6 @@ static void __init snapper9260_init_early(void) { at91_initialize(18432000); - - /* Debug on ttyS0 */ - at91_register_uart(0, 0, 0); - at91_set_serial_console(0); - - at91_register_uart(AT91SAM9260_ID_US0, 1, - ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_register_uart(AT91SAM9260_ID_US1, 2, - ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_register_uart(AT91SAM9260_ID_US2, 3, 0); } static struct at91_usbh_data __initdata snapper9260_usbh_data = { @@ -168,6 +158,14 @@ static void __init snapper9260_board_init(void) snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31); i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1); + /* Debug on ttyS0 */ + at91_register_uart(0, 0, 0); + + at91_register_uart(AT91SAM9260_ID_US0, 1, + ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_register_uart(AT91SAM9260_ID_US1, 2, + ATMEL_UART_CTS | ATMEL_UART_RTS); + at91_register_uart(AT91SAM9260_ID_US2, 3, 0); at91_add_device_serial(); at91_add_device_usbh(&snapper9260_usbh_data); at91_add_device_udc(&snapper9260_udc_data); diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index 7640049410a0..ee86f9d7ee72 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c @@ -36,44 +36,6 @@ void __init stamp9g20_init_early(void) { /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* DGBU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); -} - -static void __init stamp9g20evb_init_early(void) -{ - stamp9g20_init_early(); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR - | ATMEL_UART_DCD | ATMEL_UART_RI); -} - -static void __init portuxg20_init_early(void) -{ - stamp9g20_init_early(); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR - | ATMEL_UART_DCD | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART4 on ttyS5. (Rx, Tx only) */ - at91_register_uart(AT91SAM9260_ID_US4, 5, 0); - - /* USART5 on ttyS6. (Rx, Tx only) */ - at91_register_uart(AT91SAM9260_ID_US5, 6, 0); } /* @@ -254,6 +216,8 @@ void add_w1(void) void __init stamp9g20_board_init(void) { /* Serial */ + /* DGBU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* NAND */ add_device_nand(); @@ -269,6 +233,22 @@ void __init stamp9g20_board_init(void) static void __init portuxg20_board_init(void) { + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR + | ATMEL_UART_DCD | ATMEL_UART_RI); + + /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ + at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); + + /* USART4 on ttyS5. (Rx, Tx only) */ + at91_register_uart(AT91SAM9260_ID_US4, 5, 0); + + /* USART5 on ttyS6. (Rx, Tx only) */ + at91_register_uart(AT91SAM9260_ID_US5, 6, 0); stamp9g20_board_init(); /* USB Host */ at91_add_device_usbh(&usbh_data); @@ -286,6 +266,10 @@ static void __init portuxg20_board_init(void) static void __init stamp9g20evb_board_init(void) { + /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR + | ATMEL_UART_DCD | ATMEL_UART_RI); stamp9g20_board_init(); /* USB Host */ at91_add_device_usbh(&usbh_data); @@ -303,7 +287,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20") /* Maintainer: taskit GmbH */ .timer = &at91sam926x_timer, .map_io = at91_map_io, - .init_early = portuxg20_init_early, + .init_early = stamp9g20_init_early, .init_irq = at91_init_irq_default, .init_machine = portuxg20_board_init, MACHINE_END @@ -312,7 +296,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20") /* Maintainer: taskit GmbH */ .timer = &at91sam926x_timer, .map_io = at91_map_io, - .init_early = stamp9g20evb_init_early, + .init_early = stamp9g20_init_early, .init_irq = at91_init_irq_default, .init_machine = stamp9g20evb_board_init, MACHINE_END diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c index b7483a3d0980..332ecd40bd02 100644 --- a/arch/arm/mach-at91/board-usb-a926x.c +++ b/arch/arm/mach-at91/board-usb-a926x.c @@ -53,12 +53,6 @@ static void __init ek_init_early(void) { /* Initialize processor: 12.00 MHz crystal */ at91_initialize(12000000); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -325,6 +319,8 @@ static void __init ek_add_device_leds(void) static void __init ek_board_init(void) { /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c index 38dd279d30b2..d56665ea4b55 100644 --- a/arch/arm/mach-at91/board-yl-9200.c +++ b/arch/arm/mach-at91/board-yl-9200.c @@ -58,26 +58,6 @@ static void __init yl9200_init_early(void) /* Initialize processor: 18.432 MHz crystal */ at91_initialize(18432000); - - /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ - at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); - - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART0 on ttyS2. (Rx & Tx only to JP3) */ - at91_register_uart(AT91RM9200_ID_US0, 2, 0); - - /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */ - at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); } /* @@ -560,7 +540,23 @@ void __init yl9200_add_device_video(void) {} static void __init yl9200_board_init(void) { + /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ + at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17); + /* Serial */ + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ + at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS + | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD + | ATMEL_UART_RI); + + /* USART0 on ttyS2. (Rx & Tx only to JP3) */ + at91_register_uart(AT91RM9200_ID_US0, 2, 0); + + /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */ + at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS); at91_add_device_serial(); /* Ethernet */ at91_add_device_eth(&yl9200_eth_data); diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index a0f4d7424cdc..6b692824c988 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -35,6 +35,7 @@ #include "generic.h" void __iomem *at91_pmc_base; +EXPORT_SYMBOL_GPL(at91_pmc_base); /* * There's a lot more which can be done with clocks, including cpufreq diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c index ece1f9aefb47..0c6381516a5a 100644 --- a/arch/arm/mach-at91/cpuidle.c +++ b/arch/arm/mach-at91/cpuidle.c @@ -21,6 +21,7 @@ #include <linux/export.h> #include <asm/proc-fns.h> #include <asm/cpuidle.h> +#include <mach/cpu.h> #include "pm.h" @@ -33,7 +34,12 @@ static int at91_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - at91_standby(); + if (cpu_is_at91rm9200()) + at91rm9200_standby(); + else if (cpu_is_at91sam9g45()) + at91sam9g45_standby(); + else + at91sam9_standby(); return index; } diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index dd9b346c451d..0a60bf837037 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -40,17 +40,6 @@ extern struct sys_timer at91sam926x_timer; extern struct sys_timer at91x40_timer; /* Clocks */ -/* - * function to specify the clock of the default console. As we do not - * use the device/driver bus, the dev_name is not intialize. So we need - * to link the clock to a specific con_id only "usart" - */ -extern void __init at91rm9200_set_console_clock(int id); -extern void __init at91sam9260_set_console_clock(int id); -extern void __init at91sam9261_set_console_clock(int id); -extern void __init at91sam9263_set_console_clock(int id); -extern void __init at91sam9rl_set_console_clock(int id); -extern void __init at91sam9g45_set_console_clock(int id); #ifdef CONFIG_AT91_PMC_UNIT extern int __init at91_clock_init(unsigned long main_clock); extern int __init at91_dt_clock_init(void); diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 36604782a78f..ea2c57a86ca6 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base; #define at91_pmc_write(field, value) \ __raw_writel(value, at91_pmc_base + field) #else -.extern at91_aic_base +.extern at91_pmc_base #endif #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index 603e6aac2a4f..e67317c67761 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h @@ -88,11 +88,6 @@ #define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ #define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ -#define AT91_USART0 AT91RM9200_BASE_US0 -#define AT91_USART1 AT91RM9200_BASE_US1 -#define AT91_USART2 AT91RM9200_BASE_US2 -#define AT91_USART3 AT91RM9200_BASE_US3 - /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 08ae9afd00fe..416c7b6c56d3 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -95,13 +95,6 @@ #define AT91SAM9260_BASE_WDT 0xfffffd40 #define AT91SAM9260_BASE_GPBR 0xfffffd50 -#define AT91_USART0 AT91SAM9260_BASE_US0 -#define AT91_USART1 AT91SAM9260_BASE_US1 -#define AT91_USART2 AT91SAM9260_BASE_US2 -#define AT91_USART3 AT91SAM9260_BASE_US3 -#define AT91_USART4 AT91SAM9260_BASE_US4 -#define AT91_USART5 AT91SAM9260_BASE_US5 - /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 44fbdc12ee62..a041406d06ee 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -79,10 +79,6 @@ #define AT91SAM9261_BASE_WDT 0xfffffd40 #define AT91SAM9261_BASE_GPBR 0xfffffd50 -#define AT91_USART0 AT91SAM9261_BASE_US0 -#define AT91_USART1 AT91SAM9261_BASE_US1 -#define AT91_USART2 AT91SAM9261_BASE_US2 - /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index d96cbb2e03c4..d201029d60b3 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -95,10 +95,6 @@ #define AT91SAM9263_BASE_RTT1 0xfffffd50 #define AT91SAM9263_BASE_GPBR 0xfffffd60 -#define AT91_USART0 AT91SAM9263_BASE_US0 -#define AT91_USART1 AT91SAM9263_BASE_US1 -#define AT91_USART2 AT91SAM9263_BASE_US2 - #define AT91_SMC AT91_SMC0 /* diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index d052abcff852..3a4da24d5911 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -106,11 +106,6 @@ #define AT91SAM9G45_BASE_RTC 0xfffffdb0 #define AT91SAM9G45_BASE_GPBR 0xfffffd60 -#define AT91_USART0 AT91SAM9G45_BASE_US0 -#define AT91_USART1 AT91SAM9G45_BASE_US1 -#define AT91_USART2 AT91SAM9G45_BASE_US2 -#define AT91_USART3 AT91SAM9G45_BASE_US3 - /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index e0073eb10144..a15db56d33fa 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -89,11 +89,6 @@ #define AT91SAM9RL_BASE_GPBR 0xfffffd60 #define AT91SAM9RL_BASE_RTC 0xfffffe00 -#define AT91_USART0 AT91SAM9RL_BASE_US0 -#define AT91_USART1 AT91SAM9RL_BASE_US1 -#define AT91_USART2 AT91SAM9RL_BASE_US2 -#define AT91_USART3 AT91SAM9RL_BASE_US3 - /* * Internal Memory. diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 88e43d534cdf..c75ee19b58d3 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -55,14 +55,6 @@ #define AT91SAM9X5_BASE_USART2 0xf8024000 /* - * Base addresses for early serial code (uncompress.h) - */ -#define AT91_DBGU AT91_BASE_DBGU0 -#define AT91_USART0 AT91SAM9X5_BASE_USART0 -#define AT91_USART1 AT91SAM9X5_BASE_USART1 -#define AT91_USART2 AT91SAM9X5_BASE_USART2 - -/* * Internal Memory. */ #define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index 49a821192c65..369afc2ffc5b 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -121,7 +121,6 @@ extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_de #define ATMEL_UART_RI 0x20 extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins); -extern void __init at91_set_serial_console(unsigned portnr); extern struct platform_device *atmel_default_console_device; diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 0118c3338552..73d2fd209ce4 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -54,6 +54,7 @@ #define ARCH_REVISON_9200_BGA (0 << 0) #define ARCH_REVISON_9200_PQFP (1 << 0) +#ifndef __ASSEMBLY__ enum at91_soc_type { /* 920T */ AT91_SOC_RM9200, @@ -106,7 +107,7 @@ static inline int at91_soc_is_detected(void) return at91_soc_initdata.type != AT91_SOC_NONE; } -#ifdef CONFIG_ARCH_AT91RM9200 +#ifdef CONFIG_SOC_AT91RM9200 #define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) #define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) #define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) @@ -116,45 +117,37 @@ static inline int at91_soc_is_detected(void) #define cpu_is_at91rm9200_pqfp() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9260 +#ifdef CONFIG_SOC_AT91SAM9260 #define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) #define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) +#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) #else #define cpu_is_at91sam9xe() (0) #define cpu_is_at91sam9260() (0) -#endif - -#ifdef CONFIG_ARCH_AT91SAM9G20 -#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) -#else #define cpu_is_at91sam9g20() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9261 +#ifdef CONFIG_SOC_AT91SAM9261 #define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) -#else -#define cpu_is_at91sam9261() (0) -#endif - -#ifdef CONFIG_ARCH_AT91SAM9G10 #define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) #else +#define cpu_is_at91sam9261() (0) #define cpu_is_at91sam9g10() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9263 +#ifdef CONFIG_SOC_AT91SAM9263 #define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) #else #define cpu_is_at91sam9263() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9RL +#ifdef CONFIG_SOC_AT91SAM9RL #define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) #else #define cpu_is_at91sam9rl() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9G45 +#ifdef CONFIG_SOC_AT91SAM9G45 #define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) #define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) #define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) @@ -168,7 +161,7 @@ static inline int at91_soc_is_detected(void) #define cpu_is_at91sam9m11() (0) #endif -#ifdef CONFIG_ARCH_AT91SAM9X5 +#ifdef CONFIG_SOC_AT91SAM9X5 #define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) #define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) #define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) @@ -189,5 +182,6 @@ static inline int at91_soc_is_detected(void) * definitions may reduce clutter in common drivers. */ #define cpu_is_at32ap7000() (0) +#endif /* __ASSEMBLY__ */ #endif /* __MACH_CPU_H__ */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index e9e29a6c3868..3a01f8ff7e74 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -22,27 +22,17 @@ /* 9263, 9g45 */ #define AT91_BASE_DBGU1 0xffffee00 -#if defined(CONFIG_ARCH_AT91RM9200) +#if defined(CONFIG_ARCH_AT91X40) +#include <mach/at91x40.h> +#else #include <mach/at91rm9200.h> -#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) #include <mach/at91sam9260.h> -#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) #include <mach/at91sam9261.h> -#elif defined(CONFIG_ARCH_AT91SAM9263) #include <mach/at91sam9263.h> -#elif defined(CONFIG_ARCH_AT91SAM9RL) #include <mach/at91sam9rl.h> -#elif defined(CONFIG_ARCH_AT91SAM9G45) #include <mach/at91sam9g45.h> -#elif defined(CONFIG_ARCH_AT91SAM9X5) #include <mach/at91sam9x5.h> -#elif defined(CONFIG_ARCH_AT91X40) -#include <mach/at91x40.h> -#else -#error "Unsupported AT91 processor" -#endif -#if !defined(CONFIG_ARCH_AT91X40) /* * On all at91 except rm9200 and x40 have the System Controller starts * at address 0xffffc000 and has a size of 16KiB. diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h index 4218647c1fcd..6f6118d1576a 100644 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ b/arch/arm/mach-at91/include/mach/uncompress.h @@ -1,7 +1,8 @@ /* * arch/arm/mach-at91/include/mach/uncompress.h * - * Copyright (C) 2003 SAN People + * Copyright (C) 2003 SAN People + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,22 +26,147 @@ #include <linux/atmel_serial.h> #include <mach/hardware.h> -#if defined(CONFIG_AT91_EARLY_DBGU0) -#define UART_OFFSET AT91_BASE_DBGU0 -#elif defined(CONFIG_AT91_EARLY_DBGU1) -#define UART_OFFSET AT91_BASE_DBGU1 -#elif defined(CONFIG_AT91_EARLY_USART0) -#define UART_OFFSET AT91_USART0 -#elif defined(CONFIG_AT91_EARLY_USART1) -#define UART_OFFSET AT91_USART1 -#elif defined(CONFIG_AT91_EARLY_USART2) -#define UART_OFFSET AT91_USART2 -#elif defined(CONFIG_AT91_EARLY_USART3) -#define UART_OFFSET AT91_USART3 -#elif defined(CONFIG_AT91_EARLY_USART4) -#define UART_OFFSET AT91_USART4 -#elif defined(CONFIG_AT91_EARLY_USART5) -#define UART_OFFSET AT91_USART5 +#include <mach/at91_dbgu.h> +#include <mach/cpu.h> + +void __iomem *at91_uart; + +#if !defined(CONFIG_ARCH_AT91X40) +static const u32 uarts_rm9200[] = { + AT91_BASE_DBGU0, + AT91RM9200_BASE_US0, + AT91RM9200_BASE_US1, + AT91RM9200_BASE_US2, + AT91RM9200_BASE_US3, + 0, +}; + +static const u32 uarts_sam9260[] = { + AT91_BASE_DBGU0, + AT91SAM9260_BASE_US0, + AT91SAM9260_BASE_US1, + AT91SAM9260_BASE_US2, + AT91SAM9260_BASE_US3, + AT91SAM9260_BASE_US4, + AT91SAM9260_BASE_US5, + 0, +}; + +static const u32 uarts_sam9261[] = { + AT91_BASE_DBGU0, + AT91SAM9261_BASE_US0, + AT91SAM9261_BASE_US1, + AT91SAM9261_BASE_US2, + 0, +}; + +static const u32 uarts_sam9263[] = { + AT91_BASE_DBGU1, + AT91SAM9263_BASE_US0, + AT91SAM9263_BASE_US1, + AT91SAM9263_BASE_US2, + 0, +}; + +static const u32 uarts_sam9g45[] = { + AT91_BASE_DBGU1, + AT91SAM9G45_BASE_US0, + AT91SAM9G45_BASE_US1, + AT91SAM9G45_BASE_US2, + AT91SAM9G45_BASE_US3, + 0, +}; + +static const u32 uarts_sam9rl[] = { + AT91_BASE_DBGU0, + AT91SAM9RL_BASE_US0, + AT91SAM9RL_BASE_US1, + AT91SAM9RL_BASE_US2, + AT91SAM9RL_BASE_US3, + 0, +}; + +static const u32 uarts_sam9x5[] = { + AT91_BASE_DBGU0, + AT91SAM9X5_BASE_USART0, + AT91SAM9X5_BASE_USART1, + AT91SAM9X5_BASE_USART2, + 0, +}; + +static inline const u32* decomp_soc_detect(u32 dbgu_base) +{ + u32 cidr, socid; + + cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR); + socid = cidr & ~AT91_CIDR_VERSION; + + switch (socid) { + case ARCH_ID_AT91RM9200: + return uarts_rm9200; + + case ARCH_ID_AT91SAM9G20: + case ARCH_ID_AT91SAM9260: + return uarts_sam9260; + + case ARCH_ID_AT91SAM9261: + return uarts_sam9261; + + case ARCH_ID_AT91SAM9263: + return uarts_sam9263; + + case ARCH_ID_AT91SAM9G45: + return uarts_sam9g45; + + case ARCH_ID_AT91SAM9RL64: + return uarts_sam9rl; + + case ARCH_ID_AT91SAM9X5: + return uarts_sam9x5; + } + + /* at91sam9g10 */ + if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { + return uarts_sam9261; + } + /* at91sam9xe */ + else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { + return uarts_sam9260; + } + + return NULL; +} + +static inline void arch_decomp_setup(void) +{ + int i = 0; + const u32* usarts; + + usarts = decomp_soc_detect(AT91_BASE_DBGU0); + + if (!usarts) + usarts = decomp_soc_detect(AT91_BASE_DBGU1); + if (!usarts) { + at91_uart = NULL; + return; + } + + do { + /* physical address */ + at91_uart = (void __iomem *)usarts[i]; + + if (__raw_readl(at91_uart + ATMEL_US_BRGR)) + return; + i++; + } while (usarts[i]); + + at91_uart = NULL; +} +#else +static inline void arch_decomp_setup(void) +{ + at91_uart = NULL; +} #endif /* @@ -52,28 +178,24 @@ */ static void putc(int c) { -#ifdef UART_OFFSET - void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ + if (!at91_uart) + return; - while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY)) + while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY)) barrier(); - __raw_writel(c, sys + ATMEL_US_THR); -#endif + __raw_writel(c, at91_uart + ATMEL_US_THR); } static inline void flush(void) { -#ifdef UART_OFFSET - void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ + if (!at91_uart) + return; /* wait for transmission to complete */ - while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) + while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) barrier(); -#endif } -#define arch_decomp_setup() - #define arch_decomp_wdog() #endif diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index f630250c6b87..1bfaad628731 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -261,7 +261,12 @@ static int at91_pm_enter(suspend_state_t state) * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ - at91_standby(); + if (cpu_is_at91rm9200()) + at91rm9200_standby(); + else if (cpu_is_at91sam9g45()) + at91sam9g45_standby(); + else + at91sam9_standby(); break; case PM_SUSPEND_ON: @@ -307,10 +312,9 @@ static int __init at91_pm_init(void) pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); -#ifdef CONFIG_ARCH_AT91RM9200 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ - at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); -#endif + if (cpu_is_at91rm9200()) + at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0); suspend_set_ops(&at91_pm_ops); diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 89f56f3a802e..38f467c6b710 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -12,7 +12,6 @@ #define __ARCH_ARM_MACH_AT91_PM #include <mach/at91_ramc.h> -#ifdef CONFIG_ARCH_AT91RM9200 #include <mach/at91rm9200_sdramc.h> /* @@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void) "r" (lpr)); } -#define at91_standby at91rm9200_standby - -#elif defined(CONFIG_ARCH_AT91SAM9G45) - /* We manage both DDRAM/SDRAM controllers, we need more than one value to * remember. */ @@ -75,11 +70,7 @@ static inline void at91sam9g45_standby(void) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } -#define at91_standby at91sam9g45_standby - -#else - -#ifdef CONFIG_ARCH_AT91SAM9263 +#ifdef CONFIG_SOC_AT91SAM9263 /* * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; * handle those cases both here and in the Suspend-To-RAM support. @@ -102,8 +93,4 @@ static inline void at91sam9_standby(void) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr); } -#define at91_standby at91sam9_standby - -#endif - #endif diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index db5452123f17..098c28ddf025 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -18,7 +18,7 @@ #include <mach/at91_ramc.h> -#ifdef CONFIG_ARCH_AT91SAM9263 +#ifdef CONFIG_SOC_AT91SAM9263 /* * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; * handle those cases both here and in the Suspend-To-RAM support. diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 97cc04dc8073..f44a2e7272e3 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -54,6 +54,7 @@ void __init at91_init_interrupts(unsigned int *priority) } void __iomem *at91_ramc_base[2]; +EXPORT_SYMBOL_GPL(at91_ramc_base); void __init at91_ioremap_ramc(int id, u32 addr, u32 size) { @@ -292,6 +293,7 @@ void __init at91_ioremap_rstc(u32 base_addr) } void __iomem *at91_matrix_base; +EXPORT_SYMBOL_GPL(at91_matrix_base); void __init at91_ioremap_matrix(u32 base_addr) { diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 5db4aa45404a..683dddfd8b13 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -26,30 +26,30 @@ static inline int at91_soc_is_enabled(void) return at91_boot_soc.init != NULL; } -#if !defined(CONFIG_ARCH_AT91RM9200) +#if !defined(CONFIG_SOC_AT91RM9200) #define at91rm9200_soc at91_boot_soc #endif -#if !(defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)) +#if !defined(CONFIG_SOC_AT91SAM9260) #define at91sam9260_soc at91_boot_soc #endif -#if !(defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)) +#if !defined(CONFIG_SOC_AT91SAM9261) #define at91sam9261_soc at91_boot_soc #endif -#if !defined(CONFIG_ARCH_AT91SAM9263) +#if !defined(CONFIG_SOC_AT91SAM9263) #define at91sam9263_soc at91_boot_soc #endif -#if !defined(CONFIG_ARCH_AT91SAM9G45) +#if !defined(CONFIG_SOC_AT91SAM9G45) #define at91sam9g45_soc at91_boot_soc #endif -#if !defined(CONFIG_ARCH_AT91SAM9RL) +#if !defined(CONFIG_SOC_AT91SAM9RL) #define at91sam9rl_soc at91_boot_soc #endif -#if !defined(CONFIG_ARCH_AT91SAM9X5) +#if !defined(CONFIG_SOC_AT91SAM9X5) #define at91sam9x5_soc at91_boot_soc #endif diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index 22e4e0a28ad1..adbfb1994582 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -52,8 +52,8 @@ #include <mach/csp/chipcHw_inline.h> #include <mach/csp/tmrHw_reg.h> -static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL); -static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL); +static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL); +static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL); static struct clk pll1_clk = { .name = "PLL1", diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index 3c5b5bbf24e5..b6dfd2f22cd4 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -36,7 +36,6 @@ #include <asm/page.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <asm/hardware/clps7111.h> #include <asm/system_misc.h> /* @@ -44,8 +43,8 @@ */ static struct map_desc clps711x_io_desc[] __initdata = { { - .virtual = CLPS7111_VIRT_BASE, - .pfn = __phys_to_pfn(CLPS7111_PHYS_BASE), + .virtual = (unsigned long)CLPS711X_VIRT_BASE, + .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE), .length = SZ_1M, .type = MT_DEVICE } diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S index b802e8a51831..118b3d930573 100644 --- a/arch/arm/mach-clps711x/include/mach/debug-macro.S +++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S @@ -12,7 +12,6 @@ */ #include <mach/hardware.h> -#include <asm/hardware/clps7111.h> .macro addruart, rp, rv, tmp #ifndef CONFIG_DEBUG_CLPS711X_UART2 @@ -20,8 +19,8 @@ #else mov \rp, #0x1000 @ UART2 #endif - orr \rv, \rp, #CLPS7111_VIRT_BASE - orr \rp, \rp, #CLPS7111_PHYS_BASE + orr \rv, \rp, #CLPS711X_VIRT_BASE + orr \rp, \rp, #CLPS711X_PHYS_BASE .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S index 125af59d7a29..56e5c2c23504 100644 --- a/arch/arm/mach-clps711x/include/mach/entry-macro.S +++ b/arch/arm/mach-clps711x/include/mach/entry-macro.S @@ -8,7 +8,6 @@ * warranty of any kind, whether express or implied. */ #include <mach/hardware.h> -#include <asm/hardware/clps7111.h> .macro get_irqnr_preamble, base, tmp .endm @@ -18,7 +17,7 @@ #endif .macro get_irqnr_and_base, irqnr, stat, base, mask - mov \base, #CLPS7111_BASE + mov \base, #CLPS711X_VIRT_BASE ldr \stat, [\base, #INTSR1] ldr \mask, [\base, #INTMR1] mov \irqnr, #4 diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index d0b7d870be9c..1026ac968706 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -19,12 +19,21 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H +#include <asm/hardware/clps7111.h> + +#define CLPS711X_VIRT_BASE IOMEM(0xff000000) -#define CLPS7111_VIRT_BASE 0xff000000 -#define CLPS7111_BASE CLPS7111_VIRT_BASE +#ifndef __ASSEMBLY__ +#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off)) +#define clps_readw(off) readw(CLPS711X_VIRT_BASE + (off)) +#define clps_readl(off) readl(CLPS711X_VIRT_BASE + (off)) +#define clps_writeb(val,off) writeb(val, CLPS711X_VIRT_BASE + (off)) +#define clps_writew(val,off) writew(val, CLPS711X_VIRT_BASE + (off)) +#define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off)) +#endif /* * The physical addresses that the external chip select signals map to is @@ -54,14 +63,10 @@ #if defined (CONFIG_ARCH_EP7211) -#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE -#define EP7211_BASE CLPS7111_VIRT_BASE #include <asm/hardware/ep7211.h> #elif defined (CONFIG_ARCH_EP7212) -#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE -#define EP7212_BASE CLPS7111_VIRT_BASE #include <asm/hardware/ep7212.h> #endif @@ -71,10 +76,6 @@ #if defined (CONFIG_ARCH_AUTCPU12) -#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE -#define CS89712_BASE CLPS7111_VIRT_BASE - -#include <asm/hardware/clps7111.h> #include <asm/hardware/ep7212.h> #include <asm/hardware/cs89712.h> @@ -83,15 +84,9 @@ #if defined (CONFIG_ARCH_CDB89712) -#include <asm/hardware/clps7111.h> #include <asm/hardware/ep7212.h> #include <asm/hardware/cs89712.h> -/* static cdb89712_map_io() areas */ -#define REGISTER_START 0x80000000 -#define REGISTER_SIZE 0x4000 -#define REGISTER_BASE 0xff000000 - #define ETHER_START 0x20000000 #define ETHER_SIZE 0x1000 #define ETHER_BASE 0xfe000000 @@ -154,13 +149,8 @@ #if defined (CONFIG_ARCH_CEIVA) -#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE -#define CEIVA_BASE CLPS7111_VIRT_BASE - -#include <asm/hardware/clps7111.h> #include <asm/hardware/ep7212.h> - /* * The two flash banks are wired to chip selects 0 and 1. This is the mapping * for them. diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h index 61fef9129c6a..5f65865884ce 100644 --- a/arch/arm/mach-clps711x/include/mach/time.h +++ b/arch/arm/mach-clps711x/include/mach/time.h @@ -18,7 +18,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <asm/leds.h> -#include <asm/hardware/clps7111.h> +#include <mach/hardware.h> extern void clps711x_setup_timer(void); diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h index 35ed731b9f16..263f8393ccb7 100644 --- a/arch/arm/mach-clps711x/include/mach/uncompress.h +++ b/arch/arm/mach-clps711x/include/mach/uncompress.h @@ -17,15 +17,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <mach/hardware.h> #include <asm/hardware/clps7111.h> -#undef CLPS7111_BASE -#define CLPS7111_BASE CLPS7111_PHYS_BASE - -#define __raw_readl(p) (*(unsigned long *)(p)) -#define __raw_writel(v,p) (*(unsigned long *)(p) = (v)) - #ifdef CONFIG_DEBUG_CLPS711X_UART2 #define SYSFLGx SYSFLG2 #define UARTDRx UARTDR2 @@ -34,19 +27,25 @@ #define UARTDRx UARTDR1 #endif +#define phys_reg(x) (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x))) + /* + * The following code assumes the serial port has already been + * initialized by the bootloader. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * * This does not append a newline */ static inline void putc(int c) { - while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) + while (phys_reg(SYSFLGx) & SYSFLG_UTXFF) barrier(); - clps_writel(c, UARTDRx); + phys_reg(UARTDRx) = c; } static inline void flush(void) { - while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) + while (phys_reg(SYSFLGx) & SYSFLG_UBUSY) barrier(); } diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c index dd9a6cdbeb02..bbc449fbe14a 100644 --- a/arch/arm/mach-clps711x/p720t-leds.c +++ b/arch/arm/mach-clps711x/p720t-leds.c @@ -27,9 +27,6 @@ #include <asm/leds.h> #include <asm/mach-types.h> -#include <asm/hardware/clps7111.h> -#include <asm/hardware/ep7212.h> - static void p720t_leds_event(led_event_t ledevt) { unsigned long flags; diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 97a249395b5a..fe3c1fa5462b 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -2,6 +2,11 @@ if ARCH_EP93XX menu "Cirrus EP93xx Implementation Options" +config EP93XX_SOC_COMMON + bool + default y + select LEDS_GPIO_REGISTER + config CRUNCH bool "Support for MaverickCrunch" help diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 8d2589588713..66b1494f23a6 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -241,11 +241,7 @@ unsigned int ep93xx_chip_revision(void) * EP93xx GPIO *************************************************************************/ static struct resource ep93xx_gpio_resource[] = { - { - .start = EP93XX_GPIO_PHYS_BASE, - .end = EP93XX_GPIO_PHYS_BASE + 0xcc - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), }; static struct platform_device ep93xx_gpio_device = { @@ -288,11 +284,7 @@ static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE, { IRQ_EP93XX_UART3 }, &ep93xx_uart_data); static struct resource ep93xx_rtc_resource[] = { - { - .start = EP93XX_RTC_PHYS_BASE, - .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c), }; static struct platform_device ep93xx_rtc_device = { @@ -304,16 +296,8 @@ static struct platform_device ep93xx_rtc_device = { static struct resource ep93xx_ohci_resources[] = { - [0] = { - .start = EP93XX_USB_PHYS_BASE, - .end = EP93XX_USB_PHYS_BASE + 0x0fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_EP93XX_USB, - .end = IRQ_EP93XX_USB, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), + DEFINE_RES_IRQ(IRQ_EP93XX_USB), }; @@ -372,15 +356,8 @@ void __init ep93xx_register_flash(unsigned int width, static struct ep93xx_eth_data ep93xx_eth_data; static struct resource ep93xx_eth_resource[] = { - { - .start = EP93XX_ETHERNET_PHYS_BASE, - .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_EP93XX_ETHERNET, - .end = IRQ_EP93XX_ETHERNET, - .flags = IORESOURCE_IRQ, - } + DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000), + DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET), }; static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32); @@ -461,16 +438,8 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data, static struct ep93xx_spi_info ep93xx_spi_master_data; static struct resource ep93xx_spi_resources[] = { - { - .start = EP93XX_SPI_PHYS_BASE, - .end = EP93XX_SPI_PHYS_BASE + 0x18 - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_EP93XX_SSP, - .end = IRQ_EP93XX_SSP, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18), + DEFINE_RES_IRQ(IRQ_EP93XX_SSP), }; static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32); @@ -513,7 +482,7 @@ void __init ep93xx_register_spi(struct ep93xx_spi_info *info, /************************************************************************* * EP93xx LEDs *************************************************************************/ -static struct gpio_led ep93xx_led_pins[] = { +static const struct gpio_led ep93xx_led_pins[] __initconst = { { .name = "platform:grled", .gpio = EP93XX_GPIO_LINE_GRLED, @@ -523,29 +492,16 @@ static struct gpio_led ep93xx_led_pins[] = { }, }; -static struct gpio_led_platform_data ep93xx_led_data = { +static const struct gpio_led_platform_data ep93xx_led_data __initconst = { .num_leds = ARRAY_SIZE(ep93xx_led_pins), .leds = ep93xx_led_pins, }; -static struct platform_device ep93xx_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &ep93xx_led_data, - }, -}; - - /************************************************************************* * EP93xx pwm peripheral handling *************************************************************************/ static struct resource ep93xx_pwm0_resource[] = { - { - .start = EP93XX_PWM_PHYS_BASE, - .end = EP93XX_PWM_PHYS_BASE + 0x10 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10), }; static struct platform_device ep93xx_pwm0_device = { @@ -556,11 +512,7 @@ static struct platform_device ep93xx_pwm0_device = { }; static struct resource ep93xx_pwm1_resource[] = { - { - .start = EP93XX_PWM_PHYS_BASE + 0x20, - .end = EP93XX_PWM_PHYS_BASE + 0x30 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10), }; static struct platform_device ep93xx_pwm1_device = { @@ -628,11 +580,7 @@ EXPORT_SYMBOL(ep93xx_pwm_release_gpio); static struct ep93xxfb_mach_info ep93xxfb_data; static struct resource ep93xx_fb_resource[] = { - { - .start = EP93XX_RASTER_PHYS_BASE, - .end = EP93XX_RASTER_PHYS_BASE + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800), }; static struct platform_device ep93xx_fb_device = { @@ -680,15 +628,8 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) static struct ep93xx_keypad_platform_data ep93xx_keypad_data; static struct resource ep93xx_keypad_resource[] = { - { - .start = EP93XX_KEY_MATRIX_PHYS_BASE, - .end = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_EP93XX_KEY, - .end = IRQ_EP93XX_KEY, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c), + DEFINE_RES_IRQ(IRQ_EP93XX_KEY), }; static struct platform_device ep93xx_keypad_device = { @@ -761,11 +702,7 @@ EXPORT_SYMBOL(ep93xx_keypad_release_gpio); * EP93xx I2S audio peripheral handling *************************************************************************/ static struct resource ep93xx_i2s_resource[] = { - { - .start = EP93XX_I2S_PHYS_BASE, - .end = EP93XX_I2S_PHYS_BASE + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), }; static struct platform_device ep93xx_i2s_device = { @@ -824,16 +761,8 @@ EXPORT_SYMBOL(ep93xx_i2s_release); * EP93xx AC97 audio peripheral handling *************************************************************************/ static struct resource ep93xx_ac97_resources[] = { - { - .start = EP93XX_AAC_PHYS_BASE, - .end = EP93XX_AAC_PHYS_BASE + 0xac - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_EP93XX_AACINTR, - .end = IRQ_EP93XX_AACINTR, - .flags = IORESOURCE_IRQ, - }, + DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac), + DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR), }; static struct platform_device ep93xx_ac97_device = { @@ -889,8 +818,9 @@ void __init ep93xx_init_devices(void) platform_device_register(&ep93xx_rtc_device); platform_device_register(&ep93xx_ohci_device); - platform_device_register(&ep93xx_leds); platform_device_register(&ep93xx_wdt_device); + + gpio_led_register_device(-1, &ep93xx_led_data); } void ep93xx_restart(char mode, const char *cmd) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 0491ceef1cda..e81c35f936b5 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -368,6 +368,7 @@ comment "Flattened Device Tree based board for EXYNOS SoCs" config MACH_EXYNOS4_DT bool "Samsung Exynos4 Machine using device tree" + depends on ARCH_EXYNOS4 select CPU_EXYNOS4210 select USE_OF select ARM_AMBA @@ -380,6 +381,7 @@ config MACH_EXYNOS4_DT config MACH_EXYNOS5_DT bool "SAMSUNG EXYNOS5 Machine using device tree" + depends on ARCH_EXYNOS5 select SOC_EXYNOS5250 select USE_OF select ARM_AMBA diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index df54c2a92225..6efd1e5919fd 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = { .ctrlbit = (1 << 3), }, { .name = "hsmmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 5), }, { .name = "hsmmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 6), }, { .name = "hsmmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), }, { .name = "hsmmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos4_clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = { static struct clksrc_clk exynos4_clk_sclk_mmc0 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos4_clk_dout_mmc0.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = { static struct clksrc_clk exynos4_clk_sclk_mmc1 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos4_clk_dout_mmc1.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = { static struct clksrc_clk exynos4_clk_sclk_mmc2 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos4_clk_dout_mmc2.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = { static struct clksrc_clk exynos4_clk_sclk_mmc3 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos4_clk_dout_mmc3.clk, .enable = exynos4_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), - CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index d013982d0f8e..5cd7a8b8868c 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = { .ctrlbit = (1 << 20), }, { .name = "hsmmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 12), }, { .name = "hsmmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 13), }, { .name = "hsmmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 14), }, { .name = "hsmmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 15), @@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { static struct clksrc_clk exynos5_clk_sclk_mmc0 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.0", + .devname = "exynos4-sdhci.0", .parent = &exynos5_clk_dout_mmc0.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { static struct clksrc_clk exynos5_clk_sclk_mmc1 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.1", + .devname = "exynos4-sdhci.1", .parent = &exynos5_clk_dout_mmc1.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { static struct clksrc_clk exynos5_clk_sclk_mmc2 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.2", + .devname = "exynos4-sdhci.2", .parent = &exynos5_clk_dout_mmc2.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .clk = { .name = "sclk_mmc", - .devname = "s3c-sdhci.3", + .devname = "exynos4-sdhci.3", .parent = &exynos5_clk_dout_mmc3.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), - CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), - CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 8614aab47cc0..5ccd6e80a607 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -326,6 +326,11 @@ static void __init exynos4_map_io(void) s3c_fimc_setname(2, "exynos4-fimc"); s3c_fimc_setname(3, "exynos4-fimc"); + s3c_sdhci_setname(0, "exynos4-sdhci"); + s3c_sdhci_setname(1, "exynos4-sdhci"); + s3c_sdhci_setname(2, "exynos4-sdhci"); + s3c_sdhci_setname(3, "exynos4-sdhci"); + /* The I2C bus controllers are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); @@ -344,6 +349,11 @@ static void __init exynos5_map_io(void) s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC; s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC; + s3c_sdhci_setname(0, "exynos4-sdhci"); + s3c_sdhci_setname(1, "exynos4-sdhci"); + s3c_sdhci_setname(2, "exynos4-sdhci"); + s3c_sdhci_setname(3, "exynos4-sdhci"); + /* The I2C bus controllers are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); @@ -537,7 +547,9 @@ void __init exynos5_init_irq(void) { int irq; - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); +#ifdef CONFIG_OF + of_irq_init(exynos4_dt_irq_match); +#endif for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) { combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c index b025db4bf602..79035018fb74 100644 --- a/arch/arm/mach-exynos/dev-dwmci.c +++ b/arch/arm/mach-exynos/dev-dwmci.c @@ -16,6 +16,7 @@ #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <linux/interrupt.h> +#include <linux/ioport.h> #include <linux/mmc/dw_mmc.h> #include <plat/devs.h> @@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data) } static struct resource exynos4_dwmci_resource[] = { - [0] = { - .start = EXYNOS4_PA_DWMCI, - .end = EXYNOS4_PA_DWMCI + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DWMCI, - .end = IRQ_DWMCI, - .flags = IORESOURCE_IRQ, - } + [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K), + [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI), }; static struct dw_mci_board exynos4_dwci_pdata = { diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 9bee8535d9e0..591e78521a9f 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -212,6 +212,8 @@ #define IRQ_MFC EXYNOS4_IRQ_MFC #define IRQ_SDO EXYNOS4_IRQ_SDO +#define IRQ_I2S0 EXYNOS4_IRQ_I2S0 + #define IRQ_ADC EXYNOS4_IRQ_ADC0 #define IRQ_TC EXYNOS4_IRQ_PEN0 diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 024d38ff1718..6e6d11ff352a 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -89,6 +89,10 @@ #define EXYNOS4_PA_MDMA1 0x12840000 #define EXYNOS4_PA_PDMA0 0x12680000 #define EXYNOS4_PA_PDMA1 0x12690000 +#define EXYNOS5_PA_MDMA0 0x10800000 +#define EXYNOS5_PA_MDMA1 0x11C10000 +#define EXYNOS5_PA_PDMA0 0x121A0000 +#define EXYNOS5_PA_PDMA1 0x121B0000 #define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 #define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index e141c1fd68d8..d9578a58ae7f 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -255,9 +255,15 @@ /* For EXYNOS5250 */ +#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) #define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) #define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) +#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) #define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) +#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) +#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) +#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) + #define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) #define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 0d26f50081ad..4711c8920e37 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -45,7 +45,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "exynos4210-uart.3", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), - OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), {}, }; diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index b3982c867c9c..ed90aef404c3 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c @@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = { .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_ERASE), + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; @@ -307,49 +308,7 @@ static struct i2c_board_info i2c1_devs[] __initdata = { }; /* TSP */ -static u8 mxt_init_vals[] = { - /* MXT_GEN_COMMAND(6) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_GEN_POWER(7) */ - 0x20, 0xff, 0x32, - /* MXT_GEN_ACQUIRE(8) */ - 0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23, - /* MXT_TOUCH_MULTI(9) */ - 0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, - /* MXT_TOUCH_KEYARRAY(15) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x00, - /* MXT_SPT_GPIOPWM(19) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_PROCI_GRIPFACE(20) */ - 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04, - 0x0f, 0x0a, - /* MXT_PROCG_NOISE(22) */ - 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00, - 0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03, - /* MXT_TOUCH_PROXIMITY(23) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_PROCI_ONETOUCH(24) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_SPT_SELFTEST(25) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - /* MXT_PROCI_TWOTOUCH(27) */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* MXT_SPT_CTECONFIG(28) */ - 0x00, 0x00, 0x02, 0x08, 0x10, 0x00, -}; - static struct mxt_platform_data mxt_platform_data = { - .config = mxt_init_vals, - .config_length = ARRAY_SIZE(mxt_init_vals), - .x_line = 18, .y_line = 11, .x_size = 1024, @@ -571,7 +530,7 @@ static struct regulator_init_data __initdata max8997_ldo7_data = { static struct regulator_init_data __initdata max8997_ldo8_data = { .constraints = { - .name = "VUSB/VDAC_3.3V_C210", + .name = "VUSB+VDAC_3.3V_C210", .min_uV = 3300000, .max_uV = 3300000, .valid_ops_mask = REGULATOR_CHANGE_STATUS, @@ -1347,6 +1306,7 @@ static struct platform_device *nuri_devices[] __initdata = { static void __init nuri_map_io(void) { + clk_xusbxti.rate = 24000000; exynos_init_io(NULL, 0); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); @@ -1379,7 +1339,6 @@ static void __init nuri_machine_init(void) nuri_camera_init(); nuri_ehci_init(); - clk_xusbxti.rate = 24000000; /* Last */ platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index 6bb9dbdd73fd..cb2b027f09a6 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c @@ -29,6 +29,7 @@ #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/clock.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/iic.h> @@ -746,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { .max_width = 8, .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; @@ -1057,6 +1059,7 @@ static struct platform_device *universal_devices[] __initdata = { static void __init universal_map_io(void) { + clk_xusbxti.rate = 24000000; exynos_init_io(NULL, 0); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7561eca131b0..f72d399ff3d6 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -571,8 +571,10 @@ config MACH_MX35_3DS select MXC_DEBUG_BOARD select IMX_HAVE_PLATFORM_FSL_USB2_UDC select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_FB select IMX_HAVE_PLATFORM_IMX_I2C select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_IPU_CORE select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 5f2f91d1798b..b46cab0ced53 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -243,7 +243,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = { static void __maybe_unused ads7846_dev_init(void) { if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) { - printk(KERN_ERR "can't get ads746 pen down GPIO\n"); + printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); return; } gpio_direction_input(ADS7846_PENDOWN); diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c index 861ceb8232d6..ed38d03c61f2 100644 --- a/arch/arm/mach-imx/imx27-dt.c +++ b/arch/arm/mach-imx/imx27-dt.c @@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = { static int __init imx27_avic_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { - irq_domain_add_simple(np, 0); + irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL); return 0; } @@ -44,7 +44,9 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np, { static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; - irq_domain_add_simple(np, gpio_irq_base); + gpio_irq_base -= 32; + irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, + NULL); return 0; } diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 8ecc872b2547..c515f8ede1a1 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c @@ -194,7 +194,7 @@ static void __init eukrea_cpuimx35_timer_init(void) mx35_clocks_init(); } -struct sys_timer eukrea_cpuimx35_timer = { +static struct sys_timer eukrea_cpuimx35_timer = { .init = eukrea_cpuimx35_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 97046088ff1a..7274e7928136 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -134,7 +134,7 @@ static void __init mx1ads_timer_init(void) mx1_clocks_init(32000); } -struct sys_timer mx1ads_timer = { +static struct sys_timer mx1ads_timer = { .init = mx1ads_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index e432d4acee1f..d14bbe949a4f 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -304,8 +304,7 @@ static void __init mx21ads_board_init(void) imx21_add_mxc_nand(&mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - platform_device_register_full( - (struct platform_device_info *)&mx21ads_cs8900_devinfo); + platform_device_register_full(&mx21ads_cs8900_devinfo); } static void __init mx21ads_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index 0abef5f13df5..686c60587980 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c @@ -283,7 +283,7 @@ static void __init mx31lite_timer_init(void) mx31_clocks_init(26000000); } -struct sys_timer mx31lite_timer = { +static struct sys_timer mx31lite_timer = { .init = mx31lite_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index f17a15f28316..1dfe3c7a7be1 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c @@ -580,7 +580,7 @@ static void __init mx31moboard_timer_init(void) mx31_clocks_init(26000000); } -struct sys_timer mx31moboard_timer = { +static struct sys_timer mx31moboard_timer = { .init = mx31moboard_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index 6ae51c6b95b7..c433187988a2 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c @@ -419,7 +419,7 @@ static void __init mx35pdk_timer_init(void) mx35_clocks_init(); } -struct sys_timer mx35pdk_timer = { +static struct sys_timer mx35pdk_timer = { .init = mx35pdk_timer_init, }; diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c index 586e9f822124..86e96ef11f9d 100644 --- a/arch/arm/mach-imx/mach-mx51_efikamx.c +++ b/arch/arm/mach-imx/mach-mx51_efikamx.c @@ -284,8 +284,7 @@ static struct sys_timer mx51_efikamx_timer = { .init = mx51_efikamx_timer_init, }; -MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") - /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */ +MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)") .atag_offset = 0x100, .map_io = mx51_map_io, .init_early = imx51_init_early, diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c index 24aded9e109f..88f837a6cc76 100644 --- a/arch/arm/mach-imx/mach-mx51_efikasb.c +++ b/arch/arm/mach-imx/mach-mx51_efikasb.c @@ -280,7 +280,7 @@ static struct sys_timer mx51_efikasb_timer = { .init = mx51_efikasb_timer_init, }; -MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook") +MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)") .atag_offset = 0x100, .map_io = mx51_map_io, .init_early = imx51_init_early, diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 5fddf94cc969..10c9795934a3 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -683,7 +683,7 @@ static void __init pcm037_timer_init(void) mx31_clocks_init(26000000); } -struct sys_timer pcm037_timer = { +static struct sys_timer pcm037_timer = { .init = pcm037_timer_init, }; diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index 237474fcca23..73585f55cca0 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c @@ -399,7 +399,7 @@ static void __init pcm043_timer_init(void) mx35_clocks_init(); } -struct sys_timer pcm043_timer = { +static struct sys_timer pcm043_timer = { .init = pcm043_timer_init, }; diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 033257e553ef..add8c69c6c1a 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c @@ -310,7 +310,7 @@ static void __init vpr200_timer_init(void) mx35_clocks_init(); } -struct sys_timer vpr200_timer = { +static struct sys_timer vpr200_timer = { .init = vpr200_timer_init, }; diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index 05250aed61fb..e10f3914fcfe 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -35,7 +35,7 @@ static void imx5_idle(void) } clk_enable(gpc_dvfs_clk); mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); - if (tzic_enable_wake() != 0) + if (!tzic_enable_wake()) cpu_do_idle(); clk_disable(gpc_dvfs_clk); } diff --git a/arch/arm/mach-ixp2000/Kconfig b/arch/arm/mach-ixp2000/Kconfig deleted file mode 100644 index 08d2707f6ca8..000000000000 --- a/arch/arm/mach-ixp2000/Kconfig +++ /dev/null @@ -1,72 +0,0 @@ - -if ARCH_IXP2000 - -config ARCH_SUPPORTS_BIG_ENDIAN - bool - default y - -menu "Intel IXP2400/2800 Implementation Options" - -comment "IXP2400/2800 Platforms" - -config ARCH_ENP2611 - bool "Support Radisys ENP-2611" - help - Say 'Y' here if you want your kernel to support the Radisys - ENP2611 PCI network processing card. For more information on - this card, see <file:Documentation/arm/IXP2000>. - -config ARCH_IXDP2400 - bool "Support Intel IXDP2400" - help - Say 'Y' here if you want your kernel to support the Intel - IXDP2400 reference platform. For more information on - this platform, see <file:Documentation/arm/IXP2000>. - -config ARCH_IXDP2800 - bool "Support Intel IXDP2800" - help - Say 'Y' here if you want your kernel to support the Intel - IXDP2800 reference platform. For more information on - this platform, see <file:Documentation/arm/IXP2000>. - -config ARCH_IXDP2X00 - bool - depends on ARCH_IXDP2400 || ARCH_IXDP2800 - default y - -config ARCH_IXDP2401 - bool "Support Intel IXDP2401" - help - Say 'Y' here if you want your kernel to support the Intel - IXDP2401 reference platform. For more information on - this platform, see <file:Documentation/arm/IXP2000>. - -config ARCH_IXDP2801 - bool "Support Intel IXDP2801 and IXDP28x5" - help - Say 'Y' here if you want your kernel to support the Intel - IXDP2801/2805/2855 reference platforms. For more information on - this platform, see <file:Documentation/arm/IXP2000>. - -config MACH_IXDP28X5 - bool - depends on ARCH_IXDP2801 - default y - -config ARCH_IXDP2X01 - bool - depends on ARCH_IXDP2401 || ARCH_IXDP2801 - default y - -config IXP2000_SUPPORT_BROKEN_PCI_IO - bool "Support broken PCI I/O on older IXP2000s" - default y - help - Say 'N' here if you only intend to run your kernel on an - IXP2000 B0 or later model and do not need the PCI I/O - byteswap workaround. Say 'Y' otherwise. - -endmenu - -endif diff --git a/arch/arm/mach-ixp2000/Makefile b/arch/arm/mach-ixp2000/Makefile deleted file mode 100644 index 1e6139d42a92..000000000000 --- a/arch/arm/mach-ixp2000/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Makefile for the linux kernel. -# -obj-y := core.o pci.o -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_ARCH_ENP2611) += enp2611.o -obj-$(CONFIG_ARCH_IXDP2400) += ixdp2400.o -obj-$(CONFIG_ARCH_IXDP2800) += ixdp2800.o -obj-$(CONFIG_ARCH_IXDP2X00) += ixdp2x00.o -obj-$(CONFIG_ARCH_IXDP2X01) += ixdp2x01.o - diff --git a/arch/arm/mach-ixp2000/Makefile.boot b/arch/arm/mach-ixp2000/Makefile.boot deleted file mode 100644 index 9c7af91d93da..000000000000 --- a/arch/arm/mach-ixp2000/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 - diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c deleted file mode 100644 index f214cdff01cb..000000000000 --- a/arch/arm/mach-ixp2000/core.c +++ /dev/null @@ -1,520 +0,0 @@ -/* - * arch/arm/mach-ixp2000/core.c - * - * Common routines used by all IXP2400/2800 based platforms. - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2004 (C) MontaVista Software, Inc. - * - * Based on work Copyright (C) 2002-2003 Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/serial_8250.h> -#include <linux/mm.h> -#include <linux/export.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> - -#include <asm/mach/map.h> -#include <asm/mach/time.h> -#include <asm/mach/irq.h> - -#include <mach/gpio-ixp2000.h> - -static DEFINE_SPINLOCK(ixp2000_slowport_lock); -static unsigned long ixp2000_slowport_irq_flags; - -/************************************************************************* - * Slowport access routines - *************************************************************************/ -void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg) -{ - spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags); - - old_cfg->CCR = *IXP2000_SLOWPORT_CCR; - old_cfg->WTC = *IXP2000_SLOWPORT_WTC2; - old_cfg->RTC = *IXP2000_SLOWPORT_RTC2; - old_cfg->PCR = *IXP2000_SLOWPORT_PCR; - old_cfg->ADC = *IXP2000_SLOWPORT_ADC; - - ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR); - ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC); - ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC); - ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR); - ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC); -} - -void ixp2000_release_slowport(struct slowport_cfg *old_cfg) -{ - ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR); - ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC); - ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC); - ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR); - ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC); - - spin_unlock_irqrestore(&ixp2000_slowport_lock, - ixp2000_slowport_irq_flags); -} - -/************************************************************************* - * Chip specific mappings shared by all IXP2000 systems - *************************************************************************/ -static struct map_desc ixp2000_io_desc[] __initdata = { - { - .virtual = IXP2000_CAP_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE), - .length = IXP2000_CAP_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_INTCTL_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE), - .length = IXP2000_INTCTL_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_CREG_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE), - .length = IXP2000_PCI_CREG_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_CSR_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE), - .length = IXP2000_PCI_CSR_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_MSF_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE), - .length = IXP2000_MSF_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_SCRATCH_RING_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE), - .length = IXP2000_SCRATCH_RING_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_SRAM0_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE), - .length = IXP2000_SRAM0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE), - .length = IXP2000_PCI_IO_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_CFG0_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE), - .length = IXP2000_PCI_CFG0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = IXP2000_PCI_CFG1_VIRT_BASE, - .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE), - .length = IXP2000_PCI_CFG1_SIZE, - .type = MT_DEVICE, - } -}; - -void __init ixp2000_map_io(void) -{ - iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); - - /* Set slowport to 8-bit mode. */ - ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1); -} - - -/************************************************************************* - * Serial port support for IXP2000 - *************************************************************************/ -static struct plat_serial8250_port ixp2000_serial_port[] = { - { - .mapbase = IXP2000_UART_PHYS_BASE, - .membase = (char *)(IXP2000_UART_VIRT_BASE + 3), - .irq = IRQ_IXP2000_UART, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = 50000000, - }, - { }, -}; - -static struct resource ixp2000_uart_resource = { - .start = IXP2000_UART_PHYS_BASE, - .end = IXP2000_UART_PHYS_BASE + 0x1f, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixp2000_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = ixp2000_serial_port, - }, - .num_resources = 1, - .resource = &ixp2000_uart_resource, -}; - -void __init ixp2000_uart_init(void) -{ - platform_device_register(&ixp2000_serial_device); -} - - -/************************************************************************* - * Timer-tick functions for IXP2000 - *************************************************************************/ -static unsigned ticks_per_jiffy; -static unsigned ticks_per_usec; -static unsigned next_jiffy_time; -static volatile unsigned long *missing_jiffy_timer_csr; - -unsigned long ixp2000_gettimeoffset (void) -{ - unsigned long offset; - - offset = next_jiffy_time - *missing_jiffy_timer_csr; - - return offset / ticks_per_usec; -} - -static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id) -{ - /* clear timer 1 */ - ixp2000_reg_wrb(IXP2000_T1_CLR, 1); - - while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr) - >= ticks_per_jiffy) { - timer_tick(); - next_jiffy_time -= ticks_per_jiffy; - } - - return IRQ_HANDLED; -} - -static struct irqaction ixp2000_timer_irq = { - .name = "IXP2000 Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = ixp2000_timer_interrupt, -}; - -void __init ixp2000_init_time(unsigned long tick_rate) -{ - ticks_per_jiffy = (tick_rate + HZ/2) / HZ; - ticks_per_usec = tick_rate / 1000000; - - /* - * We use timer 1 as our timer interrupt. - */ - ixp2000_reg_write(IXP2000_T1_CLR, 0); - ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1); - ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7)); - - /* - * We use a second timer as a monotonic counter for tracking - * missed jiffies. The IXP2000 has four timers, but if we're - * on an A-step IXP2800, timer 2 and 3 don't work, so on those - * chips we use timer 4. Timer 4 is the only timer that can - * be used for the watchdog, so we use timer 2 if we're on a - * non-buggy chip. - */ - if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) { - printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n"); - - ixp2000_reg_write(IXP2000_T4_CLR, 0); - ixp2000_reg_write(IXP2000_T4_CLD, -1); - ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7)); - missing_jiffy_timer_csr = IXP2000_T4_CSR; - } else { - ixp2000_reg_write(IXP2000_T2_CLR, 0); - ixp2000_reg_write(IXP2000_T2_CLD, -1); - ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7)); - missing_jiffy_timer_csr = IXP2000_T2_CSR; - } - next_jiffy_time = 0xffffffff; - - /* register for interrupt */ - setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq); -} - -/************************************************************************* - * GPIO helpers - *************************************************************************/ -static unsigned long GPIO_IRQ_falling_edge; -static unsigned long GPIO_IRQ_rising_edge; -static unsigned long GPIO_IRQ_level_low; -static unsigned long GPIO_IRQ_level_high; - -static void update_gpio_int_csrs(void) -{ - ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge); - ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge); - ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low); - ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high); -} - -void gpio_line_config(int line, int direction) -{ - unsigned long flags; - - local_irq_save(flags); - if (direction == GPIO_OUT) { - /* if it's an output, it ain't an interrupt anymore */ - GPIO_IRQ_falling_edge &= ~(1 << line); - GPIO_IRQ_rising_edge &= ~(1 << line); - GPIO_IRQ_level_low &= ~(1 << line); - GPIO_IRQ_level_high &= ~(1 << line); - update_gpio_int_csrs(); - - ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line); - } else if (direction == GPIO_IN) { - ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line); - } - local_irq_restore(flags); -} -EXPORT_SYMBOL(gpio_line_config); - - -/************************************************************************* - * IRQ handling IXP2000 - *************************************************************************/ -static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - int i; - unsigned long status = *IXP2000_GPIO_INST; - - for (i = 0; i <= 7; i++) { - if (status & (1<<i)) { - generic_handle_irq(i + IRQ_IXP2000_GPIO0); - } - } -} - -static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type) -{ - int line = d->irq - IRQ_IXP2000_GPIO0; - - /* - * First, configure this GPIO line as an input. - */ - ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line); - - /* - * Then, set the proper trigger type. - */ - if (type & IRQ_TYPE_EDGE_FALLING) - GPIO_IRQ_falling_edge |= 1 << line; - else - GPIO_IRQ_falling_edge &= ~(1 << line); - if (type & IRQ_TYPE_EDGE_RISING) - GPIO_IRQ_rising_edge |= 1 << line; - else - GPIO_IRQ_rising_edge &= ~(1 << line); - if (type & IRQ_TYPE_LEVEL_LOW) - GPIO_IRQ_level_low |= 1 << line; - else - GPIO_IRQ_level_low &= ~(1 << line); - if (type & IRQ_TYPE_LEVEL_HIGH) - GPIO_IRQ_level_high |= 1 << line; - else - GPIO_IRQ_level_high &= ~(1 << line); - update_gpio_int_csrs(); - - return 0; -} - -static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d) -{ - unsigned int irq = d->irq; - - ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); - - ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); - ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); - ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0))); -} - -static void ixp2000_GPIO_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); -} - -static void ixp2000_GPIO_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0))); -} - -static struct irq_chip ixp2000_GPIO_irq_chip = { - .irq_ack = ixp2000_GPIO_irq_mask_ack, - .irq_mask = ixp2000_GPIO_irq_mask, - .irq_unmask = ixp2000_GPIO_irq_unmask, - .irq_set_type = ixp2000_GPIO_irq_type, -}; - -static void ixp2000_pci_irq_mask(struct irq_data *d) -{ - unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; - if (d->irq == IRQ_IXP2000_PCIA) - ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26))); - else if (d->irq == IRQ_IXP2000_PCIB) - ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27))); -} - -static void ixp2000_pci_irq_unmask(struct irq_data *d) -{ - unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; - if (d->irq == IRQ_IXP2000_PCIA) - ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26))); - else if (d->irq == IRQ_IXP2000_PCIB) - ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27))); -} - -/* - * Error interrupts. These are used extensively by the microengine drivers - */ -static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - int i; - unsigned long status = *IXP2000_IRQ_ERR_STATUS; - - for(i = 31; i >= 0; i--) { - if(status & (1 << i)) { - generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i); - } - } -} - -static void ixp2000_err_irq_mask(struct irq_data *d) -{ - ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR, - (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR))); -} - -static void ixp2000_err_irq_unmask(struct irq_data *d) -{ - ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET, - (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR))); -} - -static struct irq_chip ixp2000_err_irq_chip = { - .irq_ack = ixp2000_err_irq_mask, - .irq_mask = ixp2000_err_irq_mask, - .irq_unmask = ixp2000_err_irq_unmask -}; - -static struct irq_chip ixp2000_pci_irq_chip = { - .irq_ack = ixp2000_pci_irq_mask, - .irq_mask = ixp2000_pci_irq_mask, - .irq_unmask = ixp2000_pci_irq_unmask -}; - -static void ixp2000_irq_mask(struct irq_data *d) -{ - ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq)); -} - -static void ixp2000_irq_unmask(struct irq_data *d) -{ - ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq)); -} - -static struct irq_chip ixp2000_irq_chip = { - .irq_ack = ixp2000_irq_mask, - .irq_mask = ixp2000_irq_mask, - .irq_unmask = ixp2000_irq_unmask -}; - -void __init ixp2000_init_irq(void) -{ - int irq; - - /* - * Mask all sources - */ - ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff); - ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff); - - /* clear all GPIO edge/level detects */ - ixp2000_reg_write(IXP2000_GPIO_REDR, 0); - ixp2000_reg_write(IXP2000_GPIO_FEDR, 0); - ixp2000_reg_write(IXP2000_GPIO_LSHR, 0); - ixp2000_reg_write(IXP2000_GPIO_LSLR, 0); - ixp2000_reg_write(IXP2000_GPIO_INCR, -1); - - /* clear PCI interrupt sources */ - ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0); - - /* - * Certain bits in the IRQ status register of the - * IXP2000 are reserved. Instead of trying to map - * things non 1:1 from bit position to IRQ number, - * we mark the reserved IRQs as invalid. This makes - * our mask/unmask code much simpler. - */ - for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { - if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { - irq_set_chip_and_handler(irq, &ixp2000_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } else set_irq_flags(irq, 0); - } - - for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { - if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & - IXP2000_VALID_ERR_IRQ_MASK) { - irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - else - set_irq_flags(irq, 0); - } - irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); - - for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { - irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); - - /* - * Enable PCI irqs. The actual PCI[AB] decoding is done in - * entry-macro.S, so we don't need a chained handler for the - * PCI interrupt source. - */ - ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); - for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { - irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } -} - -void ixp2000_restart(char mode, const char *cmd) -{ - ixp2000_reg_wrb(IXP2000_RESET0, RSTALL); -} diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c deleted file mode 100644 index 4867f408617c..000000000000 --- a/arch/arm/mach-ixp2000/enp2611.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * arch/arm/mach-ixp2000/enp2611.c - * - * Radisys ENP-2611 support. - * - * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The - * original version carries the following notices: - * - * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002-2003 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach/flash.h> - -/************************************************************************* - * ENP-2611 timer tick configuration - *************************************************************************/ -static void __init enp2611_timer_init(void) -{ - ixp2000_init_time(50 * 1000 * 1000); -} - -static struct sys_timer enp2611_timer = { - .init = enp2611_timer_init, - .offset = ixp2000_gettimeoffset, -}; - - -/************************************************************************* - * ENP-2611 I/O - *************************************************************************/ -static struct map_desc enp2611_io_desc[] __initdata = { - { - .virtual = ENP2611_CALEB_VIRT_BASE, - .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE), - .length = ENP2611_CALEB_SIZE, - .type = MT_DEVICE, - }, { - .virtual = ENP2611_PM3386_0_VIRT_BASE, - .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE), - .length = ENP2611_PM3386_0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = ENP2611_PM3386_1_VIRT_BASE, - .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE), - .length = ENP2611_PM3386_1_SIZE, - .type = MT_DEVICE, - } -}; - -void __init enp2611_map_io(void) -{ - ixp2000_map_io(); - iotable_init(enp2611_io_desc, ARRAY_SIZE(enp2611_io_desc)); -} - - -/************************************************************************* - * ENP-2611 PCI - *************************************************************************/ -static int enp2611_pci_setup(int nr, struct pci_sys_data *sys) -{ - sys->mem_offset = 0xe0000000; - ixp2000_pci_setup(nr, sys); - return 1; -} - -static void __init enp2611_pci_preinit(void) -{ - ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000); - ixp2000_pci_preinit(); - pcibios_setup("firmware"); -} - -static inline int enp2611_pci_valid_device(struct pci_bus *bus, - unsigned int devfn) -{ - /* The 82559 ethernet controller appears at both PCI:1:0:0 and - * PCI:1:2:0, so let's pretend the second one isn't there. - */ - if (bus->number == 0x01 && devfn == 0x10) - return 0; - - return 1; -} - -static int enp2611_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *value) -{ - if (enp2611_pci_valid_device(bus, devfn)) - return ixp2000_pci_read_config(bus, devfn, where, size, value); - - return PCIBIOS_DEVICE_NOT_FOUND; -} - -static int enp2611_pci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 value) -{ - if (enp2611_pci_valid_device(bus, devfn)) - return ixp2000_pci_write_config(bus, devfn, where, size, value); - - return PCIBIOS_DEVICE_NOT_FOUND; -} - -static struct pci_ops enp2611_pci_ops = { - .read = enp2611_pci_read_config, - .write = enp2611_pci_write_config -}; - -static struct pci_bus * __init enp2611_pci_scan_bus(int nr, - struct pci_sys_data *sys) -{ - return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys, - &sys->resources); -} - -static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 0) { - /* IXP2400. */ - irq = IRQ_IXP2000_PCIA; - } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 1) { - /* 21555 non-transparent bridge. */ - irq = IRQ_IXP2000_PCIB; - } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 4) { - /* PCI2050B transparent bridge. */ - irq = -1; - } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) { - /* 82559 ethernet. */ - irq = IRQ_IXP2000_PCIA; - } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 1) { - /* SPI-3 option board. */ - irq = IRQ_IXP2000_PCIB; - } else { - printk(KERN_ERR "enp2611_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -struct hw_pci enp2611_pci __initdata = { - .nr_controllers = 1, - .setup = enp2611_pci_setup, - .preinit = enp2611_pci_preinit, - .scan = enp2611_pci_scan_bus, - .map_irq = enp2611_pci_map_irq, -}; - -int __init enp2611_pci_init(void) -{ - if (machine_is_enp2611()) - pci_common_init(&enp2611_pci); - - return 0; -} - -subsys_initcall(enp2611_pci_init); - - -/************************************************************************* - * ENP-2611 Machine Initialization - *************************************************************************/ -static struct flash_platform_data enp2611_flash_platform_data = { - .map_name = "cfi_probe", - .width = 1, -}; - -static struct ixp2000_flash_data enp2611_flash_data = { - .platform_data = &enp2611_flash_platform_data, - .nr_banks = 1 -}; - -static struct resource enp2611_flash_resource = { - .start = 0xc4000000, - .end = 0xc4000000 + 0x00ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device enp2611_flash = { - .name = "IXP2000-Flash", - .id = 0, - .dev = { - .platform_data = &enp2611_flash_data, - }, - .num_resources = 1, - .resource = &enp2611_flash_resource, -}; - -static struct ixp2000_i2c_pins enp2611_i2c_gpio_pins = { - .sda_pin = ENP2611_GPIO_SDA, - .scl_pin = ENP2611_GPIO_SCL, -}; - -static struct platform_device enp2611_i2c_controller = { - .name = "IXP2000-I2C", - .id = 0, - .dev = { - .platform_data = &enp2611_i2c_gpio_pins - }, - .num_resources = 0 -}; - -static struct platform_device *enp2611_devices[] __initdata = { - &enp2611_flash, - &enp2611_i2c_controller -}; - -static void __init enp2611_init_machine(void) -{ - platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices)); - ixp2000_uart_init(); -} - - -MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board") - /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ - .atag_offset = 0x100, - .map_io = enp2611_map_io, - .init_irq = ixp2000_init_irq, - .timer = &enp2611_timer, - .init_machine = enp2611_init_machine, - .restart = ixp2000_restart, -MACHINE_END - - diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S deleted file mode 100644 index bdd3ccdc2890..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-ixp2000/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart, rp, rv, tmp - mov \rp, #0x00030000 -#ifdef __ARMEB__ - orr \rp, \rp, #0x00000003 -#endif - orr \rv, \rp, #0xfe000000 @ virtual base - orr \rv, \rv, #0x00f00000 - orr \rp, \rp, #0xc0000000 @ Physical base - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h deleted file mode 100644 index 9ce3690061d5..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/enp2611.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/enp2611.h - * - * Register and other defines for Radisys ENP-2611 - * - * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The - * original version carries the following notices: - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ENP2611_H -#define __ENP2611_H - -#define ENP2611_CALEB_PHYS_BASE 0xc5000000 -#define ENP2611_CALEB_VIRT_BASE 0xfe000000 -#define ENP2611_CALEB_SIZE 0x00100000 - -#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000 -#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000 -#define ENP2611_PM3386_0_SIZE 0x00100000 - -#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000 -#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000 -#define ENP2611_PM3386_1_SIZE 0x00100000 - -#define ENP2611_GPIO_SCL 7 -#define ENP2611_GPIO_SDA 6 - -#define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4 -#define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3 -#define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2 -#define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1 -#define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0 - - -#endif diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S deleted file mode 100644 index c4444dff9202..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/entry-macro.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for IXP2000-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/irqs.h> - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \irqnr, #0x0 @clear out irqnr as default - mov \base, #0xfe000000 - orr \base, \base, #0x00e00000 - orr \base, \base, #0x08 - ldr \irqstat, [\base] @ get interrupts - - cmp \irqstat, #0 - beq 1001f - - clz \irqnr, \irqstat - mov \base, #31 - subs \irqnr, \base, \irqnr - - /* - * We handle PCIA and PCIB here so we don't have an - * extra layer of code just to check these two bits. - */ - cmp \irqnr, #IRQ_IXP2000_PCI - bne 1001f - - mov \base, #0xfe000000 - orr \base, \base, #0x00c00000 - orr \base, \base, #0x00000100 - orr \base, \base, #0x00000058 - ldr \irqstat, [\base] - - mov \tmp, #(1<<26) - tst \irqstat, \tmp - movne \irqnr, #IRQ_IXP2000_PCIA - bne 1001f - - mov \tmp, #(1<<27) - tst \irqstat, \tmp - movne \irqnr, #IRQ_IXP2000_PCIB - -1001: - .endm - diff --git a/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h b/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h deleted file mode 100644 index af836c76c3f1..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/gpio.h - * - * Copyright (C) 2002 Intel Corporation. - * - * This program is free software, you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * IXP2000 GPIO in/out, edge/level detection for IRQs: - * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High - * or both Falling-edge and Rising-edge. - * This must be called *before* the corresponding IRQ is registerd. - * Use this instead of directly setting the GPIO registers. - * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb) - */ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#ifndef __ASSEMBLY__ - -#define GPIO_IN 0 -#define GPIO_OUT 1 - -#define IXP2000_GPIO_LOW 0 -#define IXP2000_GPIO_HIGH 1 - -extern void gpio_line_config(int line, int direction); - -static inline int gpio_line_get(int line) -{ - return (((*IXP2000_GPIO_PLR) >> line) & 1); -} - -static inline void gpio_line_set(int line, int value) -{ - if (value == IXP2000_GPIO_HIGH) { - ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line); - } else if (value == IXP2000_GPIO_LOW) { - ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line); - } -} - -#endif /* !__ASSEMBLY__ */ - -#endif /* ASM_ARCH_IXP2000_GPIO_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h deleted file mode 100644 index cdaf1db84003..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/hardware.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/hardware.h - * - * Hardware definitions for IXP2400/2800 based systems - * - * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> - * - * Maintainer: Deepak Saxena <dsaxena@mvista.com> - * - * Copyright (C) 2001-2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#define __ASM_ARCH_HARDWARE_H__ - -#include "ixp2000-regs.h" /* Chipset Registers */ - -/* - * Platform helper functions - */ -#include "platform.h" - -/* - * Platform-specific bits - */ -#include "enp2611.h" /* ENP-2611 */ -#include "ixdp2x00.h" /* IXDP2400/2800 */ -#include "ixdp2x01.h" /* IXDP2401/2801 */ - -#endif /* _ASM_ARCH_HARDWARE_H__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h deleted file mode 100644 index f6552d6f35ab..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/io.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/io.h - * - * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyrgiht (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * The A? revisions of the IXP2000s assert byte lanes for PCI I/O - * transactions the other way round (MEM transactions don't have this - * issue), so if we want to support those models, we need to override - * the standard I/O functions. - * - * B0 and later have a bit that can be set to 1 to get the proper - * behavior for I/O transactions, which then allows us to use the - * standard I/O functions. This is what we do if the user does not - * explicitly ask for support for pre-B0. - */ -#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO -#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) - -#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3) -#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2) - -#define outb(v,p) __raw_writeb((v),alignb(___io(p))) -#define outw(v,p) __raw_writew((v),alignw(___io(p))) -#define outl(v,p) __raw_writel((v),___io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; }) -#define inw(p) \ - ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; }) -#define inl(p) \ - ({ unsigned int __v = (__raw_readl(___io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l) -#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l) -#define outsl(p,d,l) __raw_writesl(___io(p),d,l) - -#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l) -#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) -#define insl(p,d,l) __raw_readsl(___io(p),d,l) - -#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE) - -#define ioread8(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readb(alignb(p)); \ - } else { \ - __v = __raw_readb(p); \ - } \ - \ - __v; \ - }) \ - -#define ioread16(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readw(alignw(p)); \ - } else { \ - __v = le16_to_cpu(__raw_readw(p)); \ - } \ - \ - __v; \ - }) - -#define ioread32(p) \ - ({ \ - unsigned int __v; \ - \ - if (__is_io_address(p)) { \ - __v = __raw_readl(p); \ - } else { \ - __v = le32_to_cpu(__raw_readl(p)); \ - } \ - \ - __v; \ - }) - -#define iowrite8(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writeb((v), alignb(p)); \ - } else { \ - __raw_writeb((v), p); \ - } \ - }) - -#define iowrite16(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writew((v), alignw(p)); \ - } else { \ - __raw_writew(cpu_to_le16(v), p); \ - } \ - }) - -#define iowrite32(v,p) \ - ({ \ - if (__is_io_address(p)) { \ - __raw_writel((v), p); \ - } else { \ - __raw_writel(cpu_to_le32(v), p); \ - } \ - }) - -#define ioport_map(port, nr) ___io(port) - -#define ioport_unmap(addr) -#else -#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) -#endif - - -#endif diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h deleted file mode 100644 index bee96bcafdca..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/irqs.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/irqs.h - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IRQS_H -#define _IRQS_H - -/* - * Do NOT add #ifdef MACHINE_FOO in here. - * Simpy add your machine IRQs here and increase NR_IRQS if needed to - * hold your machine's IRQ table. - */ - -/* - * Some interrupt numbers go unused b/c the IRQ mask/ummask/status - * register has those bit reserved. We just mark those interrupts - * as invalid and this allows us to do mask/unmask with a single - * shift operation instead of having to map the IRQ number to - * a HW IRQ number. - */ -#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */ -#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/ -#define IRQ_IXP2000_UART 2 -#define IRQ_IXP2000_GPIO 3 -#define IRQ_IXP2000_TIMER1 4 -#define IRQ_IXP2000_TIMER2 5 -#define IRQ_IXP2000_TIMER3 6 -#define IRQ_IXP2000_TIMER4 7 -#define IRQ_IXP2000_PMU 8 -#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */ -#define IRQ_IXP2000_DMA1 10 -#define IRQ_IXP2000_DMA2 11 -#define IRQ_IXP2000_DMA3 12 -#define IRQ_IXP2000_PCI_DOORBELL 13 -#define IRQ_IXP2000_ME_ATTN 14 -#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */ -#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */ -#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */ -#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */ -#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */ -#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */ -#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */ -#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */ -#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */ - -/* define generic GPIOs */ -#define IRQ_IXP2000_GPIO0 32 -#define IRQ_IXP2000_GPIO1 33 -#define IRQ_IXP2000_GPIO2 34 -#define IRQ_IXP2000_GPIO3 35 -#define IRQ_IXP2000_GPIO4 36 -#define IRQ_IXP2000_GPIO5 37 -#define IRQ_IXP2000_GPIO6 38 -#define IRQ_IXP2000_GPIO7 39 - -/* split off the 2 PCI sources */ -#define IRQ_IXP2000_PCIA 40 -#define IRQ_IXP2000_PCIB 41 - -/* Int sources from IRQ_ERROR_STATUS */ -#define IRQ_IXP2000_DRAM0_MIN_ERR 42 -#define IRQ_IXP2000_DRAM0_MAJ_ERR 43 -#define IRQ_IXP2000_DRAM1_MIN_ERR 44 -#define IRQ_IXP2000_DRAM1_MAJ_ERR 45 -#define IRQ_IXP2000_DRAM2_MIN_ERR 46 -#define IRQ_IXP2000_DRAM2_MAJ_ERR 47 -/* 48-57 reserved */ -#define IRQ_IXP2000_SRAM0_ERR 58 -#define IRQ_IXP2000_SRAM1_ERR 59 -#define IRQ_IXP2000_SRAM2_ERR 60 -#define IRQ_IXP2000_SRAM3_ERR 61 -/* 62-65 reserved */ -#define IRQ_IXP2000_MEDIA_ERR 66 -#define IRQ_IXP2000_PCI_ERR 67 -#define IRQ_IXP2000_SP_INT 68 - -#define NR_IXP2000_IRQS 69 - -#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x)) - -#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS)) - -#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) -#define IXP2000_VALID_ERR_IRQ_MASK (\ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \ - IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) ) - -/* - * This allows for all the on-chip sources plus up to 32 CPLD based - * IRQs. Should be more than enough. - */ -#define IXP2000_BOARD_IRQS 32 -#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS) - - -/* - * IXDP2400 specific IRQs - */ -#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1) -#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5) -#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6) -#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7) - -#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1) -#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS - -/* IXDP2800 specific IRQs */ -#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1) -#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5) - -#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1) -#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS - -/* - * IRQs on both IXDP2x01 boards - */ -#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2) -#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3) -#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4) -#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5) -#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6) -#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7) -#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8) -#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16) -#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17) -#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18) -#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19) -#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21) -#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22) -#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24) -#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25) -#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26) - -#define IXDP2X01_VALID_IRQ_MASK ( \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) ) - -/* - * IXDP2401 specific IRQs - */ -#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1) - -#define IXDP2401_VALID_IRQ_MASK ( \ - IXDP2X01_VALID_IRQ_MASK | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546)) - -/* - * IXDP2801-specific IRQs - */ -#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0) -#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27) -#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28) - -#define IXDP2801_VALID_IRQ_MASK ( \ - IXDP2X01_VALID_IRQ_MASK | \ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\ - IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF)) - -#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1) - -#endif /*_IRQS_H*/ diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h deleted file mode 100644 index 5df8479d9481..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h - * - * Register and other defines for IXDP2[48]00 platforms - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _IXDP2X00_H_ -#define _IXDP2X00_H_ - -/* - * On board CPLD memory map - */ -#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000 -#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000 -#define IXDP2X00_CPLD_SIZE 0x00100000 - - -#define IXDP2X00_CPLD_REG(x) \ - (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x) - -/* - * IXDP2400 CPLD registers - */ -#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0) -#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4) -#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8) -#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc) -#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10) -#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14) -#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18) -#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48) - -/* - * IXDP2800 CPLD registers - */ -#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0) -#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140) - - -#define IXDP2X00_GPIO_I2C_ENABLE 0x02 -#define IXDP2X00_GPIO_SCL 0x07 -#define IXDP2X00_GPIO_SDA 0x06 - -/* - * PCI devfns for on-board devices. We need these to be able to - * properly translate IRQs and for device removal. - */ -#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */ -#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */ -#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */ -#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ - -#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */ -#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */ -#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ - -#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */ -#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */ -#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */ -#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */ -#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */ - -#ifndef __ASSEMBLY__ -/* - * The master NPU is always PCI master. - */ -static inline unsigned int ixdp2x00_master_npu(void) -{ - return !!ixp2000_is_pcimaster(); -} - -/* - * Helper functions used by ixdp2400 and ixdp2800 specific code - */ -void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long); -void ixdp2x00_slave_pci_postinit(void); -void ixdp2x00_init_machine(void); -void ixdp2x00_map_io(void); - -#endif - -#endif /*_IXDP2X00_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h deleted file mode 100644 index 4c1f04083e54..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h - * - * Platform definitions for IXDP2X01 && IXDP2801 systems - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2004 (c) MontaVista Software, Inc. - * - * Based on original code Copyright (c) 2002-2003 Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __IXDP2X01_H__ -#define __IXDP2X01_H__ - -#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000 -#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000 -#define IXDP2X01_CPLD_REGION_SIZE 0x00100000 - -#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg) -#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg) - -#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40) -#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40) - -#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60) -#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60) - -#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80) -#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16) - -#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00) -#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08) -#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C) -#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10) -#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG -#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14) - -#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20) - -#define IXDP2X01_CPLD_FLASH_INTERN 0x8000 -#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF -#define IXDP2X01_FLASH_WINDOW_BITS 25 -#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS) -#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1) - -#define IXDP2X01_UART_CLK 1843200 - -#define IXDP2X01_GPIO_I2C_ENABLE 0x02 -#define IXDP2X01_GPIO_SCL 0x07 -#define IXDP2X01_GPIO_SDA 0x06 - -#endif /* __IXDP2x01_H__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h deleted file mode 100644 index 822f63f2f4a2..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h - * - * Chipset register definitions for IXP2400/2800 based systems. - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _IXP2000_REGS_H_ -#define _IXP2000_REGS_H_ - -/* - * IXP2000 linux memory map: - * - * virt phys size - * fb000000 db000000 16M PCI CFG1 - * fc000000 da000000 16M PCI CFG0 - * fd000000 d8000000 16M PCI I/O - * fe[0-7]00000 8M per-platform mappings - * fe900000 80000000 1M SRAM #0 (first MB) - * fea00000 cb400000 1M SCRATCH ring get/put - * feb00000 c8000000 1M MSF - * fec00000 df000000 1M PCI CSRs - * fed00000 de000000 1M PCI CREG - * fee00000 d6000000 1M INTCTL - * fef00000 c0000000 1M CAP - */ - -/* - * Static I/O regions. - * - * Most of the registers are clumped in 4K regions spread throughout - * the 0xc0000000 -> 0xc0100000 address range, but we just map in - * the whole range using a single 1 MB section instead of small - * 4K pages. - * - * CAP stands for CSR Access Proxy. - * - * If you change the virtual address of this mapping, please propagate - * the change to arch/arm/kernel/debug.S, which hardcodes the virtual - * address of the UART located in this region. - */ - -#define IXP2000_CAP_PHYS_BASE 0xc0000000 -#define IXP2000_CAP_VIRT_BASE 0xfef00000 -#define IXP2000_CAP_SIZE 0x00100000 - -/* - * Addresses for specific on-chip peripherals. - */ -#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 -#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 -#define IXP2000_UART_PHYS_BASE 0xc0030000 -#define IXP2000_UART_VIRT_BASE 0xfef30000 -#define IXP2000_TIMER_VIRT_BASE 0xfef20000 -#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000 -#define IXP2000_GPIO_VIRT_BASE 0xfef10000 - -/* - * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual - * addresses of the INTCTL and PCI_CSR mappings are hardcoded in - * entry-macro.S, so if you ever change these please propagate - * the change. - */ -#define IXP2000_INTCTL_PHYS_BASE 0xd6000000 -#define IXP2000_INTCTL_VIRT_BASE 0xfee00000 -#define IXP2000_INTCTL_SIZE 0x00100000 - -#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000 -#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000 -#define IXP2000_PCI_CREG_SIZE 0x00100000 - -#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000 -#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 -#define IXP2000_PCI_CSR_SIZE 0x00100000 - -#define IXP2000_MSF_PHYS_BASE 0xc8000000 -#define IXP2000_MSF_VIRT_BASE 0xfeb00000 -#define IXP2000_MSF_SIZE 0x00100000 - -#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000 -#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000 -#define IXP2000_SCRATCH_RING_SIZE 0x00100000 - -#define IXP2000_SRAM0_PHYS_BASE 0x80000000 -#define IXP2000_SRAM0_VIRT_BASE 0xfe900000 -#define IXP2000_SRAM0_SIZE 0x00100000 - -#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 -#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 -#define IXP2000_PCI_IO_SIZE 0x01000000 - -#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000 -#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000 -#define IXP2000_PCI_CFG0_SIZE 0x01000000 - -#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000 -#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000 -#define IXP2000_PCI_CFG1_SIZE 0x01000000 - -/* - * Timers - */ -#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x))) -/* Timer control */ -#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00) -#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04) -#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08) -#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c) -/* Store initial value */ -#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10) -#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14) -#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18) -#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c) -/* Read current value */ -#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20) -#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24) -#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28) -#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c) -/* Clear associated timer interrupt */ -#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30) -#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34) -#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38) -#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c) -/* Timer watchdog enable for T4 */ -#define IXP2000_TWDE IXP2000_TIMER_REG(0x40) - -#define WDT_ENABLE 0x00000001 -#define TIMER_DIVIDER_256 0x00000008 -#define TIMER_ENABLE 0x00000080 -#define IRQ_MASK_TIMER1 (1 << 4) - -/* - * Interrupt controller registers - */ -#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x)) -#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08) -#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10) -#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10) -#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18) -#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14) -#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24) -#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c) -#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30) -#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34) -#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60) -#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64) -#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68) -#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c) -#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80) -#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) -#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) -#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) -#define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0) -#define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4) -#define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8) -#define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec) -#define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100) -#define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104) -#define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108) -#define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c) -#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) -#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) -#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) -#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c) -#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180) -#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184) -#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188) -#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208) -#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c) - -/* - * Mask of valid IRQs in the 32-bit IRQ register. We use - * this to mark certain IRQs as being invalid. - */ -#define IXP2000_VALID_IRQ_MASK 0x0f0fffff - -/* - * PCI config register access from core - */ -#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x)) -#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04) -#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10) -#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14) -#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18) - -/* - * PCI CSRs - */ -#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x)) - -/* - * PCI outbound interrupts - */ -#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30) -#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34) -/* - * PCI communications - */ -#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50) -#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54) -#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58) -#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C) -#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60) -#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64) -#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70) -#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74) - -/* - * DMA engines - */ -#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80) -#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84) -#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88) -#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C) -#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90) -#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94) -#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0) -#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4) -#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8) -#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC) -#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0) -#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4) -#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0) -#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4) -#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8) -#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC) -#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0) -#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4) -#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0) -/* - * Size masks for BARs - */ -#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC) -#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100) -/* - * Control and uEngine related - */ -#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C) -#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140) -#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148) -#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C) -#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150) -#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154) -/* - * Inbound PCI interrupt control - */ -#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158) -#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) - -#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ -#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */ -#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ - -/* These are from the IRQ register in the PCI ISR register */ -#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */ -#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ -#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ -#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ -#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */ - -#define IXP2000_PCI_RST_REL (1 << 2) -#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) -#define CFG_PCI_BOOT_HOST (1 << 2) -#define CFG_BOOT_PROM (1 << 1) - -/* - * SlowPort CSRs - * - * The slowport is used to access things like flash, SONET framer control - * ports, slave microprocessors, CPLDs, and others of chip memory mapped - * peripherals. - */ -#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x)) - -#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00) -#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04) -#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08) -#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c) -#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10) -#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14) -#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18) -#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C) -#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20) -#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24) -#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28) - -/* - * CCR values. - * The CCR configures the clock division for the slowport interface. - */ -#define SLOWPORT_CCR_DIV_1 0x00 -#define SLOWPORT_CCR_DIV_2 0x01 -#define SLOWPORT_CCR_DIV_4 0x02 -#define SLOWPORT_CCR_DIV_6 0x03 -#define SLOWPORT_CCR_DIV_8 0x04 -#define SLOWPORT_CCR_DIV_10 0x05 -#define SLOWPORT_CCR_DIV_12 0x06 -#define SLOWPORT_CCR_DIV_14 0x07 -#define SLOWPORT_CCR_DIV_16 0x08 -#define SLOWPORT_CCR_DIV_18 0x09 -#define SLOWPORT_CCR_DIV_20 0x0a -#define SLOWPORT_CCR_DIV_22 0x0b -#define SLOWPORT_CCR_DIV_24 0x0c -#define SLOWPORT_CCR_DIV_26 0x0d -#define SLOWPORT_CCR_DIV_28 0x0e -#define SLOWPORT_CCR_DIV_30 0x0f - -/* - * PCR values. PCR configure the mode of the interface. - */ -#define SLOWPORT_MODE_FLASH 0x00 -#define SLOWPORT_MODE_LUCENT 0x01 -#define SLOWPORT_MODE_PMC_SIERRA 0x02 -#define SLOWPORT_MODE_INTEL_UP 0x03 -#define SLOWPORT_MODE_MOTOROLA_UP 0x04 - -/* - * ADC values. Defines data and address bus widths. - */ -#define SLOWPORT_ADDR_WIDTH_8 0x00 -#define SLOWPORT_ADDR_WIDTH_16 0x01 -#define SLOWPORT_ADDR_WIDTH_24 0x02 -#define SLOWPORT_ADDR_WIDTH_32 0x03 -#define SLOWPORT_DATA_WIDTH_8 0x00 -#define SLOWPORT_DATA_WIDTH_16 0x10 -#define SLOWPORT_DATA_WIDTH_24 0x20 -#define SLOWPORT_DATA_WIDTH_32 0x30 - -/* - * Masks and shifts for various fields in the WTC and RTC registers. - */ -#define SLOWPORT_WRTC_MASK_HD 0x0003 -#define SLOWPORT_WRTC_MASK_PW 0x003c -#define SLOWPORT_WRTC_MASK_SU 0x03c0 - -#define SLOWPORT_WRTC_SHIFT_HD 0x00 -#define SLOWPORT_WRTC_SHIFT_SU 0x02 -#define SLOWPORT_WRTC_SHFIT_PW 0x06 - - -/* - * GPIO registers & GPIO interface. - */ -#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x))) -#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00) -#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04) -#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08) -#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c) -#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10) -#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14) -#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18) -#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c) -#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20) -#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24) -#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28) -#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c) -#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30) -#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34) -#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38) -#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c) -#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40) - -/* - * "Global" registers...whatever that's supposed to mean. - */ -#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00) -#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x)) - -#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000 -#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000 -#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00 -#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200 -#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100 -#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000 -#define IXP2000_MAJ_REV_MASK 0x000000F0 -#define IXP2000_MIN_REV_MASK 0x0000000F -#define IXP2000_PROD_ID_MASK 0xFFFFFFFF - -#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00) -#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04) -#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08) -#define IXP2000_RESET0 GLOBAL_REG(0x0c) -#define IXP2000_RESET1 GLOBAL_REG(0x10) -#define IXP2000_CCR GLOBAL_REG(0x14) -#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18) - -#define RSTALL (1 << 16) -#define WDT_RESET_ENABLE 0x01000000 - - -/* - * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF - * units, but the registers that differ between the two don't overlap, - * so we can have one register list for both. - */ -#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x))) -#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000) -#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004) -#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008) -#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c) -#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010) -#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014) -#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018) -#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024) -#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028) -#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c) -#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040) -#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044) -#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048) -#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054) -#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058) -#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060) -#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064) -#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068) -#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070) -#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070) -#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080) -#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084) -#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088) -#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c) -#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090) -#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094) -#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098) -#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c) -#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0) -#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4) -#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8) -#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000) -#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400) - - -#endif /* _IXP2000_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h deleted file mode 100644 index 5f0c4fd4076a..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/memory.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/memory.h - * - * Copyright (c) 2002 Intel Corp. - * Copyright (c) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#define PLAT_PHYS_OFFSET UL(0x00000000) - -#include <mach/ixp2000-regs.h> - -#define IXP2000_PCI_SDRAM_OFFSET (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0) - -#define __phys_to_bus(x) ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) -#define __bus_to_phys(x) ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) - -#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) -#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) -#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) -#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) - -#endif - diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h deleted file mode 100644 index bb0f8dcf9ee1..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/platform.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/platform.h - * - * Various bits of code used by platform-level code. - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - - -#ifndef __ASSEMBLY__ - -static inline unsigned long ixp2000_reg_read(volatile void *reg) -{ - return *((volatile unsigned long *)reg); -} - -static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) -{ - *((volatile unsigned long *)reg) = val; -} - -/* - * On the IXP2400, we can't use XCB=000 due to chip bugs. We use - * XCB=101 instead, but that makes all I/O accesses bufferable. This - * is not a problem in general, but we do have to be slightly more - * careful because I/O writes are no longer automatically flushed out - * of the write buffer. - * - * In cases where we want to make sure that a write has been flushed - * out of the write buffer before we proceed, for example when masking - * a device interrupt before re-enabling IRQs in CPSR, we can use this - * function, ixp2000_reg_wrb, which performs a write, a readback, and - * issues a dummy instruction dependent on the value of the readback - * (mov rX, rX) to make sure that the readback has completed before we - * continue. - */ -static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) -{ - unsigned long dummy; - - *((volatile unsigned long *)reg) = val; - - dummy = *((volatile unsigned long *)reg); - __asm__ __volatile__("mov %0, %0" : "+r" (dummy)); -} - -/* - * Boards may multiplex different devices on the 2nd channel of - * the slowport interface that each need different configuration - * settings. For example, the IXDP2400 uses channel 2 on the interface - * to access the CPLD, the switch fabric card, and the media card. Each - * one needs a different mode so drivers must save/restore the mode - * before and after each operation. - * - * acquire_slowport(&your_config); - * ... - * do slowport operations - * ... - * release_slowport(); - * - * Note that while you have the slowport, you are holding a spinlock, - * so your code should be written as if you explicitly acquired a lock. - * - * The configuration only affects device 2 on the slowport, so the - * MTD map driver does not acquire/release the slowport. - */ -struct slowport_cfg { - unsigned long CCR; /* Clock divide */ - unsigned long WTC; /* Write Timing Control */ - unsigned long RTC; /* Read Timing Control */ - unsigned long PCR; /* Protocol Control Register */ - unsigned long ADC; /* Address/Data Width Control */ -}; - - -void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *); -void ixp2000_release_slowport(struct slowport_cfg *); - -/* - * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires - * tweaking of addresses in the MTD driver. - */ -static inline unsigned ixp2000_has_broken_slowport(void) -{ - unsigned long id = *IXP2000_PRODUCT_ID; - unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK | - IXP2000_MIN_PROD_TYPE_MASK); - return (((id_prod == - /* fixed in IXP2400-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2400)) && - ((id & IXP2000_MAJ_REV_MASK) == 0)) || - ((id_prod == - /* fixed in IXP2800-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2800)) && - ((id & IXP2000_MAJ_REV_MASK) == 0)) || - ((id_prod == - /* fixed in IXP2850-B0 */ - (IXP2000_MAJ_PROD_TYPE_IXP2000 | - IXP2000_MIN_PROD_TYPE_IXP2850)) && - ((id & IXP2000_MAJ_REV_MASK) == 0))); -} - -static inline unsigned int ixp2000_has_flash(void) -{ - return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM)); -} - -static inline unsigned int ixp2000_is_pcimaster(void) -{ - return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST)); -} - -void ixp2000_map_io(void); -void ixp2000_uart_init(void); -void ixp2000_init_irq(void); -void ixp2000_init_time(unsigned long); -void ixp2000_restart(char, const char *); -unsigned long ixp2000_gettimeoffset(void); - -struct pci_sys_data; - -u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where); -void ixp2000_pci_preinit(void); -int ixp2000_pci_setup(int, struct pci_sys_data*); -struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*); -int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *); -int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32); - -/* - * Several of the IXP2000 systems have banked flash so we need to extend the - * flash_platform_data structure with some private pointers - */ -struct ixp2000_flash_data { - struct flash_platform_data *platform_data; - int nr_banks; - unsigned long (*bank_setup)(unsigned long); -}; - -struct ixp2000_i2c_pins { - unsigned long sda_pin; - unsigned long scl_pin; -}; - - -#endif /* !__ASSEMBLY__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h deleted file mode 100644 index 835e659f93d4..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/timex.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/timex.h - * - * IXP2000 architecture timex specifications - */ - - -/* - * Default clock is 50MHz APB, but platform code can override this - */ -#define CLOCK_TICK_RATE 50000000 - - diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h deleted file mode 100644 index ce363087df78..000000000000 --- a/arch/arm/mach-ixp2000/include/mach/uncompress.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-ixp2000/include/mach/uncompress.h - * - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2002 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/serial_reg.h> - -#define UART_BASE 0xc0030000 - -#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x)) - -#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */ -#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/ -#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/ -#define UARTIER PHYS(0x04) /* Interrupt enable reg */ -#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/ -#define UARTLCR PHYS(0x0c) /* Control reg */ -#define UARTSR PHYS(0x14) /* Status reg */ - - -static inline void putc(int c) -{ - int j = 0x1000; - - while (--j && !(*UARTSR & UART_LSR_THRE)) - barrier(); - - *UARTDR = c; -} - -static inline void flush(void) -{ -} - -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c deleted file mode 100644 index 915ad49e3b8f..000000000000 --- a/arch/arm/mach-ixp2000/ixdp2400.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * arch/arm/mach-ixp2000/ixdp2400.c - * - * IXDP2400 platform support - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/device.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/flash.h> -#include <asm/mach/arch.h> - -/************************************************************************* - * IXDP2400 timer tick - *************************************************************************/ -static void __init ixdp2400_timer_init(void) -{ - int numerator, denominator; - int denom_array[] = {2, 4, 8, 16, 1, 2, 4, 8}; - - numerator = (*(IXDP2400_CPLD_SYS_CLK_M) & 0xFF) *2; - denominator = denom_array[(*(IXDP2400_CPLD_SYS_CLK_N) & 0x7)]; - - ixp2000_init_time(((3125000 * numerator) / (denominator)) / 2); -} - -static struct sys_timer ixdp2400_timer = { - .init = ixdp2400_timer_init, - .offset = ixp2000_gettimeoffset, -}; - -/************************************************************************* - * IXDP2400 PCI - *************************************************************************/ -void __init ixdp2400_pci_preinit(void) -{ - ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000); - ixp2000_pci_preinit(); - pcibios_setup("firmware"); -} - -int ixdp2400_pci_setup(int nr, struct pci_sys_data *sys) -{ - sys->mem_offset = 0xe0000000; - - ixp2000_pci_setup(nr, sys); - - return 1; -} - -static int __init ixdp2400_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - if (ixdp2x00_master_npu()) { - - /* - * Root bus devices. Slave NPU is only one with interrupt. - * Everything else, we just return -1 b/c nothing else - * on the root bus has interrupts. - */ - if(!dev->bus->self) { - if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN ) - return IRQ_IXDP2400_INGRESS_NPU; - - return -1; - } - - /* - * Bridge behind the PMC slot. - * NOTE: Only INTA from the PMC slot is routed. VERY BAD. - */ - if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN && - dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN && - !dev->bus->parent->self->bus->parent) - return IRQ_IXDP2400_PMC; - - /* - * Device behind the first bridge - */ - if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) { - switch(dev->devfn) { - case IXDP2400_MASTER_ENET_DEVFN: - return IRQ_IXDP2400_ENET; - - case IXDP2400_MEDIA_DEVFN: - return IRQ_IXDP2400_MEDIA_PCI; - - case IXDP2400_SWITCH_FABRIC_DEVFN: - return IRQ_IXDP2400_SF_PCI; - - case IXDP2X00_PMC_DEVFN: - return IRQ_IXDP2400_PMC; - } - } - - return -1; - } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */ -} - - -static void ixdp2400_pci_postinit(void) -{ - struct pci_dev *dev; - - if (ixdp2x00_master_npu()) { - dev = pci_get_bus_and_slot(1, IXDP2400_SLAVE_ENET_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - } else { - dev = pci_get_bus_and_slot(1, IXDP2400_MASTER_ENET_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - - ixdp2x00_slave_pci_postinit(); - } -} - -static struct hw_pci ixdp2400_pci __initdata = { - .nr_controllers = 1, - .setup = ixdp2400_pci_setup, - .preinit = ixdp2400_pci_preinit, - .postinit = ixdp2400_pci_postinit, - .scan = ixp2000_pci_scan_bus, - .map_irq = ixdp2400_pci_map_irq, -}; - -int __init ixdp2400_pci_init(void) -{ - if (machine_is_ixdp2400()) - pci_common_init(&ixdp2400_pci); - - return 0; -} - -subsys_initcall(ixdp2400_pci_init); - -void __init ixdp2400_init_irq(void) -{ - ixdp2x00_init_irq(IXDP2400_CPLD_INT_STAT, IXDP2400_CPLD_INT_MASK, IXDP2400_NR_IRQS); -} - -MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x00_map_io, - .init_irq = ixdp2400_init_irq, - .timer = &ixdp2400_timer, - .init_machine = ixdp2x00_init_machine, - .restart = ixp2000_restart, -MACHINE_END - diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c deleted file mode 100644 index a9f1819ea049..000000000000 --- a/arch/arm/mach-ixp2000/ixdp2800.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * arch/arm/mach-ixp2000/ixdp2800.c - * - * IXDP2800 platform support - * - * Original Author: Jeffrey Daly <jeffrey.daly@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/device.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/flash.h> -#include <asm/mach/arch.h> - -/************************************************************************* - * IXDP2800 timer tick - *************************************************************************/ - -static void __init ixdp2800_timer_init(void) -{ - ixp2000_init_time(50000000); -} - -static struct sys_timer ixdp2800_timer = { - .init = ixdp2800_timer_init, - .offset = ixp2000_gettimeoffset, -}; - -/************************************************************************* - * IXDP2800 PCI - *************************************************************************/ -static void __init ixdp2800_slave_disable_pci_master(void) -{ - *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -} - -static void __init ixdp2800_master_wait_for_slave(void) -{ - volatile u32 *addr; - - printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure " - "its BAR sizes\n"); - - addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, - PCI_BASE_ADDRESS_1); - do { - *addr = 0xffffffff; - cpu_relax(); - } while (*addr != 0xfe000008); - - addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, - PCI_BASE_ADDRESS_2); - do { - *addr = 0xffffffff; - cpu_relax(); - } while (*addr != 0xc0000008); - - /* - * Configure the slave's SDRAM BAR by hand. - */ - *addr = 0x40000008; -} - -static void __init ixdp2800_slave_wait_for_master_enable(void) -{ - printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n"); - - while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0) - cpu_relax(); -} - -void __init ixdp2800_pci_preinit(void) -{ - printk("ixdp2x00_pci_preinit called\n"); - - *IXP2000_PCI_ADDR_EXT = 0x0001e000; - - if (!ixdp2x00_master_npu()) - ixdp2800_slave_disable_pci_master(); - - *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff; - *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff; - - ixp2000_pci_preinit(); - - if (ixdp2x00_master_npu()) { - /* - * Wait until the slave set its SRAM/SDRAM BAR sizes - * correctly before we proceed to scan and enumerate - * the bus. - */ - ixdp2800_master_wait_for_slave(); - - /* - * We configure the SDRAM BARs by hand because they - * are 1G and fall outside of the regular allocated - * PCI address space. - */ - *IXP2000_PCI_SDRAM_BAR = 0x00000008; - } else { - /* - * Wait for the master to complete scanning the bus - * and assigning resources before we proceed to scan - * the bus ourselves. Set pci=firmware to honor the - * master's resource assignment. - */ - ixdp2800_slave_wait_for_master_enable(); - pcibios_setup("firmware"); - } -} - -/* - * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside - * of the regular PCI window, because there's only 512M of outbound PCI - * memory window on each IXP, while we need 1G for each of the BARs. - */ -static void __devinit ixp2800_pci_fixup(struct pci_dev *dev) -{ - if (machine_is_ixdp2800()) { - dev->resource[2].start = 0; - dev->resource[2].end = 0; - dev->resource[2].flags = 0; - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup); - -static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys) -{ - sys->mem_offset = 0x00000000; - - ixp2000_pci_setup(nr, sys); - - return 1; -} - -static int __init ixdp2800_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - if (ixdp2x00_master_npu()) { - - /* - * Root bus devices. Slave NPU is only one with interrupt. - * Everything else, we just return -1 which is invalid. - */ - if(!dev->bus->self) { - if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN ) - return IRQ_IXDP2800_INGRESS_NPU; - - return -1; - } - - /* - * Bridge behind the PMC slot. - */ - if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN && - dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN && - !dev->bus->parent->self->bus->parent) - return IRQ_IXDP2800_PMC; - - /* - * Device behind the first bridge - */ - if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) { - switch(dev->devfn) { - case IXDP2X00_PMC_DEVFN: - return IRQ_IXDP2800_PMC; - - case IXDP2800_MASTER_ENET_DEVFN: - return IRQ_IXDP2800_EGRESS_ENET; - - case IXDP2800_SWITCH_FABRIC_DEVFN: - return IRQ_IXDP2800_FABRIC; - } - } - - return -1; - } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */ -} - -static void __init ixdp2800_master_enable_slave(void) -{ - volatile u32 *addr; - - printk(KERN_INFO "IXDP2800: enabling slave NPU\n"); - - addr = (volatile u32 *)ixp2000_pci_config_addr(0, - IXDP2X00_SLAVE_NPU_DEVFN, - PCI_COMMAND); - - *addr |= PCI_COMMAND_MASTER; -} - -static void __init ixdp2800_master_wait_for_slave_bus_scan(void) -{ - volatile u32 *addr; - - printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n"); - - addr = (volatile u32 *)ixp2000_pci_config_addr(0, - IXDP2X00_SLAVE_NPU_DEVFN, - PCI_COMMAND); - while ((*addr & PCI_COMMAND_MEMORY) == 0) - cpu_relax(); -} - -static void __init ixdp2800_slave_signal_bus_scan_completion(void) -{ - printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n"); - *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY; -} - -static void __init ixdp2800_pci_postinit(void) -{ - if (!ixdp2x00_master_npu()) { - ixdp2x00_slave_pci_postinit(); - ixdp2800_slave_signal_bus_scan_completion(); - } -} - -struct __initdata hw_pci ixdp2800_pci __initdata = { - .nr_controllers = 1, - .setup = ixdp2800_pci_setup, - .preinit = ixdp2800_pci_preinit, - .postinit = ixdp2800_pci_postinit, - .scan = ixp2000_pci_scan_bus, - .map_irq = ixdp2800_pci_map_irq, -}; - -int __init ixdp2800_pci_init(void) -{ - if (machine_is_ixdp2800()) { - struct pci_dev *dev; - - pci_common_init(&ixdp2800_pci); - if (ixdp2x00_master_npu()) { - dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - - ixdp2800_master_enable_slave(); - ixdp2800_master_wait_for_slave_bus_scan(); - } else { - dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - } - } - - return 0; -} - -subsys_initcall(ixdp2800_pci_init); - -void __init ixdp2800_init_irq(void) -{ - ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS); -} - -MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x00_map_io, - .init_irq = ixdp2800_init_irq, - .timer = &ixdp2800_timer, - .init_machine = ixdp2x00_init_machine, - .restart = ixp2000_restart, -MACHINE_END - diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c deleted file mode 100644 index 421e38dc0fac..000000000000 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * arch/arm/mach-ixp2000/ixdp2x00.c - * - * Code common to IXDP2400 and IXDP2800 platforms. - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/flash.h> -#include <asm/mach/arch.h> - -#include <mach/gpio-ixp2000.h> - -/************************************************************************* - * IXDP2x00 IRQ Initialization - *************************************************************************/ -static volatile unsigned long *board_irq_mask; -static volatile unsigned long *board_irq_stat; -static unsigned long board_irq_count; - -#ifdef CONFIG_ARCH_IXDP2400 -/* - * Slowport configuration for accessing CPLD registers on IXDP2x00 - */ -static struct slowport_cfg slowport_cpld_cfg = { - .CCR = SLOWPORT_CCR_DIV_2, - .WTC = 0x00000070, - .RTC = 0x00000070, - .PCR = SLOWPORT_MODE_FLASH, - .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8 -}; -#endif - -static void ixdp2x00_irq_mask(struct irq_data *d) -{ - unsigned long dummy; - static struct slowport_cfg old_cfg; - - /* - * This is ugly in common code but really don't know - * of a better way to handle it. :( - */ -#ifdef CONFIG_ARCH_IXDP2400 - if (machine_is_ixdp2400()) - ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); -#endif - - dummy = *board_irq_mask; - dummy |= IXP2000_BOARD_IRQ_MASK(d->irq); - ixp2000_reg_wrb(board_irq_mask, dummy); - -#ifdef CONFIG_ARCH_IXDP2400 - if (machine_is_ixdp2400()) - ixp2000_release_slowport(&old_cfg); -#endif -} - -static void ixdp2x00_irq_unmask(struct irq_data *d) -{ - unsigned long dummy; - static struct slowport_cfg old_cfg; - -#ifdef CONFIG_ARCH_IXDP2400 - if (machine_is_ixdp2400()) - ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); -#endif - - dummy = *board_irq_mask; - dummy &= ~IXP2000_BOARD_IRQ_MASK(d->irq); - ixp2000_reg_wrb(board_irq_mask, dummy); - - if (machine_is_ixdp2400()) - ixp2000_release_slowport(&old_cfg); -} - -static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - volatile u32 ex_interrupt = 0; - static struct slowport_cfg old_cfg; - int i; - - desc->irq_data.chip->irq_mask(&desc->irq_data); - -#ifdef CONFIG_ARCH_IXDP2400 - if (machine_is_ixdp2400()) - ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); -#endif - ex_interrupt = *board_irq_stat & 0xff; - if (machine_is_ixdp2400()) - ixp2000_release_slowport(&old_cfg); - - if(!ex_interrupt) { - printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n"); - return; - } - - for(i = 0; i < board_irq_count; i++) { - if(ex_interrupt & (1 << i)) { - int cpld_irq = IXP2000_BOARD_IRQ(0) + i; - generic_handle_irq(cpld_irq); - } - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixdp2x00_cpld_irq_chip = { - .irq_ack = ixdp2x00_irq_mask, - .irq_mask = ixdp2x00_irq_mask, - .irq_unmask = ixdp2x00_irq_unmask -}; - -void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs) -{ - unsigned int irq; - - ixp2000_init_irq(); - - if (!ixdp2x00_master_npu()) - return; - - board_irq_stat = stat_reg; - board_irq_mask = mask_reg; - board_irq_count = nr_of_irqs; - - *board_irq_mask = 0xffffffff; - - for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { - irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - /* Hook into PCI interrupt */ - irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); -} - -/************************************************************************* - * IXDP2x00 memory map - *************************************************************************/ -static struct map_desc ixdp2x00_io_desc __initdata = { - .virtual = IXDP2X00_VIRT_CPLD_BASE, - .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE), - .length = IXDP2X00_CPLD_SIZE, - .type = MT_DEVICE -}; - -void __init ixdp2x00_map_io(void) -{ - ixp2000_map_io(); - - iotable_init(&ixdp2x00_io_desc, 1); -} - -/************************************************************************* - * IXDP2x00-common PCI init - * - * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board - * contains two NPUs (ingress and egress) connected over PCI, both running - * instances of the kernel. So far so good. Peers on the PCI bus running - * Linux is a common design in telecom systems. The problem is that instead - * of all the devices being controlled by a single host, different - * devices are controlled by different NPUs on the same bus, leading to - * multiple hosts on the bus. The exact bus layout looks like: - * - * Bus 0 - * Master NPU <-------------------+-------------------> Slave NPU - * | - * | - * P2P - * | - * - * Bus 1 | - * <--+------+---------+---------+------+--> - * | | | | | - * | | | | | - * ... Dev PMC Media Eth0 Eth1 ... - * - * The master controls all but Eth1, which is controlled by the - * slave. What this means is that the both the master and the slave - * have to scan the bus, but only one of them can enumerate the bus. - * In addition, after the bus is scanned, each kernel must remove - * the device(s) it does not control from the PCI dev list otherwise - * a driver on each NPU will try to manage it and we will have horrible - * conflicts. Oh..and the slave NPU needs to see the master NPU - * for Intel's drivers to work properly. Closed source drivers... - * - * The way we deal with this is fairly simple but ugly: - * - * 1) Let master scan and enumerate the bus completely. - * 2) Master deletes Eth1 from device list. - * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave) - * from device list. - * 4) Find HW designers and LART them. - * - * The boards also do not do normal PCI IRQ routing, or any sort of - * sensical swizzling, so we just need to check where on the bus a - * device sits and figure out to which CPLD pin the interrupt is routed. - * See ixdp2[48]00.c files. - * - *************************************************************************/ -void ixdp2x00_slave_pci_postinit(void) -{ - struct pci_dev *dev; - - /* - * Remove PMC device is there is one - */ - if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) { - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); - } - - dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN); - pci_stop_and_remove_bus_device(dev); - pci_dev_put(dev); -} - -/************************************************************************** - * IXDP2x00 Machine Setup - *************************************************************************/ -static struct flash_platform_data ixdp2x00_platform_data = { - .map_name = "cfi_probe", - .width = 1, -}; - -static struct ixp2000_flash_data ixdp2x00_flash_data = { - .platform_data = &ixdp2x00_platform_data, - .nr_banks = 1 -}; - -static struct resource ixdp2x00_flash_resource = { - .start = 0xc4000000, - .end = 0xc4000000 + 0x00ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2x00_flash = { - .name = "IXP2000-Flash", - .id = 0, - .dev = { - .platform_data = &ixdp2x00_flash_data, - }, - .num_resources = 1, - .resource = &ixdp2x00_flash_resource, -}; - -static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = { - .sda_pin = IXDP2X00_GPIO_SDA, - .scl_pin = IXDP2X00_GPIO_SCL, -}; - -static struct platform_device ixdp2x00_i2c_controller = { - .name = "IXP2000-I2C", - .id = 0, - .dev = { - .platform_data = &ixdp2x00_i2c_gpio_pins, - }, - .num_resources = 0 -}; - -static struct platform_device *ixdp2x00_devices[] __initdata = { - &ixdp2x00_flash, - &ixdp2x00_i2c_controller -}; - -void __init ixdp2x00_init_machine(void) -{ - gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1); - gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT); - - platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices)); - ixp2000_uart_init(); -} - diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c deleted file mode 100644 index 5196c39cdba4..000000000000 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ /dev/null @@ -1,483 +0,0 @@ -/* - * arch/arm/mach-ixp2000/ixdp2x01.c - * - * Code common to Intel IXDP2401 and IXDP2801 platforms - * - * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2002-2003 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/pci.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#include <asm/mach/pci.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach/flash.h> - -/************************************************************************* - * IXDP2x01 IRQ Handling - *************************************************************************/ -static void ixdp2x01_irq_mask(struct irq_data *d) -{ - ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG, - IXP2000_BOARD_IRQ_MASK(d->irq)); -} - -static void ixdp2x01_irq_unmask(struct irq_data *d) -{ - ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG, - IXP2000_BOARD_IRQ_MASK(d->irq)); -} - -static u32 valid_irq_mask; - -static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 ex_interrupt; - int i; - - desc->irq_data.chip->irq_mask(&desc->irq_data); - - ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask; - - if (!ex_interrupt) { - printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n"); - return; - } - - for (i = 0; i < IXP2000_BOARD_IRQS; i++) { - if (ex_interrupt & (1 << i)) { - int cpld_irq = IXP2000_BOARD_IRQ(0) + i; - generic_handle_irq(cpld_irq); - } - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixdp2x01_irq_chip = { - .irq_mask = ixdp2x01_irq_mask, - .irq_ack = ixdp2x01_irq_mask, - .irq_unmask = ixdp2x01_irq_unmask -}; - -/* - * We only do anything if we are the master NPU on the board. - * The slave NPU only has the ethernet chip going directly to - * the PCIB interrupt input. - */ -void __init ixdp2x01_init_irq(void) -{ - int irq = 0; - - /* initialize chip specific interrupts */ - ixp2000_init_irq(); - - if (machine_is_ixdp2401()) - valid_irq_mask = IXDP2401_VALID_IRQ_MASK; - else - valid_irq_mask = IXDP2801_VALID_IRQ_MASK; - - /* Mask all interrupts from CPLD, disable simulation */ - ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff); - ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0); - - for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { - if (irq & valid_irq_mask) { - irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } else { - set_irq_flags(irq, 0); - } - } - - /* Hook into PCI interrupts */ - irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); -} - - -/************************************************************************* - * IXDP2x01 memory map - *************************************************************************/ -static struct map_desc ixdp2x01_io_desc __initdata = { - .virtual = IXDP2X01_VIRT_CPLD_BASE, - .pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE), - .length = IXDP2X01_CPLD_REGION_SIZE, - .type = MT_DEVICE -}; - -static void __init ixdp2x01_map_io(void) -{ - ixp2000_map_io(); - iotable_init(&ixdp2x01_io_desc, 1); -} - - -/************************************************************************* - * IXDP2x01 serial ports - *************************************************************************/ -static struct plat_serial8250_port ixdp2x01_serial_port1[] = { - { - .mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE, - .membase = (char *)IXDP2X01_UART1_VIRT_BASE, - .irq = IRQ_IXDP2X01_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM32, - .regshift = 2, - .uartclk = IXDP2X01_UART_CLK, - }, - { } -}; - -static struct resource ixdp2x01_uart_resource1 = { - .start = IXDP2X01_UART1_PHYS_BASE, - .end = IXDP2X01_UART1_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2x01_serial_device1 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = ixdp2x01_serial_port1, - }, - .num_resources = 1, - .resource = &ixdp2x01_uart_resource1, -}; - -static struct plat_serial8250_port ixdp2x01_serial_port2[] = { - { - .mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE, - .membase = (char *)IXDP2X01_UART2_VIRT_BASE, - .irq = IRQ_IXDP2X01_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM32, - .regshift = 2, - .uartclk = IXDP2X01_UART_CLK, - }, - { } -}; - -static struct resource ixdp2x01_uart_resource2 = { - .start = IXDP2X01_UART2_PHYS_BASE, - .end = IXDP2X01_UART2_PHYS_BASE + 0xffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2x01_serial_device2 = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = ixdp2x01_serial_port2, - }, - .num_resources = 1, - .resource = &ixdp2x01_uart_resource2, -}; - -static void ixdp2x01_uart_init(void) -{ - platform_device_register(&ixdp2x01_serial_device1); - platform_device_register(&ixdp2x01_serial_device2); -} - - -/************************************************************************* - * IXDP2x01 timer tick configuration - *************************************************************************/ -static unsigned int ixdp2x01_clock; - -static int __init ixdp2x01_clock_setup(char *str) -{ - ixdp2x01_clock = simple_strtoul(str, NULL, 10); - - return 1; -} - -__setup("ixdp2x01_clock=", ixdp2x01_clock_setup); - -static void __init ixdp2x01_timer_init(void) -{ - if (!ixdp2x01_clock) - ixdp2x01_clock = 50000000; - - ixp2000_init_time(ixdp2x01_clock); -} - -static struct sys_timer ixdp2x01_timer = { - .init = ixdp2x01_timer_init, - .offset = ixp2000_gettimeoffset, -}; - -/************************************************************************* - * IXDP2x01 PCI - *************************************************************************/ -void __init ixdp2x01_pci_preinit(void) -{ - ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000); - ixp2000_pci_preinit(); - pcibios_setup("firmware"); -} - -#define DEVPIN(dev, pin) ((pin) | ((dev) << 3)) - -static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - u8 bus = dev->bus->number; - u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin); - struct pci_bus *tmp_bus = dev->bus; - - /* Primary bus, no interrupts here */ - if (bus == 0) { - return -1; - } - - /* Lookup first leaf in bus tree */ - while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) { - tmp_bus = tmp_bus->parent; - } - - /* Select between known bridges */ - switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) { - /* Device is located after first MB bridge */ - case 0x0008: - if (tmp_bus == dev->bus) { - /* Device is located directly after first MB bridge */ - switch (devpin) { - case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ - if (machine_is_ixdp2401()) - return IRQ_IXDP2401_INTA_82546; - return -1; - case DEVPIN(1, 2): /* Onboard 82546 ch 1 */ - if (machine_is_ixdp2401()) - return IRQ_IXDP2401_INTB_82546; - return -1; - case DEVPIN(0, 1): /* PMC INTA# */ - return IRQ_IXDP2X01_SPCI_PMC_INTA; - case DEVPIN(0, 2): /* PMC INTB# */ - return IRQ_IXDP2X01_SPCI_PMC_INTB; - case DEVPIN(0, 3): /* PMC INTC# */ - return IRQ_IXDP2X01_SPCI_PMC_INTC; - case DEVPIN(0, 4): /* PMC INTD# */ - return IRQ_IXDP2X01_SPCI_PMC_INTD; - } - } - break; - case 0x0010: - if (tmp_bus == dev->bus) { - /* Device is located directly after second MB bridge */ - /* Secondary bus of second bridge */ - switch (devpin) { - case DEVPIN(0, 1): /* DB#0 */ - return IRQ_IXDP2X01_SPCI_DB_0; - case DEVPIN(1, 1): /* DB#1 */ - return IRQ_IXDP2X01_SPCI_DB_1; - } - } else { - /* Device is located indirectly after second MB bridge */ - /* Not supported now */ - } - break; - } - - return -1; -} - - -static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys) -{ - sys->mem_offset = 0xe0000000; - - if (machine_is_ixdp2801() || machine_is_ixdp28x5()) - sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16); - - return ixp2000_pci_setup(nr, sys); -} - -struct hw_pci ixdp2x01_pci __initdata = { - .nr_controllers = 1, - .setup = ixdp2x01_pci_setup, - .preinit = ixdp2x01_pci_preinit, - .scan = ixp2000_pci_scan_bus, - .map_irq = ixdp2x01_pci_map_irq, -}; - -int __init ixdp2x01_pci_init(void) -{ - if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\ - machine_is_ixdp28x5()) - pci_common_init(&ixdp2x01_pci); - - return 0; -} - -subsys_initcall(ixdp2x01_pci_init); - -/************************************************************************* - * IXDP2x01 Machine Initialization - *************************************************************************/ -static struct flash_platform_data ixdp2x01_flash_platform_data = { - .map_name = "cfi_probe", - .width = 1, -}; - -static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs) -{ - ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG, - ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN)); - return (ofs & IXDP2X01_FLASH_WINDOW_MASK); -} - -static struct ixp2000_flash_data ixdp2x01_flash_data = { - .platform_data = &ixdp2x01_flash_platform_data, - .bank_setup = ixdp2x01_flash_bank_setup -}; - -static struct resource ixdp2x01_flash_resource = { - .start = 0xc4000000, - .end = 0xc4000000 + 0x01ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2x01_flash = { - .name = "IXP2000-Flash", - .id = 0, - .dev = { - .platform_data = &ixdp2x01_flash_data, - }, - .num_resources = 1, - .resource = &ixdp2x01_flash_resource, -}; - -static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = { - .sda_pin = IXDP2X01_GPIO_SDA, - .scl_pin = IXDP2X01_GPIO_SCL, -}; - -static struct platform_device ixdp2x01_i2c_controller = { - .name = "IXP2000-I2C", - .id = 0, - .dev = { - .platform_data = &ixdp2x01_i2c_gpio_pins, - }, - .num_resources = 0 -}; - -static struct platform_device *ixdp2x01_devices[] __initdata = { - &ixdp2x01_flash, - &ixdp2x01_i2c_controller -}; - -static void __init ixdp2x01_init_machine(void) -{ - ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG, - (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN)); - - ixdp2x01_flash_data.nr_banks = - ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1); - - platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices)); - ixp2000_uart_init(); - ixdp2x01_uart_init(); -} - -static void ixdp2401_restart(char mode, const char *cmd) -{ - /* - * Reset flash banking register so that we are pointing at - * RedBoot bank. - */ - ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, - ((0 >> IXDP2X01_FLASH_WINDOW_BITS) - | IXDP2X01_CPLD_FLASH_INTERN)); - ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff); - - ixp2000_restart(mode, cmd); -} - -static void ixdp280x_restart(char mode, const char *cmd) -{ - /* - * On IXDP2801 we need to write this magic sequence to the CPLD - * to cause a complete reset of the CPU and all external devices - * and move the flash bank register back to 0. - */ - unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; - - reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); - ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg); - ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000); - - ixp2000_restart(mode, cmd); -} - -#ifdef CONFIG_ARCH_IXDP2401 -MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x01_map_io, - .init_irq = ixdp2x01_init_irq, - .timer = &ixdp2x01_timer, - .init_machine = ixdp2x01_init_machine, - .restart = ixdp2401_restart, -MACHINE_END -#endif - -#ifdef CONFIG_ARCH_IXDP2801 -MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x01_map_io, - .init_irq = ixdp2x01_init_irq, - .timer = &ixdp2x01_timer, - .init_machine = ixdp2x01_init_machine, - .restart = ixdp280x_restart, -MACHINE_END - -/* - * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel - * changed the machine ID in the bootloader - */ -MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = ixdp2x01_map_io, - .init_irq = ixdp2x01_init_irq, - .timer = &ixdp2x01_timer, - .init_machine = ixdp2x01_init_machine, - .restart = ixdp280x_restart, -MACHINE_END -#endif - - diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c deleted file mode 100644 index 9c02de932fac..000000000000 --- a/arch/arm/mach-ixp2000/pci.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * arch/arm/mach-ixp2000/pci.c - * - * PCI routines for IXDP2400/IXDP2800 boards - * - * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Maintained by: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2002 Intel Corp. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <mach/hardware.h> - -#include <asm/mach/pci.h> - -static volatile int pci_master_aborts = 0; - -static int clear_master_aborts(void); - -u32 * -ixp2000_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where) -{ - u32 *paddress; - - if (PCI_SLOT(devfn) > 7) - return 0; - - /* Must be dword aligned */ - where &= ~3; - - /* - * For top bus, generate type 0, else type 1 - */ - if (!bus_nr) { - /* only bits[23:16] are used for IDSEL */ - paddress = (u32 *) (IXP2000_PCI_CFG0_VIRT_BASE - | (1 << (PCI_SLOT(devfn) + 16)) - | (PCI_FUNC(devfn) << 8) | where); - } else { - paddress = (u32 *) (IXP2000_PCI_CFG1_VIRT_BASE - | (bus_nr << 16) - | (PCI_SLOT(devfn) << 11) - | (PCI_FUNC(devfn) << 8) | where); - } - - return paddress; -} - -/* - * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. - * 0 and 3 are not valid indexes... - */ -static u32 bytemask[] = { - /*0*/ 0, - /*1*/ 0xff, - /*2*/ 0xffff, - /*3*/ 0, - /*4*/ 0xffffffff, -}; - - -int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - u32 n; - u32 *addr; - - n = where % 4; - - addr = ixp2000_pci_config_addr(bus->number, devfn, where); - if (!addr) - return PCIBIOS_DEVICE_NOT_FOUND; - - pci_master_aborts = 0; - *value = (*addr >> (8*n)) & bytemask[size]; - if (pci_master_aborts) { - pci_master_aborts = 0; - *value = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - return PCIBIOS_SUCCESSFUL; -} - -/* - * We don't do error checks by calling clear_master_aborts() b/c the - * assumption is that the caller did a read first to make sure a device - * exists. - */ -int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - u32 mask; - u32 *addr; - u32 temp; - - mask = ~(bytemask[size] << ((where % 0x4) * 8)); - addr = ixp2000_pci_config_addr(bus->number, devfn, where); - if (!addr) - return PCIBIOS_DEVICE_NOT_FOUND; - temp = (u32) (value) << ((where % 0x4) * 8); - *addr = (*addr & mask) | temp; - - clear_master_aborts(); - - return PCIBIOS_SUCCESSFUL; -} - - -static struct pci_ops ixp2000_pci_ops = { - .read = ixp2000_pci_read_config, - .write = ixp2000_pci_write_config -}; - -struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata) -{ - return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops, - sysdata, &sysdata->resources); -} - - -int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - - volatile u32 temp; - unsigned long flags; - - pci_master_aborts = 1; - - local_irq_save(flags); - temp = *(IXP2000_PCI_CONTROL); - if (temp & ((1 << 8) | (1 << 5))) { - ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp); - } - - temp = *(IXP2000_PCI_CMDSTAT); - if (temp & (1 << 29)) { - while (temp & (1 << 29)) { - ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp); - temp = *(IXP2000_PCI_CMDSTAT); - } - } - local_irq_restore(flags); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -int -clear_master_aborts(void) -{ - volatile u32 temp; - unsigned long flags; - - local_irq_save(flags); - temp = *(IXP2000_PCI_CONTROL); - if (temp & ((1 << 8) | (1 << 5))) { - ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp); - } - - temp = *(IXP2000_PCI_CMDSTAT); - if (temp & (1 << 29)) { - while (temp & (1 << 29)) { - ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp); - temp = *(IXP2000_PCI_CMDSTAT); - } - } - local_irq_restore(flags); - - return 0; -} - -void __init -ixp2000_pci_preinit(void) -{ - pci_set_flags(0); - - pcibios_min_io = 0; - pcibios_min_mem = 0; - -#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO - /* - * Configure the PCI unit to properly byteswap I/O transactions, - * and verify that it worked. - */ - ixp2000_reg_write(IXP2000_PCI_CONTROL, - (*IXP2000_PCI_CONTROL | PCI_CONTROL_IEE)); - - if ((*IXP2000_PCI_CONTROL & PCI_CONTROL_IEE) == 0) - panic("IXP2000: PCI I/O is broken on this ixp model, and " - "the needed workaround has not been configured in"); -#endif - - hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0, - "PCI config cycle to non-existent device"); -} - - -/* - * IXP2000 systems often have large resource requirements, so we just - * use our own resource space. - */ -static struct resource ixp2000_pci_mem_space = { - .start = 0xe0000000, - .end = 0xffffffff, - .flags = IORESOURCE_MEM, - .name = "PCI Mem Space" -}; - -static struct resource ixp2000_pci_io_space = { - .start = 0x00010000, - .end = 0x0001ffff, - .flags = IORESOURCE_IO, - .name = "PCI I/O Space" -}; - -int ixp2000_pci_setup(int nr, struct pci_sys_data *sys) -{ - if (nr >= 1) - return 0; - - pci_add_resource_offset(&sys->resources, - &ixp2000_pci_io_space, sys->io_offset); - pci_add_resource_offset(&sys->resources, - &ixp2000_pci_mem_space, sys->mem_offset); - - return 1; -} - diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig deleted file mode 100644 index 982670ec3866..000000000000 --- a/arch/arm/mach-ixp23xx/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if ARCH_IXP23XX - -config ARCH_SUPPORTS_BIG_ENDIAN - bool - default y - -menu "Intel IXP23xx Implementation Options" - -comment "IXP23xx Platforms" - -config MACH_ESPRESSO - bool "Support IP Fabrics Double Espresso platform" - help - -config MACH_IXDP2351 - bool "Support Intel IXDP2351 platform" - help - -config MACH_ROADRUNNER - bool "Support ADI RoadRunner platform" - help - -endmenu - -endif diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile deleted file mode 100644 index 288b371b6d03..000000000000 --- a/arch/arm/mach-ixp23xx/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for the linux kernel. -# -obj-y := core.o pci.o -obj-m := -obj-n := -obj- := - -obj-$(CONFIG_MACH_ESPRESSO) += espresso.o -obj-$(CONFIG_MACH_IXDP2351) += ixdp2351.o -obj-$(CONFIG_MACH_ROADRUNNER) += roadrunner.o diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot deleted file mode 100644 index 44fb4a717c3f..000000000000 --- a/arch/arm/mach-ixp23xx/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c deleted file mode 100644 index d34542425990..000000000000 --- a/arch/arm/mach-ixp23xx/core.c +++ /dev/null @@ -1,455 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/core.c - * - * Core routines for IXP23xx chips - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2005 (c) MontaVista Software, Inc. - * - * Based on 2.4 code Copyright 2004 (c) Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/serial_8250.h> -#include <linux/serial_core.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/time.h> -#include <linux/timex.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> -#include <asm/system_misc.h> - -#include <asm/mach/map.h> -#include <asm/mach/time.h> -#include <asm/mach/irq.h> -#include <asm/mach/arch.h> - - -/************************************************************************* - * Chip specific mappings shared by all IXP23xx systems - *************************************************************************/ -static struct map_desc ixp23xx_io_desc[] __initdata = { - { /* XSI-CPP CSRs */ - .virtual = IXP23XX_XSI2CPP_CSR_VIRT, - .pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS), - .length = IXP23XX_XSI2CPP_CSR_SIZE, - .type = MT_DEVICE, - }, { /* Expansion Bus Config */ - .virtual = IXP23XX_EXP_CFG_VIRT, - .pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS), - .length = IXP23XX_EXP_CFG_SIZE, - .type = MT_DEVICE, - }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */ - .virtual = IXP23XX_PERIPHERAL_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS), - .length = IXP23XX_PERIPHERAL_SIZE, - .type = MT_DEVICE, - }, { /* CAP CSRs */ - .virtual = IXP23XX_CAP_CSR_VIRT, - .pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS), - .length = IXP23XX_CAP_CSR_SIZE, - .type = MT_DEVICE, - }, { /* MSF CSRs */ - .virtual = IXP23XX_MSF_CSR_VIRT, - .pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS), - .length = IXP23XX_MSF_CSR_SIZE, - .type = MT_DEVICE, - }, { /* PCI I/O Space */ - .virtual = IXP23XX_PCI_IO_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS), - .length = IXP23XX_PCI_IO_SIZE, - .type = MT_DEVICE, - }, { /* PCI Config Space */ - .virtual = IXP23XX_PCI_CFG_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS), - .length = IXP23XX_PCI_CFG_SIZE, - .type = MT_DEVICE, - }, { /* PCI local CFG CSRs */ - .virtual = IXP23XX_PCI_CREG_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS), - .length = IXP23XX_PCI_CREG_SIZE, - .type = MT_DEVICE, - }, { /* PCI MEM Space */ - .virtual = IXP23XX_PCI_MEM_VIRT, - .pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS), - .length = IXP23XX_PCI_MEM_SIZE, - .type = MT_DEVICE, - } -}; - -void __init ixp23xx_map_io(void) -{ - iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc)); -} - - -/*************************************************************************** - * IXP23xx Interrupt Handling - ***************************************************************************/ -enum ixp23xx_irq_type { - IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE -}; - -static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type); - -static int ixp23xx_irq_set_type(struct irq_data *d, unsigned int type) -{ - int line = d->irq - IRQ_IXP23XX_GPIO6 + 6; - u32 int_style; - enum ixp23xx_irq_type irq_type; - volatile u32 *int_reg; - - /* - * Only GPIOs 6-15 are wired to interrupts on IXP23xx - */ - if (line < 6 || line > 15) - return -EINVAL; - - switch (type) { - case IRQ_TYPE_EDGE_BOTH: - int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL; - irq_type = IXP23XX_IRQ_EDGE; - break; - case IRQ_TYPE_EDGE_RISING: - int_style = IXP23XX_GPIO_STYLE_RISING_EDGE; - irq_type = IXP23XX_IRQ_EDGE; - break; - case IRQ_TYPE_EDGE_FALLING: - int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE; - irq_type = IXP23XX_IRQ_EDGE; - break; - case IRQ_TYPE_LEVEL_HIGH: - int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH; - irq_type = IXP23XX_IRQ_LEVEL; - break; - case IRQ_TYPE_LEVEL_LOW: - int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW; - irq_type = IXP23XX_IRQ_LEVEL; - break; - default: - return -EINVAL; - } - - ixp23xx_config_irq(d->irq, irq_type); - - if (line >= 8) { /* pins 8-15 */ - line -= 8; - int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R; - } else { /* pins 0-7 */ - int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R; - } - - /* - * Clear pending interrupts - */ - *IXP23XX_GPIO_GPISR = (1 << line); - - /* Clear the style for the appropriate pin */ - *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK << - (line * IXP23XX_GPIO_STYLE_SIZE)); - - /* Set the new style */ - *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE)); - - return 0; -} - -static void ixp23xx_irq_mask(struct irq_data *d) -{ - volatile unsigned long *intr_reg; - unsigned int irq = d->irq; - - if (irq >= 56) - irq += 8; - - intr_reg = IXP23XX_INTR_EN1 + (irq / 32); - *intr_reg &= ~(1 << (irq % 32)); -} - -static void ixp23xx_irq_ack(struct irq_data *d) -{ - int line = d->irq - IRQ_IXP23XX_GPIO6 + 6; - - if ((line < 6) || (line > 15)) - return; - - *IXP23XX_GPIO_GPISR = (1 << line); -} - -/* - * Level triggered interrupts on GPIO lines can only be cleared when the - * interrupt condition disappears. - */ -static void ixp23xx_irq_level_unmask(struct irq_data *d) -{ - volatile unsigned long *intr_reg; - unsigned int irq = d->irq; - - ixp23xx_irq_ack(d); - - if (irq >= 56) - irq += 8; - - intr_reg = IXP23XX_INTR_EN1 + (irq / 32); - *intr_reg |= (1 << (irq % 32)); -} - -static void ixp23xx_irq_edge_unmask(struct irq_data *d) -{ - volatile unsigned long *intr_reg; - unsigned int irq = d->irq; - - if (irq >= 56) - irq += 8; - - intr_reg = IXP23XX_INTR_EN1 + (irq / 32); - *intr_reg |= (1 << (irq % 32)); -} - -static struct irq_chip ixp23xx_irq_level_chip = { - .irq_ack = ixp23xx_irq_mask, - .irq_mask = ixp23xx_irq_mask, - .irq_unmask = ixp23xx_irq_level_unmask, - .irq_set_type = ixp23xx_irq_set_type -}; - -static struct irq_chip ixp23xx_irq_edge_chip = { - .irq_ack = ixp23xx_irq_ack, - .irq_mask = ixp23xx_irq_mask, - .irq_unmask = ixp23xx_irq_edge_unmask, - .irq_set_type = ixp23xx_irq_set_type -}; - -static void ixp23xx_pci_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq)); -} - -static void ixp23xx_pci_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq; - - *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq)); -} - -/* - * TODO: Should this just be done at ASM level? - */ -static void pci_handler(unsigned int irq, struct irq_desc *desc) -{ - u32 pci_interrupt; - unsigned int irqno; - - pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS; - - desc->irq_data.chip->irq_ack(&desc->irq_data); - - /* See which PCI_INTA, or PCI_INTB interrupted */ - if (pci_interrupt & (1 << 26)) { - irqno = IRQ_IXP23XX_INTB; - } else if (pci_interrupt & (1 << 27)) { - irqno = IRQ_IXP23XX_INTA; - } else { - BUG(); - } - - generic_handle_irq(irqno); - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixp23xx_pci_irq_chip = { - .irq_ack = ixp23xx_pci_irq_mask, - .irq_mask = ixp23xx_pci_irq_mask, - .irq_unmask = ixp23xx_pci_irq_unmask -}; - -static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) -{ - switch (type) { - case IXP23XX_IRQ_LEVEL: - irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip, - handle_level_irq); - break; - case IXP23XX_IRQ_EDGE: - irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip, - handle_edge_irq); - break; - } - set_irq_flags(irq, IRQF_VALID); -} - -void __init ixp23xx_init_irq(void) -{ - int irq; - - /* Route everything to IRQ */ - *IXP23XX_INTR_SEL1 = 0x0; - *IXP23XX_INTR_SEL2 = 0x0; - *IXP23XX_INTR_SEL3 = 0x0; - *IXP23XX_INTR_SEL4 = 0x0; - - /* Mask all sources */ - *IXP23XX_INTR_EN1 = 0x0; - *IXP23XX_INTR_EN2 = 0x0; - *IXP23XX_INTR_EN3 = 0x0; - *IXP23XX_INTR_EN4 = 0x0; - - /* - * Configure all IRQs for level-sensitive operation - */ - for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) { - ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL); - } - - for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { - irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip, - handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); -} - - -/************************************************************************* - * Timer-tick functions for IXP23xx - *************************************************************************/ -#define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC) - -static unsigned long next_jiffy_time; - -static unsigned long -ixp23xx_gettimeoffset(void) -{ - unsigned long elapsed; - - elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH); - - return elapsed / CLOCK_TICKS_PER_USEC; -} - -static irqreturn_t -ixp23xx_timer_interrupt(int irq, void *dev_id) -{ - /* Clear Pending Interrupt by writing '1' to it */ - *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND; - while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) { - timer_tick(); - next_jiffy_time += LATCH; - } - - return IRQ_HANDLED; -} - -static struct irqaction ixp23xx_timer_irq = { - .name = "IXP23xx Timer Tick", - .handler = ixp23xx_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, -}; - -void __init ixp23xx_init_timer(void) -{ - /* Clear Pending Interrupt by writing '1' to it */ - *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND; - - /* Setup the Timer counter value */ - *IXP23XX_TIMER1_RELOAD = - (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE; - - *IXP23XX_TIMER_CONT = 0; - next_jiffy_time = LATCH; - - /* Connect the interrupt handler and enable the interrupt */ - setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq); -} - -struct sys_timer ixp23xx_timer = { - .init = ixp23xx_init_timer, - .offset = ixp23xx_gettimeoffset, -}; - - -/************************************************************************* - * IXP23xx Platform Initialization - *************************************************************************/ -static struct resource ixp23xx_uart_resources[] = { - { - .start = IXP23XX_UART1_PHYS, - .end = IXP23XX_UART1_PHYS + 0x0fff, - .flags = IORESOURCE_MEM - }, { - .start = IXP23XX_UART2_PHYS, - .end = IXP23XX_UART2_PHYS + 0x0fff, - .flags = IORESOURCE_MEM - } -}; - -static struct plat_serial8250_port ixp23xx_uart_data[] = { - { - .mapbase = IXP23XX_UART1_PHYS, - .membase = (char *)(IXP23XX_UART1_VIRT + 3), - .irq = IRQ_IXP23XX_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP23XX_UART_XTAL, - }, { - .mapbase = IXP23XX_UART2_PHYS, - .membase = (char *)(IXP23XX_UART2_VIRT + 3), - .irq = IRQ_IXP23XX_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP23XX_UART_XTAL, - }, - { }, -}; - -static struct platform_device ixp23xx_uart = { - .name = "serial8250", - .id = 0, - .dev.platform_data = ixp23xx_uart_data, - .num_resources = 2, - .resource = ixp23xx_uart_resources, -}; - -static struct platform_device *ixp23xx_devices[] __initdata = { - &ixp23xx_uart, -}; - -void __init ixp23xx_sys_init(void) -{ - /* by default, the idle code is disabled */ - disable_hlt(); - - *IXP23XX_EXP_UNIT_FUSE |= 0xf; - platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices)); -} - -void ixp23xx_restart(char mode, const char *cmd) -{ - /* Use on-chip reset capability */ - *IXP23XX_RESET0 |= IXP23XX_RST_ALL; -} diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c deleted file mode 100644 index d142d45dea12..000000000000 --- a/arch/arm/mach-ixp23xx/espresso.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/espresso.c - * - * Double Espresso-specific routines - * - * Author: Lennert Buytenhek <buytenh@wantstofly.org> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/ioport.h> -#include <linux/serial_8250.h> -#include <linux/serial_core.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/pci.h> -#include <linux/mtd/physmap.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/irq.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> - -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> - -static int __init espresso_pci_init(void) -{ - if (machine_is_espresso()) - ixp23xx_pci_slave_init(); - - return 0; -}; -subsys_initcall(espresso_pci_init); - -static struct physmap_flash_data espresso_flash_data = { - .width = 2, -}; - -static struct resource espresso_flash_resource = { - .start = 0x90000000, - .end = 0x91ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device espresso_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &espresso_flash_data, - }, - .num_resources = 1, - .resource = &espresso_flash_resource, -}; - -static void __init espresso_init(void) -{ - platform_device_register(&espresso_flash); - - /* - * Mark flash as writeable. - */ - IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE; - - ixp23xx_sys_init(); -} - -MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso") - /* Maintainer: Lennert Buytenhek */ - .map_io = ixp23xx_map_io, - .init_irq = ixp23xx_init_irq, - .timer = &ixp23xx_timer, - .atag_offset = 0x100, - .init_machine = espresso_init, - .restart = ixp23xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S deleted file mode 100644 index 5ff524c13744..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <mach/ixp23xx.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =IXP23XX_PERIPHERAL_PHYS @ physical - ldr \rv, =IXP23XX_PERIPHERAL_VIRT @ virtual -#ifdef __ARMEB__ - orr \rp, \rp, #0x00000003 - orr \rv, \rv, #0x00000003 -#endif - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S deleted file mode 100644 index 3fd2cb984e42..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/entry-macro.S - */ - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET) - ldr \irqnr, [\irqnr] @ get interrupt number - cmp \irqnr, #0x0 @ spurious interrupt ? - movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits - subne \irqnr, \irqnr, #1 @ convert to 0 based - -#if 0 - cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH - bne 1001f - mov \irqnr, #IRQ_IXP23XX_INTA - - ldr \irqnr, =0xf5000030 - - mov \tmp, #(1<<26) - tst \irqnr, \tmp - movne \irqnr, #IRQ_IXP23XX_INTB - - mov \tmp, #(1<<27) - tst \irqnr, \tmp - movne \irqnr, #IRQ_IXP23XX_INTA -1001: -#endif - .endm diff --git a/arch/arm/mach-ixp23xx/include/mach/hardware.h b/arch/arm/mach-ixp23xx/include/mach/hardware.h deleted file mode 100644 index 60e55fa10238..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/hardware.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/hardware.h - * - * Copyright (C) 2002-2004 Intel Corporation. - * Copyricht (C) 2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Hardware definitions for IXP23XX based systems - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* PCI IO info */ - -#include "ixp23xx.h" - -/* - * Platform helper functions - */ -#include "platform.h" - -/* - * Platform-specific headers - */ -#include "ixdp2351.h" - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h deleted file mode 100644 index a7aceb55c130..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/io.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/io.h - * - * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright (C) 2003-2005 Intel Corp. - * Copyright (C) 2005 MontaVista Software, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT)) - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/irqs.h b/arch/arm/mach-ixp23xx/include/mach/irqs.h deleted file mode 100644 index 3af33a04b8a2..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/irqs.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/irqs.h - * - * IRQ definitions for IXP23XX based systems - * - * Author: Naeem Afzal <naeem.m.afzal@intel.com> - * - * Copyright (C) 2003-2004 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1 -#define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS - - -#define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */ -#define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */ -#define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */ -#define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */ -#define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */ -#define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */ -#define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */ -#define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */ -#define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */ -#define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */ -#define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */ -#define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */ -#define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */ -#define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */ -#define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */ -#define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */ -#define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */ -#define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */ -#define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */ -#define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */ -#define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */ -#define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */ -#define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */ -#define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */ -#define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */ -#define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */ -#define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */ -#define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */ -#define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */ -#define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */ -#define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */ -#define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */ -#define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */ -#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */ -#define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */ -#define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */ -#define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */ -#define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */ -#define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */ -#define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */ -#define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */ -#define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */ -#define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */ -#define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */ -#define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */ -#define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */ -#define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */ -#define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */ -#define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */ -#define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */ - -#define NUM_IXP23XX_RAW_IRQS 120 - -#define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */ -#define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */ - -#define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1) - -/* - * We default to 32 per-board IRQs. Increase this number if you need - * more, but keep it realistic. - */ -#define NR_IXP23XX_MACH_IRQS 32 - -#define NR_IRQS (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS) - -#define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq)) - - -/* - * IXDP2351-specific interrupts - */ - -/* - * External PCI interrupts signaled through INTB - * - */ -#define IXDP2351_INTB_IRQ_BASE 0 -#define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0) -#define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1) -#define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2) -#define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3) -#define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4) -#define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5) -#define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6) -#define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7) -#define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8) - -#define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0)) -#define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq)) -#define IXDP2351_INTB_IRQ_VALID 0x01FF -#define IXDP2351_INTB_IRQ_NUM 16 - -/* - * Other external interrupts signaled through INTA - */ -#define IXDP2351_INTA_IRQ_BASE 16 -#define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16) -#define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17) -#define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18) -#define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19) -#define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20) -#define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21) -#define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24) -#define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25) -#define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26) -#define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27) -#define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28) -#define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29) -#define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30) -#define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31) - -#define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16)) -#define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq)) -#define IXDP2351_INTA_IRQ_VALID 0xFF3F -#define IXDP2351_INTA_IRQ_NUM 16 - - -/* - * ADI RoadRunner IRQs - */ -#define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA -#define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB -#define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11 -#define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12 - -/* - * Put new board definitions here - */ - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h b/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h deleted file mode 100644 index 663951027de5..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/ixdp2351.h - * - * Register and other defines for IXDP2351 - * - * Copyright (c) 2002-2004 Intel Corp. - * Copytight (c) 2005 MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_IXDP2351_H -#define __ASM_ARCH_IXDP2351_H - -/* - * NP module memory map - */ -#define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE) -#define IXDP2351_NP_PHYS_SIZE 0x00100000 -#define IXDP2351_NP_VIRT_BASE 0xeff00000 - -#define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE) -#define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16) - -#define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000) - -#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg)) - -#define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00) -#define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02) -#define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04) - -/* - * Base board module memory map - */ - -#define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE) -#define IXDP2351_BB_SIZE 0x01000000 -#define IXDP2351_BB_BASE_VIRT (0xee000000) - -#define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset) - -#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0) -#define IXDP2351_NVRAM_SIZE (0x20000) - -#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP2351_BB_AREA_BASE(0x00020000) -#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0) -#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000) -#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000) -#define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000) -#define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000) - -/* - * On board CPLD registers - */ -#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg)) - -#define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00) -#define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04) - -#define IXDP2351_CPLD_RESET1_MAGIC 0x55AA -#define IXDP2351_CPLD_RESET1_ENABLE 0x8000 - -#define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08) -#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10) -#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14) -#define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18) -#define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C) -#define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */ -#define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */ -#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */ -#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */ -#define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28) -#define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C) - /* Interrupt bits are defined in irqs.h */ -#define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30) -#define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34) - -/* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */ -/* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */ -/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */ -/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */ -/* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */ - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h deleted file mode 100644 index 6d02481b1d6d..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h +++ /dev/null @@ -1,298 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/ixp23xx.h - * - * Register definitions for IXP23XX - * - * Copyright (C) 2003-2005 Intel Corporation. - * Copyright (C) 2005 MontaVista Software, Inc. - * - * Maintainer: Deepak Saxena <dsaxena@plexity.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_IXP23XX_H -#define __ASM_ARCH_IXP23XX_H - -/* - * IXP2300 linux memory map: - * - * virt phys size - * fffd0000 a0000000 64K XSI2CPP_CSR - * fffc0000 c4000000 4K EXP_CFG - * fff00000 c8000000 64K PERIPHERAL - * fe000000 1c0000000 16M CAP_CSR - * fd000000 1c8000000 16M MSF_CSR - * fb000000 16M --- - * fa000000 1d8000000 32M PCI_IO - * f8000000 1da000000 32M PCI_CFG - * f6000000 1de000000 32M PCI_CREG - * f4000000 32M --- - * f0000000 1e0000000 64M PCI_MEM - * e[c-f]000000 per-platform mappings - */ - - -/**************************************************************************** - * Static mappings. - ****************************************************************************/ -#define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000 -#define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000 -#define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000 - -#define IXP23XX_EXP_CFG_PHYS 0xc4000000 -#define IXP23XX_EXP_CFG_VIRT 0xfffc0000 -#define IXP23XX_EXP_CFG_SIZE 0x00001000 - -#define IXP23XX_PERIPHERAL_PHYS 0xc8000000 -#define IXP23XX_PERIPHERAL_VIRT 0xfff00000 -#define IXP23XX_PERIPHERAL_SIZE 0x00010000 - -#define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL -#define IXP23XX_CAP_CSR_VIRT 0xfe000000 -#define IXP23XX_CAP_CSR_SIZE 0x01000000 - -#define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL -#define IXP23XX_MSF_CSR_VIRT 0xfd000000 -#define IXP23XX_MSF_CSR_SIZE 0x01000000 - -#define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL -#define IXP23XX_PCI_IO_VIRT 0xfa000000 -#define IXP23XX_PCI_IO_SIZE 0x02000000 - -#define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL -#define IXP23XX_PCI_CFG_VIRT 0xf8000000 -#define IXP23XX_PCI_CFG_SIZE 0x02000000 -#define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT -#define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000) - -#define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL -#define IXP23XX_PCI_CREG_VIRT 0xf6000000 -#define IXP23XX_PCI_CREG_SIZE 0x02000000 -#define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000) - -#define IXP23XX_PCI_MEM_START 0xe0000000 -#define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL -#define IXP23XX_PCI_MEM_VIRT 0xf0000000 -#define IXP23XX_PCI_MEM_SIZE 0x04000000 - - -/**************************************************************************** - * XSI2CPP CSRs. - ****************************************************************************/ -#define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x))) -#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8) -#define IXP23XX_CPP2XSI_ADDR_31 (1 << 19) -#define IXP23XX_CPP2XSI_PSH_OFF (1 << 20) -#define IXP23XX_CPP2XSI_COH_OFF (1 << 21) - - -/**************************************************************************** - * Expansion Bus Config. - ****************************************************************************/ -#define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x))) -#define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00) -#define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04) -#define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08) -#define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c) -#define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10) -#define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14) -#define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18) -#define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c) -#define IXP23XX_FLASH_WRITABLE (0x2) -#define IXP23XX_FLASH_BUS8 (0x1) - -#define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20) -#define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24) -#define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31) -#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22) -#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21) -#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19) -#define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18) -#define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16) -#define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14) -#define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13) -#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12) -#define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5) -#define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4) -#define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3) -#define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2) -#define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1) -#define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0) - -#define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28) -#define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30) -#define IXP23XX_EXP_CFG_FUSE IXP23XX_EXP_CFG_REG(0x34) - -#define IXP23XX_EXP_BUS_PHYS 0x90000000 -#define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000 - -#define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000) -#define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000) -#define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000) -#define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000) -#define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000) -#define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000) -#define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000) -#define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000) - - -/**************************************************************************** - * Peripherals. - ****************************************************************************/ -#define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000) -#define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000) -#define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000) -#define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000) -#define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000) -#define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000) -#define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000) -#define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000) -#define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000) -#define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000) -#define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000) -#define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000) -#define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000) -#define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000) - -#define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000) -#define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000) -#define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000) -#define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000) -#define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000) -#define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000) -#define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000) -#define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000) -#define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000) -#define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000) -#define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000) -#define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000) -#define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000) -#define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000) - - -/**************************************************************************** - * Interrupt controller. - ****************************************************************************/ -#define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x))) -#define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00) -#define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04) -#define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08) -#define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c) -#define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10) -#define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14) -#define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18) -#define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c) -#define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20) -#define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24) -#define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28) -#define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c) -#define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30) -#define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34) -#define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38) -#define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c) -#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54 - - -/**************************************************************************** - * GPIO. - ****************************************************************************/ -#define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x))) -#define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00) -#define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04) -#define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08) -#define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c) -#define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10) -#define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14) -#define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18) -#define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c) - -#define IXP23XX_GPIO_STYLE_MASK 0x7 -#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0 -#define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1 -#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2 -#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3 -#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4 - -#define IXP23XX_GPIO_STYLE_SIZE 3 - - -/**************************************************************************** - * Timer. - ****************************************************************************/ -#define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x))) -#define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00) -#define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04) -#define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08) -#define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c) -#define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10) -#define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14) -#define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18) -#define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c) -#define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e -#define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20) -#define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24) -#define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28) - -#define IXP23XX_TIMER_ENABLE (1 << 0) -#define IXP23XX_TIMER_ONE_SHOT (1 << 1) -/* Low order bits of reload value ignored */ -#define IXP23XX_TIMER_RELOAD_MASK (0x3) -#define IXP23XX_TIMER_DISABLED (0x0) -#define IXP23XX_TIMER1_INT_PEND (1 << 0) -#define IXP23XX_TIMER2_INT_PEND (1 << 1) -#define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2) -#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3) -#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4) - - -/**************************************************************************** - * CAP CSRs. - ****************************************************************************/ -#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x))) -#define IXP23XX_PRODUCT_ID IXP23XX_GLOBAL_REG(0x00) -#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04) -#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08) -#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c) -#define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10) -#define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18) - -#define IXP23XX_ENABLE_WATCHDOG (1 << 24) -#define IXP23XX_SHPC_INIT_COMP (1 << 21) -#define IXP23XX_RST_ALL (1 << 16) -#define IXP23XX_RESET_PCI (1 << 2) -#define IXP23XX_PCI_UNIT_RESET (1 << 1) -#define IXP23XX_XSCALE_RESET (1 << 0) - -#define IXP23XX_UENGINE_CSR_VIRT_BASE (IXP23XX_CAP_CSR_VIRT + 0x18000) - - -/**************************************************************************** - * PCI CSRs. - ****************************************************************************/ -#define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x))) -#define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04) -#define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14) -#define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18) - - -#define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x))) -#define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030) -#define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034) -#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc) -#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100) -#define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c) -#define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140) -#define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148) -#define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c) -#define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150) -#define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150) -#define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154) -#define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158) -#define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c) -#define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160) - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h deleted file mode 100644 index 6cf0704e946a..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/memory.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/memory.h - * - * Copyright (c) 2003-2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include <mach/hardware.h> - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET (0x00000000) - -#define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0) - -#define __phys_to_bus(x) ((x) + (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET)) -#define __bus_to_phys(x) ((x) - (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET)) - -#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) -#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) -#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) -#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) - -#define arch_is_coherent() 1 - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/platform.h b/arch/arm/mach-ixp23xx/include/mach/platform.h deleted file mode 100644 index 50de558e722e..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/platform.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/platform.h - * - * Various bits of code used by platform-level code. - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2005 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASSEMBLY__ - -static inline unsigned long ixp2000_reg_read(volatile void *reg) -{ - return *((volatile unsigned long *)reg); -} - -static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) -{ - *((volatile unsigned long *)reg) = val; -} - -static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) -{ - *((volatile unsigned long *)reg) = val; -} - -struct pci_sys_data; - -void ixp23xx_map_io(void); -void ixp23xx_init_irq(void); -void ixp23xx_sys_init(void); -void ixp23xx_restart(char, const char *); -int ixp23xx_pci_setup(int, struct pci_sys_data *); -void ixp23xx_pci_preinit(void); -struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); -void ixp23xx_pci_slave_init(void); - -extern struct sys_timer ixp23xx_timer; - -#define IXP23XX_UART_XTAL 14745600 - -#ifndef __ASSEMBLY__ -/* - * Is system memory on the XSI or CPP bus? - */ -static inline unsigned ixp23xx_cpp_boot(void) -{ - return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES); -} -#endif - - -#endif diff --git a/arch/arm/mach-ixp23xx/include/mach/time.h b/arch/arm/mach-ixp23xx/include/mach/time.h deleted file mode 100644 index b61dafc884ac..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/time.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/time.h - */ diff --git a/arch/arm/mach-ixp23xx/include/mach/timex.h b/arch/arm/mach-ixp23xx/include/mach/timex.h deleted file mode 100644 index e341e9cf9c37..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/timex.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/timex.h - * - * XScale architecture timex specifications - */ - -#define CLOCK_TICK_RATE 75000000 diff --git a/arch/arm/mach-ixp23xx/include/mach/uncompress.h b/arch/arm/mach-ixp23xx/include/mach/uncompress.h deleted file mode 100644 index 8b4c358d2c04..000000000000 --- a/arch/arm/mach-ixp23xx/include/mach/uncompress.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/include/mach/uncompress.h - * - * Copyright (C) 2002-2004 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <mach/ixp23xx.h> -#include <linux/serial_reg.h> - -#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS) - -static inline void putc(char c) -{ - int j; - - for (j = 0; j < 0x1000; j++) { - if (UART_BASE[UART_LSR] & UART_LSR_THRE) - break; - barrier(); - } - - UART_BASE[UART_TX] = c; -} - -static inline void flush(void) -{ -} - -#define arch_decomp_setup() -#define arch_decomp_wdog() - - -#endif diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c deleted file mode 100644 index b0e07db5ceaf..000000000000 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/ixdp2351.c - * - * IXDP2351 board-specific routines - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2005 (c) MontaVista Software, Inc. - * - * Based on 2.4 code Copyright 2004 (c) Intel Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/ioport.h> -#include <linux/serial_8250.h> -#include <linux/serial_core.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/pci.h> -#include <linux/mtd/physmap.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> - -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> - -/* - * IXDP2351 Interrupt Handling - */ -static void ixdp2351_inta_mask(struct irq_data *d) -{ - *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(d->irq); -} - -static void ixdp2351_inta_unmask(struct irq_data *d) -{ - *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(d->irq); -} - -static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc) -{ - u16 ex_interrupt = - *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID; - int i; - - desc->irq_data.chip->irq_mask(&desc->irq_data); - - for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) { - if (ex_interrupt & (1 << i)) { - int cpld_irq = - IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i); - generic_handle_irq(cpld_irq); - } - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixdp2351_inta_chip = { - .irq_ack = ixdp2351_inta_mask, - .irq_mask = ixdp2351_inta_mask, - .irq_unmask = ixdp2351_inta_unmask -}; - -static void ixdp2351_intb_mask(struct irq_data *d) -{ - *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(d->irq); -} - -static void ixdp2351_intb_unmask(struct irq_data *d) -{ - *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(d->irq); -} - -static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc) -{ - u16 ex_interrupt = - *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID; - int i; - - desc->irq_data.chip->irq_ack(&desc->irq_data); - - for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) { - if (ex_interrupt & (1 << i)) { - int cpld_irq = - IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i); - generic_handle_irq(cpld_irq); - } - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -static struct irq_chip ixdp2351_intb_chip = { - .irq_ack = ixdp2351_intb_mask, - .irq_mask = ixdp2351_intb_mask, - .irq_unmask = ixdp2351_intb_unmask -}; - -void __init ixdp2351_init_irq(void) -{ - int irq; - - /* Mask all interrupts from CPLD, disable simulation */ - *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1; - *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1; - *IXDP2351_CPLD_INTA_SIM_REG = 0; - *IXDP2351_CPLD_INTB_SIM_REG = 0; - - ixp23xx_init_irq(); - - for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE); - irq < - IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM); - irq++) { - if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { - set_irq_flags(irq, IRQF_VALID); - irq_set_chip_and_handler(irq, &ixdp2351_inta_chip, - handle_level_irq); - } - } - - for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE); - irq < - IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM); - irq++) { - if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { - set_irq_flags(irq, IRQF_VALID); - irq_set_chip_and_handler(irq, &ixdp2351_intb_chip, - handle_level_irq); - } - } - - irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); - irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); -} - -/* - * IXDP2351 PCI - */ - -/* - * This board does not do normal PCI IRQ routing, or any - * sort of swizzling, so we just need to check where on the - * bus the device is and figure out what CPLD pin it is - * being routed to. - */ -#define DEVPIN(dev, pin) ((pin) | ((dev) << 3)) - -static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - u8 bus = dev->bus->number; - u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin); - struct pci_bus *tmp_bus = dev->bus; - - /* Primary bus, no interrupts here */ - if (!bus) - return -1; - - /* Lookup first leaf in bus tree */ - while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) - tmp_bus = tmp_bus->parent; - - /* Select between known bridges */ - switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) { - /* Device is located after first bridge */ - case 0x0008: - if (tmp_bus == dev->bus) { - /* Device is located directy after first bridge */ - switch (devpin) { - /* Onboard 82546 */ - case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ - return IRQ_IXDP2351_INTA_82546; - case DEVPIN(1, 2): /* Onboard 82546 ch 1 */ - return IRQ_IXDP2351_INTB_82546; - /* PMC SLOT */ - case DEVPIN(0, 1): /* PMCP INTA# */ - case DEVPIN(2, 4): /* PMCS INTD# */ - return IRQ_IXDP2351_SPCI_PMC_INTA; - case DEVPIN(0, 2): /* PMCP INTB# */ - case DEVPIN(2, 1): /* PMCS INTA# */ - return IRQ_IXDP2351_SPCI_PMC_INTB; - case DEVPIN(0, 3): /* PMCP INTC# */ - case DEVPIN(2, 2): /* PMCS INTB# */ - return IRQ_IXDP2351_SPCI_PMC_INTC; - case DEVPIN(0, 4): /* PMCP INTD# */ - case DEVPIN(2, 3): /* PMCS INTC# */ - return IRQ_IXDP2351_SPCI_PMC_INTD; - } - } else { - /* Device is located indirectly after first bridge */ - /* Not supported now */ - return -1; - } - break; - case 0x0010: - if (tmp_bus == dev->bus) { - /* Device is located directy after second bridge */ - /* Secondary bus of second bridge */ - switch (devpin) { - case DEVPIN(0, 1): /* DB#0 */ - case DEVPIN(0, 2): - case DEVPIN(0, 3): - case DEVPIN(0, 4): - return IRQ_IXDP2351_SPCI_DB_0; - case DEVPIN(1, 1): /* DB#1 */ - case DEVPIN(1, 2): - case DEVPIN(1, 3): - case DEVPIN(1, 4): - return IRQ_IXDP2351_SPCI_DB_1; - case DEVPIN(2, 1): /* FIC1 */ - case DEVPIN(2, 2): - case DEVPIN(2, 3): - case DEVPIN(2, 4): - case DEVPIN(3, 1): /* FIC2 */ - case DEVPIN(3, 2): - case DEVPIN(3, 3): - case DEVPIN(3, 4): - return IRQ_IXDP2351_SPCI_FIC; - } - } else { - /* Device is located indirectly after second bridge */ - /* Not supported now */ - return -1; - } - break; - } - - return -1; -} - -struct hw_pci ixdp2351_pci __initdata = { - .nr_controllers = 1, - .preinit = ixp23xx_pci_preinit, - .setup = ixp23xx_pci_setup, - .scan = ixp23xx_pci_scan_bus, - .map_irq = ixdp2351_map_irq, -}; - -int __init ixdp2351_pci_init(void) -{ - if (machine_is_ixdp2351()) - pci_common_init(&ixdp2351_pci); - - return 0; -} - -subsys_initcall(ixdp2351_pci_init); - -/* - * IXDP2351 Static Mapped I/O - */ -static struct map_desc ixdp2351_io_desc[] __initdata = { - { - .virtual = IXDP2351_NP_VIRT_BASE, - .pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE), - .length = IXDP2351_NP_PHYS_SIZE, - .type = MT_DEVICE - }, { - .virtual = IXDP2351_BB_BASE_VIRT, - .pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS), - .length = IXDP2351_BB_SIZE, - .type = MT_DEVICE - } -}; - -static void __init ixdp2351_map_io(void) -{ - ixp23xx_map_io(); - iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc)); -} - -static struct physmap_flash_data ixdp2351_flash_data = { - .width = 1, -}; - -static struct resource ixdp2351_flash_resource = { - .start = 0x90000000, - .end = 0x93ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ixdp2351_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ixdp2351_flash_data, - }, - .num_resources = 1, - .resource = &ixdp2351_flash_resource, -}; - -static void __init ixdp2351_init(void) -{ - platform_device_register(&ixdp2351_flash); - - /* - * Mark flash as writeable - */ - IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE; - - ixp23xx_sys_init(); -} - -static void ixdp2351_restart(char mode, const char *cmd) -{ - /* First try machine specific support */ - - *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC; - (void) *IXDP2351_CPLD_RESET1_REG; - *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE; - - ixp23xx_restart(mode, cmd); -} - -MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform") - /* Maintainer: MontaVista Software, Inc. */ - .map_io = ixdp2351_map_io, - .init_irq = ixdp2351_init_irq, - .timer = &ixp23xx_timer, - .atag_offset = 0x100, - .init_machine = ixdp2351_init, - .restart = ixdp2351_restart, -MACHINE_END diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c deleted file mode 100644 index 911f5a58e006..000000000000 --- a/arch/arm/mach-ixp23xx/pci.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/pci.c - * - * PCI routines for IXP23XX based systems - * - * Copyright (c) 2005 MontaVista Software, Inc. - * - * based on original code: - * - * Author: Naeem Afzal <naeem.m.afzal@intel.com> - * Copyright 2002-2005 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/sched.h> -#include <linux/kernel.h> -#include <linux/pci.h> -#include <linux/interrupt.h> -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/delay.h> -#include <linux/io.h> - -#include <asm/irq.h> -#include <asm/sizes.h> -#include <asm/mach/pci.h> -#include <mach/hardware.h> - -extern int (*external_fault) (unsigned long, struct pt_regs *); - -static volatile int pci_master_aborts = 0; - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -int clear_master_aborts(void); - -static u32 -*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where) -{ - u32 *paddress; - - /* - * Must be dword aligned - */ - where &= ~3; - - /* - * For top bus, generate type 0, else type 1 - */ - if (!bus_nr) { - if (PCI_SLOT(devfn) >= 8) - return 0; - - paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT - | (1 << (PCI_SLOT(devfn) + 16)) - | (PCI_FUNC(devfn) << 8) | where); - } else { - paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT - | (bus_nr << 16) - | (PCI_SLOT(devfn) << 11) - | (PCI_FUNC(devfn) << 8) | where); - } - - return paddress; -} - -/* - * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. - * 0 and 3 are not valid indexes... - */ -static u32 bytemask[] = { - /*0*/ 0, - /*1*/ 0xff, - /*2*/ 0xffff, - /*3*/ 0, - /*4*/ 0xffffffff, -}; - -static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *value) -{ - u32 n; - u32 *addr; - - n = where % 4; - - DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where, - bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - addr = ixp23xx_pci_config_addr(bus->number, devfn, where); - if (!addr) - return PCIBIOS_DEVICE_NOT_FOUND; - - pci_master_aborts = 0; - *value = (*addr >> (8*n)) & bytemask[size]; - if (pci_master_aborts) { - pci_master_aborts = 0; - *value = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - return PCIBIOS_SUCCESSFUL; -} - -/* - * We don't do error checking on the address for writes. - * It's assumed that the user checked for the device existing first - * by doing a read first. - */ -static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 value) -{ - u32 mask; - u32 *addr; - u32 temp; - - mask = ~(bytemask[size] << ((where % 0x4) * 8)); - addr = ixp23xx_pci_config_addr(bus->number, devfn, where); - if (!addr) - return PCIBIOS_DEVICE_NOT_FOUND; - temp = (u32) (value) << ((where % 0x4) * 8); - *addr = (*addr & mask) | temp; - - clear_master_aborts(); - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops ixp23xx_pci_ops = { - .read = ixp23xx_pci_read_config, - .write = ixp23xx_pci_write_config, -}; - -struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata) -{ - return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops, - sysdata, &sysdata->resources); -} - -int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - volatile unsigned long temp; - unsigned long flags; - - pci_master_aborts = 1; - - local_irq_save(flags); - temp = *IXP23XX_PCI_CONTROL; - - /* - * master abort and cmd tgt err - */ - if (temp & ((1 << 8) | (1 << 5))) - *IXP23XX_PCI_CONTROL = temp; - - temp = *IXP23XX_PCI_CMDSTAT; - - if (temp & (1 << 29)) - *IXP23XX_PCI_CMDSTAT = temp; - local_irq_restore(flags); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -int clear_master_aborts(void) -{ - volatile u32 temp; - - temp = *IXP23XX_PCI_CONTROL; - - /* - * master abort and cmd tgt err - */ - if (temp & ((1 << 8) | (1 << 5))) - *IXP23XX_PCI_CONTROL = temp; - - temp = *IXP23XX_PCI_CMDSTAT; - - if (temp & (1 << 29)) - *IXP23XX_PCI_CMDSTAT = temp; - - return 0; -} - -static void __init ixp23xx_pci_common_init(void) -{ -#ifdef __ARMEB__ - *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */ -#endif - /* - * ADDR_31 needs to be clear for PCI memory access to CPP memory - */ - *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31; - *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF; - - /* - * Select correct memory for PCI inbound transactions - */ - if (ixp23xx_cpp_boot()) { - *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1); - } else { - *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1); - - /* - * Enable coherency on A2 silicon. - */ - if (arch_is_coherent()) - *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF; - } -} - -void __init ixp23xx_pci_preinit(void) -{ - pcibios_min_io = 0; - pcibios_min_mem = 0xe0000000; - - pci_set_flags(0); - - ixp23xx_pci_common_init(); - - hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0, - "PCI config cycle to non-existent device"); - - *IXP23XX_PCI_ADDR_EXT = 0x0000e000; -} - -/* - * Prevent PCI layer from seeing the inbound host-bridge resources - */ -static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev) -{ - int i; - - dev->class &= 0xff; - dev->class |= PCI_CLASS_BRIDGE_HOST << 8; - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx); - -/* - * IXP2300 systems often have large resource requirements, so we just - * use our own resource space. - */ -static struct resource ixp23xx_pci_mem_space = { - .start = IXP23XX_PCI_MEM_START, - .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM, - .name = "PCI Mem Space" -}; - -static struct resource ixp23xx_pci_io_space = { - .start = 0x00000100, - .end = 0x01ffffff, - .flags = IORESOURCE_IO, - .name = "PCI I/O Space" -}; - -int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys) -{ - if (nr >= 1) - return 0; - - pci_add_resource_offset(&sys->resources, - &ixp23xx_pci_io_space, sys->io_offset); - pci_add_resource_offset(&sys->resources, - &ixp23xx_pci_mem_space, sys->mem_offset); - - return 1; -} - -void __init ixp23xx_pci_slave_init(void) -{ - ixp23xx_pci_common_init(); -} diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c deleted file mode 100644 index eaaa3fa9fd05..000000000000 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * arch/arm/mach-ixp23xx/roadrunner.c - * - * RoadRunner board-specific routines - * - * Author: Deepak Saxena <dsaxena@plexity.net> - * - * Copyright 2005 (c) MontaVista Software, Inc. - * - * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/serial.h> -#include <linux/tty.h> -#include <linux/bitops.h> -#include <linux/ioport.h> -#include <linux/serial_8250.h> -#include <linux/serial_core.h> -#include <linux/device.h> -#include <linux/mm.h> -#include <linux/pci.h> -#include <linux/mtd/physmap.h> - -#include <asm/types.h> -#include <asm/setup.h> -#include <asm/memory.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> -#include <asm/irq.h> -#include <asm/tlbflush.h> -#include <asm/pgtable.h> - -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> - -/* - * Interrupt mapping - */ -#define INTA IRQ_ROADRUNNER_PCI_INTA -#define INTB IRQ_ROADRUNNER_PCI_INTB -#define INTC IRQ_ROADRUNNER_PCI_INTC -#define INTD IRQ_ROADRUNNER_PCI_INTD - -#define INTC_PIN IXP23XX_GPIO_PIN_11 -#define INTD_PIN IXP23XX_GPIO_PIN_12 - -static int __init roadrunner_map_irq(const struct pci_dev *dev, u8 idsel, - u8 pin) -{ - static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA}; - static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD}; - static int usb_irq[] = {INTB, INTC, INTD, -1}; - static int mini_pci_1_irq[] = {INTB, INTC, -1, -1}; - static int mini_pci_2_irq[] = {INTC, INTD, -1, -1}; - - switch(dev->bus->number) { - case 0: - switch(dev->devfn) { - case 0x0: // PCI-PCI bridge - break; - case 0x8: // PCI Card Slot - return pci_card_slot_irq[pin - 1]; - case 0x10: // PMC Slot - return pmc_card_slot_irq[pin - 1]; - case 0x18: // PMC Slot Secondary Agent - break; - case 0x20: // IXP Processor - break; - default: - return NO_IRQ; - } - break; - - case 1: - switch(dev->devfn) { - case 0x0: // IDE Controller - return (pin == 1) ? INTC : -1; - case 0x8: // USB fun 0 - case 0x9: // USB fun 1 - case 0xa: // USB fun 2 - return usb_irq[pin - 1]; - case 0x10: // Mini PCI 1 - return mini_pci_1_irq[pin-1]; - case 0x18: // Mini PCI 2 - return mini_pci_2_irq[pin-1]; - case 0x20: // MEM slot - return (pin == 1) ? INTA : -1; - default: - return NO_IRQ; - } - break; - - default: - return NO_IRQ; - } - - return NO_IRQ; -} - -static void __init roadrunner_pci_preinit(void) -{ - irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); - - ixp23xx_pci_preinit(); -} - -static struct hw_pci roadrunner_pci __initdata = { - .nr_controllers = 1, - .preinit = roadrunner_pci_preinit, - .setup = ixp23xx_pci_setup, - .scan = ixp23xx_pci_scan_bus, - .map_irq = roadrunner_map_irq, -}; - -static int __init roadrunner_pci_init(void) -{ - if (machine_is_roadrunner()) - pci_common_init(&roadrunner_pci); - - return 0; -}; - -subsys_initcall(roadrunner_pci_init); - -static struct physmap_flash_data roadrunner_flash_data = { - .width = 2, -}; - -static struct resource roadrunner_flash_resource = { - .start = 0x90000000, - .end = 0x93ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device roadrunner_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &roadrunner_flash_data, - }, - .num_resources = 1, - .resource = &roadrunner_flash_resource, -}; - -static void __init roadrunner_init(void) -{ - platform_device_register(&roadrunner_flash); - - /* - * Mark flash as writeable - */ - IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE; - IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE; - - ixp23xx_sys_init(); -} - -MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform") - /* Maintainer: Deepak Saxena */ - .map_io = ixp23xx_map_io, - .init_irq = ixp23xx_init_irq, - .timer = &ixp23xx_timer, - .atag_offset = 0x100, - .init_machine = roadrunner_init, - .restart = ixp23xx_restart, -MACHINE_END diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c index 3698a370d636..26aac363a064 100644 --- a/arch/arm/mach-msm/board-halibut.c +++ b/arch/arm/mach-msm/board-halibut.c @@ -86,9 +86,6 @@ static void __init halibut_init(void) static void __init halibut_fixup(struct tag *tags, char **cmdline, struct meminfo *mi) { - mi->nr_banks=1; - mi->bank[0].start = PHYS_OFFSET; - mi->bank[0].size = (101*1024*1024); } static void __init halibut_map_io(void) diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 962e71169750..fb3496a52ef4 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -17,6 +17,7 @@ #include <linux/irqdomain.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/memblock.h> @@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void) msm_map_msm8x60_io(); } +#ifdef CONFIG_OF +static struct of_device_id msm_dt_gic_match[] __initdata = { + { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init }, + {} +}; +#endif + static void __init msm8x60_init_irq(void) { - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, - (void *)MSM_QGIC_CPU_BASE); + if (!of_have_populated_dt()) + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); +#ifdef CONFIG_OF + else + of_irq_init(msm_dt_gic_match); +#endif /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); @@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { {} }; -static struct of_device_id msm_dt_gic_match[] __initdata = { - { .compatible = "qcom,msm-8660-qgic", }, - {} -}; - static void __init msm8x60_dt_init(void) { - irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS, - GIC_SPI_START); - if (of_machine_is_compatible("qcom,msm8660-surf")) { printk(KERN_INFO "Init surf UART registers\n"); msm8x60_init_uart12dm(); diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c index 25105c1027fe..89bf6b426699 100644 --- a/arch/arm/mach-msm/board-trout-panel.c +++ b/arch/arm/mach-msm/board-trout-panel.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <asm/mach-types.h> +#include <asm/system_info.h> #include <mach/msm_fb.h> #include <mach/vreg.h> diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c index 5414f76ec0a9..d4060a37e23d 100644 --- a/arch/arm/mach-msm/board-trout.c +++ b/arch/arm/mach-msm/board-trout.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/clkdev.h> +#include <asm/system_info.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c index 67e701c7f183..9980dc736e7b 100644 --- a/arch/arm/mach-msm/proc_comm.c +++ b/arch/arm/mach-msm/proc_comm.c @@ -121,7 +121,7 @@ int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2) * and unknown state. This function should be called early to * wait on the ARM9. */ -void __init proc_comm_boot_wait(void) +void __devinit proc_comm_boot_wait(void) { void __iomem *base = MSM_SHARED_RAM_BASE; diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 9923f92b5450..398e9e53e189 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -12,6 +12,9 @@ endif obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o +# OCPI interconnect support for 1710, 1610 and 5912 +obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o + # Power Management obj-$(CONFIG_PM) += pm.o sleep.o @@ -28,13 +31,15 @@ usb-fs-$(CONFIG_USB) := usb.o obj-y += $(usb-fs-m) $(usb-fs-y) # Specific board support -obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o +obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o \ + board-nand.o obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o -obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o -obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o +obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o board-nand.o +obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o board-nand.o obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o -obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o +obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o \ + board-nand.o obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c index fcce7ff37630..31197bd2dedc 100644 --- a/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/arch/arm/mach-omap1/ams-delta-fiq.c @@ -102,7 +102,7 @@ void __init ams_delta_init_fiq(void) } retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq, - IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0); + IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL); if (retval < 0) { pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval); release_fiq(&fh); diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 80bd43c7f4ec..4a4afb371022 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -185,20 +185,6 @@ static struct platform_device nor_device = { .resource = &nor_resource, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - #define FSAMPLE_NAND_RB_GPIO_PIN 62 static int nand_dev_ready(struct mtd_info *mtd) @@ -216,7 +202,7 @@ static struct platform_nand_data nand_data = { .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, }; diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 553a2e535764..057ec13f0649 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -179,20 +179,6 @@ static struct mtd_partition h2_nand_partitions[] = { }, }; -static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - #define H2_NAND_RB_GPIO_PIN 62 static int h2_nand_dev_ready(struct mtd_info *mtd) @@ -212,9 +198,8 @@ static struct platform_nand_data h2_nand_platdata = { .part_probe_types = h2_part_probes, }, .ctrl = { - .cmd_ctrl = h2_nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = h2_nand_dev_ready, - }, }; diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 4c19f4c06851..f6ddf8759657 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -181,20 +181,6 @@ static struct mtd_partition nand_partitions[] = { }, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - #define H3_NAND_RB_GPIO_PIN 10 static int nand_dev_ready(struct mtd_info *mtd) @@ -214,7 +200,7 @@ static struct platform_nand_data nand_platdata = { .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, diff --git a/arch/arm/mach-omap1/board-nand.c b/arch/arm/mach-omap1/board-nand.c new file mode 100644 index 000000000000..4d0835327d20 --- /dev/null +++ b/arch/arm/mach-omap1/board-nand.c @@ -0,0 +1,37 @@ +/* + * linux/arch/arm/mach-omap1/board-nand.c + * + * Common OMAP1 board NAND code + * + * Copyright (C) 2004, 2012 Texas Instruments, Inc. + * Copyright (C) 2002 MontaVista Software, Inc. + * Copyright (C) 2001 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> + +#include "common.h" + +void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long mask; + + if (cmd == NAND_CMD_NONE) + return; + + mask = (ctrl & NAND_CLE) ? 0x02 : 0; + if (ctrl & NAND_ALE) + mask |= 0x04; + + writeb(cmd, this->IO_ADDR_W + mask); +} + diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index a2c5abcd7c84..61ed4f0247ce 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -289,10 +289,10 @@ palmz71_gpio_setup(int early) gpio_direction_input(PALMZ71_USBDETECT_GPIO); if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO), palmz71_powercable, IRQF_SAMPLE_RANDOM, - "palmz71-cable", 0)) + "palmz71-cable", NULL)) printk(KERN_ERR "IRQ request for power cable failed!\n"); - palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), 0); + palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), NULL); } } diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 76d4ee05a814..a2c88890e767 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -143,20 +143,6 @@ static struct platform_device nor_device = { .resource = &nor_resource, }; -static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)this->IO_ADDR_W | mask); -} - #define P2_NAND_RB_GPIO_PIN 62 static int nand_dev_ready(struct mtd_info *mtd) @@ -174,7 +160,7 @@ static struct platform_nand_data nand_data = { .part_probe_types = part_probes, }, .ctrl = { - .cmd_ctrl = nand_cmd_ctl, + .cmd_ctrl = omap1_nand_cmd_ctl, .dev_ready = nand_dev_ready, }, }; diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 67382ddd8c83..a9ee06b6cb42 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -194,9 +194,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) { /* Find the highest supported frequency <= rate and switch to it */ struct mpu_rate * ptr; - unsigned long dpll1_rate, ref_rate; + unsigned long ref_rate; - dpll1_rate = ck_dpll1_p->rate; ref_rate = ck_ref_p->rate; for (ptr = omap1_rate_table; ptr->rate; ptr++) { diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index af658ad338ec..bb7779b57795 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -27,6 +27,7 @@ #define __ARCH_ARM_MACH_OMAP1_COMMON_H #include <plat/common.h> +#include <linux/mtd/mtd.h> #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) void omap7xx_map_io(void); @@ -56,8 +57,20 @@ void omap1_init_early(void); void omap1_init_irq(void); void omap1_restart(char, const char *); +extern void __init omap_check_revision(void); + +extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, + unsigned int ctrl); + extern struct sys_timer omap1_timer; extern bool omap_32k_timer_init(void); -extern void __init omap_init_consistent_dma_size(void); + +extern u32 omap_irq_flags; + +#ifdef CONFIG_ARCH_OMAP16XX +extern int ocpi_enable(void); +#else +static inline int ocpi_enable(void) { return 0; } +#endif #endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */ diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 76c67b3f9f61..29ec50fc688d 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -87,7 +87,7 @@ static void fpga_mask_ack_irq(struct irq_data *d) fpga_ack_irq(d); } -void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc) +static void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc) { u32 stat; int fpga_irq; diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index 2b28e1da14b0..a1b846aacdaf 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -21,6 +21,8 @@ #include <mach/hardware.h> +#include "common.h" + #define OMAP_DIE_ID_0 0xfffe1800 #define OMAP_DIE_ID_1 0xfffe1804 #define OMAP_PRODUCTION_ID_0 0xfffe2000 diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index d969a7203d14..71ce017bf5d8 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -18,13 +18,12 @@ #include <plat/mux.h> #include <plat/tc.h> +#include <plat/dma.h> #include "iomap.h" #include "common.h" #include "clock.h" -extern void omap_check_revision(void); - /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 4448114fab72..6995fb6a3345 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -49,6 +49,8 @@ #include <mach/hardware.h> +#include "common.h" + #define IRQ_BANK(irq) ((irq) >> 5) #define IRQ_BIT(irq) ((irq) & 0x1f) diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c index 86ace9aaa663..5769c71815b2 100644 --- a/arch/arm/mach-omap1/lcd_dma.c +++ b/arch/arm/mach-omap1/lcd_dma.c @@ -57,7 +57,7 @@ static struct lcd_dma_info { void *cb_data; int active; - unsigned long addr, size; + unsigned long addr; int rotate, data_type, xres, yres; int vxres; int mirror; @@ -77,11 +77,6 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, } EXPORT_SYMBOL(omap_set_lcd_dma_b1); -void omap_set_lcd_dma_src_port(int port) -{ - lcd_dma.src_port = port; -} - void omap_set_lcd_dma_ext_controller(int external) { lcd_dma.ext_ctrl = external; diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 087dba0df47e..e9cc52d4cb28 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -27,6 +27,7 @@ #include <linux/io.h> #include <linux/spinlock.h> +#include <mach/hardware.h> #include <plat/mux.h> diff --git a/arch/arm/plat-omap/ocpi.c b/arch/arm/mach-omap1/ocpi.c index ebe0c73c8901..238170cab5b7 100644 --- a/arch/arm/plat-omap/ocpi.c +++ b/arch/arm/mach-omap1/ocpi.c @@ -4,6 +4,7 @@ * Minimal OCP bus support for omap16xx * * Copyright (C) 2003 - 2005 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Written by Tony Lindgren <tony@atomide.com> * * Modified for clock framework by Paul Mundt <paul.mundt@nokia.com>. @@ -35,6 +36,8 @@ #include <mach/hardware.h> +#include "common.h" + #define OCPI_BASE 0xfffec320 #define OCPI_FAULT (OCPI_BASE + 0x00) #define OCPI_CMD_FAULT (OCPI_BASE + 0x04) @@ -64,7 +67,7 @@ int ocpi_enable(void) /* Enable access for OHCI in OCPI */ val = omap_readl(OCPI_PROT); val &= ~0xff; - //val &= (1 << 0); /* Allow access only to EMIFS */ + /* val &= (1 << 0); Allow access only to EMIFS */ omap_writel(val, OCPI_PROT); val = omap_readl(OCPI_SEC); @@ -86,7 +89,7 @@ static int __init omap_ocpi_init(void) clk_enable(ocpi_ck); ocpi_enable(); - printk("OMAP OCPI interconnect driver loaded\n"); + pr_info("OMAP OCPI interconnect driver loaded\n"); return 0; } diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index f66c32912b22..b2560d32b3a0 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -569,11 +569,10 @@ static int omap_pm_read_proc( static void omap_pm_init_proc(void) { - struct proc_dir_entry *entry; - - entry = create_proc_read_entry("driver/omap_pm", - S_IWUSR | S_IRUGO, NULL, - omap_pm_read_proc, NULL); + /* XXX Appears to leak memory */ + create_proc_read_entry("driver/omap_pm", + S_IWUSR | S_IRUGO, NULL, + omap_pm_read_proc, NULL); } #endif /* DEBUG && CONFIG_PROC_FS */ diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c index f255b153b863..b17709103866 100644 --- a/arch/arm/mach-omap1/reset.c +++ b/arch/arm/mach-omap1/reset.c @@ -8,6 +8,8 @@ #include <mach/hardware.h> +#include "common.h" + void omap1_restart(char mode, const char *cmd) { /* diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 6e90665a7c47..64c65bcb2d67 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -47,15 +47,14 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev, int n = (pdev->id - 1) << 1; u32 l; - l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); + l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); l |= source << n; - __raw_writel(l, MOD_CONF_CTRL_1); + omap_writel(l, MOD_CONF_CTRL_1); return 0; } - -int __init omap1_dm_timer_init(void) +static int __init omap1_dm_timer_init(void) { int i; int ret; diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index 19de03b074e3..e61afd922766 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -29,6 +29,8 @@ #include <plat/mux.h> #include <plat/usb.h> +#include "common.h" + /* These routines should handle the standard chip-specific modes * for usb0/1/2 ports, covering basic mux and transceiver setup. * @@ -138,6 +140,7 @@ static inline void ohci_device_init(struct omap_usb_config *pdata) if (cpu_is_omap7xx()) ohci_resources[1].start = INT_7XX_USB_HHC_1; pdata->ohci_device = &ohci_device; + pdata->ocpi_enable = &ocpi_enable; } #else diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index 1f97e7475206..447682c4e11c 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c @@ -39,26 +39,23 @@ static struct platform_device am35xx_emac_mdio_device = { static void am35xx_enable_emac_int(void) { - u32 regval; - - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | - AM35XX_CPGMAC_C0_TX_PULSE_CLR | - AM35XX_CPGMAC_C0_MISC_PULSE_CLR | - AM35XX_CPGMAC_C0_RX_THRESH_CLR); - omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + u32 v; + + v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR | + AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR); + omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); + omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ } static void am35xx_disable_emac_int(void) { - u32 regval; + u32 v; - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | - AM35XX_CPGMAC_C0_TX_PULSE_CLR); - omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR); + omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR); + omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */ } static struct emac_platform_data am35xx_emac_pdata = { @@ -92,7 +89,7 @@ static struct platform_device am35xx_emac_device = { void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) { - unsigned int regval; + u32 v; int err; am35xx_emac_pdata.rmii_en = rmii_en; @@ -110,8 +107,8 @@ void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) return; } - regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); - regval = regval & (~(AM35XX_CPGMACSS_SW_RST)); - omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); - regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + v &= ~AM35XX_CPGMACSS_SW_RST; + omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET); + omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */ } diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index da75f239873e..37abb0d49b51 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -37,7 +37,7 @@ #include <plat/dma.h> #include <plat/gpmc.h> #include <video/omapdss.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/gpmc-smc91x.h> @@ -113,9 +113,6 @@ static struct gpio sdp3430_dss_gpios[] __initdata = { {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"}, }; -static int lcd_enabled; -static int dvi_enabled; - static void __init sdp3430_display_init(void) { int r; @@ -129,44 +126,18 @@ static void __init sdp3430_display_init(void) static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) { - if (dvi_enabled) { - printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); - return -EINVAL; - } - gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1); gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1); - lcd_enabled = 1; - return 0; } static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) { - lcd_enabled = 0; - gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0); gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0); } -static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - - dvi_enabled = 1; - - return 0; -} - -static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - dvi_enabled = 0; -} - static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) { return 0; @@ -186,15 +157,14 @@ static struct omap_dss_device sdp3430_lcd_device = { .platform_disable = sdp3430_panel_disable_lcd, }; -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = sdp3430_panel_enable_dvi, - .platform_disable = sdp3430_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = -1, }; static struct omap_dss_device sdp3430_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index a39fc4bbd2b8..b4ad706c145a 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -20,6 +20,7 @@ #include <linux/usb/otg.h> #include <linux/spi/spi.h> #include <linux/i2c/twl.h> +#include <linux/mfd/twl6040.h> #include <linux/gpio_keys.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> @@ -560,7 +561,7 @@ static struct regulator_init_data sdp4430_vusim = { }, }; -static struct twl4030_codec_data twl6040_codec = { +static struct twl6040_codec_data twl6040_codec = { /* single-step ramp for headset and handsfree */ .hs_left_step = 0x0f, .hs_right_step = 0x0f, @@ -568,7 +569,7 @@ static struct twl4030_codec_data twl6040_codec = { .hf_right_step = 0x1d, }; -static struct twl4030_vibra_data twl6040_vibra = { +static struct twl6040_vibra_data twl6040_vibra = { .vibldrv_res = 8, .vibrdrv_res = 3, .viblmotor_res = 10, @@ -577,16 +578,14 @@ static struct twl4030_vibra_data twl6040_vibra = { .vddvibr_uV = 0, /* fixed volt supply - VBAT */ }; -static struct twl4030_audio_data twl6040_audio = { +static struct twl6040_platform_data twl6040_data = { .codec = &twl6040_codec, .vibra = &twl6040_vibra, .audpwron_gpio = 127, - .naudint_irq = OMAP44XX_IRQ_SYS_2N, .irq_base = TWL6040_CODEC_IRQ_BASE, }; static struct twl4030_platform_data sdp4430_twldata = { - .audio = &twl6040_audio, /* Regulators */ .vusim = &sdp4430_vusim, .vaux1 = &sdp4430_vaux1, @@ -617,7 +616,8 @@ static int __init omap4_i2c_init(void) TWL_COMMON_REGULATOR_VCXIO | TWL_COMMON_REGULATOR_VUSB | TWL_COMMON_REGULATOR_CLK32KG); - omap4_pmic_init("twl6030", &sdp4430_twldata); + omap4_pmic_init("twl6030", &sdp4430_twldata, + &twl6040_data, OMAP44XX_IRQ_SYS_2N); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); @@ -666,6 +666,10 @@ static struct nokia_dsi_panel_data dsi1_panel = { .use_ext_te = false, .ext_te_gpio = 101, .esd_interval = 0, + .pin_config = { + .num_pins = 6, + .pins = { 0, 1, 2, 3, 4, 5 }, + }, }; static struct omap_dss_device sdp4430_lcd_device = { @@ -674,13 +678,6 @@ static struct omap_dss_device sdp4430_lcd_device = { .type = OMAP_DISPLAY_TYPE_DSI, .data = &dsi1_panel, .phy.dsi = { - .clk_lane = 1, - .clk_pol = 0, - .data1_lane = 2, - .data1_pol = 0, - .data2_lane = 3, - .data2_pol = 0, - .module = 0, }, @@ -715,6 +712,10 @@ static struct nokia_dsi_panel_data dsi2_panel = { .use_ext_te = false, .ext_te_gpio = 103, .esd_interval = 0, + .pin_config = { + .num_pins = 6, + .pins = { 0, 1, 2, 3, 4, 5 }, + }, }; static struct omap_dss_device sdp4430_lcd2_device = { @@ -723,12 +724,6 @@ static struct omap_dss_device sdp4430_lcd2_device = { .type = OMAP_DISPLAY_TYPE_DSI, .data = &dsi2_panel, .phy.dsi = { - .clk_lane = 1, - .clk_pol = 0, - .data1_lane = 2, - .data1_pol = 0, - .data2_lane = 3, - .data2_pol = 0, .module = 1, }, @@ -758,21 +753,6 @@ static struct omap_dss_device sdp4430_lcd2_device = { .channel = OMAP_DSS_CHANNEL_LCD2, }; -static void sdp4430_lcd_init(void) -{ - int r; - - r = gpio_request_one(dsi1_panel.reset_gpio, GPIOF_DIR_OUT, - "lcd1_reset_gpio"); - if (r) - pr_err("%s: Could not get lcd1_reset_gpio\n", __func__); - - r = gpio_request_one(dsi2_panel.reset_gpio, GPIOF_DIR_OUT, - "lcd2_reset_gpio"); - if (r) - pr_err("%s: Could not get lcd2_reset_gpio\n", __func__); -} - static struct omap_dss_hdmi_data sdp4430_hdmi_data = { .hpd_gpio = HDMI_GPIO_HPD, }; @@ -858,7 +838,6 @@ static void __init omap_4430sdp_display_init(void) if (r) pr_err("%s: Could not get display_sel GPIO\n", __func__); - sdp4430_lcd_init(); sdp4430_picodlp_init(); omap_display_init(&sdp4430_dss_data); /* diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 3645285a3e2b..99790eb646e8 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -37,7 +37,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include "am35xx-emac.h" #include "mux.h" @@ -207,31 +207,14 @@ static struct omap_dss_device am3517_evm_tv_device = { .platform_disable = am3517_evm_panel_disable_tv, }; -static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - dvi_enabled = 1; - - return 0; -} - -static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - dvi_enabled = 0; -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = am3517_evm_panel_enable_dvi, - .platform_disable = am3517_evm_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = -1, }; static struct omap_dss_device am3517_evm_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 909a8b91b564..45746cb56c68 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -44,7 +44,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/mcspi.h> #include <mach/hardware.h> @@ -218,25 +218,6 @@ static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) gpio_set_value(CM_T35_LCD_EN_GPIO, 0); } -static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - - gpio_set_value(CM_T35_DVI_EN_GPIO, 0); - dvi_enabled = 1; - - return 0; -} - -static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value(CM_T35_DVI_EN_GPIO, 1); - dvi_enabled = 0; -} - static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) { return 0; @@ -260,15 +241,14 @@ static struct omap_dss_device cm_t35_lcd_device = { .phy.dpi.data_lines = 18, }; -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = cm_t35_panel_enable_dvi, - .platform_disable = cm_t35_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = CM_T35_DVI_EN_GPIO, }; static struct omap_dss_device cm_t35_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -316,7 +296,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { static struct gpio cm_t35_dss_gpios[] __initdata = { { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" }, { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" }, - { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable" }, }; static void __init cm_t35_init_display(void) @@ -335,7 +314,6 @@ static void __init cm_t35_init_display(void) gpio_export(CM_T35_LCD_EN_GPIO, 0); gpio_export(CM_T35_LCD_BL_GPIO, 0); - gpio_export(CM_T35_DVI_EN_GPIO, 0); msleep(50); gpio_set_value(CM_T35_LCD_EN_GPIO, 1); diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index a2010f07de31..b063f0d2faa6 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -47,7 +47,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/mcspi.h> #include <linux/input/matrix_keypad.h> @@ -118,19 +118,6 @@ static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) gpio_set_value_cansleep(dssdev->reset_gpio, 0); } -static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value_cansleep(dssdev->reset_gpio, 1); - return 0; -} - -static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value_cansleep(dssdev->reset_gpio, 0); -} - static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = { REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), }; @@ -154,15 +141,14 @@ static struct omap_dss_device devkit8000_lcd_device = { .phy.dpi.data_lines = 24, }; -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = devkit8000_panel_enable_dvi, - .platform_disable = devkit8000_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = -1, }; static struct omap_dss_device devkit8000_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -244,13 +230,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev, } /* gpio + 7 is "DVI_PD" (out, active low) */ - devkit8000_dvi_device.reset_gpio = gpio + 7; - ret = gpio_request_one(devkit8000_dvi_device.reset_gpio, - GPIOF_OUT_INIT_LOW, "DVI PowerDown"); - if (ret < 0) { - devkit8000_dvi_device.reset_gpio = -EINVAL; - printk(KERN_ERR "Failed to request GPIO for DVI PowerDown\n"); - } + dvi_panel.power_down_gpio = gpio + 7; return 0; } diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 74e1687b5170..098d183a0086 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -137,7 +137,7 @@ static struct twl4030_platform_data sdp4430_twldata = { static void __init omap4_i2c_init(void) { - omap4_pmic_init("twl6030", &sdp4430_twldata); + omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0); } static void __init omap4_init(void) diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 930c0d380435..04816c96e829 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -32,7 +32,7 @@ #include <plat/gpmc.h> #include <plat/usb.h> #include <video/omapdss.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/onenand.h> #include "mux.h" @@ -444,28 +444,15 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { .setup = igep_twl_gpio_setup, }; -static int igep2_enable_dvi(struct omap_dss_device *dssdev) -{ - gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1); - - return 0; -} - -static void igep2_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0); -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = igep2_enable_dvi, - .platform_disable = igep2_disable_dvi, - .i2c_bus_num = 3, +static struct tfp410_platform_data dvi_panel = { + .i2c_bus_num = 3, + .power_down_gpio = IGEP2_GPIO_DVI_PUP, }; static struct omap_dss_device igep2_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -480,14 +467,6 @@ static struct omap_dss_board_info igep2_dss_data = { .default_device = &igep2_dvi_device, }; -static void __init igep2_display_init(void) -{ - int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH, - "GPIO_DVI_PUP"); - if (err) - pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n"); -} - static struct platform_device *igep_devices[] __initdata = { &igep_vwlan_device, }; @@ -668,7 +647,6 @@ static void __init igep_init(void) if (machine_is_igep0020()) { omap_display_init(&igep2_dss_data); - igep2_display_init(); igep2_init_smsc911x(); usbhs_init(&igep2_usbhs_bdata); } else { diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 7be8d659d91d..8ede8d20d7b2 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -42,7 +42,7 @@ #include <plat/board.h> #include "common.h" #include <video/omapdss.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/gpmc.h> #include <plat/nand.h> #include <plat/usb.h> @@ -189,33 +189,17 @@ static struct mtd_partition omap3beagle_nand_partitions[] = { /* DSS */ -static int beagle_enable_dvi(struct omap_dss_device *dssdev) -{ - if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value(dssdev->reset_gpio, 1); - - return 0; -} - -static void beagle_disable_dvi(struct omap_dss_device *dssdev) -{ - if (gpio_is_valid(dssdev->reset_gpio)) - gpio_set_value(dssdev->reset_gpio, 0); -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = beagle_enable_dvi, - .platform_disable = beagle_disable_dvi, +static struct tfp410_platform_data dvi_panel = { .i2c_bus_num = 3, + .power_down_gpio = -1, }; static struct omap_dss_device beagle_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, - .reset_gpio = -EINVAL, }; static struct omap_dss_device beagle_tv_device = { @@ -236,16 +220,6 @@ static struct omap_dss_board_info beagle_dss_data = { .default_device = &beagle_dvi_device, }; -static void __init beagle_display_init(void) -{ - int r; - - r = gpio_request_one(beagle_dvi_device.reset_gpio, GPIOF_OUT_INIT_LOW, - "DVI reset"); - if (r < 0) - printk(KERN_ERR "Unable to get DVI reset GPIO\n"); -} - #include "sdram-micron-mt46h32m32lf-6.h" static struct omap2_hsmmc_info mmc[] = { @@ -309,7 +283,7 @@ static int beagle_twl_gpio_setup(struct device *dev, if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC")) pr_err("%s: unable to configure EHCI_nOC\n", __func__); } - beagle_dvi_device.reset_gpio = beagle_config.reset_gpio; + dvi_panel.power_down_gpio = beagle_config.reset_gpio; gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level, "nEN_USB_PWR"); @@ -552,7 +526,6 @@ static void __init omap3_beagle_init(void) omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); - beagle_display_init(); beagle_opp_init(); } diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 49df12735b41..ace3c675e9c2 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -46,7 +46,7 @@ #include "common.h" #include <plat/mcspi.h> #include <video/omapdss.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" @@ -219,35 +219,14 @@ static struct omap_dss_device omap3_evm_tv_device = { .platform_disable = omap3_evm_disable_tv, }; -static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - - gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); - - dvi_enabled = 1; - return 0; -} - -static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); - - dvi_enabled = 0; -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = omap3_evm_enable_dvi, - .platform_disable = omap3_evm_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, }; static struct omap_dss_device omap3_evm_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; @@ -630,13 +609,13 @@ static struct regulator_consumer_supply dummy_supplies[] = { static void __init omap3_evm_init(void) { + struct omap_board_mux *obm; + omap3_evm_get_revision(); regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - if (cpu_is_omap3630()) - omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB); - else - omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB); + obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux; + omap3_mux_init(obm, OMAP_PACKAGE_CBB); omap_board_config = omap3_evm_config; omap_board_config_size = ARRAY_SIZE(omap3_evm_config); diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 4dffc95bddd2..4396bae91677 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -42,7 +42,7 @@ #include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/mcspi.h> #include <linux/input/matrix_keypad.h> @@ -92,9 +92,6 @@ static inline void __init omap3stalker_init_eth(void) #define LCD_PANEL_BKLIGHT_GPIO 210 #define ENABLE_VPLL2_DEV_GRP 0xE0 -static int lcd_enabled; -static int dvi_enabled; - static void __init omap3_stalker_display_init(void) { return; @@ -122,32 +119,14 @@ static struct omap_dss_device omap3_stalker_tv_device = { .platform_disable = omap3_stalker_disable_tv, }; -static int omap3_stalker_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - gpio_set_value(DSS_ENABLE_GPIO, 1); - dvi_enabled = 1; - return 0; -} - -static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value(DSS_ENABLE_GPIO, 0); - dvi_enabled = 0; -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = omap3_stalker_enable_dvi, - .platform_disable = omap3_stalker_disable_dvi, +static struct tfp410_platform_data dvi_panel = { + .power_down_gpio = DSS_ENABLE_GPIO, }; static struct omap_dss_device omap3_stalker_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index d8c0e89f0126..59dd8b7f5b4f 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -25,6 +25,7 @@ #include <linux/gpio.h> #include <linux/usb/otg.h> #include <linux/i2c/twl.h> +#include <linux/mfd/twl6040.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> #include <linux/wl12xx.h> @@ -41,7 +42,7 @@ #include "common.h" #include <plat/usb.h> #include <plat/mmc.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include "hsmmc.h" #include "control.h" @@ -230,7 +231,7 @@ static struct platform_device omap_vwlan_device = { }, }; -struct wl12xx_platform_data omap_panda_wlan_data __initdata = { +static struct wl12xx_platform_data omap_panda_wlan_data __initdata = { /* PANDA ref clock is 38.4 MHz */ .board_ref_clock = 2, }; @@ -284,7 +285,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) return 0; } -static struct twl4030_codec_data twl6040_codec = { +static struct twl6040_codec_data twl6040_codec = { /* single-step ramp for headset and handsfree */ .hs_left_step = 0x0f, .hs_right_step = 0x0f, @@ -292,17 +293,14 @@ static struct twl4030_codec_data twl6040_codec = { .hf_right_step = 0x1d, }; -static struct twl4030_audio_data twl6040_audio = { +static struct twl6040_platform_data twl6040_data = { .codec = &twl6040_codec, .audpwron_gpio = 127, - .naudint_irq = OMAP44XX_IRQ_SYS_2N, .irq_base = TWL6040_CODEC_IRQ_BASE, }; /* Panda board uses the common PMIC configuration */ -static struct twl4030_platform_data omap4_panda_twldata = { - .audio = &twl6040_audio, -}; +static struct twl4030_platform_data omap4_panda_twldata; /* * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM @@ -326,7 +324,8 @@ static int __init omap4_panda_i2c_init(void) TWL_COMMON_REGULATOR_VCXIO | TWL_COMMON_REGULATOR_VUSB | TWL_COMMON_REGULATOR_CLK32KG); - omap4_pmic_init("twl6030", &omap4_panda_twldata); + omap4_pmic_init("twl6030", &omap4_panda_twldata, + &twl6040_data, OMAP44XX_IRQ_SYS_2N); omap_register_i2c_bus(2, 400, NULL, 0); /* * Bus 3 is attached to the DVI port where devices like the pico DLP @@ -421,47 +420,22 @@ static struct omap_board_mux board_mux[] __initdata = { /* Display DVI */ #define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0 -static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value(dssdev->reset_gpio, 1); - return 0; -} - -static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev) -{ - gpio_set_value(dssdev->reset_gpio, 0); -} - /* Using generic display panel */ -static struct panel_dvi_platform_data omap4_dvi_panel = { - .platform_enable = omap4_panda_enable_dvi, - .platform_disable = omap4_panda_disable_dvi, - .i2c_bus_num = 3, +static struct tfp410_platform_data omap4_dvi_panel = { + .i2c_bus_num = 3, + .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, }; -struct omap_dss_device omap4_panda_dvi_device = { +static struct omap_dss_device omap4_panda_dvi_device = { .type = OMAP_DISPLAY_TYPE_DPI, .name = "dvi", - .driver_name = "dvi", + .driver_name = "tfp410", .data = &omap4_dvi_panel, .phy.dpi.data_lines = 24, .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, .channel = OMAP_DSS_CHANNEL_LCD2, }; -int __init omap4_panda_dvi_init(void) -{ - int r; - - /* Requesting TFP410 DVI GPIO and disabling it, at bootup */ - r = gpio_request_one(omap4_panda_dvi_device.reset_gpio, - GPIOF_OUT_INIT_LOW, "DVI PD"); - if (r) - pr_err("Failed to get DVI powerdown GPIO\n"); - - return r; -} - static struct gpio panda_hdmi_gpios[] = { { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, @@ -510,13 +484,8 @@ static struct omap_dss_board_info omap4_panda_dss_data = { .default_device = &omap4_panda_dvi_device, }; -void __init omap4_panda_display_init(void) +static void __init omap4_panda_display_init(void) { - int r; - - r = omap4_panda_dvi_init(); - if (r) - pr_err("error initializing panda DVI\n"); omap_display_init(&omap4_panda_dss_data); diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 33aa3910b09e..5527c1979a16 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -46,7 +46,7 @@ #include "common.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> -#include <video/omap-panel-dvi.h> +#include <video/omap-panel-tfp410.h> #include <plat/gpmc.h> #include <mach/hardware.h> #include <plat/nand.h> @@ -167,32 +167,15 @@ static void __init overo_display_init(void) gpio_export(OVERO_GPIO_LCD_BL, 0); } -static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) -{ - if (lcd_enabled) { - printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); - return -EINVAL; - } - dvi_enabled = 1; - - return 0; -} - -static void overo_panel_disable_dvi(struct omap_dss_device *dssdev) -{ - dvi_enabled = 0; -} - -static struct panel_dvi_platform_data dvi_panel = { - .platform_enable = overo_panel_enable_dvi, - .platform_disable = overo_panel_disable_dvi, +static struct tfp410_platform_data dvi_panel = { .i2c_bus_num = 3, + .power_down_gpio = -1, }; static struct omap_dss_device overo_dvi_device = { .name = "dvi", .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "dvi", + .driver_name = "tfp410", .data = &dvi_panel, .phy.dpi.data_lines = 24, }; diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index d87ee0612098..ae957c92081b 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -872,11 +872,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = { .resource_config = twl4030_rconfig, }; -struct twl4030_vibra_data rx51_vibra_data __initdata = { +static struct twl4030_vibra_data rx51_vibra_data __initdata = { .coexist = 0, }; -struct twl4030_audio_data rx51_audio_data __initdata = { +static struct twl4030_audio_data rx51_audio_data __initdata = { .audio_mclk = 26000000, .vibra = &rx51_vibra_data, }; diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 27f01f051dff..2da92a6ba40a 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -59,25 +59,24 @@ static struct platform_device leds_gpio = { }; /* - * cpuidle C-states definition override from the default values. - * The 'exit_latency' field is the sum of sleep and wake-up latencies. - */ -static struct cpuidle_params rx51_cpuidle_params[] = { - /* C1 */ - {110 + 162, 5 , 1}, - /* C2 */ - {106 + 180, 309, 1}, - /* C3 */ - {107 + 410, 46057, 0}, - /* C4 */ - {121 + 3374, 46057, 0}, - /* C5 */ - {855 + 1146, 46057, 1}, - /* C6 */ - {7580 + 4134, 484329, 0}, - /* C7 */ - {7505 + 15274, 484329, 1}, -}; + * cpuidle C-states definition for rx51. + * + * The 'exit_latency' field is the sum of sleep + * and wake-up latencies. + + --------------------------------------------- + | state | exit_latency | target_residency | + --------------------------------------------- + | C1 | 110 + 162 | 5 | + | C2 | 106 + 180 | 309 | + | C3 | 107 + 410 | 46057 | + | C4 | 121 + 3374 | 46057 | + | C5 | 855 + 1146 | 46057 | + | C6 | 7580 + 4134 | 484329 | + | C7 | 7505 + 15274 | 484329 | + --------------------------------------------- + +*/ extern void __init rx51_peripherals_init(void); @@ -98,7 +97,6 @@ static void __init rx51_init(void) struct omap_sdrc_params *sdrc_params; omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3_pm_init_cpuidle(rx51_cpuidle_params); omap_serial_init(); sdrc_params = nokia_get_sdram_timings(); diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index a43a765dd092..28187f134fff 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -16,6 +16,7 @@ #include <linux/spi/spi.h> #include <plat/mcspi.h> #include <video/omapdss.h> +#include <mach/board-zoom.h> #define LCD_PANEL_RESET_GPIO_PROD 96 #define LCD_PANEL_RESET_GPIO_PILOT 55 diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 7072e0d651b1..3d9d746b221a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -165,83 +165,3 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) return 0; } - -#ifdef CONFIG_CPU_FREQ -/* - * Walk PRCM rate table and fillout cpufreq freq_table - * XXX This should be replaced by an OPP layer in the near future - */ -static struct cpufreq_frequency_table *freq_table; - -void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) -{ - const struct prcm_config *prcm; - int i = 0; - int tbl_sz = 0; - - if (!cpu_is_omap24xx()) - return; - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sclk->rate) - continue; - - /* don't put bypass rates in table */ - if (prcm->dpll_speed == prcm->xtal_speed) - continue; - - tbl_sz++; - } - - /* - * XXX Ensure that we're doing what CPUFreq expects for this error - * case and the following one - */ - if (tbl_sz == 0) { - pr_warning("%s: no matching entries in rate_table\n", - __func__); - return; - } - - /* Include the CPUFREQ_TABLE_END terminator entry */ - tbl_sz++; - - freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz, - GFP_ATOMIC); - if (!freq_table) { - pr_err("%s: could not kzalloc frequency table\n", __func__); - return; - } - - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sclk->rate) - continue; - - /* don't put bypass rates in table */ - if (prcm->dpll_speed == prcm->xtal_speed) - continue; - - freq_table[i].index = i; - freq_table[i].frequency = prcm->mpu_speed / 1000; - i++; - } - - freq_table[i].index = i; - freq_table[i].frequency = CPUFREQ_TABLE_END; - - *table = &freq_table[0]; -} - -void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) -{ - if (!cpu_is_omap24xx()) - return; - - kfree(freq_table); -} - -#endif diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index f57ed5baeccf..d9f4931513f9 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -536,10 +536,5 @@ struct clk_functions omap2_clk_functions = { .clk_set_rate = omap2_clk_set_rate, .clk_set_parent = omap2_clk_set_parent, .clk_disable_unused = omap2_clk_disable_unused, -#ifdef CONFIG_CPU_FREQ - /* These will be removed when the OPP code is integrated */ - .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, - .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, -#endif }; diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b8c2a686481c..a1bb23a23351 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -146,14 +146,6 @@ extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; -#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ) -extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table); -extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); -#else -#define omap2_clk_init_cpufreq_table 0 -#define omap2_clk_exit_cpufreq_table 0 -#endif - extern const struct clkops clkops_omap2_iclk_dflt_wait; extern const struct clkops clkops_omap2_iclk_dflt; extern const struct clkops clkops_omap2_iclk_idle_only; diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 57da7f406e28..0e95efccd2d7 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -134,8 +134,6 @@ void omap4_map_io(void); void ti81xx_map_io(void); void omap_barriers_init(void); -extern void __init omap_init_consistent_dma_size(void); - /** * omap_test_timeout - busy-loop, testing a condition * @cond: condition to test until it evaluates to true diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 535866489ce3..207bc1c7759f 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -38,40 +38,44 @@ #ifdef CONFIG_CPU_IDLE -/* - * The latencies/thresholds for various C states have - * to be configured from the respective board files. - * These are some default values (which might not provide - * the best power savings) used on boards which do not - * pass these details from the board file. - */ -static struct cpuidle_params cpuidle_params_table[] = { - /* C1 */ - {2 + 2, 5, 1}, - /* C2 */ - {10 + 10, 30, 1}, - /* C3 */ - {50 + 50, 300, 1}, - /* C4 */ - {1500 + 1800, 4000, 1}, - /* C5 */ - {2500 + 7500, 12000, 1}, - /* C6 */ - {3000 + 8500, 15000, 1}, - /* C7 */ - {10000 + 30000, 300000, 1}, -}; -#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table) - /* Mach specific information to be recorded in the C-state driver_data */ struct omap3_idle_statedata { u32 mpu_state; u32 core_state; - u8 valid; }; -struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES]; -struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; +static struct omap3_idle_statedata omap3_idle_data[] = { + { + .mpu_state = PWRDM_POWER_ON, + .core_state = PWRDM_POWER_ON, + }, + { + .mpu_state = PWRDM_POWER_ON, + .core_state = PWRDM_POWER_ON, + }, + { + .mpu_state = PWRDM_POWER_RET, + .core_state = PWRDM_POWER_ON, + }, + { + .mpu_state = PWRDM_POWER_OFF, + .core_state = PWRDM_POWER_ON, + }, + { + .mpu_state = PWRDM_POWER_RET, + .core_state = PWRDM_POWER_RET, + }, + { + .mpu_state = PWRDM_POWER_OFF, + .core_state = PWRDM_POWER_RET, + }, + { + .mpu_state = PWRDM_POWER_OFF, + .core_state = PWRDM_POWER_OFF, + }, +}; + +static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; static int _cpuidle_allow_idle(struct powerdomain *pwrdm, struct clockdomain *clkdm) @@ -91,8 +95,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - struct omap3_idle_statedata *cx = - cpuidle_get_statedata(&dev->states_usage[index]); + struct omap3_idle_statedata *cx = &omap3_idle_data[index]; u32 mpu_state = cx->mpu_state, core_state = cx->core_state; local_fiq_disable(); @@ -169,14 +172,12 @@ static inline int omap3_enter_idle(struct cpuidle_device *dev, * if it satisfies the enable_off_mode condition. */ static int next_valid_state(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) + struct cpuidle_driver *drv, int index) { - struct cpuidle_state_usage *curr_usage = &dev->states_usage[index]; - struct cpuidle_state *curr = &drv->states[index]; - struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage); + struct omap3_idle_statedata *cx = &omap3_idle_data[index]; u32 mpu_deepest_state = PWRDM_POWER_RET; u32 core_deepest_state = PWRDM_POWER_RET; + int idx; int next_index = -1; if (enable_off_mode) { @@ -191,45 +192,29 @@ static int next_valid_state(struct cpuidle_device *dev, } /* Check if current state is valid */ - if ((cx->valid) && - (cx->mpu_state >= mpu_deepest_state) && - (cx->core_state >= core_deepest_state)) { + if ((cx->mpu_state >= mpu_deepest_state) && + (cx->core_state >= core_deepest_state)) return index; - } else { - int idx = OMAP3_NUM_STATES - 1; - - /* Reach the current state starting at highest C-state */ - for (; idx >= 0; idx--) { - if (&drv->states[idx] == curr) { - next_index = idx; - break; - } - } - - /* Should never hit this condition */ - WARN_ON(next_index == -1); - /* - * Drop to next valid state. - * Start search from the next (lower) state. - */ - idx--; - for (; idx >= 0; idx--) { - cx = cpuidle_get_statedata(&dev->states_usage[idx]); - if ((cx->valid) && - (cx->mpu_state >= mpu_deepest_state) && - (cx->core_state >= core_deepest_state)) { - next_index = idx; - break; - } + /* + * Drop to next valid state. + * Start search from the next (lower) state. + */ + for (idx = index - 1; idx >= 0; idx--) { + cx = &omap3_idle_data[idx]; + if ((cx->mpu_state >= mpu_deepest_state) && + (cx->core_state >= core_deepest_state)) { + next_index = idx; + break; } - /* - * C1 is always valid. - * So, no need to check for 'next_index == -1' outside - * this loop. - */ } + /* + * C1 is always valid. + * So, no need to check for 'next_index == -1' outside + * this loop. + */ + return next_index; } @@ -273,7 +258,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, * Prevent PER off if CORE is not in retention or off as this * would disable PER wakeups completely. */ - cx = cpuidle_get_statedata(&dev->states_usage[index]); + cx = &omap3_idle_data[index]; core_next_state = cx->core_state; per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); if ((per_next_state == PWRDM_POWER_OFF) && @@ -298,57 +283,71 @@ select_state: DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); -void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) -{ - int i; - - if (!cpuidle_board_params) - return; - - for (i = 0; i < OMAP3_NUM_STATES; i++) { - cpuidle_params_table[i].valid = cpuidle_board_params[i].valid; - cpuidle_params_table[i].exit_latency = - cpuidle_board_params[i].exit_latency; - cpuidle_params_table[i].target_residency = - cpuidle_board_params[i].target_residency; - } - return; -} - struct cpuidle_driver omap3_idle_driver = { .name = "omap3_idle", .owner = THIS_MODULE, + .states = { + { + .enter = omap3_enter_idle, + .exit_latency = 2 + 2, + .target_residency = 5, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C1", + .desc = "MPU ON + CORE ON", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 10 + 10, + .target_residency = 30, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C2", + .desc = "MPU ON + CORE ON", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 50 + 50, + .target_residency = 300, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C3", + .desc = "MPU RET + CORE ON", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 1500 + 1800, + .target_residency = 4000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C4", + .desc = "MPU OFF + CORE ON", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 2500 + 7500, + .target_residency = 12000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C5", + .desc = "MPU RET + CORE RET", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 3000 + 8500, + .target_residency = 15000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C6", + .desc = "MPU OFF + CORE RET", + }, + { + .enter = omap3_enter_idle_bm, + .exit_latency = 10000 + 30000, + .target_residency = 30000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C7", + .desc = "MPU OFF + CORE OFF", + }, + }, + .state_count = ARRAY_SIZE(omap3_idle_data), + .safe_state_index = 0, }; -/* Helper to fill the C-state common data*/ -static inline void _fill_cstate(struct cpuidle_driver *drv, - int idx, const char *descr) -{ - struct cpuidle_state *state = &drv->states[idx]; - - state->exit_latency = cpuidle_params_table[idx].exit_latency; - state->target_residency = cpuidle_params_table[idx].target_residency; - state->flags = CPUIDLE_FLAG_TIME_VALID; - state->enter = omap3_enter_idle_bm; - sprintf(state->name, "C%d", idx + 1); - strncpy(state->desc, descr, CPUIDLE_DESC_LEN); - -} - -/* Helper to register the driver_data */ -static inline struct omap3_idle_statedata *_fill_cstate_usage( - struct cpuidle_device *dev, - int idx) -{ - struct omap3_idle_statedata *cx = &omap3_idle_data[idx]; - struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; - - cx->valid = cpuidle_params_table[idx].valid; - cpuidle_set_statedata(state_usage, cx); - - return cx; -} - /** * omap3_idle_init - Init routine for OMAP3 idle * @@ -358,77 +357,20 @@ static inline struct omap3_idle_statedata *_fill_cstate_usage( int __init omap3_idle_init(void) { struct cpuidle_device *dev; - struct cpuidle_driver *drv = &omap3_idle_driver; - struct omap3_idle_statedata *cx; mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); per_pd = pwrdm_lookup("per_pwrdm"); cam_pd = pwrdm_lookup("cam_pwrdm"); + if (!mpu_pd || !core_pd || !per_pd || !cam_pd) + return -ENODEV; - drv->safe_state_index = -1; - dev = &per_cpu(omap3_idle_dev, smp_processor_id()); - - /* C1 . MPU WFI + Core active */ - _fill_cstate(drv, 0, "MPU ON + CORE ON"); - (&drv->states[0])->enter = omap3_enter_idle; - drv->safe_state_index = 0; - cx = _fill_cstate_usage(dev, 0); - cx->valid = 1; /* C1 is always valid */ - cx->mpu_state = PWRDM_POWER_ON; - cx->core_state = PWRDM_POWER_ON; - - /* C2 . MPU WFI + Core inactive */ - _fill_cstate(drv, 1, "MPU ON + CORE ON"); - cx = _fill_cstate_usage(dev, 1); - cx->mpu_state = PWRDM_POWER_ON; - cx->core_state = PWRDM_POWER_ON; - - /* C3 . MPU CSWR + Core inactive */ - _fill_cstate(drv, 2, "MPU RET + CORE ON"); - cx = _fill_cstate_usage(dev, 2); - cx->mpu_state = PWRDM_POWER_RET; - cx->core_state = PWRDM_POWER_ON; - - /* C4 . MPU OFF + Core inactive */ - _fill_cstate(drv, 3, "MPU OFF + CORE ON"); - cx = _fill_cstate_usage(dev, 3); - cx->mpu_state = PWRDM_POWER_OFF; - cx->core_state = PWRDM_POWER_ON; - - /* C5 . MPU RET + Core RET */ - _fill_cstate(drv, 4, "MPU RET + CORE RET"); - cx = _fill_cstate_usage(dev, 4); - cx->mpu_state = PWRDM_POWER_RET; - cx->core_state = PWRDM_POWER_RET; - - /* C6 . MPU OFF + Core RET */ - _fill_cstate(drv, 5, "MPU OFF + CORE RET"); - cx = _fill_cstate_usage(dev, 5); - cx->mpu_state = PWRDM_POWER_OFF; - cx->core_state = PWRDM_POWER_RET; - - /* C7 . MPU OFF + Core OFF */ - _fill_cstate(drv, 6, "MPU OFF + CORE OFF"); - cx = _fill_cstate_usage(dev, 6); - /* - * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot - * enable OFF mode in a stable form for previous revisions. - * We disable C7 state as a result. - */ - if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) { - cx->valid = 0; - pr_warn("%s: core off state C7 disabled due to i583\n", - __func__); - } - cx->mpu_state = PWRDM_POWER_OFF; - cx->core_state = PWRDM_POWER_OFF; - - drv->state_count = OMAP3_NUM_STATES; cpuidle_register_driver(&omap3_idle_driver); - dev->state_count = OMAP3_NUM_STATES; + dev = &per_cpu(omap3_idle_dev, smp_processor_id()); + dev->cpu = 0; + if (cpuidle_register_device(dev)) { printk(KERN_ERR "%s: CPUidle register device failed\n", __func__); diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index f386cbe9c889..be1617ca84bd 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -24,26 +24,31 @@ #ifdef CONFIG_CPU_IDLE -/* Machine specific information to be recorded in the C-state driver_data */ +/* Machine specific information */ struct omap4_idle_statedata { u32 cpu_state; u32 mpu_logic_state; u32 mpu_state; - u8 valid; }; -static struct cpuidle_params cpuidle_params_table[] = { - /* C1 - CPU0 ON + CPU1 ON + MPU ON */ - {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1}, - /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */ - {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1}, - /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ - {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1}, +static struct omap4_idle_statedata omap4_idle_data[] = { + { + .cpu_state = PWRDM_POWER_ON, + .mpu_state = PWRDM_POWER_ON, + .mpu_logic_state = PWRDM_POWER_RET, + }, + { + .cpu_state = PWRDM_POWER_OFF, + .mpu_state = PWRDM_POWER_RET, + .mpu_logic_state = PWRDM_POWER_RET, + }, + { + .cpu_state = PWRDM_POWER_OFF, + .mpu_state = PWRDM_POWER_RET, + .mpu_logic_state = PWRDM_POWER_OFF, + }, }; -#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table) - -struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES]; static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; /** @@ -60,8 +65,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - struct omap4_idle_statedata *cx = - cpuidle_get_statedata(&dev->states_usage[index]); + struct omap4_idle_statedata *cx = &omap4_idle_data[index]; u32 cpu1_state; int cpu_id = smp_processor_id(); @@ -78,7 +82,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev, cpu1_state = pwrdm_read_pwrst(cpu1_pd); if (cpu1_state != PWRDM_POWER_OFF) { index = drv->safe_state_index; - cx = cpuidle_get_statedata(&dev->states_usage[index]); + cx = &omap4_idle_data[index]; } if (index > 0) @@ -133,36 +137,39 @@ struct cpuidle_driver omap4_idle_driver = { .name = "omap4_idle", .owner = THIS_MODULE, .en_core_tk_irqen = 1, + .states = { + { + /* C1 - CPU0 ON + CPU1 ON + MPU ON */ + .exit_latency = 2 + 2, + .target_residency = 5, + .flags = CPUIDLE_FLAG_TIME_VALID, + .enter = omap4_enter_idle, + .name = "C1", + .desc = "MPUSS ON" + }, + { + /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ + .exit_latency = 328 + 440, + .target_residency = 960, + .flags = CPUIDLE_FLAG_TIME_VALID, + .enter = omap4_enter_idle, + .name = "C2", + .desc = "MPUSS CSWR", + }, + { + /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ + .exit_latency = 460 + 518, + .target_residency = 1100, + .flags = CPUIDLE_FLAG_TIME_VALID, + .enter = omap4_enter_idle, + .name = "C3", + .desc = "MPUSS OSWR", + }, + }, + .state_count = ARRAY_SIZE(omap4_idle_data), + .safe_state_index = 0, }; -static inline void _fill_cstate(struct cpuidle_driver *drv, - int idx, const char *descr) -{ - struct cpuidle_state *state = &drv->states[idx]; - - state->exit_latency = cpuidle_params_table[idx].exit_latency; - state->target_residency = cpuidle_params_table[idx].target_residency; - state->flags = CPUIDLE_FLAG_TIME_VALID; - state->enter = omap4_enter_idle; - sprintf(state->name, "C%d", idx + 1); - strncpy(state->desc, descr, CPUIDLE_DESC_LEN); -} - -static inline struct omap4_idle_statedata *_fill_cstate_usage( - struct cpuidle_device *dev, - int idx) -{ - struct omap4_idle_statedata *cx = &omap4_idle_data[idx]; - struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; - - cx->valid = cpuidle_params_table[idx].valid; - cpuidle_set_statedata(state_usage, cx); - - return cx; -} - - - /** * omap4_idle_init - Init routine for OMAP4 idle * @@ -171,9 +178,7 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage( */ int __init omap4_idle_init(void) { - struct omap4_idle_statedata *cx; struct cpuidle_device *dev; - struct cpuidle_driver *drv = &omap4_idle_driver; unsigned int cpu_id = 0; mpu_pd = pwrdm_lookup("mpu_pwrdm"); @@ -182,42 +187,15 @@ int __init omap4_idle_init(void) if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) return -ENODEV; - - drv->safe_state_index = -1; dev = &per_cpu(omap4_idle_dev, cpu_id); dev->cpu = cpu_id; - /* C1 - CPU0 ON + CPU1 ON + MPU ON */ - _fill_cstate(drv, 0, "MPUSS ON"); - drv->safe_state_index = 0; - cx = _fill_cstate_usage(dev, 0); - cx->valid = 1; /* C1 is always valid */ - cx->cpu_state = PWRDM_POWER_ON; - cx->mpu_state = PWRDM_POWER_ON; - cx->mpu_logic_state = PWRDM_POWER_RET; - - /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ - _fill_cstate(drv, 1, "MPUSS CSWR"); - cx = _fill_cstate_usage(dev, 1); - cx->cpu_state = PWRDM_POWER_OFF; - cx->mpu_state = PWRDM_POWER_RET; - cx->mpu_logic_state = PWRDM_POWER_RET; - - /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ - _fill_cstate(drv, 2, "MPUSS OSWR"); - cx = _fill_cstate_usage(dev, 2); - cx->cpu_state = PWRDM_POWER_OFF; - cx->mpu_state = PWRDM_POWER_RET; - cx->mpu_logic_state = PWRDM_POWER_OFF; - - drv->state_count = OMAP4_NUM_STATES; cpuidle_register_driver(&omap4_idle_driver); - dev->state_count = OMAP4_NUM_STATES; if (cpuidle_register_device(dev)) { pr_err("%s: CPUidle register device failed\n", __func__); - return -EIO; - } + return -EIO; + } return 0; } diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index e4336035c0ea..f3953a499286 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -42,7 +42,6 @@ static int __init omap3_l3_init(void) { - int l; struct omap_hwmod *oh; struct platform_device *pdev; char oh_name[L3_MODULES_MAX_LEN]; @@ -54,7 +53,7 @@ static int __init omap3_l3_init(void) if (!(cpu_is_omap34xx())) return -ENODEV; - l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); + snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); oh = omap_hwmod_lookup(oh_name); @@ -72,7 +71,7 @@ postcore_initcall(omap3_l3_init); static int __init omap4_l3_init(void) { - int l, i; + int i; struct omap_hwmod *oh[3]; struct platform_device *pdev; char oh_name[L3_MODULES_MAX_LEN]; @@ -89,7 +88,7 @@ static int __init omap4_l3_init(void) return -ENODEV; for (i = 0; i < L3_MODULES; i++) { - l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); + snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); oh[i] = omap_hwmod_lookup(oh_name); if (!(oh[i])) diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 2f994e5194e8..064cab03d2bd 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -58,7 +58,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); - if (!pdata) { + if (!pdata->regs) { pr_err("gpio%d: Memory allocation failed\n", id); return -ENOMEM; } diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 385b3e02c4a6..a0fa9bb2bda5 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -176,7 +176,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, const int t_wpl = 40; const int t_wph = 30; int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; - int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; + int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; int err, ticks_cez; int cs = cfg->cs, freq = *freq_ptr; @@ -240,7 +240,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, break; } - tick_ns = gpmc_ticks_to_ns(1); div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period); gpmc_clk_ns = gpmc_ticks_to_ns(div); if (gpmc_clk_ns < 15) /* >66Mhz */ diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 00d510858e28..580e684e8825 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -755,8 +755,7 @@ static int __init gpmc_init(void) irq++; } - ret = request_irq(gpmc_irq, - gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base); + ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL); if (ret) pr_err("gpmc: irq-%d could not claim: err %d\n", gpmc_irq, ret); diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c index 454dfce125ca..8763c8520dc2 100644 --- a/arch/arm/mach-omap2/hwspinlock.c +++ b/arch/arm/mach-omap2/hwspinlock.c @@ -28,7 +28,7 @@ static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = { .base_id = 0, }; -int __init hwspinlocks_init(void) +static int __init hwspinlocks_init(void) { int retval = 0; struct omap_hwmod *oh; diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 065bd768987c..2d5a57669a79 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -31,6 +31,7 @@ #include <plat/omap-pm.h> #include <plat/omap_hwmod.h> #include <plat/multi.h> +#include <plat/dma.h> #include "iomap.h" #include "voltage.h" diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 65f0d2571c9a..80f3ced0bd1a 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -25,6 +25,7 @@ #include <mach/hardware.h> #include "iomap.h" +#include "common.h" /* selected INTC register offsets */ @@ -334,7 +335,7 @@ void omap_intc_restore_context(void) void omap3_intc_suspend(void) { /* A pending interrupt would prevent OMAP from entering suspend */ - omap_ack_irq(0); + omap_ack_irq(NULL); } void omap3_intc_prepare_idle(void) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 65c33911341f..3268ee24eada 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -247,7 +247,7 @@ int __init omap_mux_init_signal(const char *muxname, int val) int mux_mode; mux_mode = omap_mux_get_by_name(muxname, &partition, &mux); - if (mux_mode < 0) + if (mux_mode < 0 || !mux) return mux_mode; old_mode = omap_mux_read(partition, mux->reg_offset); diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index d8f8ef40290f..d9ae4a53d818 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -18,6 +18,7 @@ #include <asm/cacheflush.h> #include <asm/memblock.h> +#include <plat/omap-secure.h> #include <mach/omap-secure.h> static phys_addr_t omap_secure_memblock_base; diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 42cd7fb52414..d811c7790350 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -259,7 +259,7 @@ static void irq_save_context(void) /* * Clear WakeupGen SAR backup status. */ -void irq_sar_clear(void) +static void irq_sar_clear(void) { u32 val; val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2c27fdb61e66..bf86f7e8f91f 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2,7 +2,7 @@ * omap_hwmod implementation for OMAP2/3/4 * * Copyright (C) 2009-2011 Nokia Corporation - * Copyright (C) 2011 Texas Instruments, Inc. + * Copyright (C) 2011-2012 Texas Instruments, Inc. * * Paul Walmsley, Benoît Cousson, Kevin Hilman * @@ -137,6 +137,7 @@ #include <linux/mutex.h> #include <linux/spinlock.h> #include <linux/slab.h> +#include <linux/bootmem.h> #include "common.h" #include <plat/cpu.h> @@ -159,16 +160,58 @@ /* Name of the OMAP hwmod for the MPU */ #define MPU_INITIATOR_NAME "mpu" +/* + * Number of struct omap_hwmod_link records per struct + * omap_hwmod_ocp_if record (master->slave and slave->master) + */ +#define LINKS_PER_OCP_IF 2 + /* omap_hwmod_list contains all registered struct omap_hwmods */ static LIST_HEAD(omap_hwmod_list); /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ static struct omap_hwmod *mpu_oh; +/* + * linkspace: ptr to a buffer that struct omap_hwmod_link records are + * allocated from - used to reduce the number of small memory + * allocations, which has a significant impact on performance + */ +static struct omap_hwmod_link *linkspace; + +/* + * free_ls, max_ls: array indexes into linkspace; representing the + * next free struct omap_hwmod_link index, and the maximum number of + * struct omap_hwmod_link records allocated (respectively) + */ +static unsigned short free_ls, max_ls, ls_supp; /* Private functions */ /** + * _fetch_next_ocp_if - return the next OCP interface in a list + * @p: ptr to a ptr to the list_head inside the ocp_if to return + * @i: pointer to the index of the element pointed to by @p in the list + * + * Return a pointer to the struct omap_hwmod_ocp_if record + * containing the struct list_head pointed to by @p, and increment + * @p such that a future call to this routine will return the next + * record. + */ +static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, + int *i) +{ + struct omap_hwmod_ocp_if *oi; + + oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; + *p = (*p)->next; + + *i = *i + 1; + + return oi; +} + +/** * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy * @oh: struct omap_hwmod * * @@ -582,16 +625,16 @@ static int _init_main_clk(struct omap_hwmod *oh) */ static int _init_interface_clks(struct omap_hwmod *oh) { + struct omap_hwmod_ocp_if *os; + struct list_head *p; struct clk *c; - int i; + int i = 0; int ret = 0; - if (oh->slaves_cnt == 0) - return 0; - - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; + p = oh->slave_ports.next; + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); if (!os->clk) continue; @@ -643,21 +686,22 @@ static int _init_opt_clks(struct omap_hwmod *oh) */ static int _enable_clocks(struct omap_hwmod *oh) { - int i; + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int i = 0; pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); if (oh->_clk) clk_enable(oh->_clk); - if (oh->slaves_cnt > 0) { - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; - struct clk *c = os->_clk; + p = oh->slave_ports.next; - if (c && (os->flags & OCPIF_SWSUP_IDLE)) - clk_enable(c); - } + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + + if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) + clk_enable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -673,21 +717,22 @@ static int _enable_clocks(struct omap_hwmod *oh) */ static int _disable_clocks(struct omap_hwmod *oh) { - int i; + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int i = 0; pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); if (oh->_clk) clk_disable(oh->_clk); - if (oh->slaves_cnt > 0) { - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; - struct clk *c = os->_clk; + p = oh->slave_ports.next; - if (c && (os->flags & OCPIF_SWSUP_IDLE)) - clk_disable(c); - } + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + + if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) + clk_disable(os->_clk); } /* The opt clocks are controlled by the device driver. */ @@ -781,39 +826,6 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh) } /** - * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 - * @oh: struct omap_hwmod * - * - * Disable the PRCM module mode related to the hwmod @oh. - * Return EINVAL if the modulemode is not supported and 0 in case of success. - */ -static int _omap4_disable_module(struct omap_hwmod *oh) -{ - int v; - - /* The module mode does not exist prior OMAP4 */ - if (!cpu_is_omap44xx()) - return -EINVAL; - - if (!oh->clkdm || !oh->prcm.omap4.modulemode) - return -EINVAL; - - pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); - - omap4_cminst_module_disable(oh->clkdm->prcm_partition, - oh->clkdm->cm_inst, - oh->clkdm->clkdm_offs, - oh->prcm.omap4.clkctrl_offs); - - v = _omap4_wait_target_disable(oh); - if (v) - pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", - oh->name); - - return 0; -} - -/** * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh * @oh: struct omap_hwmod *oh * @@ -883,59 +895,220 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) } /** - * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use - * @oh: struct omap_hwmod * + * _get_mpu_irq_by_name - fetch MPU interrupt line number by name + * @oh: struct omap_hwmod * to operate on + * @name: pointer to the name of the MPU interrupt number to fetch (optional) + * @irq: pointer to an unsigned int to store the MPU IRQ number to * - * Returns the array index of the OCP slave port that the MPU - * addresses the device on, or -EINVAL upon error or not found. + * Retrieve a MPU hardware IRQ line number named by @name associated + * with the IP block pointed to by @oh. The IRQ number will be filled + * into the address pointed to by @dma. When @name is non-null, the + * IRQ line number associated with the named entry will be returned. + * If @name is null, the first matching entry will be returned. Data + * order is not meaningful in hwmod data, so callers are strongly + * encouraged to use a non-null @name whenever possible to avoid + * unpredictable effects if hwmod data is later added that causes data + * ordering to change. Returns 0 upon success or a negative error + * code upon error. */ -static int __init _find_mpu_port_index(struct omap_hwmod *oh) +static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, + unsigned int *irq) { int i; - int found = 0; + bool found = false; - if (!oh || oh->slaves_cnt == 0) - return -EINVAL; + if (!oh->mpu_irqs) + return -ENOENT; - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; + i = 0; + while (oh->mpu_irqs[i].irq != -1) { + if (name == oh->mpu_irqs[i].name || + !strcmp(name, oh->mpu_irqs[i].name)) { + found = true; + break; + } + i++; + } - if (os->user & OCP_USER_MPU) { - found = 1; + if (!found) + return -ENOENT; + + *irq = oh->mpu_irqs[i].irq; + + return 0; +} + +/** + * _get_sdma_req_by_name - fetch SDMA request line ID by name + * @oh: struct omap_hwmod * to operate on + * @name: pointer to the name of the SDMA request line to fetch (optional) + * @dma: pointer to an unsigned int to store the request line ID to + * + * Retrieve an SDMA request line ID named by @name on the IP block + * pointed to by @oh. The ID will be filled into the address pointed + * to by @dma. When @name is non-null, the request line ID associated + * with the named entry will be returned. If @name is null, the first + * matching entry will be returned. Data order is not meaningful in + * hwmod data, so callers are strongly encouraged to use a non-null + * @name whenever possible to avoid unpredictable effects if hwmod + * data is later added that causes data ordering to change. Returns 0 + * upon success or a negative error code upon error. + */ +static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, + unsigned int *dma) +{ + int i; + bool found = false; + + if (!oh->sdma_reqs) + return -ENOENT; + + i = 0; + while (oh->sdma_reqs[i].dma_req != -1) { + if (name == oh->sdma_reqs[i].name || + !strcmp(name, oh->sdma_reqs[i].name)) { + found = true; break; } + i++; } - if (found) - pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", - oh->name, i); - else - pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", - oh->name); + if (!found) + return -ENOENT; + + *dma = oh->sdma_reqs[i].dma_req; - return (found) ? i : -EINVAL; + return 0; } /** - * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU - * @oh: struct omap_hwmod * + * _get_addr_space_by_name - fetch address space start & end by name + * @oh: struct omap_hwmod * to operate on + * @name: pointer to the name of the address space to fetch (optional) + * @pa_start: pointer to a u32 to store the starting address to + * @pa_end: pointer to a u32 to store the ending address to * - * Return the virtual address of the base of the register target of - * device @oh, or NULL on error. + * Retrieve address space start and end addresses for the IP block + * pointed to by @oh. The data will be filled into the addresses + * pointed to by @pa_start and @pa_end. When @name is non-null, the + * address space data associated with the named entry will be + * returned. If @name is null, the first matching entry will be + * returned. Data order is not meaningful in hwmod data, so callers + * are strongly encouraged to use a non-null @name whenever possible + * to avoid unpredictable effects if hwmod data is later added that + * causes data ordering to change. Returns 0 upon success or a + * negative error code upon error. */ -static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) +static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, + u32 *pa_start, u32 *pa_end) { + int i, j; struct omap_hwmod_ocp_if *os; - struct omap_hwmod_addr_space *mem; - int i = 0, found = 0; - void __iomem *va_start; + struct list_head *p = NULL; + bool found = false; + + p = oh->slave_ports.next; + + i = 0; + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + + if (!os->addr) + return -ENOENT; + + j = 0; + while (os->addr[j].pa_start != os->addr[j].pa_end) { + if (name == os->addr[j].name || + !strcmp(name, os->addr[j].name)) { + found = true; + break; + } + j++; + } + + if (found) + break; + } + + if (!found) + return -ENOENT; - if (!oh || oh->slaves_cnt == 0) + *pa_start = os->addr[j].pa_start; + *pa_end = os->addr[j].pa_end; + + return 0; +} + +/** + * _save_mpu_port_index - find and save the index to @oh's MPU port + * @oh: struct omap_hwmod * + * + * Determines the array index of the OCP slave port that the MPU uses + * to address the device, and saves it into the struct omap_hwmod. + * Intended to be called during hwmod registration only. No return + * value. + */ +static void __init _save_mpu_port_index(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os = NULL; + struct list_head *p; + int i = 0; + + if (!oh) + return; + + oh->_int_flags |= _HWMOD_NO_MPU_PORT; + + p = oh->slave_ports.next; + + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + if (os->user & OCP_USER_MPU) { + oh->_mpu_port = os; + oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; + break; + } + } + + return; +} + +/** + * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU + * @oh: struct omap_hwmod * + * + * Given a pointer to a struct omap_hwmod record @oh, return a pointer + * to the struct omap_hwmod_ocp_if record that is used by the MPU to + * communicate with the IP block. This interface need not be directly + * connected to the MPU (and almost certainly is not), but is directly + * connected to the IP block represented by @oh. Returns a pointer + * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon + * error or if there does not appear to be a path from the MPU to this + * IP block. + */ +static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) +{ + if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) return NULL; - os = oh->slaves[index]; + return oh->_mpu_port; +}; - if (!os->addr) +/** + * _find_mpu_rt_addr_space - return MPU register target address space for @oh + * @oh: struct omap_hwmod * + * + * Returns a pointer to the struct omap_hwmod_addr_space record representing + * the register target MPU address space; or returns NULL upon error. + */ +static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + struct omap_hwmod_addr_space *mem; + int found = 0, i = 0; + + os = _find_mpu_rt_port(oh); + if (!os || !os->addr) return NULL; do { @@ -944,20 +1117,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) found = 1; } while (!found && mem->pa_start != mem->pa_end); - if (found) { - va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); - if (!va_start) { - pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); - return NULL; - } - pr_debug("omap_hwmod: %s: MPU register target at va %p\n", - oh->name, va_start); - } else { - pr_debug("omap_hwmod: %s: no MPU register target found\n", - oh->name); - } - - return (found) ? va_start : NULL; + return (found) ? mem : NULL; } /** @@ -1205,12 +1365,11 @@ static int _wait_target_ready(struct omap_hwmod *oh) if (!oh) return -EINVAL; - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + if (oh->flags & HWMOD_NO_IDLEST) return 0; - os = oh->slaves[oh->_mpu_port_index]; - - if (oh->flags & HWMOD_NO_IDLEST) + os = _find_mpu_rt_port(oh); + if (!os) return 0; /* XXX check module SIDLEMODE */ @@ -1378,13 +1537,73 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) } /** + * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset + * @oh: struct omap_hwmod * + * + * If any hardreset line associated with @oh is asserted, then return true. + * Otherwise, if @oh has no hardreset lines associated with it, or if + * no hardreset lines associated with @oh are asserted, then return false. + * This function is used to avoid executing some parts of the IP block + * enable/disable sequence if a hardreset line is set. + */ +static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) +{ + int i; + + if (oh->rst_lines_cnt == 0) + return false; + + for (i = 0; i < oh->rst_lines_cnt; i++) + if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) + return true; + + return false; +} + +/** + * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 + * @oh: struct omap_hwmod * + * + * Disable the PRCM module mode related to the hwmod @oh. + * Return EINVAL if the modulemode is not supported and 0 in case of success. + */ +static int _omap4_disable_module(struct omap_hwmod *oh) +{ + int v; + + /* The module mode does not exist prior OMAP4 */ + if (!cpu_is_omap44xx()) + return -EINVAL; + + if (!oh->clkdm || !oh->prcm.omap4.modulemode) + return -EINVAL; + + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); + + omap4_cminst_module_disable(oh->clkdm->prcm_partition, + oh->clkdm->cm_inst, + oh->clkdm->clkdm_offs, + oh->prcm.omap4.clkctrl_offs); + + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + + v = _omap4_wait_target_disable(oh); + if (v) + pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", + oh->name); + + return 0; +} + +/** * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit * @oh: struct omap_hwmod * * * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be - * enabled for this to work. Returns -EINVAL if the hwmod cannot be - * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if - * the module did not reset in time, or 0 upon success. + * enabled for this to work. Returns -ENOENT if the hwmod cannot be + * reset this way, -EINVAL if the hwmod is in the wrong state, + * -ETIMEDOUT if the module did not reset in time, or 0 upon success. * * In OMAP3 a specific SYSSTATUS register is used to get the reset status. * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead @@ -1401,7 +1620,7 @@ static int _ocp_softreset(struct omap_hwmod *oh) if (!oh->class->sysc || !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) - return -EINVAL; + return -ENOENT; /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { @@ -1422,6 +1641,9 @@ static int _ocp_softreset(struct omap_hwmod *oh) goto dis_opt_clks; _write_sysconfig(v, oh); + if (oh->class->sysc->srst_udelay) + udelay(oh->class->sysc->srst_udelay); + if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) @@ -1459,32 +1681,60 @@ dis_opt_clks: * _reset - reset an omap_hwmod * @oh: struct omap_hwmod * * - * Resets an omap_hwmod @oh. The default software reset mechanism for - * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET - * bit. However, some hwmods cannot be reset via this method: some - * are not targets and therefore have no OCP header registers to - * access; others (like the IVA) have idiosyncratic reset sequences. - * So for these relatively rare cases, custom reset code can be - * supplied in the struct omap_hwmod_class .reset function pointer. - * Passes along the return value from either _reset() or the custom - * reset function - these must return -EINVAL if the hwmod cannot be - * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if - * the module did not reset in time, or 0 upon success. + * Resets an omap_hwmod @oh. If the module has a custom reset + * function pointer defined, then call it to reset the IP block, and + * pass along its return value to the caller. Otherwise, if the IP + * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield + * associated with it, call a function to reset the IP block via that + * method, and pass along the return value to the caller. Finally, if + * the IP block has some hardreset lines associated with it, assert + * all of those, but do _not_ deassert them. (This is because driver + * authors have expressed an apparent requirement to control the + * deassertion of the hardreset lines themselves.) + * + * The default software reset mechanism for most OMAP IP blocks is + * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some + * hwmods cannot be reset via this method. Some are not targets and + * therefore have no OCP header registers to access. Others (like the + * IVA) have idiosyncratic reset sequences. So for these relatively + * rare cases, custom reset code can be supplied in the struct + * omap_hwmod_class .reset function pointer. Passes along the return + * value from either _ocp_softreset() or the custom reset function - + * these must return -EINVAL if the hwmod cannot be reset this way or + * if the hwmod is in the wrong state, -ETIMEDOUT if the module did + * not reset in time, or 0 upon success. */ static int _reset(struct omap_hwmod *oh) { - int ret; + int i, r; pr_debug("omap_hwmod: %s: resetting\n", oh->name); - ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); + if (oh->class->reset) { + r = oh->class->reset(oh); + } else { + if (oh->rst_lines_cnt > 0) { + for (i = 0; i < oh->rst_lines_cnt; i++) + _assert_hardreset(oh, oh->rst_lines[i].name); + return 0; + } else { + r = _ocp_softreset(oh); + if (r == -ENOENT) + r = 0; + } + } + /* + * OCP_SYSCONFIG bits need to be reprogrammed after a + * softreset. The _enable() function should be split to avoid + * the rewrite of the OCP_SYSCONFIG register. + */ if (oh->class->sysc) { _update_sysc_cache(oh); _enable_sysc(oh); } - return ret; + return r; } /** @@ -1503,10 +1753,9 @@ static int _enable(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling\n", oh->name); /* - * hwmods with HWMOD_INIT_NO_IDLE flag set are left - * in enabled state at init. - * Now that someone is really trying to enable them, - * just ensure that the hwmod mux is set. + * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled + * state at init. Now that someone is really trying to enable + * them, just ensure that the hwmod mux is set. */ if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { /* @@ -1529,15 +1778,17 @@ static int _enable(struct omap_hwmod *oh) return -EINVAL; } - /* - * If an IP contains only one HW reset line, then de-assert it in order - * to allow the module state transition. Otherwise the PRCM will return - * Intransition status, and the init will failed. + * If an IP block contains HW reset lines and any of them are + * asserted, we let integration code associated with that + * block handle the enable. We've received very little + * information on what those driver authors need, and until + * detailed information is provided and the driver code is + * posted to the public lists, this is probably the best we + * can do. */ - if ((oh->_state == _HWMOD_STATE_INITIALIZED || - oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) - _deassert_hardreset(oh, oh->rst_lines[0].name); + if (_are_any_hardreset_lines_asserted(oh)) + return 0; /* Mux pins for device runtime if populated */ if (oh->mux && (!oh->mux->enabled || @@ -1612,6 +1863,9 @@ static int _idle(struct omap_hwmod *oh) return -EINVAL; } + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + if (oh->class->sysc) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); @@ -1684,7 +1938,7 @@ int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) */ static int _shutdown(struct omap_hwmod *oh) { - int ret; + int ret, i; u8 prev_state; if (oh->_state != _HWMOD_STATE_IDLE && @@ -1694,6 +1948,9 @@ static int _shutdown(struct omap_hwmod *oh) return -EINVAL; } + if (_are_any_hardreset_lines_asserted(oh)) + return 0; + pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->pre_shutdown) { @@ -1725,12 +1982,8 @@ static int _shutdown(struct omap_hwmod *oh) } /* XXX Should this code also force-disable the optional clocks? */ - /* - * If an IP contains only one HW reset line, then assert it - * after disabling the clocks and before shutting down the IP. - */ - if (oh->rst_lines_cnt == 1) - _assert_hardreset(oh, oh->rst_lines[0].name); + for (i = 0; i < oh->rst_lines_cnt; i++) + _assert_hardreset(oh, oh->rst_lines[i].name); /* Mux pins to safe mode or use populated off mode values */ if (oh->mux) @@ -1742,59 +1995,186 @@ static int _shutdown(struct omap_hwmod *oh) } /** - * _setup - do initial configuration of omap_hwmod - * @oh: struct omap_hwmod * + * _init_mpu_rt_base - populate the virtual address for a hwmod + * @oh: struct omap_hwmod * to locate the virtual address * - * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. Returns 0. + * Cache the virtual address used by the MPU to access this IP block's + * registers. This address is needed early so the OCP registers that + * are part of the device's address space can be ioremapped properly. + * No return value. */ -static int _setup(struct omap_hwmod *oh, void *data) +static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) { - int i, r; - u8 postsetup_state; + struct omap_hwmod_addr_space *mem; + void __iomem *va_start; + + if (!oh) + return; + + _save_mpu_port_index(oh); + + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return; + + mem = _find_mpu_rt_addr_space(oh); + if (!mem) { + pr_debug("omap_hwmod: %s: no MPU register target found\n", + oh->name); + return; + } + + va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); + if (!va_start) { + pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); + return; + } + + pr_debug("omap_hwmod: %s: MPU register target at va %p\n", + oh->name, va_start); + + oh->_mpu_rt_va = va_start; +} + +/** + * _init - initialize internal data for the hwmod @oh + * @oh: struct omap_hwmod * + * @n: (unused) + * + * Look up the clocks and the address space used by the MPU to access + * registers belonging to the hwmod @oh. @oh must already be + * registered at this point. This is the first of two phases for + * hwmod initialization. Code called here does not touch any hardware + * registers, it simply prepares internal data structures. Returns 0 + * upon success or if the hwmod isn't registered, or -EINVAL upon + * failure. + */ +static int __init _init(struct omap_hwmod *oh, void *data) +{ + int r; - if (oh->_state != _HWMOD_STATE_CLKS_INITED) + if (oh->_state != _HWMOD_STATE_REGISTERED) return 0; - /* Set iclk autoidle mode */ - if (oh->slaves_cnt > 0) { - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os = oh->slaves[i]; - struct clk *c = os->_clk; + _init_mpu_rt_base(oh, NULL); - if (!c) - continue; + r = _init_clocks(oh, NULL); + if (IS_ERR_VALUE(r)) { + WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); + return -EINVAL; + } - if (os->flags & OCPIF_SWSUP_IDLE) { - /* XXX omap_iclk_deny_idle(c); */ - } else { - /* XXX omap_iclk_allow_idle(c); */ - clk_enable(c); - } + oh->_state = _HWMOD_STATE_INITIALIZED; + + return 0; +} + +/** + * _setup_iclk_autoidle - configure an IP block's interface clocks + * @oh: struct omap_hwmod * + * + * Set up the module's interface clocks. XXX This function is still mostly + * a stub; implementing this properly requires iclk autoidle usecounting in + * the clock code. No return value. + */ +static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) +{ + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int i = 0; + if (oh->_state != _HWMOD_STATE_INITIALIZED) + return; + + p = oh->slave_ports.next; + + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + if (!os->_clk) + continue; + + if (os->flags & OCPIF_SWSUP_IDLE) { + /* XXX omap_iclk_deny_idle(c); */ + } else { + /* XXX omap_iclk_allow_idle(c); */ + clk_enable(os->_clk); } } - oh->_state = _HWMOD_STATE_INITIALIZED; + return; +} - /* - * In the case of hwmod with hardreset that should not be - * de-assert at boot time, we have to keep the module - * initialized, because we cannot enable it properly with the - * reset asserted. Exit without warning because that behavior is - * expected. - */ - if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) - return 0; +/** + * _setup_reset - reset an IP block during the setup process + * @oh: struct omap_hwmod * + * + * Reset the IP block corresponding to the hwmod @oh during the setup + * process. The IP block is first enabled so it can be successfully + * reset. Returns 0 upon success or a negative error code upon + * failure. + */ +static int __init _setup_reset(struct omap_hwmod *oh) +{ + int r; - r = _enable(oh); - if (r) { - pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", - oh->name, oh->_state); - return 0; + if (oh->_state != _HWMOD_STATE_INITIALIZED) + return -EINVAL; + + if (oh->rst_lines_cnt == 0) { + r = _enable(oh); + if (r) { + pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", + oh->name, oh->_state); + return -EINVAL; + } } if (!(oh->flags & HWMOD_INIT_NO_RESET)) - _reset(oh); + r = _reset(oh); + + return r; +} + +/** + * _setup_postsetup - transition to the appropriate state after _setup + * @oh: struct omap_hwmod * + * + * Place an IP block represented by @oh into a "post-setup" state -- + * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that + * this function is called at the end of _setup().) The postsetup + * state for an IP block can be changed by calling + * omap_hwmod_enter_postsetup_state() early in the boot process, + * before one of the omap_hwmod_setup*() functions are called for the + * IP block. + * + * The IP block stays in this state until a PM runtime-based driver is + * loaded for that IP block. A post-setup state of IDLE is + * appropriate for almost all IP blocks with runtime PM-enabled + * drivers, since those drivers are able to enable the IP block. A + * post-setup state of ENABLED is appropriate for kernels with PM + * runtime disabled. The DISABLED state is appropriate for unusual IP + * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers + * included, since the WDTIMER starts running on reset and will reset + * the MPU if left active. + * + * This post-setup mechanism is deprecated. Once all of the OMAP + * drivers have been converted to use PM runtime, and all of the IP + * block data and interconnect data is available to the hwmod code, it + * should be possible to replace this mechanism with a "lazy reset" + * arrangement. In a "lazy reset" setup, each IP block is enabled + * when the driver first probes, then all remaining IP blocks without + * drivers are either shut down or enabled after the drivers have + * loaded. However, this cannot take place until the above + * preconditions have been met, since otherwise the late reset code + * has no way of knowing which IP blocks are in use by drivers, and + * which ones are unused. + * + * No return value. + */ +static void __init _setup_postsetup(struct omap_hwmod *oh) +{ + u8 postsetup_state; + + if (oh->rst_lines_cnt > 0) + return; postsetup_state = oh->_postsetup_state; if (postsetup_state == _HWMOD_STATE_UNKNOWN) @@ -1818,6 +2198,35 @@ static int _setup(struct omap_hwmod *oh, void *data) WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", oh->name, postsetup_state); + return; +} + +/** + * _setup - prepare IP block hardware for use + * @oh: struct omap_hwmod * + * @n: (unused, pass NULL) + * + * Configure the IP block represented by @oh. This may include + * enabling the IP block, resetting it, and placing it into a + * post-setup state, depending on the type of IP block and applicable + * flags. IP blocks are reset to prevent any previous configuration + * by the bootloader or previous operating system from interfering + * with power management or other parts of the system. The reset can + * be avoided; see omap_hwmod_no_setup_reset(). This is the second of + * two phases for hwmod initialization. Code called here generally + * affects the IP block hardware, or system integration hardware + * associated with the IP block. Returns 0. + */ +static int __init _setup(struct omap_hwmod *oh, void *data) +{ + if (oh->_state != _HWMOD_STATE_INITIALIZED) + return 0; + + _setup_iclk_autoidle(oh); + + if (!_setup_reset(oh)) + _setup_postsetup(oh); + return 0; } @@ -1840,8 +2249,6 @@ static int _setup(struct omap_hwmod *oh, void *data) */ static int __init _register(struct omap_hwmod *oh) { - int ms_id; - if (!oh || !oh->name || !oh->class || !oh->class->name || (oh->_state != _HWMOD_STATE_UNKNOWN)) return -EINVAL; @@ -1851,14 +2258,10 @@ static int __init _register(struct omap_hwmod *oh) if (_lookup(oh->name)) return -EEXIST; - ms_id = _find_mpu_port_index(oh); - if (!IS_ERR_VALUE(ms_id)) - oh->_mpu_port_index = ms_id; - else - oh->_int_flags |= _HWMOD_NO_MPU_PORT; - list_add_tail(&oh->node, &omap_hwmod_list); + INIT_LIST_HEAD(&oh->master_ports); + INIT_LIST_HEAD(&oh->slave_ports); spin_lock_init(&oh->_lock); oh->_state = _HWMOD_STATE_REGISTERED; @@ -1873,6 +2276,160 @@ static int __init _register(struct omap_hwmod *oh) return 0; } +/** + * _alloc_links - return allocated memory for hwmod links + * @ml: pointer to a struct omap_hwmod_link * for the master link + * @sl: pointer to a struct omap_hwmod_link * for the slave link + * + * Return pointers to two struct omap_hwmod_link records, via the + * addresses pointed to by @ml and @sl. Will first attempt to return + * memory allocated as part of a large initial block, but if that has + * been exhausted, will allocate memory itself. Since ideally this + * second allocation path will never occur, the number of these + * 'supplemental' allocations will be logged when debugging is + * enabled. Returns 0. + */ +static int __init _alloc_links(struct omap_hwmod_link **ml, + struct omap_hwmod_link **sl) +{ + unsigned int sz; + + if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { + *ml = &linkspace[free_ls++]; + *sl = &linkspace[free_ls++]; + return 0; + } + + sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; + + *sl = NULL; + *ml = alloc_bootmem(sz); + + memset(*ml, 0, sz); + + *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); + + ls_supp++; + pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", + ls_supp * LINKS_PER_OCP_IF); + + return 0; +}; + +/** + * _add_link - add an interconnect between two IP blocks + * @oi: pointer to a struct omap_hwmod_ocp_if record + * + * Add struct omap_hwmod_link records connecting the master IP block + * specified in @oi->master to @oi, and connecting the slave IP block + * specified in @oi->slave to @oi. This code is assumed to run before + * preemption or SMP has been enabled, thus avoiding the need for + * locking in this code. Changes to this assumption will require + * additional locking. Returns 0. + */ +static int __init _add_link(struct omap_hwmod_ocp_if *oi) +{ + struct omap_hwmod_link *ml, *sl; + + pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, + oi->slave->name); + + _alloc_links(&ml, &sl); + + ml->ocp_if = oi; + INIT_LIST_HEAD(&ml->node); + list_add(&ml->node, &oi->master->master_ports); + oi->master->masters_cnt++; + + sl->ocp_if = oi; + INIT_LIST_HEAD(&sl->node); + list_add(&sl->node, &oi->slave->slave_ports); + oi->slave->slaves_cnt++; + + return 0; +} + +/** + * _register_link - register a struct omap_hwmod_ocp_if + * @oi: struct omap_hwmod_ocp_if * + * + * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it + * has already been registered; -EINVAL if @oi is NULL or if the + * record pointed to by @oi is missing required fields; or 0 upon + * success. + * + * XXX The data should be copied into bootmem, so the original data + * should be marked __initdata and freed after init. This would allow + * unneeded omap_hwmods to be freed on multi-OMAP configurations. + */ +static int __init _register_link(struct omap_hwmod_ocp_if *oi) +{ + if (!oi || !oi->master || !oi->slave || !oi->user) + return -EINVAL; + + if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) + return -EEXIST; + + pr_debug("omap_hwmod: registering link from %s to %s\n", + oi->master->name, oi->slave->name); + + /* + * Register the connected hwmods, if they haven't been + * registered already + */ + if (oi->master->_state != _HWMOD_STATE_REGISTERED) + _register(oi->master); + + if (oi->slave->_state != _HWMOD_STATE_REGISTERED) + _register(oi->slave); + + _add_link(oi); + + oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; + + return 0; +} + +/** + * _alloc_linkspace - allocate large block of hwmod links + * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count + * + * Allocate a large block of struct omap_hwmod_link records. This + * improves boot time significantly by avoiding the need to allocate + * individual records one by one. If the number of records to + * allocate in the block hasn't been manually specified, this function + * will count the number of struct omap_hwmod_ocp_if records in @ois + * and use that to determine the allocation size. For SoC families + * that require multiple list registrations, such as OMAP3xxx, this + * estimation process isn't optimal, so manual estimation is advised + * in those cases. Returns -EEXIST if the allocation has already occurred + * or 0 upon success. + */ +static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) +{ + unsigned int i = 0; + unsigned int sz; + + if (linkspace) { + WARN(1, "linkspace already allocated\n"); + return -EEXIST; + } + + if (max_ls == 0) + while (ois[i++]) + max_ls += LINKS_PER_OCP_IF; + + sz = sizeof(struct omap_hwmod_link) * max_ls; + + pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", + __func__, sz, max_ls); + + linkspace = alloc_bootmem(sz); + + memset(linkspace, 0, sz); + + return 0; +} /* Public functions */ @@ -1903,10 +2460,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) */ int omap_hwmod_softreset(struct omap_hwmod *oh) { - if (!oh) + u32 v; + int ret; + + if (!oh || !(oh->_sysc_cache)) return -EINVAL; - return _ocp_softreset(oh); + v = oh->_sysc_cache; + ret = _set_softreset(oh, &v); + if (ret) + goto error; + _write_sysconfig(v, oh); + +error: + return ret; } /** @@ -1991,120 +2558,101 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), } /** - * omap_hwmod_register - register an array of hwmods - * @ohs: pointer to an array of omap_hwmods to register + * omap_hwmod_register_links - register an array of hwmod links + * @ois: pointer to an array of omap_hwmod_ocp_if to register * * Intended to be called early in boot before the clock framework is - * initialized. If @ohs is not null, will register all omap_hwmods - * listed in @ohs that are valid for this chip. Returns 0. + * initialized. If @ois is not null, will register all omap_hwmods + * listed in @ois that are valid for this chip. Returns 0. */ -int __init omap_hwmod_register(struct omap_hwmod **ohs) +int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) { int r, i; - if (!ohs) + if (!ois) return 0; + if (!linkspace) { + if (_alloc_linkspace(ois)) { + pr_err("omap_hwmod: could not allocate link space\n"); + return -ENOMEM; + } + } + i = 0; do { - r = _register(ohs[i]); - WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, - r); - } while (ohs[++i]); + r = _register_link(ois[i]); + WARN(r && r != -EEXIST, + "omap_hwmod: _register_link(%s -> %s) returned %d\n", + ois[i]->master->name, ois[i]->slave->name, r); + } while (ois[++i]); return 0; } -/* - * _populate_mpu_rt_base - populate the virtual address for a hwmod +/** + * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up + * @oh: pointer to the hwmod currently being set up (usually not the MPU) * - * Must be called only from omap_hwmod_setup_*() so ioremap works properly. - * Assumes the caller takes care of locking if needed. + * If the hwmod data corresponding to the MPU subsystem IP block + * hasn't been initialized and set up yet, do so now. This must be + * done first since sleep dependencies may be added from other hwmods + * to the MPU. Intended to be called only by omap_hwmod_setup*(). No + * return value. */ -static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) +static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) { - if (oh->_state != _HWMOD_STATE_REGISTERED) - return 0; - - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) - return 0; - - oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); - - return 0; + if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) + pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", + __func__, MPU_INITIATOR_NAME); + else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) + omap_hwmod_setup_one(MPU_INITIATOR_NAME); } /** * omap_hwmod_setup_one - set up a single hwmod * @oh_name: const char * name of the already-registered hwmod to set up * - * Must be called after omap2_clk_init(). Resolves the struct clk - * names to struct clk pointers for each registered omap_hwmod. Also - * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon - * success. + * Initialize and set up a single hwmod. Intended to be used for a + * small number of early devices, such as the timer IP blocks used for + * the scheduler clock. Must be called after omap2_clk_init(). + * Resolves the struct clk names to struct clk pointers for each + * registered omap_hwmod. Also calls _setup() on each hwmod. Returns + * -EINVAL upon error or 0 upon success. */ int __init omap_hwmod_setup_one(const char *oh_name) { struct omap_hwmod *oh; - int r; pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); - if (!mpu_oh) { - pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", - oh_name, MPU_INITIATOR_NAME); - return -EINVAL; - } - oh = _lookup(oh_name); if (!oh) { WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); return -EINVAL; } - if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) - omap_hwmod_setup_one(MPU_INITIATOR_NAME); - - r = _populate_mpu_rt_base(oh, NULL); - if (IS_ERR_VALUE(r)) { - WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); - return -EINVAL; - } - - r = _init_clocks(oh, NULL); - if (IS_ERR_VALUE(r)) { - WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); - return -EINVAL; - } + _ensure_mpu_hwmod_is_setup(oh); + _init(oh, NULL); _setup(oh, NULL); return 0; } /** - * omap_hwmod_setup - do some post-clock framework initialization + * omap_hwmod_setup_all - set up all registered IP blocks * - * Must be called after omap2_clk_init(). Resolves the struct clk names - * to struct clk pointers for each registered omap_hwmod. Also calls - * _setup() on each hwmod. Returns 0 upon success. + * Initialize and set up all IP blocks registered with the hwmod code. + * Must be called after omap2_clk_init(). Resolves the struct clk + * names to struct clk pointers for each registered omap_hwmod. Also + * calls _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) { - int r; - - if (!mpu_oh) { - pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", - __func__, MPU_INITIATOR_NAME); - return -EINVAL; - } - - r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); - - r = omap_hwmod_for_each(_init_clocks, NULL); - WARN(IS_ERR_VALUE(r), - "omap_hwmod: %s: _init_clocks failed\n", __func__); + _ensure_mpu_hwmod_is_setup(NULL); + omap_hwmod_for_each(_init, NULL); omap_hwmod_for_each(_setup, NULL); return 0; @@ -2261,6 +2809,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh) return r; } +/* + * IP block data retrieval functions + */ + /** * omap_hwmod_count_resources - count number of struct resources needed by hwmod * @oh: struct omap_hwmod * @@ -2279,12 +2831,19 @@ int omap_hwmod_reset(struct omap_hwmod *oh) */ int omap_hwmod_count_resources(struct omap_hwmod *oh) { - int ret, i; + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int ret; + int i = 0; ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); - for (i = 0; i < oh->slaves_cnt; i++) - ret += _count_ocp_if_addr_spaces(oh->slaves[i]); + p = oh->slave_ports.next; + + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); + ret += _count_ocp_if_addr_spaces(os); + } return ret; } @@ -2301,7 +2860,9 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) */ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) { - int i, j, mpu_irqs_cnt, sdma_reqs_cnt; + struct omap_hwmod_ocp_if *os; + struct list_head *p; + int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; int r = 0; /* For each IRQ, DMA, memory area, fill in array.*/ @@ -2324,11 +2885,11 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) r++; } - for (i = 0; i < oh->slaves_cnt; i++) { - struct omap_hwmod_ocp_if *os; - int addr_cnt; + p = oh->slave_ports.next; - os = oh->slaves[i]; + i = 0; + while (i < oh->slaves_cnt) { + os = _fetch_next_ocp_if(&p, &i); addr_cnt = _count_ocp_if_addr_spaces(os); for (j = 0; j < addr_cnt; j++) { @@ -2344,6 +2905,69 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) } /** + * omap_hwmod_get_resource_byname - fetch IP block integration data by name + * @oh: struct omap_hwmod * to operate on + * @type: one of the IORESOURCE_* constants from include/linux/ioport.h + * @name: pointer to the name of the data to fetch (optional) + * @rsrc: pointer to a struct resource, allocated by the caller + * + * Retrieve MPU IRQ, SDMA request line, or address space start/end + * data for the IP block pointed to by @oh. The data will be filled + * into a struct resource record pointed to by @rsrc. The struct + * resource must be allocated by the caller. When @name is non-null, + * the data associated with the matching entry in the IRQ/SDMA/address + * space hwmod data arrays will be returned. If @name is null, the + * first array entry will be returned. Data order is not meaningful + * in hwmod data, so callers are strongly encouraged to use a non-null + * @name whenever possible to avoid unpredictable effects if hwmod + * data is later added that causes data ordering to change. This + * function is only intended for use by OMAP core code. Device + * drivers should not call this function - the appropriate bus-related + * data accessor functions should be used instead. Returns 0 upon + * success or a negative error code upon error. + */ +int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, + const char *name, struct resource *rsrc) +{ + int r; + unsigned int irq, dma; + u32 pa_start, pa_end; + + if (!oh || !rsrc) + return -EINVAL; + + if (type == IORESOURCE_IRQ) { + r = _get_mpu_irq_by_name(oh, name, &irq); + if (r) + return r; + + rsrc->start = irq; + rsrc->end = irq; + } else if (type == IORESOURCE_DMA) { + r = _get_sdma_req_by_name(oh, name, &dma); + if (r) + return r; + + rsrc->start = dma; + rsrc->end = dma; + } else if (type == IORESOURCE_MEM) { + r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); + if (r) + return r; + + rsrc->start = pa_start; + rsrc->end = pa_end; + } else { + return -EINVAL; + } + + rsrc->flags = type; + rsrc->name = name; + + return 0; +} + +/** * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain * @oh: struct omap_hwmod * * @@ -2357,6 +2981,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { struct clk *c; + struct omap_hwmod_ocp_if *oi; if (!oh) return NULL; @@ -2364,9 +2989,10 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) if (oh->_clk) { c = oh->_clk; } else { - if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + oi = _find_mpu_rt_port(oh); + if (!oi) return NULL; - c = oh->slaves[oh->_mpu_port_index]->_clk; + c = oi->_clk; } if (!c->clkdm) @@ -2640,10 +3266,10 @@ int omap_hwmod_for_each_by_class(const char *classname, * @state: state that _setup() should leave the hwmod in * * Sets the hwmod state that @oh will enter at the end of _setup() - * (called by omap_hwmod_setup_*()). Only valid to call between - * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns - * 0 upon success or -EINVAL if there is a problem with the arguments - * or if the hwmod is in the wrong state. + * (called by omap_hwmod_setup_*()). See also the documentation + * for _setup_postsetup(), above. Returns 0 upon success or + * -EINVAL if there is a problem with the arguments or if the hwmod is + * in the wrong state. */ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) { diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a5409ce3f323..2c087ffc6a92 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -2,6 +2,7 @@ * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips * * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -32,707 +33,268 @@ /* * OMAP2420 hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap2420_mpu_hwmod; -static struct omap_hwmod omap2420_iva_hwmod; -static struct omap_hwmod omap2420_l3_main_hwmod; -static struct omap_hwmod omap2420_l4_core_hwmod; -static struct omap_hwmod omap2420_dss_core_hwmod; -static struct omap_hwmod omap2420_dss_dispc_hwmod; -static struct omap_hwmod omap2420_dss_rfbi_hwmod; -static struct omap_hwmod omap2420_dss_venc_hwmod; -static struct omap_hwmod omap2420_wd_timer2_hwmod; -static struct omap_hwmod omap2420_gpio1_hwmod; -static struct omap_hwmod omap2420_gpio2_hwmod; -static struct omap_hwmod omap2420_gpio3_hwmod; -static struct omap_hwmod omap2420_gpio4_hwmod; -static struct omap_hwmod omap2420_dma_system_hwmod; -static struct omap_hwmod omap2420_mcspi1_hwmod; -static struct omap_hwmod omap2420_mcspi2_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { - .master = &omap2420_l3_main_hwmod, - .slave = &omap2420_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { - .master = &omap2420_mpu_hwmod, - .slave = &omap2420_l3_main_hwmod, - .user = OCP_USER_MPU, -}; - -/* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { - &omap2420_mpu__l3_main, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap2420_dss__l3 = { - .master = &omap2420_dss_core_hwmod, - .slave = &omap2420_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { - &omap2420_l3_main__l4_core, -}; - -/* L3 */ -static struct omap_hwmod omap2420_l3_main_hwmod = { - .name = "l3_main", - .class = &l3_hwmod_class, - .masters = omap2420_l3_main_masters, - .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), - .slaves = omap2420_l3_main_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -static struct omap_hwmod omap2420_l4_wkup_hwmod; -static struct omap_hwmod omap2420_uart1_hwmod; -static struct omap_hwmod omap2420_uart2_hwmod; -static struct omap_hwmod omap2420_uart3_hwmod; -static struct omap_hwmod omap2420_i2c1_hwmod; -static struct omap_hwmod omap2420_i2c2_hwmod; -static struct omap_hwmod omap2420_mcbsp1_hwmod; -static struct omap_hwmod omap2420_mcbsp2_hwmod; - -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mcspi1_hwmod, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_mcspi2_hwmod, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Slave interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { - &omap2420_l3_main__l4_core, -}; - -/* Master interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { - &omap2420_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, - &omap2420_l4_core__i2c1, - &omap2420_l4_core__i2c2 -}; - -/* L4 CORE */ -static struct omap_hwmod omap2420_l4_core_hwmod = { - .name = "l4_core", - .class = &l4_hwmod_class, - .masters = omap2420_l4_core_masters, - .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), - .slaves = omap2420_l4_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* Slave interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { - &omap2420_l4_core__l4_wkup, -}; - -/* Master interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { -}; - -/* L4 WKUP */ -static struct omap_hwmod omap2420_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &l4_hwmod_class, - .masters = omap2420_l4_wkup_masters, - .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), - .slaves = omap2420_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* Master interfaces on the MPU device */ -static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { - &omap2420_mpu__l3_main, -}; - -/* MPU */ -static struct omap_hwmod omap2420_mpu_hwmod = { - .name = "mpu", - .class = &mpu_hwmod_class, - .main_clk = "mpu_ck", - .masters = omap2420_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), -}; - /* - * IVA1 interface data + * IP blocks */ -/* IVA <- L3 interface */ -static struct omap_hwmod_ocp_if omap2420_l3__iva = { - .master = &omap2420_l3_main_hwmod, - .slave = &omap2420_iva_hwmod, - .clk = "iva1_ifck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* IVA1 (IVA1) */ +static struct omap_hwmod_class iva1_hwmod_class = { + .name = "iva1", }; -static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { - &omap2420_l3__iva, +static struct omap_hwmod_rst_info omap2420_iva_resets[] = { + { .name = "iva", .rst_shift = 8 }, }; -/* - * IVA2 (IVA2) - */ - static struct omap_hwmod omap2420_iva_hwmod = { .name = "iva", - .class = &iva_hwmod_class, - .masters = omap2420_iva_masters, - .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), + .class = &iva1_hwmod_class, + .clkdm_name = "iva1_clkdm", + .rst_lines = omap2420_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets), + .main_clk = "iva1_ifck", }; -/* always-on timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, -}; - -/* pwm timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, -}; - -/* timer1 */ -static struct omap_hwmod omap2420_timer1_hwmod; - -static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { - { - .pa_start = 0x48028000, - .pa_end = 0x48028000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } +/* DSP */ +static struct omap_hwmod_class dsp_hwmod_class = { + .name = "dsp", }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap2420_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_rst_info omap2420_dsp_resets[] = { + { .name = "logic", .rst_shift = 0 }, + { .name = "mmu", .rst_shift = 1 }, }; -/* timer1 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { - &omap2420_l4_wkup__timer1, +static struct omap_hwmod omap2420_dsp_hwmod = { + .name = "dsp", + .class = &dsp_hwmod_class, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap2420_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets), + .main_clk = "dsp_fck", }; -/* timer1 hwmod */ -static struct omap_hwmod omap2420_timer1_hwmod = { - .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), - .class = &omap2xxx_timer_hwmod_class, +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, }; -/* timer2 */ -static struct omap_hwmod omap2420_timer2_hwmod; - -/* l4_core -> timer2 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, + .rev = OMAP_I2C_IP_VERSION_1, + .reset = &omap_i2c_reset, }; -/* timer2 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { - &omap2420_l4_core__timer2, +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_NO_FIFO | + OMAP_I2C_FLAG_SIMPLE_CLOCK | + OMAP_I2C_FLAG_16BIT_DATA_REG | + OMAP_I2C_FLAG_BUS_SHIFT_2, }; -/* timer2 hwmod */ -static struct omap_hwmod omap2420_timer2_hwmod = { - .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, - .main_clk = "gpt2_fck", +/* I2C1 */ +static struct omap_hwmod omap2420_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = omap2_i2c1_mpu_irqs, + .sdma_reqs = omap2_i2c1_sdma_reqs, + .main_clk = "i2c1_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT2_SHIFT, .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer3 */ -static struct omap_hwmod omap2420_timer3_hwmod; - -/* l4_core -> timer3 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { - &omap2420_l4_core__timer3, -}; - -/* timer3 hwmod */ -static struct omap_hwmod omap2420_timer3_hwmod = { - .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, - .main_clk = "gpt3_fck", - .prcm = { - .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT3_SHIFT, - .module_offs = CORE_MOD, + .module_bit = OMAP2420_EN_I2C1_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer4 */ -static struct omap_hwmod omap2420_timer4_hwmod; - -/* l4_core -> timer4 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { - &omap2420_l4_core__timer4, + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .flags = HWMOD_16BIT_REG, }; -/* timer4 hwmod */ -static struct omap_hwmod omap2420_timer4_hwmod = { - .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, - .main_clk = "gpt4_fck", +/* I2C2 */ +static struct omap_hwmod omap2420_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = omap2_i2c2_mpu_irqs, + .sdma_reqs = omap2_i2c2_sdma_reqs, + .main_clk = "i2c2_fck", .prcm = { .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT4_SHIFT, .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer5 */ -static struct omap_hwmod omap2420_timer5_hwmod; - -/* l4_core -> timer5 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer5 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { - &omap2420_l4_core__timer5, -}; - -/* timer5 hwmod */ -static struct omap_hwmod omap2420_timer5_hwmod = { - .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, - .main_clk = "gpt5_fck", - .prcm = { - .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT5_SHIFT, - .module_offs = CORE_MOD, + .module_bit = OMAP2420_EN_I2C2_SHIFT, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, + .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer5_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - - -/* timer6 */ -static struct omap_hwmod omap2420_timer6_hwmod; - -/* l4_core -> timer6 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer6 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { - &omap2420_l4_core__timer6, + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .flags = HWMOD_16BIT_REG, }; -/* timer6 hwmod */ -static struct omap_hwmod omap2420_timer6_hwmod = { - .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, - .main_clk = "gpt6_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT6_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer6_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), - .class = &omap2xxx_timer_hwmod_class, +/* dma attributes */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32, + .lch_count = 32, }; -/* timer7 */ -static struct omap_hwmod omap2420_timer7_hwmod; - -/* l4_core -> timer7 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod omap2420_dma_system_hwmod = { + .name = "dma", + .class = &omap2xxx_dma_hwmod_class, + .mpu_irqs = omap2_dma_system_irqs, + .main_clk = "core_l3_ck", + .dev_attr = &dma_dev_attr, + .flags = HWMOD_NO_IDLEST, }; -/* timer7 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { - &omap2420_l4_core__timer7, +/* mailbox */ +static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { + { .name = "dsp", .irq = 26 }, + { .name = "iva", .irq = 34 }, + { .irq = -1 } }; -/* timer7 hwmod */ -static struct omap_hwmod omap2420_timer7_hwmod = { - .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, - .main_clk = "gpt7_fck", +static struct omap_hwmod omap2420_mailbox_hwmod = { + .name = "mailbox", + .class = &omap2xxx_mailbox_hwmod_class, + .mpu_irqs = omap2420_mailbox_irqs, + .main_clk = "mailboxes_ick", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer7_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), - .class = &omap2xxx_timer_hwmod_class, }; -/* timer8 */ -static struct omap_hwmod omap2420_timer8_hwmod; +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ -/* l4_core -> timer8 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, +static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { + .name = "mcbsp", }; -/* timer8 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { - &omap2420_l4_core__timer8, +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .irq = -1 } }; -/* timer8 hwmod */ -static struct omap_hwmod omap2420_timer8_hwmod = { - .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, - .main_clk = "gpt8_fck", +static struct omap_hwmod omap2420_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2420_mcbsp_hwmod_class, + .mpu_irqs = omap2420_mcbsp1_irqs, + .sdma_reqs = omap2_mcbsp1_sdma_reqs, + .main_clk = "mcbsp1_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2420_timer8_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer9 */ -static struct omap_hwmod omap2420_timer9_hwmod; - -/* l4_core -> timer9 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer9 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { - &omap2420_l4_core__timer9, +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, + { .irq = -1 } }; -/* timer9 hwmod */ -static struct omap_hwmod omap2420_timer9_hwmod = { - .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, - .main_clk = "gpt9_fck", +static struct omap_hwmod omap2420_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap2420_mcbsp_hwmod_class, + .mpu_irqs = omap2420_mcbsp2_irqs, + .sdma_reqs = omap2_mcbsp2_sdma_reqs, + .main_clk = "mcbsp2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, .module_offs = CORE_MOD, .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, }, }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2420_timer9_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), - .class = &omap2xxx_timer_hwmod_class, }; -/* timer10 */ -static struct omap_hwmod omap2420_timer10_hwmod; +/* + * interfaces + */ -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2420_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer10 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { - &omap2420_l4_core__timer10, -}; - -/* timer10 hwmod */ -static struct omap_hwmod omap2420_timer10_hwmod = { - .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, - .main_clk = "gpt10_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT10_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2420_timer10_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), - .class = &omap2xxx_timer_hwmod_class, +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2420_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer11 */ -static struct omap_hwmod omap2420_timer11_hwmod; - -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, +/* IVA <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__iva = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2420_iva_hwmod, + .clk = "core_l3_ck", .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer11 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { - &omap2420_l4_core__timer11, +/* DSP <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__dsp = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2420_dsp_hwmod, + .clk = "dsp_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer11 hwmod */ -static struct omap_hwmod omap2420_timer11_hwmod = { - .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, - .main_clk = "gpt11_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT11_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, - }, +static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { + { + .pa_start = 0x48028000, + .pa_end = 0x48028000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2420_timer11_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), - .class = &omap2xxx_timer_hwmod_class, + { } }; -/* timer12 */ -static struct omap_hwmod omap2420_timer12_hwmod; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2420_timer1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* timer12 slave port */ -static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { - &omap2420_l4_core__timer12, -}; - -/* timer12 hwmod */ -static struct omap_hwmod omap2420_timer12_hwmod = { - .name = "timer12", - .mpu_irqs = omap2xxx_timer12_mpu_irqs, - .main_clk = "gpt12_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT12_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2420_timer12_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { { @@ -744,364 +306,13 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_wd_timer2_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_wd_timer2_hwmod, .clk = "mpu_wdt_ick", .addr = omap2420_wd_timer2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { - &omap2420_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap2420_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap2xxx_wd_timer_hwmod_class, - .main_clk = "mpu_wdt_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, - }, - }, - .slaves = omap2420_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), -}; - -/* UART1 */ - -static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { - &omap2_l4_core__uart1, -}; - -static struct omap_hwmod omap2420_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, - }, - }, - .slaves = omap2420_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), - .class = &omap2_uart_class, -}; - -/* UART2 */ - -static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { - &omap2_l4_core__uart2, -}; - -static struct omap_hwmod omap2420_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, - }, - }, - .slaves = omap2420_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), - .class = &omap2_uart_class, -}; - -/* UART3 */ - -static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { - &omap2_l4_core__uart3, -}; - -static struct omap_hwmod omap2420_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, - .slaves = omap2420_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), - .class = &omap2_uart_class, -}; - -/* dss */ -/* dss master ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { - &omap2420_dss__l3, -}; - -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { - &omap2420_l4_core__dss, -}; - -static struct omap_hwmod_opt_clk dss_opt_clks[] = { - /* - * The DSS HW needs all DSS clocks enabled during reset. The dss_core - * driver does not use these clocks. - */ - { .role = "tv_clk", .clk = "dss_54m_fck" }, - { .role = "sys_clk", .clk = "dss2_fck" }, -}; - -static struct omap_hwmod omap2420_dss_core_hwmod = { - .name = "dss_core", - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_fck", /* instead of dss_fck */ - .sdma_reqs = omap2xxx_dss_sdma_chs, - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap2420_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), - .masters = omap2420_dss_masters, - .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), - .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, -}; - -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_dispc slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { - &omap2420_l4_core__dss_dispc, -}; - -static struct omap_hwmod omap2420_dss_dispc_hwmod = { - .name = "dss_dispc", - .class = &omap2_dispc_hwmod_class, - .mpu_irqs = omap2_dispc_irqs, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .slaves = omap2420_dss_dispc_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), - .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr -}; - -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_rfbi slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { - &omap2420_l4_core__dss_rfbi, -}; - -static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { - { .role = "ick", .clk = "dss_ick" }, -}; - -static struct omap_hwmod omap2420_dss_rfbi_hwmod = { - .name = "dss_rfbi", - .class = &omap2_rfbi_hwmod_class, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .opt_clks = dss_rfbi_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .slaves = omap2420_dss_rfbi_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { - .master = &omap2420_l4_core_hwmod, - .slave = &omap2420_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, - .flags = OMAP_FIREWALL_L4, - } - }, - .flags = OCPIF_SWSUP_IDLE, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_venc slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { - &omap2420_l4_core__dss_venc, -}; - -static struct omap_hwmod omap2420_dss_venc_hwmod = { - .name = "dss_venc", - .class = &omap2_venc_hwmod_class, - .main_clk = "dss_54m_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .slaves = omap2420_dss_venc_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* I2C common */ -static struct omap_hwmod_class_sysconfig i2c_sysc = { - .rev_offs = 0x00, - .sysc_offs = 0x20, - .syss_offs = 0x10, - .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class i2c_class = { - .name = "i2c", - .sysc = &i2c_sysc, - .rev = OMAP_I2C_IP_VERSION_1, - .reset = &omap_i2c_reset, -}; - -static struct omap_i2c_dev_attr i2c_dev_attr = { - .flags = OMAP_I2C_FLAG_NO_FIFO | - OMAP_I2C_FLAG_SIMPLE_CLOCK | - OMAP_I2C_FLAG_16BIT_DATA_REG | - OMAP_I2C_FLAG_BUS_SHIFT_2, -}; - -/* I2C1 */ - -static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { - &omap2420_l4_core__i2c1, -}; - -static struct omap_hwmod omap2420_i2c1_hwmod = { - .name = "i2c1", - .mpu_irqs = omap2_i2c1_mpu_irqs, - .sdma_reqs = omap2_i2c1_sdma_reqs, - .main_clk = "i2c1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_I2C1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, - }, - }, - .slaves = omap2420_i2c1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), - .class = &i2c_class, - .dev_attr = &i2c_dev_attr, - .flags = HWMOD_16BIT_REG, -}; - -/* I2C2 */ - -static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { - &omap2420_l4_core__i2c2, -}; - -static struct omap_hwmod omap2420_i2c2_hwmod = { - .name = "i2c2", - .mpu_irqs = omap2_i2c2_mpu_irqs, - .sdma_reqs = omap2_i2c2_sdma_reqs, - .main_clk = "i2c2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP2420_EN_I2C2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, - }, - }, - .slaves = omap2420_i2c2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), - .class = &i2c_class, - .dev_attr = &i2c_dev_attr, - .flags = HWMOD_16BIT_REG, -}; - /* l4_wkup -> gpio1 */ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { { @@ -1113,8 +324,8 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio1_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio1_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio1_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -1131,8 +342,8 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio2_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio2_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio2_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -1149,8 +360,8 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio3_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio3_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio3_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -1167,408 +378,100 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { }; static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { - .master = &omap2420_l4_wkup_hwmod, - .slave = &omap2420_gpio4_hwmod, + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio4_hwmod, .clk = "gpios_ick", .addr = omap2420_gpio4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* gpio dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = false, -}; - -/* gpio1 */ -static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { - &omap2420_l4_wkup__gpio1, -}; - -static struct omap_hwmod omap2420_gpio1_hwmod = { - .name = "gpio1", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2420_gpio1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio2 */ -static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { - &omap2420_l4_wkup__gpio2, -}; - -static struct omap_hwmod omap2420_gpio2_hwmod = { - .name = "gpio2", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2420_gpio2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio3 */ -static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { - &omap2420_l4_wkup__gpio3, -}; - -static struct omap_hwmod omap2420_gpio3_hwmod = { - .name = "gpio3", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2420_gpio3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio4 */ -static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { - &omap2420_l4_wkup__gpio4, -}; - -static struct omap_hwmod omap2420_gpio4_hwmod = { - .name = "gpio4", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2420_gpio4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* dma attributes */ -static struct omap_dma_dev_attr dma_dev_attr = { - .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | - IS_CSSA_32 | IS_CDSA_32, - .lch_count = 32, -}; - /* dma_system -> L3 */ static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { .master = &omap2420_dma_system_hwmod, - .slave = &omap2420_l3_main_hwmod, + .slave = &omap2xxx_l3_main_hwmod, .clk = "core_l3_ck", .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system master ports */ -static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { - &omap2420_dma_system__l3, -}; - /* l4_core -> dma_system */ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { - .master = &omap2420_l4_core_hwmod, + .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_dma_system_hwmod, .clk = "sdma_ick", .addr = omap2_dma_system_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* dma_system slave ports */ -static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { - &omap2420_l4_core__dma_system, -}; - -static struct omap_hwmod omap2420_dma_system_hwmod = { - .name = "dma", - .class = &omap2xxx_dma_hwmod_class, - .mpu_irqs = omap2_dma_system_irqs, - .main_clk = "core_l3_ck", - .slaves = omap2420_dma_system_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), - .masters = omap2420_dma_system_masters, - .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), - .dev_attr = &dma_dev_attr, - .flags = HWMOD_NO_IDLEST, -}; - -/* mailbox */ -static struct omap_hwmod omap2420_mailbox_hwmod; -static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { - { .name = "dsp", .irq = 26 }, - { .name = "iva", .irq = 34 }, - { .irq = -1 } -}; - /* l4_core -> mailbox */ static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { - .master = &omap2420_l4_core_hwmod, + .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mailbox_hwmod, .addr = omap2_mailbox_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mailbox slave ports */ -static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { - &omap2420_l4_core__mailbox, -}; - -static struct omap_hwmod omap2420_mailbox_hwmod = { - .name = "mailbox", - .class = &omap2xxx_mailbox_hwmod_class, - .mpu_irqs = omap2420_mailbox_irqs, - .main_clk = "mailboxes_ick", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, - }, - }, - .slaves = omap2420_mailbox_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), -}; - -/* mcspi1 */ -static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { - &omap2420_l4_core__mcspi1, -}; - -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - -static struct omap_hwmod omap2420_mcspi1_hwmod = { - .name = "mcspi1_hwmod", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, - .main_clk = "mcspi1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, - }, - }, - .slaves = omap2420_mcspi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, -}; - -/* mcspi2 */ -static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { - &omap2420_l4_core__mcspi2, -}; - -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - -static struct omap_hwmod omap2420_mcspi2_hwmod = { - .name = "mcspi2_hwmod", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, - .main_clk = "mcspi2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, - }, - }, - .slaves = omap2420_mcspi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, -}; - -/* - * 'mcbsp' class - * multi channel buffered serial port controller - */ - -static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { - .name = "mcbsp", -}; - -/* mcbsp1 */ -static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { - { .name = "tx", .irq = 59 }, - { .name = "rx", .irq = 60 }, - { .irq = -1 } -}; - /* l4_core -> mcbsp1 */ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { - .master = &omap2420_l4_core_hwmod, + .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mcbsp1_hwmod, .clk = "mcbsp1_ick", .addr = omap2_mcbsp1_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp1 slave ports */ -static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { - &omap2420_l4_core__mcbsp1, -}; - -static struct omap_hwmod omap2420_mcbsp1_hwmod = { - .name = "mcbsp1", - .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp1_irqs, - .sdma_reqs = omap2_mcbsp1_sdma_reqs, - .main_clk = "mcbsp1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, - }, - }, - .slaves = omap2420_mcbsp1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), -}; - -/* mcbsp2 */ -static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { - { .name = "tx", .irq = 62 }, - { .name = "rx", .irq = 63 }, - { .irq = -1 } -}; - /* l4_core -> mcbsp2 */ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { - .master = &omap2420_l4_core_hwmod, + .master = &omap2xxx_l4_core_hwmod, .slave = &omap2420_mcbsp2_hwmod, .clk = "mcbsp2_ick", .addr = omap2xxx_mcbsp2_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mcbsp2 slave ports */ -static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { +static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { + &omap2xxx_l3_main__l4_core, + &omap2xxx_mpu__l3_main, + &omap2xxx_dss__l3, + &omap2xxx_l4_core__mcspi1, + &omap2xxx_l4_core__mcspi2, + &omap2xxx_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, + &omap2420_l4_core__i2c1, + &omap2420_l4_core__i2c2, + &omap2420_l3__iva, + &omap2420_l3__dsp, + &omap2420_l4_wkup__timer1, + &omap2xxx_l4_core__timer2, + &omap2xxx_l4_core__timer3, + &omap2xxx_l4_core__timer4, + &omap2xxx_l4_core__timer5, + &omap2xxx_l4_core__timer6, + &omap2xxx_l4_core__timer7, + &omap2xxx_l4_core__timer8, + &omap2xxx_l4_core__timer9, + &omap2xxx_l4_core__timer10, + &omap2xxx_l4_core__timer11, + &omap2xxx_l4_core__timer12, + &omap2420_l4_wkup__wd_timer2, + &omap2xxx_l4_core__dss, + &omap2xxx_l4_core__dss_dispc, + &omap2xxx_l4_core__dss_rfbi, + &omap2xxx_l4_core__dss_venc, + &omap2420_l4_wkup__gpio1, + &omap2420_l4_wkup__gpio2, + &omap2420_l4_wkup__gpio3, + &omap2420_l4_wkup__gpio4, + &omap2420_dma_system__l3, + &omap2420_l4_core__dma_system, + &omap2420_l4_core__mailbox, + &omap2420_l4_core__mcbsp1, &omap2420_l4_core__mcbsp2, -}; - -static struct omap_hwmod omap2420_mcbsp2_hwmod = { - .name = "mcbsp2", - .class = &omap2420_mcbsp_hwmod_class, - .mpu_irqs = omap2420_mcbsp2_irqs, - .sdma_reqs = omap2_mcbsp2_sdma_reqs, - .main_clk = "mcbsp2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, - }, - }, - .slaves = omap2420_mcbsp2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), -}; - -static __initdata struct omap_hwmod *omap2420_hwmods[] = { - &omap2420_l3_main_hwmod, - &omap2420_l4_core_hwmod, - &omap2420_l4_wkup_hwmod, - &omap2420_mpu_hwmod, - &omap2420_iva_hwmod, - - &omap2420_timer1_hwmod, - &omap2420_timer2_hwmod, - &omap2420_timer3_hwmod, - &omap2420_timer4_hwmod, - &omap2420_timer5_hwmod, - &omap2420_timer6_hwmod, - &omap2420_timer7_hwmod, - &omap2420_timer8_hwmod, - &omap2420_timer9_hwmod, - &omap2420_timer10_hwmod, - &omap2420_timer11_hwmod, - &omap2420_timer12_hwmod, - - &omap2420_wd_timer2_hwmod, - &omap2420_uart1_hwmod, - &omap2420_uart2_hwmod, - &omap2420_uart3_hwmod, - /* dss class */ - &omap2420_dss_core_hwmod, - &omap2420_dss_dispc_hwmod, - &omap2420_dss_rfbi_hwmod, - &omap2420_dss_venc_hwmod, - /* i2c class */ - &omap2420_i2c1_hwmod, - &omap2420_i2c2_hwmod, - - /* gpio class */ - &omap2420_gpio1_hwmod, - &omap2420_gpio2_hwmod, - &omap2420_gpio3_hwmod, - &omap2420_gpio4_hwmod, - - /* dma_system class*/ - &omap2420_dma_system_hwmod, - - /* mailbox class */ - &omap2420_mailbox_hwmod, - - /* mcbsp class */ - &omap2420_mcbsp1_hwmod, - &omap2420_mcbsp2_hwmod, - - /* mcspi class */ - &omap2420_mcspi1_hwmod, - &omap2420_mcspi2_hwmod, NULL, }; int __init omap2420_hwmod_init(void) { - return omap_hwmod_register(omap2420_hwmods); + return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c4f56cb60d7d..71d9f8824f9d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -2,6 +2,7 @@ * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips * * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -33,1045 +34,29 @@ /* * OMAP2430 hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap2430_mpu_hwmod; -static struct omap_hwmod omap2430_iva_hwmod; -static struct omap_hwmod omap2430_l3_main_hwmod; -static struct omap_hwmod omap2430_l4_core_hwmod; -static struct omap_hwmod omap2430_dss_core_hwmod; -static struct omap_hwmod omap2430_dss_dispc_hwmod; -static struct omap_hwmod omap2430_dss_rfbi_hwmod; -static struct omap_hwmod omap2430_dss_venc_hwmod; -static struct omap_hwmod omap2430_wd_timer2_hwmod; -static struct omap_hwmod omap2430_gpio1_hwmod; -static struct omap_hwmod omap2430_gpio2_hwmod; -static struct omap_hwmod omap2430_gpio3_hwmod; -static struct omap_hwmod omap2430_gpio4_hwmod; -static struct omap_hwmod omap2430_gpio5_hwmod; -static struct omap_hwmod omap2430_dma_system_hwmod; -static struct omap_hwmod omap2430_mcbsp1_hwmod; -static struct omap_hwmod omap2430_mcbsp2_hwmod; -static struct omap_hwmod omap2430_mcbsp3_hwmod; -static struct omap_hwmod omap2430_mcbsp4_hwmod; -static struct omap_hwmod omap2430_mcbsp5_hwmod; -static struct omap_hwmod omap2430_mcspi1_hwmod; -static struct omap_hwmod omap2430_mcspi2_hwmod; -static struct omap_hwmod omap2430_mcspi3_hwmod; -static struct omap_hwmod omap2430_mmc1_hwmod; -static struct omap_hwmod omap2430_mmc2_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { - .master = &omap2430_l3_main_hwmod, - .slave = &omap2430_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { - .master = &omap2430_mpu_hwmod, - .slave = &omap2430_l3_main_hwmod, - .user = OCP_USER_MPU, -}; - -/* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { - &omap2430_mpu__l3_main, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap2430_dss__l3 = { - .master = &omap2430_dss_core_hwmod, - .slave = &omap2430_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { - &omap2430_l3_main__l4_core, -}; - -/* L3 */ -static struct omap_hwmod omap2430_l3_main_hwmod = { - .name = "l3_main", - .class = &l3_hwmod_class, - .masters = omap2430_l3_main_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), - .slaves = omap2430_l3_main_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -static struct omap_hwmod omap2430_l4_wkup_hwmod; -static struct omap_hwmod omap2430_uart1_hwmod; -static struct omap_hwmod omap2430_uart2_hwmod; -static struct omap_hwmod omap2430_uart3_hwmod; -static struct omap_hwmod omap2430_i2c1_hwmod; -static struct omap_hwmod omap2430_i2c2_hwmod; - -static struct omap_hwmod omap2430_usbhsotg_hwmod; - -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { - .master = &omap2430_usbhsotg_hwmod, - .slave = &omap2430_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU, -}; - -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap2xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap2xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap2xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* -* usbhsotg interface data -*/ -static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { - { - .pa_start = OMAP243X_HS_BASE, - .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core ->usbhsotg interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_usbhsotg_hwmod, - .clk = "usb_l4_ick", - .addr = omap2430_usbhsotg_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { - &omap2430_usbhsotg__l3, -}; - -static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { - &omap2430_l4_core__usbhsotg, -}; - -/* L4 CORE -> MMC1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> MMC2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Slave interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { - &omap2430_l3_main__l4_core, -}; - -/* Master interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { - &omap2430_l4_core__l4_wkup, - &omap2430_l4_core__mmc1, - &omap2430_l4_core__mmc2, -}; - -/* L4 CORE */ -static struct omap_hwmod omap2430_l4_core_hwmod = { - .name = "l4_core", - .class = &l4_hwmod_class, - .masters = omap2430_l4_core_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), - .slaves = omap2430_l4_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* Slave interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { - &omap2430_l4_core__l4_wkup, - &omap2_l4_core__uart1, - &omap2_l4_core__uart2, - &omap2_l4_core__uart3, -}; - -/* Master interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { -}; - -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi1_hwmod, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi2_hwmod, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi3 interface */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcspi3_hwmod, - .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 WKUP */ -static struct omap_hwmod omap2430_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &l4_hwmod_class, - .masters = omap2430_l4_wkup_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), - .slaves = omap2430_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* Master interfaces on the MPU device */ -static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { - &omap2430_mpu__l3_main, -}; - -/* MPU */ -static struct omap_hwmod omap2430_mpu_hwmod = { - .name = "mpu", - .class = &mpu_hwmod_class, - .main_clk = "mpu_ck", - .masters = omap2430_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), -}; - -/* - * IVA2_1 interface data + * IP blocks */ -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap2430_l3__iva = { - .master = &omap2430_l3_main_hwmod, - .slave = &omap2430_iva_hwmod, - .clk = "dsp_fck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { - &omap2430_l3__iva, +/* IVA2 (IVA2) */ +static struct omap_hwmod_rst_info omap2430_iva_resets[] = { + { .name = "logic", .rst_shift = 0 }, + { .name = "mmu", .rst_shift = 1 }, }; -/* - * IVA2 (IVA2) - */ - static struct omap_hwmod omap2430_iva_hwmod = { .name = "iva", .class = &iva_hwmod_class, - .masters = omap2430_iva_masters, - .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), -}; - -/* always-on timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, -}; - -/* pwm timers dev attribute */ -static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, -}; - -/* timer1 */ -static struct omap_hwmod omap2430_timer1_hwmod; - -static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { - { - .pa_start = 0x49018000, - .pa_end = 0x49018000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap2430_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer1 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { - &omap2430_l4_wkup__timer1, -}; - -/* timer1 hwmod */ -static struct omap_hwmod omap2430_timer1_hwmod = { - .name = "timer1", - .mpu_irqs = omap2_timer1_mpu_irqs, - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer2 */ -static struct omap_hwmod omap2430_timer2_hwmod; - -/* l4_core -> timer2 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap2xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer2 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { - &omap2430_l4_core__timer2, -}; - -/* timer2 hwmod */ -static struct omap_hwmod omap2430_timer2_hwmod = { - .name = "timer2", - .mpu_irqs = omap2_timer2_mpu_irqs, - .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT2_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer3 */ -static struct omap_hwmod omap2430_timer3_hwmod; - -/* l4_core -> timer3 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap2xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { - &omap2430_l4_core__timer3, -}; - -/* timer3 hwmod */ -static struct omap_hwmod omap2430_timer3_hwmod = { - .name = "timer3", - .mpu_irqs = omap2_timer3_mpu_irqs, - .main_clk = "gpt3_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT3_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer4 */ -static struct omap_hwmod omap2430_timer4_hwmod; - -/* l4_core -> timer4 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap2xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { - &omap2430_l4_core__timer4, -}; - -/* timer4 hwmod */ -static struct omap_hwmod omap2430_timer4_hwmod = { - .name = "timer4", - .mpu_irqs = omap2_timer4_mpu_irqs, - .main_clk = "gpt4_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT4_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer5 */ -static struct omap_hwmod omap2430_timer5_hwmod; - -/* l4_core -> timer5 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap2xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer5 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { - &omap2430_l4_core__timer5, -}; - -/* timer5 hwmod */ -static struct omap_hwmod omap2430_timer5_hwmod = { - .name = "timer5", - .mpu_irqs = omap2_timer5_mpu_irqs, - .main_clk = "gpt5_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT5_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer5_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer6 */ -static struct omap_hwmod omap2430_timer6_hwmod; - -/* l4_core -> timer6 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap2xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer6 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { - &omap2430_l4_core__timer6, -}; - -/* timer6 hwmod */ -static struct omap_hwmod omap2430_timer6_hwmod = { - .name = "timer6", - .mpu_irqs = omap2_timer6_mpu_irqs, - .main_clk = "gpt6_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT6_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer6_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer7 */ -static struct omap_hwmod omap2430_timer7_hwmod; - -/* l4_core -> timer7 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap2xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer7 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { - &omap2430_l4_core__timer7, -}; - -/* timer7 hwmod */ -static struct omap_hwmod omap2430_timer7_hwmod = { - .name = "timer7", - .mpu_irqs = omap2_timer7_mpu_irqs, - .main_clk = "gpt7_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT7_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer7_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer8 */ -static struct omap_hwmod omap2430_timer8_hwmod; - -/* l4_core -> timer8 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap2xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer8 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { - &omap2430_l4_core__timer8, -}; - -/* timer8 hwmod */ -static struct omap_hwmod omap2430_timer8_hwmod = { - .name = "timer8", - .mpu_irqs = omap2_timer8_mpu_irqs, - .main_clk = "gpt8_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT8_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, - }, - }, - .dev_attr = &capability_alwon_dev_attr, - .slaves = omap2430_timer8_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer9 */ -static struct omap_hwmod omap2430_timer9_hwmod; - -/* l4_core -> timer9 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap2xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer9 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { - &omap2430_l4_core__timer9, -}; - -/* timer9 hwmod */ -static struct omap_hwmod omap2430_timer9_hwmod = { - .name = "timer9", - .mpu_irqs = omap2_timer9_mpu_irqs, - .main_clk = "gpt9_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT9_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2430_timer9_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer10 */ -static struct omap_hwmod omap2430_timer10_hwmod; - -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer10 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { - &omap2430_l4_core__timer10, -}; - -/* timer10 hwmod */ -static struct omap_hwmod omap2430_timer10_hwmod = { - .name = "timer10", - .mpu_irqs = omap2_timer10_mpu_irqs, - .main_clk = "gpt10_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT10_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2430_timer10_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer11 */ -static struct omap_hwmod omap2430_timer11_hwmod; - -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer11 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { - &omap2430_l4_core__timer11, -}; - -/* timer11 hwmod */ -static struct omap_hwmod omap2430_timer11_hwmod = { - .name = "timer11", - .mpu_irqs = omap2_timer11_mpu_irqs, - .main_clk = "gpt11_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT11_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2430_timer11_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* timer12 */ -static struct omap_hwmod omap2430_timer12_hwmod; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap2xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer12 slave port */ -static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { - &omap2430_l4_core__timer12, -}; - -/* timer12 hwmod */ -static struct omap_hwmod omap2430_timer12_hwmod = { - .name = "timer12", - .mpu_irqs = omap2xxx_timer12_mpu_irqs, - .main_clk = "gpt12_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPT12_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, - }, - }, - .dev_attr = &capability_pwm_dev_attr, - .slaves = omap2430_timer12_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), - .class = &omap2xxx_timer_hwmod_class, -}; - -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { - { - .pa_start = 0x49016000, - .pa_end = 0x4901607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_wd_timer2_hwmod, - .clk = "mpu_wdt_ick", - .addr = omap2430_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { - &omap2430_l4_wkup__wd_timer2, -}; - -static struct omap_hwmod omap2430_wd_timer2_hwmod = { - .name = "wd_timer2", - .class = &omap2xxx_wd_timer_hwmod_class, - .main_clk = "mpu_wdt_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, - }, - }, - .slaves = omap2430_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), -}; - -/* UART1 */ - -static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { - &omap2_l4_core__uart1, -}; - -static struct omap_hwmod omap2430_uart1_hwmod = { - .name = "uart1", - .mpu_irqs = omap2_uart1_mpu_irqs, - .sdma_reqs = omap2_uart1_sdma_reqs, - .main_clk = "uart1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, - }, - }, - .slaves = omap2430_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), - .class = &omap2_uart_class, -}; - -/* UART2 */ - -static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { - &omap2_l4_core__uart2, -}; - -static struct omap_hwmod omap2430_uart2_hwmod = { - .name = "uart2", - .mpu_irqs = omap2_uart2_mpu_irqs, - .sdma_reqs = omap2_uart2_sdma_reqs, - .main_clk = "uart2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_UART2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, - }, - }, - .slaves = omap2430_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), - .class = &omap2_uart_class, -}; - -/* UART3 */ - -static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { - &omap2_l4_core__uart3, -}; - -static struct omap_hwmod omap2430_uart3_hwmod = { - .name = "uart3", - .mpu_irqs = omap2_uart3_mpu_irqs, - .sdma_reqs = omap2_uart3_sdma_reqs, - .main_clk = "uart3_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 2, - .module_bit = OMAP24XX_EN_UART3_SHIFT, - .idlest_reg_id = 2, - .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, - .slaves = omap2430_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), - .class = &omap2_uart_class, -}; - -/* dss */ -/* dss master ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { - &omap2430_dss__l3, -}; - -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { - &omap2430_l4_core__dss, -}; - -static struct omap_hwmod_opt_clk dss_opt_clks[] = { - /* - * The DSS HW needs all DSS clocks enabled during reset. The dss_core - * driver does not use these clocks. - */ - { .role = "tv_clk", .clk = "dss_54m_fck" }, - { .role = "sys_clk", .clk = "dss2_fck" }, -}; - -static struct omap_hwmod omap2430_dss_core_hwmod = { - .name = "dss_core", - .class = &omap2_dss_hwmod_class, - .main_clk = "dss1_fck", /* instead of dss_fck */ - .sdma_reqs = omap2xxx_dss_sdma_chs, - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .opt_clks = dss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap2430_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), - .masters = omap2430_dss_masters, - .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), - .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, -}; - -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_dispc slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { - &omap2430_l4_core__dss_dispc, -}; - -static struct omap_hwmod omap2430_dss_dispc_hwmod = { - .name = "dss_dispc", - .class = &omap2_dispc_hwmod_class, - .mpu_irqs = omap2_dispc_irqs, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, - .slaves = omap2430_dss_dispc_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), - .flags = HWMOD_NO_IDLEST, - .dev_attr = &omap2_3_dss_dispc_dev_attr -}; - -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_rfbi slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { - &omap2430_l4_core__dss_rfbi, -}; - -static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { - { .role = "ick", .clk = "dss_ick" }, -}; - -static struct omap_hwmod omap2430_dss_rfbi_hwmod = { - .name = "dss_rfbi", - .class = &omap2_rfbi_hwmod_class, - .main_clk = "dss1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .opt_clks = dss_rfbi_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .slaves = omap2430_dss_rfbi_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), - .flags = HWMOD_NO_IDLEST, -}; - -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .flags = OCPIF_SWSUP_IDLE, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_venc slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { - &omap2430_l4_core__dss_venc, -}; - -static struct omap_hwmod omap2430_dss_venc_hwmod = { - .name = "dss_venc", - .class = &omap2_venc_hwmod_class, - .main_clk = "dss_54m_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, - }, - }, - .slaves = omap2430_dss_venc_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), - .flags = HWMOD_NO_IDLEST, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap2430_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), + .main_clk = "dsp_fck", }; /* I2C common */ @@ -1099,11 +84,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* I2C1 */ - -static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { - &omap2430_l4_core__i2c1, -}; - static struct omap_hwmod omap2430_i2c1_hwmod = { .name = "i2c1", .flags = HWMOD_16BIT_REG, @@ -1127,18 +107,11 @@ static struct omap_hwmod omap2430_i2c1_hwmod = { .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, }, }, - .slaves = omap2430_i2c1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), .class = &i2c_class, .dev_attr = &i2c_dev_attr, }; /* I2C2 */ - -static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { - &omap2430_l4_core__i2c2, -}; - static struct omap_hwmod omap2430_i2c2_hwmod = { .name = "i2c2", .flags = HWMOD_16BIT_REG, @@ -1154,218 +127,16 @@ static struct omap_hwmod omap2430_i2c2_hwmod = { .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, }, }, - .slaves = omap2430_i2c2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), .class = &i2c_class, .dev_attr = &i2c_dev_attr, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { - { - .pa_start = 0x4900C000, - .pa_end = 0x4900C1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio1_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio2 */ -static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { - { - .pa_start = 0x4900E000, - .pa_end = 0x4900E1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio2_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio3 */ -static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { - { - .pa_start = 0x49010000, - .pa_end = 0x490101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio3_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup -> gpio4 */ -static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { - { - .pa_start = 0x49012000, - .pa_end = 0x490121ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { - .master = &omap2430_l4_wkup_hwmod, - .slave = &omap2430_gpio4_hwmod, - .clk = "gpios_ick", - .addr = omap2430_gpio4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_core -> gpio5 */ -static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { - { - .pa_start = 0x480B6000, - .pa_end = 0x480B61ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_gpio5_hwmod, - .clk = "gpio5_ick", - .addr = omap2430_gpio5_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio dev_attr */ -static struct omap_gpio_dev_attr gpio_dev_attr = { - .bank_width = 32, - .dbck_flag = false, -}; - -/* gpio1 */ -static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { - &omap2430_l4_wkup__gpio1, -}; - -static struct omap_hwmod omap2430_gpio1_hwmod = { - .name = "gpio1", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio1_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, - }, - }, - .slaves = omap2430_gpio1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio2 */ -static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { - &omap2430_l4_wkup__gpio2, -}; - -static struct omap_hwmod omap2430_gpio2_hwmod = { - .name = "gpio2", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio2_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2430_gpio2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio3 */ -static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { - &omap2430_l4_wkup__gpio3, -}; - -static struct omap_hwmod omap2430_gpio3_hwmod = { - .name = "gpio3", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio3_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2430_gpio3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - -/* gpio4 */ -static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { - &omap2430_l4_wkup__gpio4, -}; - -static struct omap_hwmod omap2430_gpio4_hwmod = { - .name = "gpio4", - .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, - .mpu_irqs = omap2_gpio4_irqs, - .main_clk = "gpios_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_GPIOS_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, - }, - }, - .slaves = omap2430_gpio4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), - .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, -}; - /* gpio5 */ static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ { .irq = -1 } }; -static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { - &omap2430_l4_core__gpio5, -}; - static struct omap_hwmod omap2430_gpio5_hwmod = { .name = "gpio5", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -1380,10 +151,8 @@ static struct omap_hwmod omap2430_gpio5_hwmod = { .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, }, }, - .slaves = omap2430_gpio5_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), .class = &omap2xxx_gpio_hwmod_class, - .dev_attr = &gpio_dev_attr, + .dev_attr = &omap2xxx_gpio_dev_attr, }; /* dma attributes */ @@ -1393,66 +162,21 @@ static struct omap_dma_dev_attr dma_dev_attr = { .lch_count = 32, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { - .master = &omap2430_dma_system_hwmod, - .slave = &omap2430_l3_main_hwmod, - .clk = "core_l3_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system master ports */ -static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { - &omap2430_dma_system__l3, -}; - -/* l4_core -> dma_system */ -static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_dma_system_hwmod, - .clk = "sdma_ick", - .addr = omap2_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system slave ports */ -static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { - &omap2430_l4_core__dma_system, -}; - static struct omap_hwmod omap2430_dma_system_hwmod = { .name = "dma", .class = &omap2xxx_dma_hwmod_class, .mpu_irqs = omap2_dma_system_irqs, .main_clk = "core_l3_ck", - .slaves = omap2430_dma_system_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), - .masters = omap2430_dma_system_masters, - .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, }; /* mailbox */ -static struct omap_hwmod omap2430_mailbox_hwmod; static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { { .irq = 26 }, { .irq = -1 } }; -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mailbox_hwmod, - .addr = omap2_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mailbox slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { - &omap2430_l4_core__mailbox, -}; - static struct omap_hwmod omap2430_mailbox_hwmod = { .name = "mailbox", .class = &omap2xxx_mailbox_hwmod_class, @@ -1467,66 +191,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, }, }, - .slaves = omap2430_mailbox_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), -}; - -/* mcspi1 */ -static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { - &omap2430_l4_core__mcspi1, -}; - -static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { - .num_chipselect = 4, -}; - -static struct omap_hwmod omap2430_mcspi1_hwmod = { - .name = "mcspi1_hwmod", - .mpu_irqs = omap2_mcspi1_mpu_irqs, - .sdma_reqs = omap2_mcspi1_sdma_reqs, - .main_clk = "mcspi1_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, - }, - }, - .slaves = omap2430_mcspi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi1_dev_attr, -}; - -/* mcspi2 */ -static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { - &omap2430_l4_core__mcspi2, -}; - -static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { - .num_chipselect = 2, -}; - -static struct omap_hwmod omap2430_mcspi2_hwmod = { - .name = "mcspi2_hwmod", - .mpu_irqs = omap2_mcspi2_mpu_irqs, - .sdma_reqs = omap2_mcspi2_sdma_reqs, - .main_clk = "mcspi2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 1, - .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, - }, - }, - .slaves = omap2430_mcspi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), - .class = &omap2xxx_mcspi_class, - .dev_attr = &omap_mcspi2_dev_attr, }; /* mcspi3 */ @@ -1543,16 +207,12 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { - &omap2430_l4_core__mcspi3, -}; - static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { .num_chipselect = 2, }; static struct omap_hwmod omap2430_mcspi3_hwmod = { - .name = "mcspi3_hwmod", + .name = "mcspi3", .mpu_irqs = omap2430_mcspi3_mpu_irqs, .sdma_reqs = omap2430_mcspi3_sdma_reqs, .main_clk = "mcspi3_fck", @@ -1565,15 +225,11 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = { .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, }, }, - .slaves = omap2430_mcspi3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), .class = &omap2xxx_mcspi_class, .dev_attr = &omap_mcspi3_dev_attr, }; -/* - * usbhsotg - */ +/* usbhsotg */ static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { .rev_offs = 0x0400, .sysc_offs = 0x0404, @@ -1612,10 +268,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, }, }, - .masters = omap2430_usbhsotg_masters, - .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), - .slaves = omap2430_usbhsotg_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), .class = &usbotg_class, /* * Erratum ID: i479 idle_req / idle_ack mechanism potentially @@ -1653,20 +305,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { { .irq = -1 } }; -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap2_mcbsp1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp1 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { - &omap2430_l4_core__mcbsp1, -}; - static struct omap_hwmod omap2430_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap2430_mcbsp_hwmod_class, @@ -1682,8 +320,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, }, }, - .slaves = omap2430_mcbsp1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), }; /* mcbsp2 */ @@ -1694,20 +330,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { { .irq = -1 } }; -/* l4_core -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp2_hwmod, - .clk = "mcbsp2_ick", - .addr = omap2xxx_mcbsp2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp2 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { - &omap2430_l4_core__mcbsp2, -}; - static struct omap_hwmod omap2430_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap2430_mcbsp_hwmod_class, @@ -1723,8 +345,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, }, }, - .slaves = omap2430_mcbsp2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), }; /* mcbsp3 */ @@ -1735,30 +355,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808C000, - .pa_end = 0x4808C0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp3_hwmod, - .clk = "mcbsp3_ick", - .addr = omap2430_mcbsp3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp3 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { - &omap2430_l4_core__mcbsp3, -}; - static struct omap_hwmod omap2430_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap2430_mcbsp_hwmod_class, @@ -1774,8 +370,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, }, }, - .slaves = omap2430_mcbsp3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), }; /* mcbsp4 */ @@ -1792,30 +386,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4808E000, - .pa_end = 0x4808E0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp4_hwmod, - .clk = "mcbsp4_ick", - .addr = omap2430_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp4 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { - &omap2430_l4_core__mcbsp4, -}; - static struct omap_hwmod omap2430_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap2430_mcbsp_hwmod_class, @@ -1831,8 +401,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, }, }, - .slaves = omap2430_mcbsp4_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), }; /* mcbsp5 */ @@ -1849,30 +417,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp5 */ -static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { - .master = &omap2430_l4_core_hwmod, - .slave = &omap2430_mcbsp5_hwmod, - .clk = "mcbsp5_ick", - .addr = omap2430_mcbsp5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp5 slave ports */ -static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { - &omap2430_l4_core__mcbsp5, -}; - static struct omap_hwmod omap2430_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap2430_mcbsp_hwmod_class, @@ -1888,12 +432,9 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, }, }, - .slaves = omap2430_mcbsp5_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), }; /* MMC/SD/SDIO common */ - static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { .rev_offs = 0x1fc, .sysc_offs = 0x10, @@ -1911,7 +452,6 @@ static struct omap_hwmod_class omap2430_mmc_class = { }; /* MMC/SD/SDIO1 */ - static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { { .irq = 83 }, { .irq = -1 } @@ -1927,10 +467,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { { .role = "dbck", .clk = "mmchsdb1_fck" }, }; -static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { - &omap2430_l4_core__mmc1, -}; - static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; @@ -1953,13 +489,10 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { }, }, .dev_attr = &mmc1_dev_attr, - .slaves = omap2430_mmc1_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), .class = &omap2430_mmc_class, }; /* MMC/SD/SDIO2 */ - static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { { .irq = 86 }, { .irq = -1 } @@ -1975,10 +508,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { { .role = "dbck", .clk = "mmchsdb2_fck" }, }; -static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { - &omap2430_l4_core__mmc2, -}; - static struct omap_hwmod omap2430_mmc2_hwmod = { .name = "mmc2", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -1996,78 +525,371 @@ static struct omap_hwmod omap2430_mmc2_hwmod = { .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, }, }, - .slaves = omap2430_mmc2_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), .class = &omap2430_mmc_class, }; -static __initdata struct omap_hwmod *omap2430_hwmods[] = { - &omap2430_l3_main_hwmod, - &omap2430_l4_core_hwmod, - &omap2430_l4_wkup_hwmod, - &omap2430_mpu_hwmod, - &omap2430_iva_hwmod, - - &omap2430_timer1_hwmod, - &omap2430_timer2_hwmod, - &omap2430_timer3_hwmod, - &omap2430_timer4_hwmod, - &omap2430_timer5_hwmod, - &omap2430_timer6_hwmod, - &omap2430_timer7_hwmod, - &omap2430_timer8_hwmod, - &omap2430_timer9_hwmod, - &omap2430_timer10_hwmod, - &omap2430_timer11_hwmod, - &omap2430_timer12_hwmod, - - &omap2430_wd_timer2_hwmod, - &omap2430_uart1_hwmod, - &omap2430_uart2_hwmod, - &omap2430_uart3_hwmod, - /* dss class */ - &omap2430_dss_core_hwmod, - &omap2430_dss_dispc_hwmod, - &omap2430_dss_rfbi_hwmod, - &omap2430_dss_venc_hwmod, - /* i2c class */ - &omap2430_i2c1_hwmod, - &omap2430_i2c2_hwmod, - &omap2430_mmc1_hwmod, - &omap2430_mmc2_hwmod, - - /* gpio class */ - &omap2430_gpio1_hwmod, - &omap2430_gpio2_hwmod, - &omap2430_gpio3_hwmod, - &omap2430_gpio4_hwmod, - &omap2430_gpio5_hwmod, - - /* dma_system class*/ - &omap2430_dma_system_hwmod, - - /* mcbsp class */ - &omap2430_mcbsp1_hwmod, - &omap2430_mcbsp2_hwmod, - &omap2430_mcbsp3_hwmod, - &omap2430_mcbsp4_hwmod, - &omap2430_mcbsp5_hwmod, - - /* mailbox class */ - &omap2430_mailbox_hwmod, - - /* mcspi class */ - &omap2430_mcspi1_hwmod, - &omap2430_mcspi2_hwmod, - &omap2430_mcspi3_hwmod, - - /* usbotg class*/ - &omap2430_usbhsotg_hwmod, +/* + * interfaces + */ + +/* L3 -> L4_CORE interface */ +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { + .master = &omap2430_usbhsotg_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { + { + .pa_start = OMAP243X_HS_BASE, + .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core ->usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_usbhsotg_hwmod, + .clk = "usb_l4_ick", + .addr = omap2430_usbhsotg_addrs, + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcspi3_hwmod, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap2430_l3__iva = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2430_iva_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { + { + .pa_start = 0x49018000, + .pa_end = 0x49018000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2430_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { + { + .pa_start = 0x49016000, + .pa_end = 0x4901607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2430_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { + { + .pa_start = 0x4900C000, + .pa_end = 0x4900C1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio1_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio2 */ +static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { + { + .pa_start = 0x4900E000, + .pa_end = 0x4900E1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio2_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio3 */ +static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { + { + .pa_start = 0x49010000, + .pa_end = 0x490101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio3_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio4 */ +static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { + { + .pa_start = 0x49012000, + .pa_end = 0x490121ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { + .master = &omap2xxx_l4_wkup_hwmod, + .slave = &omap2xxx_gpio4_hwmod, + .clk = "gpios_ick", + .addr = omap2430_gpio4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> gpio5 */ +static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { + { + .pa_start = 0x480B6000, + .pa_end = 0x480B61ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_gpio5_hwmod, + .clk = "gpio5_ick", + .addr = omap2430_gpio5_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { + .master = &omap2430_dma_system_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dma_system */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_dma_system_hwmod, + .clk = "sdma_ick", + .addr = omap2_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mailbox_hwmod, + .addr = omap2_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap2xxx_mcbsp2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808C000, + .pa_end = 0x4808C0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap2430_mcbsp3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808E000, + .pa_end = 0x4808E0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap2430_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2430_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap2430_mcbsp5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { + &omap2xxx_l3_main__l4_core, + &omap2xxx_mpu__l3_main, + &omap2xxx_dss__l3, + &omap2430_usbhsotg__l3, + &omap2430_l4_core__i2c1, + &omap2430_l4_core__i2c2, + &omap2xxx_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, + &omap2430_l4_core__usbhsotg, + &omap2430_l4_core__mmc1, + &omap2430_l4_core__mmc2, + &omap2xxx_l4_core__mcspi1, + &omap2xxx_l4_core__mcspi2, + &omap2430_l4_core__mcspi3, + &omap2430_l3__iva, + &omap2430_l4_wkup__timer1, + &omap2xxx_l4_core__timer2, + &omap2xxx_l4_core__timer3, + &omap2xxx_l4_core__timer4, + &omap2xxx_l4_core__timer5, + &omap2xxx_l4_core__timer6, + &omap2xxx_l4_core__timer7, + &omap2xxx_l4_core__timer8, + &omap2xxx_l4_core__timer9, + &omap2xxx_l4_core__timer10, + &omap2xxx_l4_core__timer11, + &omap2xxx_l4_core__timer12, + &omap2430_l4_wkup__wd_timer2, + &omap2xxx_l4_core__dss, + &omap2xxx_l4_core__dss_dispc, + &omap2xxx_l4_core__dss_rfbi, + &omap2xxx_l4_core__dss_venc, + &omap2430_l4_wkup__gpio1, + &omap2430_l4_wkup__gpio2, + &omap2430_l4_wkup__gpio3, + &omap2430_l4_wkup__gpio4, + &omap2430_l4_core__gpio5, + &omap2430_dma_system__l3, + &omap2430_l4_core__dma_system, + &omap2430_l4_core__mailbox, + &omap2430_l4_core__mcbsp1, + &omap2430_l4_core__mcbsp2, + &omap2430_l4_core__mcbsp3, + &omap2430_l4_core__mcbsp4, + &omap2430_l4_core__mcbsp5, NULL, }; int __init omap2430_hwmod_init(void) { - return omap_hwmod_register(omap2430_hwmods); + return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 4f3547c2a49e..5178e40e84f9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -15,10 +15,12 @@ #include <plat/omap_hwmod.h> #include <plat/serial.h> +#include <plat/l3_2xxx.h> +#include <plat/l4_2xxx.h> #include "omap_hwmod_common_data.h" -struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { +static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { { .pa_start = OMAP2_UART1_BASE, .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, @@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { +static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { { .pa_start = OMAP2_UART2_BASE, .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, @@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { +static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { { .pa_start = OMAP2_UART3_BASE, .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, @@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { { .pa_start = 0x4802a000, .pa_end = 0x4802a000 + SZ_1K - 1, @@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { { .pa_start = 0x48078000, .pa_end = 0x48078000 + SZ_1K - 1, @@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { { .pa_start = 0x4807a000, .pa_end = 0x4807a000 + SZ_1K - 1, @@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { { .pa_start = 0x4807c000, .pa_end = 0x4807c000 + SZ_1K - 1, @@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { { .pa_start = 0x4807e000, .pa_end = 0x4807e000 + SZ_1K - 1, @@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { { .pa_start = 0x48080000, .pa_end = 0x48080000 + SZ_1K - 1, @@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { { .pa_start = 0x48082000, .pa_end = 0x48082000 + SZ_1K - 1, @@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { { } }; -struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { +static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { { .pa_start = 0x48084000, .pa_end = 0x48084000 + SZ_1K - 1, @@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { { } }; +/* + * Common interconnect data + */ + +/* L3 -> L4_CORE interface */ +struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = { + .master = &omap2xxx_l3_main_hwmod, + .slave = &omap2xxx_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* MPU -> L3 interface */ +struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = { + .master = &omap2xxx_mpu_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .user = OCP_USER_MPU, +}; + +/* DSS -> l3 */ +struct omap_hwmod_ocp_if omap2xxx_dss__l3 = { + .master = &omap2xxx_dss_core_hwmod, + .slave = &omap2xxx_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4_CORE -> L4_WKUP interface */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART1 interface */ +struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi1 interface */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer2 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer3 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer4 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer5 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer6 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer7 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer8 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer9 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer10 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer11 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer12 */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2xxx_timer12_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_dispc */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_rfbi */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_venc */ +struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = { + .master = &omap2xxx_l4_core_hwmod, + .slave = &omap2xxx_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 2a6729741b06..45aaa07e3025 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -10,6 +10,7 @@ */ #include <plat/omap_hwmod.h> #include <plat/serial.h> +#include <plat/gpio.h> #include <plat/dma.h> #include <plat/dmtimer.h> #include <plat/mcspi.h> @@ -17,6 +18,8 @@ #include <mach/irqs.h> #include "omap_hwmod_common_data.h" +#include "cm-regbits-24xx.h" +#include "prm-regbits-24xx.h" #include "wd_timer.h" struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { @@ -170,3 +173,562 @@ struct omap_hwmod_class omap2xxx_mcspi_class = { .sysc = &omap2xxx_mcspi_sysc, .rev = OMAP2_MCSPI_REV, }; + +/* + * IP blocks + */ + +/* L3 */ +struct omap_hwmod omap2xxx_l3_main_hwmod = { + .name = "l3_main", + .class = &l3_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* L4 CORE */ +struct omap_hwmod omap2xxx_l4_core_hwmod = { + .name = "l4_core", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* L4 WKUP */ +struct omap_hwmod omap2xxx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, +}; + +/* MPU */ +struct omap_hwmod omap2xxx_mpu_hwmod = { + .name = "mpu", + .class = &mpu_hwmod_class, + .main_clk = "mpu_ck", +}; + +/* IVA2 */ +struct omap_hwmod omap2xxx_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, +}; + +/* always-on timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { + .timer_capability = OMAP_TIMER_ALWON, +}; + +/* pwm timers dev attribute */ +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { + .timer_capability = OMAP_TIMER_HAS_PWM, +}; + +/* timer1 */ + +struct omap_hwmod omap2xxx_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2_timer1_mpu_irqs, + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer2 */ + +struct omap_hwmod omap2xxx_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2_timer2_mpu_irqs, + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer3 */ + +struct omap_hwmod omap2xxx_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2_timer3_mpu_irqs, + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer4 */ + +struct omap_hwmod omap2xxx_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2_timer4_mpu_irqs, + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer5 */ + +struct omap_hwmod omap2xxx_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2_timer5_mpu_irqs, + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer6 */ + +struct omap_hwmod omap2xxx_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2_timer6_mpu_irqs, + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer7 */ + +struct omap_hwmod omap2xxx_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2_timer7_mpu_irqs, + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer8 */ + +struct omap_hwmod omap2xxx_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2_timer8_mpu_irqs, + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, + }, + }, + .dev_attr = &capability_alwon_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer9 */ + +struct omap_hwmod omap2xxx_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2_timer9_mpu_irqs, + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer10 */ + +struct omap_hwmod omap2xxx_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2_timer10_mpu_irqs, + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer11 */ + +struct omap_hwmod omap2xxx_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2_timer11_mpu_irqs, + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* timer12 */ + +struct omap_hwmod omap2xxx_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2xxx_timer12_mpu_irqs, + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, + }, + }, + .dev_attr = &capability_pwm_dev_attr, + .class = &omap2xxx_timer_hwmod_class, +}; + +/* wd_timer2 */ +struct omap_hwmod omap2xxx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2xxx_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, + }, +}; + +/* UART1 */ + +struct omap_hwmod omap2xxx_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = omap2_uart1_mpu_irqs, + .sdma_reqs = omap2_uart1_sdma_reqs, + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, + }, + .class = &omap2_uart_class, +}; + +/* UART2 */ + +struct omap_hwmod omap2xxx_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = omap2_uart2_mpu_irqs, + .sdma_reqs = omap2_uart2_sdma_reqs, + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, + }, + .class = &omap2_uart_class, +}; + +/* UART3 */ + +struct omap_hwmod omap2xxx_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = omap2_uart3_mpu_irqs, + .sdma_reqs = omap2_uart3_sdma_reqs, + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, + .class = &omap2_uart_class, +}; + +/* dss */ + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + /* + * The DSS HW needs all DSS clocks enabled during reset. The dss_core + * driver does not use these clocks. + */ + { .role = "tv_clk", .clk = "dss_54m_fck" }, + { .role = "sys_clk", .clk = "dss2_fck" }, +}; + +struct omap_hwmod omap2xxx_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2_dss_hwmod_class, + .main_clk = "dss1_fck", /* instead of dss_fck */ + .sdma_reqs = omap2xxx_dss_sdma_chs, + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, +}; + +struct omap_hwmod omap2xxx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap2_dispc_hwmod_class, + .mpu_irqs = omap2_dispc_irqs, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .flags = HWMOD_NO_IDLEST, + .dev_attr = &omap2_3_dss_dispc_dev_attr +}; + +static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { + { .role = "ick", .clk = "dss_ick" }, +}; + +struct omap_hwmod omap2xxx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2_rfbi_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .opt_clks = dss_rfbi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), + .flags = HWMOD_NO_IDLEST, +}; + +struct omap_hwmod omap2xxx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2_venc_hwmod_class, + .main_clk = "dss_54m_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .flags = HWMOD_NO_IDLEST, +}; + +/* gpio dev_attr */ +struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = false, +}; + +/* gpio1 */ +struct omap_hwmod omap2xxx_gpio1_hwmod = { + .name = "gpio1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio1_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, +}; + +/* gpio2 */ +struct omap_hwmod omap2xxx_gpio2_hwmod = { + .name = "gpio2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio2_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, +}; + +/* gpio3 */ +struct omap_hwmod omap2xxx_gpio3_hwmod = { + .name = "gpio3", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio3_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, +}; + +/* gpio4 */ +struct omap_hwmod omap2xxx_gpio4_hwmod = { + .name = "gpio4", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2_gpio4_irqs, + .main_clk = "gpios_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPIOS_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, + }, + }, + .class = &omap2xxx_gpio_hwmod_class, + .dev_attr = &omap2xxx_gpio_dev_attr, +}; + +/* mcspi1 */ +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +struct omap_hwmod omap2xxx_mcspi1_hwmod = { + .name = "mcspi1", + .mpu_irqs = omap2_mcspi1_mpu_irqs, + .sdma_reqs = omap2_mcspi1_sdma_reqs, + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, + }, + }, + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, +}; + +/* mcspi2 */ +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +struct omap_hwmod omap2xxx_mcspi2_hwmod = { + .name = "mcspi2", + .mpu_irqs = omap2_mcspi2_mpu_irqs, + .sdma_reqs = omap2_mcspi2_sdma_reqs, + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, + }, + }, + .class = &omap2xxx_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 34b9766d1d23..0c65079c2b69 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -2,6 +2,7 @@ * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips * * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. * Paul Walmsley * * This program is free software; you can redistribute it and/or modify @@ -38,491 +39,56 @@ /* * OMAP3xxx hardware module integration data * - * ALl of the data in this section should be autogeneratable from the + * All of the data in this section should be autogeneratable from the * TI hardware database or other technical documentation. Data that * is driver-specific or driver-kernel integration-specific belongs * elsewhere. */ -static struct omap_hwmod omap3xxx_mpu_hwmod; -static struct omap_hwmod omap3xxx_iva_hwmod; -static struct omap_hwmod omap3xxx_l3_main_hwmod; -static struct omap_hwmod omap3xxx_l4_core_hwmod; -static struct omap_hwmod omap3xxx_l4_per_hwmod; -static struct omap_hwmod omap3xxx_wd_timer2_hwmod; -static struct omap_hwmod omap3430es1_dss_core_hwmod; -static struct omap_hwmod omap3xxx_dss_core_hwmod; -static struct omap_hwmod omap3xxx_dss_dispc_hwmod; -static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; -static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; -static struct omap_hwmod omap3xxx_dss_venc_hwmod; -static struct omap_hwmod omap3xxx_i2c1_hwmod; -static struct omap_hwmod omap3xxx_i2c2_hwmod; -static struct omap_hwmod omap3xxx_i2c3_hwmod; -static struct omap_hwmod omap3xxx_gpio1_hwmod; -static struct omap_hwmod omap3xxx_gpio2_hwmod; -static struct omap_hwmod omap3xxx_gpio3_hwmod; -static struct omap_hwmod omap3xxx_gpio4_hwmod; -static struct omap_hwmod omap3xxx_gpio5_hwmod; -static struct omap_hwmod omap3xxx_gpio6_hwmod; -static struct omap_hwmod omap34xx_sr1_hwmod; -static struct omap_hwmod omap34xx_sr2_hwmod; -static struct omap_hwmod omap34xx_mcspi1; -static struct omap_hwmod omap34xx_mcspi2; -static struct omap_hwmod omap34xx_mcspi3; -static struct omap_hwmod omap34xx_mcspi4; -static struct omap_hwmod omap3xxx_mmc1_hwmod; -static struct omap_hwmod omap3xxx_mmc2_hwmod; -static struct omap_hwmod omap3xxx_mmc3_hwmod; -static struct omap_hwmod am35xx_usbhsotg_hwmod; - -static struct omap_hwmod omap3xxx_dma_system_hwmod; - -static struct omap_hwmod omap3xxx_mcbsp1_hwmod; -static struct omap_hwmod omap3xxx_mcbsp2_hwmod; -static struct omap_hwmod omap3xxx_mcbsp3_hwmod; -static struct omap_hwmod omap3xxx_mcbsp4_hwmod; -static struct omap_hwmod omap3xxx_mcbsp5_hwmod; -static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; -static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; -static struct omap_hwmod omap3xxx_usb_host_hs_hwmod; -static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod; - -/* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_l4_core_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L3 -> L4_PER interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_l4_per_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; +/* + * IP blocks + */ -/* L3 taret configuration and error log registers */ +/* L3 */ static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { { .irq = INT_34XX_L3_DBG_IRQ }, { .irq = INT_34XX_L3_APP_IRQ }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { - { - .pa_start = 0x68000000, - .pa_end = 0x6800ffff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -/* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { - .master = &omap3xxx_mpu_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .addr = omap3xxx_l3_main_addrs, - .user = OCP_USER_MPU, -}; - -/* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { - &omap3xxx_mpu__l3_main, -}; - -/* DSS -> l3 */ -static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { - .master = &omap3xxx_dss_core_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .fw = { - .omap2 = { - .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, - .flags = OMAP_FIREWALL_L3, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { - &omap3xxx_l3_main__l4_core, - &omap3xxx_l3_main__l4_per, -}; - -/* L3 */ static struct omap_hwmod omap3xxx_l3_main_hwmod = { .name = "l3_main", .class = &l3_hwmod_class, .mpu_irqs = omap3xxx_l3_main_irqs, - .masters = omap3xxx_l3_main_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), - .slaves = omap3xxx_l3_main_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), .flags = HWMOD_NO_IDLEST, }; -static struct omap_hwmod omap3xxx_l4_wkup_hwmod; -static struct omap_hwmod omap3xxx_uart1_hwmod; -static struct omap_hwmod omap3xxx_uart2_hwmod; -static struct omap_hwmod omap3xxx_uart3_hwmod; -static struct omap_hwmod omap3xxx_uart4_hwmod; -static struct omap_hwmod am35xx_uart4_hwmod; -static struct omap_hwmod omap3xxx_usbhsotg_hwmod; - -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { - .master = &omap3xxx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, -}; - -/* l3_core -> am35xx_usbhsotg interface */ -static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { - .master = &am35xx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, -}; -/* L4_CORE -> L4_WKUP interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_l4_wkup_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> MMC1 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mmc1_hwmod, - .clk = "mmchs1_ick", - .addr = omap2430_mmc1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 -}; - -/* L4 CORE -> MMC2 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mmc2_hwmod, - .clk = "mmchs2_ick", - .addr = omap2430_mmc2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 -}; - -/* L4 CORE -> MMC3 interface */ -static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { - { - .pa_start = 0x480ad000, - .pa_end = 0x480ad1ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mmc3_hwmod, - .clk = "mmchs3_ick", - .addr = omap3xxx_mmc3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, - .flags = OMAP_FIREWALL_L4 -}; - -/* L4 CORE -> UART1 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { - { - .pa_start = OMAP3_UART1_BASE, - .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart1_hwmod, - .clk = "uart1_ick", - .addr = omap3xxx_uart1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> UART2 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { - { - .pa_start = OMAP3_UART2_BASE, - .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_uart2_hwmod, - .clk = "uart2_ick", - .addr = omap3xxx_uart2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART3 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { - { - .pa_start = OMAP3_UART3_BASE, - .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart3_hwmod, - .clk = "uart3_ick", - .addr = omap3xxx_uart3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 PER -> UART4 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { - { - .pa_start = OMAP3_UART4_BASE, - .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart4_hwmod, - .clk = "uart4_ick", - .addr = omap3xxx_uart4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* AM35xx: L4 CORE -> UART4 interface */ -static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { - { - .pa_start = OMAP3_UART4_AM35XX_BASE, - .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, - }, -}; - -static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_uart4_hwmod, - .clk = "uart4_ick", - .addr = am35xx_uart4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C1 interface */ -static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c1_hwmod, - .clk = "i2c1_ick", - .addr = omap2_i2c1_addr_space, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C2 interface */ -static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c2_hwmod, - .clk = "i2c2_ick", - .addr = omap2_i2c2_addr_space, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* L4 CORE -> I2C3 interface */ -static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { - { - .pa_start = 0x48060000, - .pa_end = 0x48060000 + SZ_128 - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_i2c3_hwmod, - .clk = "i2c3_ick", - .addr = omap3xxx_i2c3_addr_space, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, - .l4_prot_group = 7, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { - { .irq = 18}, - { .irq = -1 } -}; - -static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { - { .irq = 19}, - { .irq = -1 } -}; - -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { - { - .pa_start = OMAP34XX_SR1_BASE, - .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_sr1_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr1_addr_space, - .user = OCP_USER_MPU, -}; - -/* L4 CORE -> SR1 interface */ -static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { - { - .pa_start = OMAP34XX_SR2_BASE, - .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_sr2_hwmod, - .clk = "sr_l4_ick", - .addr = omap3_sr2_addr_space, - .user = OCP_USER_MPU, -}; - -/* -* usbhsotg interface data -*/ - -static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { - { - .pa_start = OMAP34XX_HSUSB_OTG_BASE, - .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_usbhsotg_hwmod, - .clk = "l4_ick", - .addr = omap3xxx_usbhsotg_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { - &omap3xxx_usbhsotg__l3, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { - &omap3xxx_l4_core__usbhsotg, -}; - -static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { - { - .pa_start = AM35XX_IPSS_USBOTGSS_BASE, - .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_usbhsotg_hwmod, - .clk = "l4_ick", - .addr = am35xx_usbhsotg_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { - &am35xx_usbhsotg__l3, -}; - -static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { - &am35xx_l4_core__usbhsotg, -}; -/* Slave interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { - &omap3xxx_l3_main__l4_core, -}; - /* L4 CORE */ static struct omap_hwmod omap3xxx_l4_core_hwmod = { .name = "l4_core", .class = &l4_hwmod_class, - .slaves = omap3xxx_l4_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), .flags = HWMOD_NO_IDLEST, }; -/* Slave interfaces on the L4_PER interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { - &omap3xxx_l3_main__l4_per, -}; - /* L4 PER */ static struct omap_hwmod omap3xxx_l4_per_hwmod = { .name = "l4_per", .class = &l4_hwmod_class, - .slaves = omap3xxx_l4_per_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), .flags = HWMOD_NO_IDLEST, }; -/* Slave interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { - &omap3xxx_l4_core__l4_wkup, -}; - /* L4 WKUP */ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { .name = "l4_wkup", .class = &l4_hwmod_class, - .slaves = omap3xxx_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), .flags = HWMOD_NO_IDLEST, }; -/* Master interfaces on the MPU device */ -static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { - &omap3xxx_mpu__l3_main, +/* L4 SEC */ +static struct omap_hwmod omap3xxx_l4_sec_hwmod = { + .name = "l4_sec", + .class = &l4_hwmod_class, + .flags = HWMOD_NO_IDLEST, }; /* MPU */ @@ -530,35 +96,22 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { .name = "mpu", .class = &mpu_hwmod_class, .main_clk = "arm_fck", - .masters = omap3xxx_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), }; -/* - * IVA2_2 interface data - */ - -/* IVA2 <- L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { - .master = &omap3xxx_l3_main_hwmod, - .slave = &omap3xxx_iva_hwmod, - .clk = "iva2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, +/* IVA2 (IVA2) */ +static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { + { .name = "logic", .rst_shift = 0 }, + { .name = "seq0", .rst_shift = 1 }, + { .name = "seq1", .rst_shift = 2 }, }; -static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { - &omap3xxx_l3__iva, -}; - -/* - * IVA2 (IVA2) - */ - static struct omap_hwmod omap3xxx_iva_hwmod = { .name = "iva", .class = &iva_hwmod_class, - .masters = omap3xxx_iva_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), + .clkdm_name = "iva2_clkdm", + .rst_lines = omap3xxx_iva_resets, + .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), + .main_clk = "iva2_ck", }; /* timer class */ @@ -597,46 +150,20 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { /* secure timers dev attribute */ static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { - .timer_capability = OMAP_TIMER_SECURE, + .timer_capability = OMAP_TIMER_SECURE, }; /* always-on timers dev attribute */ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { - .timer_capability = OMAP_TIMER_ALWON, + .timer_capability = OMAP_TIMER_ALWON, }; /* pwm timers dev attribute */ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { - .timer_capability = OMAP_TIMER_HAS_PWM, + .timer_capability = OMAP_TIMER_HAS_PWM, }; /* timer1 */ -static struct omap_hwmod omap3xxx_timer1_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { - { - .pa_start = 0x48318000, - .pa_end = 0x48318000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_timer1_hwmod, - .clk = "gpt1_ick", - .addr = omap3xxx_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer1 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { - &omap3xxx_l4_wkup__timer1, -}; - -/* timer1 hwmod */ static struct omap_hwmod omap3xxx_timer1_hwmod = { .name = "timer1", .mpu_irqs = omap2_timer1_mpu_irqs, @@ -651,38 +178,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, }; /* timer2 */ -static struct omap_hwmod omap3xxx_timer2_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { - { - .pa_start = 0x49032000, - .pa_end = 0x49032000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer2_hwmod, - .clk = "gpt2_ick", - .addr = omap3xxx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer2 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { - &omap3xxx_l4_per__timer2, -}; - -/* timer2 hwmod */ static struct omap_hwmod omap3xxx_timer2_hwmod = { .name = "timer2", .mpu_irqs = omap2_timer2_mpu_irqs, @@ -697,38 +196,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, }; /* timer3 */ -static struct omap_hwmod omap3xxx_timer3_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { - { - .pa_start = 0x49034000, - .pa_end = 0x49034000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer3_hwmod, - .clk = "gpt3_ick", - .addr = omap3xxx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { - &omap3xxx_l4_per__timer3, -}; - -/* timer3 hwmod */ static struct omap_hwmod omap3xxx_timer3_hwmod = { .name = "timer3", .mpu_irqs = omap2_timer3_mpu_irqs, @@ -743,38 +214,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer4 */ -static struct omap_hwmod omap3xxx_timer4_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { - { - .pa_start = 0x49036000, - .pa_end = 0x49036000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer4_hwmod, - .clk = "gpt4_ick", - .addr = omap3xxx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { - &omap3xxx_l4_per__timer4, -}; - -/* timer4 hwmod */ static struct omap_hwmod omap3xxx_timer4_hwmod = { .name = "timer4", .mpu_irqs = omap2_timer4_mpu_irqs, @@ -789,38 +232,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer5 */ -static struct omap_hwmod omap3xxx_timer5_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x49038000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer5 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer5_hwmod, - .clk = "gpt5_ick", - .addr = omap3xxx_timer5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer5 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { - &omap3xxx_l4_per__timer5, -}; - -/* timer5 hwmod */ static struct omap_hwmod omap3xxx_timer5_hwmod = { .name = "timer5", .mpu_irqs = omap2_timer5_mpu_irqs, @@ -835,38 +250,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer5_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer6 */ -static struct omap_hwmod omap3xxx_timer6_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { - { - .pa_start = 0x4903A000, - .pa_end = 0x4903A000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer6 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer6_hwmod, - .clk = "gpt6_ick", - .addr = omap3xxx_timer6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer6 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { - &omap3xxx_l4_per__timer6, -}; - -/* timer6 hwmod */ static struct omap_hwmod omap3xxx_timer6_hwmod = { .name = "timer6", .mpu_irqs = omap2_timer6_mpu_irqs, @@ -881,38 +268,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer6_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer7 */ -static struct omap_hwmod omap3xxx_timer7_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { - { - .pa_start = 0x4903C000, - .pa_end = 0x4903C000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer7 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer7_hwmod, - .clk = "gpt7_ick", - .addr = omap3xxx_timer7_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer7 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { - &omap3xxx_l4_per__timer7, -}; - -/* timer7 hwmod */ static struct omap_hwmod omap3xxx_timer7_hwmod = { .name = "timer7", .mpu_irqs = omap2_timer7_mpu_irqs, @@ -927,38 +286,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap3xxx_timer7_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer8 */ -static struct omap_hwmod omap3xxx_timer8_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { - { - .pa_start = 0x4903E000, - .pa_end = 0x4903E000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer8 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer8_hwmod, - .clk = "gpt8_ick", - .addr = omap3xxx_timer8_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer8 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { - &omap3xxx_l4_per__timer8, -}; - -/* timer8 hwmod */ static struct omap_hwmod omap3xxx_timer8_hwmod = { .name = "timer8", .mpu_irqs = omap2_timer8_mpu_irqs, @@ -973,38 +304,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap3xxx_timer8_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer9 */ -static struct omap_hwmod omap3xxx_timer9_hwmod; - -static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { - { - .pa_start = 0x49040000, - .pa_end = 0x49040000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer9_hwmod, - .clk = "gpt9_ick", - .addr = omap3xxx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer9 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { - &omap3xxx_l4_per__timer9, -}; - -/* timer9 hwmod */ static struct omap_hwmod omap3xxx_timer9_hwmod = { .name = "timer9", .mpu_irqs = omap2_timer9_mpu_irqs, @@ -1019,29 +322,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap3xxx_timer9_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), .class = &omap3xxx_timer_hwmod_class, }; /* timer10 */ -static struct omap_hwmod omap3xxx_timer10_hwmod; - -/* l4_core -> timer10 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer10_hwmod, - .clk = "gpt10_ick", - .addr = omap2_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer10 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { - &omap3xxx_l4_core__timer10, -}; - -/* timer10 hwmod */ static struct omap_hwmod omap3xxx_timer10_hwmod = { .name = "timer10", .mpu_irqs = omap2_timer10_mpu_irqs, @@ -1056,29 +340,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap3xxx_timer10_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), .class = &omap3xxx_timer_1ms_hwmod_class, }; /* timer11 */ -static struct omap_hwmod omap3xxx_timer11_hwmod; - -/* l4_core -> timer11 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer11_hwmod, - .clk = "gpt11_ick", - .addr = omap2_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer11 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { - &omap3xxx_l4_core__timer11, -}; - -/* timer11 hwmod */ static struct omap_hwmod omap3xxx_timer11_hwmod = { .name = "timer11", .mpu_irqs = omap2_timer11_mpu_irqs, @@ -1093,42 +358,15 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap3xxx_timer11_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), .class = &omap3xxx_timer_hwmod_class, }; -/* timer12*/ -static struct omap_hwmod omap3xxx_timer12_hwmod; +/* timer12 */ static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { { .irq = 95, }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { - { - .pa_start = 0x48304000, - .pa_end = 0x48304000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_timer12_hwmod, - .clk = "gpt12_ick", - .addr = omap3xxx_timer12_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer12 slave port */ -static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { - &omap3xxx_l4_core__timer12, -}; - -/* timer12 hwmod */ static struct omap_hwmod omap3xxx_timer12_hwmod = { .name = "timer12", .mpu_irqs = omap3xxx_timer12_mpu_irqs, @@ -1143,29 +381,9 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = { }, }, .dev_attr = &capability_secure_dev_attr, - .slaves = omap3xxx_timer12_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), .class = &omap3xxx_timer_hwmod_class, }; -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { - { - .pa_start = 0x48314000, - .pa_end = 0x4831407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_wd_timer2_hwmod, - .clk = "wdt2_ick", - .addr = omap3xxx_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* * 'wd_timer' class * 32-bit watchdog upward counter that generates a pulse on the reset pin on @@ -1203,11 +421,6 @@ static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { .pre_shutdown = &omap2_wd_timer_disable }; -/* wd_timer2 */ -static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { - &omap3xxx_l4_wkup__wd_timer2, -}; - static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap3xxx_wd_timer_hwmod_class, @@ -1221,8 +434,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, }, }, - .slaves = omap3xxx_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), /* * XXX: Use software supervised mode, HW supervised smartidle seems to * block CORE power domain idle transitions. Maybe a HW bug in wdt2? @@ -1231,11 +442,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { }; /* UART1 */ - -static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { - &omap3_l4_core__uart1, -}; - static struct omap_hwmod omap3xxx_uart1_hwmod = { .name = "uart1", .mpu_irqs = omap2_uart1_mpu_irqs, @@ -1250,17 +456,10 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = { .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, }, }, - .slaves = omap3xxx_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), .class = &omap2_uart_class, }; /* UART2 */ - -static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { - &omap3_l4_core__uart2, -}; - static struct omap_hwmod omap3xxx_uart2_hwmod = { .name = "uart2", .mpu_irqs = omap2_uart2_mpu_irqs, @@ -1275,17 +474,10 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = { .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, }, }, - .slaves = omap3xxx_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), .class = &omap2_uart_class, }; /* UART3 */ - -static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { - &omap3_l4_per__uart3, -}; - static struct omap_hwmod omap3xxx_uart3_hwmod = { .name = "uart3", .mpu_irqs = omap2_uart3_mpu_irqs, @@ -1300,13 +492,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = { .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, }, }, - .slaves = omap3xxx_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), .class = &omap2_uart_class, }; /* UART4 */ - static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { { .irq = INT_36XX_UART4_IRQ, }, { .irq = -1 } @@ -1318,11 +507,7 @@ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { - &omap3_l4_per__uart4, -}; - -static struct omap_hwmod omap3xxx_uart4_hwmod = { +static struct omap_hwmod omap36xx_uart4_hwmod = { .name = "uart4", .mpu_irqs = uart4_mpu_irqs, .sdma_reqs = uart4_sdma_reqs, @@ -1336,8 +521,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, }, }, - .slaves = omap3xxx_uart4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), .class = &omap2_uart_class, }; @@ -1350,16 +533,12 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, }; -static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = { - &am35xx_l4_core__uart4, -}; - static struct omap_hwmod am35xx_uart4_hwmod = { - .name = "uart4", - .mpu_irqs = am35xx_uart4_mpu_irqs, - .sdma_reqs = am35xx_uart4_sdma_reqs, - .main_clk = "uart4_fck", - .prcm = { + .name = "uart4", + .mpu_irqs = am35xx_uart4_mpu_irqs, + .sdma_reqs = am35xx_uart4_sdma_reqs, + .main_clk = "uart4_fck", + .prcm = { .omap2 = { .module_offs = CORE_MOD, .prcm_reg_id = 1, @@ -1368,12 +547,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = { .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, }, }, - .slaves = am35xx_uart4_slaves, - .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves), - .class = &omap2_uart_class, + .class = &omap2_uart_class, }; - static struct omap_hwmod_class i2c_class = { .name = "i2c", .sysc = &i2c_sysc, @@ -1388,51 +564,6 @@ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { }; /* dss */ -/* dss master ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { - &omap3xxx_dss__l3, -}; - -/* l4_core -> dss */ -static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3430es1_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_core_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss slave ports */ -static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { - &omap3430es1_l4_core__dss, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { - &omap3xxx_l4_core__dss, -}; - static struct omap_hwmod_opt_clk dss_opt_clks[] = { /* * The DSS HW needs all DSS clocks enabled during reset. The dss_core @@ -1460,10 +591,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { }, .opt_clks = dss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap3430es1_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), - .masters = omap3xxx_dss_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, }; @@ -1485,10 +612,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { }, .opt_clks = dss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap3xxx_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), - .masters = omap3xxx_dss_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), }; /* @@ -1513,27 +636,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = { .sysc = &omap3_dispc_sysc, }; -/* l4_core -> dss_dispc */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_dispc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_dispc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_dispc slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { - &omap3xxx_l4_core__dss_dispc, -}; - static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap3_dispc_hwmod_class, @@ -1546,8 +648,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .module_offs = OMAP3430_DSS_MOD, }, }, - .slaves = omap3xxx_dss_dispc_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), .flags = HWMOD_NO_IDLEST, .dev_attr = &omap2_3_dss_dispc_dev_attr }; @@ -1567,36 +667,6 @@ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { }; /* dss_dsi1 */ -static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { - { - .pa_start = 0x4804FC00, - .pa_end = 0x4804FFFF, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_dsi1_hwmod, - .clk = "dss_ick", - .addr = omap3xxx_dss_dsi1_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_dsi1 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { - &omap3xxx_l4_core__dss_dsi1, -}; - static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { { .role = "sys_clk", .clk = "dss2_alwon_fck" }, }; @@ -1615,32 +685,9 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { }, .opt_clks = dss_dsi1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), - .slaves = omap3xxx_dss_dsi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), .flags = HWMOD_NO_IDLEST, }; -/* l4_core -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_rfbi_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_rfbi_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , - .flags = OMAP_FIREWALL_L4, - } - }, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_rfbi slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { - &omap3xxx_l4_core__dss_rfbi, -}; - static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "dss_ick" }, }; @@ -1658,33 +705,9 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { }, .opt_clks = dss_rfbi_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .slaves = omap3xxx_dss_rfbi_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), .flags = HWMOD_NO_IDLEST, }; -/* l4_core -> dss_venc */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dss_venc_hwmod, - .clk = "dss_ick", - .addr = omap2_dss_venc_addrs, - .fw = { - .omap2 = { - .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, - .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, - .flags = OMAP_FIREWALL_L4, - } - }, - .flags = OCPIF_SWSUP_IDLE, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss_venc slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { - &omap3xxx_l4_core__dss_venc, -}; - static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { /* required only on OMAP3430 */ { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, @@ -1703,13 +726,10 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = { }, .opt_clks = dss_venc_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), - .slaves = omap3xxx_dss_venc_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), .flags = HWMOD_NO_IDLEST, }; /* I2C1 */ - static struct omap_i2c_dev_attr i2c1_dev_attr = { .fifo_depth = 8, /* bytes */ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | @@ -1717,10 +737,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = { OMAP_I2C_FLAG_BUS_SHIFT_2, }; -static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { - &omap3_l4_core__i2c1, -}; - static struct omap_hwmod omap3xxx_i2c1_hwmod = { .name = "i2c1", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, @@ -1736,14 +752,11 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = { .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, }, }, - .slaves = omap3xxx_i2c1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), .class = &i2c_class, .dev_attr = &i2c1_dev_attr, }; /* I2C2 */ - static struct omap_i2c_dev_attr i2c2_dev_attr = { .fifo_depth = 8, /* bytes */ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | @@ -1751,10 +764,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = { OMAP_I2C_FLAG_BUS_SHIFT_2, }; -static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { - &omap3_l4_core__i2c2, -}; - static struct omap_hwmod omap3xxx_i2c2_hwmod = { .name = "i2c2", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, @@ -1770,14 +779,11 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = { .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, }, }, - .slaves = omap3xxx_i2c2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), .class = &i2c_class, .dev_attr = &i2c2_dev_attr, }; /* I2C3 */ - static struct omap_i2c_dev_attr i2c3_dev_attr = { .fifo_depth = 64, /* bytes */ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | @@ -1796,10 +802,6 @@ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { - &omap3_l4_core__i2c3, -}; - static struct omap_hwmod omap3xxx_i2c3_hwmod = { .name = "i2c3", .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, @@ -1815,114 +817,10 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = { .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, }, }, - .slaves = omap3xxx_i2c3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), .class = &i2c_class, .dev_attr = &i2c3_dev_attr, }; -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { - { - .pa_start = 0x48310000, - .pa_end = 0x483101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_gpio1_hwmod, - .addr = omap3xxx_gpio1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio2 */ -static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { - { - .pa_start = 0x49050000, - .pa_end = 0x490501ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio2_hwmod, - .addr = omap3xxx_gpio2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio3 */ -static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { - { - .pa_start = 0x49052000, - .pa_end = 0x490521ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio3_hwmod, - .addr = omap3xxx_gpio3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio4 */ -static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { - { - .pa_start = 0x49054000, - .pa_end = 0x490541ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio4_hwmod, - .addr = omap3xxx_gpio4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio5 */ -static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { - { - .pa_start = 0x49056000, - .pa_end = 0x490561ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio5_hwmod, - .addr = omap3xxx_gpio5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per -> gpio6 */ -static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { - { - .pa_start = 0x49058000, - .pa_end = 0x490581ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_gpio6_hwmod, - .addr = omap3xxx_gpio6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* * 'gpio' class * general purpose io module @@ -1945,7 +843,7 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { .rev = 1, }; -/* gpio_dev_attr*/ +/* gpio_dev_attr */ static struct omap_gpio_dev_attr gpio_dev_attr = { .bank_width = 32, .dbck_flag = true, @@ -1956,10 +854,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { - &omap3xxx_l4_wkup__gpio1, -}; - static struct omap_hwmod omap3xxx_gpio1_hwmod = { .name = "gpio1", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -1976,8 +870,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, }, }, - .slaves = omap3xxx_gpio1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -1987,10 +879,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { - &omap3xxx_l4_per__gpio2, -}; - static struct omap_hwmod omap3xxx_gpio2_hwmod = { .name = "gpio2", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2007,8 +895,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, }, }, - .slaves = omap3xxx_gpio2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -2018,10 +904,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { - &omap3xxx_l4_per__gpio3, -}; - static struct omap_hwmod omap3xxx_gpio3_hwmod = { .name = "gpio3", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2038,8 +920,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, }, }, - .slaves = omap3xxx_gpio3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -2049,10 +929,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { { .role = "dbclk", .clk = "gpio4_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { - &omap3xxx_l4_per__gpio4, -}; - static struct omap_hwmod omap3xxx_gpio4_hwmod = { .name = "gpio4", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2069,8 +945,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, }, }, - .slaves = omap3xxx_gpio4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -2085,10 +959,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { { .role = "dbclk", .clk = "gpio5_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { - &omap3xxx_l4_per__gpio5, -}; - static struct omap_hwmod omap3xxx_gpio5_hwmod = { .name = "gpio5", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2105,8 +975,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, }, }, - .slaves = omap3xxx_gpio5_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; @@ -2121,10 +989,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { { .role = "dbclk", .clk = "gpio6_dbck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { - &omap3xxx_l4_per__gpio6, -}; - static struct omap_hwmod omap3xxx_gpio6_hwmod = { .name = "gpio6", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2141,20 +1005,10 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, }, }, - .slaves = omap3xxx_gpio6_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), .class = &omap3xxx_gpio_hwmod_class, .dev_attr = &gpio_dev_attr, }; -/* dma_system -> L3 */ -static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { - .master = &omap3xxx_dma_system_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* dma attributes */ static struct omap_dma_dev_attr dma_dev_attr = { .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | @@ -2181,34 +1035,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { }; /* dma_system */ -static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { - { - .pa_start = 0x48056000, - .pa_end = 0x48056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* dma_system master ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { - &omap3xxx_dma_system__l3, -}; - -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_dma_system_hwmod, - .clk = "core_l4_ick", - .addr = omap3xxx_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { - &omap3xxx_l4_core__dma_system, -}; - static struct omap_hwmod omap3xxx_dma_system_hwmod = { .name = "dma", .class = &omap3xxx_dma_hwmod_class, @@ -2223,10 +1049,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = { .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, }, }, - .slaves = omap3xxx_dma_system_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), - .masters = omap3xxx_dma_system_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), .dev_attr = &dma_dev_attr, .flags = HWMOD_NO_IDLEST, }; @@ -2259,30 +1081,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48074000, - .pa_end = 0x480740ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mcbsp1_hwmod, - .clk = "mcbsp1_ick", - .addr = omap3xxx_mcbsp1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp1 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { - &omap3xxx_l4_core__mcbsp1, -}; - static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { .name = "mcbsp1", .class = &omap3xxx_mcbsp_hwmod_class, @@ -2298,8 +1096,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, }, }, - .slaves = omap3xxx_mcbsp1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), }; /* mcbsp2 */ @@ -2310,30 +1106,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp2_hwmod, - .clk = "mcbsp2_ick", - .addr = omap3xxx_mcbsp2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp2 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { - &omap3xxx_l4_per__mcbsp2, -}; - static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { .sidetone = "mcbsp2_sidetone", }; @@ -2353,8 +1125,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, }, }, - .slaves = omap3xxx_mcbsp2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), .dev_attr = &omap34xx_mcbsp2_dev_attr, }; @@ -2366,32 +1136,8 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp3_hwmod, - .clk = "mcbsp3_ick", - .addr = omap3xxx_mcbsp3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp3 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { - &omap3xxx_l4_per__mcbsp3, -}; - static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { - .sidetone = "mcbsp3_sidetone", + .sidetone = "mcbsp3_sidetone", }; static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { @@ -2409,8 +1155,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, }, }, - .slaves = omap3xxx_mcbsp3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), .dev_attr = &omap34xx_mcbsp3_dev_attr, }; @@ -2428,30 +1172,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { - { - .name = "mpu", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp4_hwmod, - .clk = "mcbsp4_ick", - .addr = omap3xxx_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp4 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { - &omap3xxx_l4_per__mcbsp4, -}; - static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { .name = "mcbsp4", .class = &omap3xxx_mcbsp_hwmod_class, @@ -2467,8 +1187,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, }, }, - .slaves = omap3xxx_mcbsp4_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), }; /* mcbsp5 */ @@ -2485,30 +1203,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { - { - .name = "mpu", - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_core -> mcbsp5 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mcbsp5_hwmod, - .clk = "mcbsp5_ick", - .addr = omap3xxx_mcbsp5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp5 slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { - &omap3xxx_l4_core__mcbsp5, -}; - static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { .name = "mcbsp5", .class = &omap3xxx_mcbsp_hwmod_class, @@ -2524,11 +1218,9 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, }, }, - .slaves = omap3xxx_mcbsp5_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), }; -/* 'mcbsp sidetone' class */ +/* 'mcbsp sidetone' class */ static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { .sysc_offs = 0x0010, .sysc_flags = SYSC_HAS_AUTOIDLE, @@ -2546,30 +1238,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { - { - .name = "sidetone", - .pa_start = 0x49028000, - .pa_end = 0x490280ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp2_sidetone */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp2_sidetone_hwmod, - .clk = "mcbsp2_ick", - .addr = omap3xxx_mcbsp2_sidetone_addrs, - .user = OCP_USER_MPU, -}; - -/* mcbsp2_sidetone slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { - &omap3xxx_l4_per__mcbsp2_sidetone, -}; - static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { .name = "mcbsp2_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, @@ -2584,8 +1252,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, }, }, - .slaves = omap3xxx_mcbsp2_sidetone_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), }; /* mcbsp3_sidetone */ @@ -2594,30 +1260,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { - { - .name = "sidetone", - .pa_start = 0x4902A000, - .pa_end = 0x4902A0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp3_sidetone */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_mcbsp3_sidetone_hwmod, - .clk = "mcbsp3_ick", - .addr = omap3xxx_mcbsp3_sidetone_addrs, - .user = OCP_USER_MPU, -}; - -/* mcbsp3_sidetone slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { - &omap3xxx_l4_per__mcbsp3_sidetone, -}; - static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { .name = "mcbsp3_sidetone", .class = &omap3xxx_mcbsp_sidetone_hwmod_class, @@ -2632,11 +1274,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, }, }, - .slaves = omap3xxx_mcbsp3_sidetone_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), }; - /* SR common */ static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { .clkact_shift = 20, @@ -2657,7 +1296,7 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { .sidle_shift = 24, - .enwkup_shift = 26 + .enwkup_shift = 26, }; static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { @@ -2679,12 +1318,13 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = { .sensor_voltdm_name = "mpu_iva", }; -static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { - &omap3_l4_core__sr1, +static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { + { .irq = 18 }, + { .irq = -1 } }; static struct omap_hwmod omap34xx_sr1_hwmod = { - .name = "sr1_hwmod", + .name = "sr1", .class = &omap34xx_smartreflex_hwmod_class, .main_clk = "sr1_fck", .prcm = { @@ -2696,15 +1336,13 @@ static struct omap_hwmod omap34xx_sr1_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, }, }, - .slaves = omap3_sr1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), .dev_attr = &sr1_dev_attr, .mpu_irqs = omap3_smartreflex_mpu_irqs, .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; static struct omap_hwmod omap36xx_sr1_hwmod = { - .name = "sr1_hwmod", + .name = "sr1", .class = &omap36xx_smartreflex_hwmod_class, .main_clk = "sr1_fck", .prcm = { @@ -2716,8 +1354,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, }, }, - .slaves = omap3_sr1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), .dev_attr = &sr1_dev_attr, .mpu_irqs = omap3_smartreflex_mpu_irqs, }; @@ -2727,12 +1363,13 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = { .sensor_voltdm_name = "core", }; -static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { - &omap3_l4_core__sr2, +static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { + { .irq = 19 }, + { .irq = -1 } }; static struct omap_hwmod omap34xx_sr2_hwmod = { - .name = "sr2_hwmod", + .name = "sr2", .class = &omap34xx_smartreflex_hwmod_class, .main_clk = "sr2_fck", .prcm = { @@ -2744,15 +1381,13 @@ static struct omap_hwmod omap34xx_sr2_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, }, }, - .slaves = omap3_sr2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), .dev_attr = &sr2_dev_attr, .mpu_irqs = omap3_smartreflex_core_irqs, .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; static struct omap_hwmod omap36xx_sr2_hwmod = { - .name = "sr2_hwmod", + .name = "sr2", .class = &omap36xx_smartreflex_hwmod_class, .main_clk = "sr2_fck", .prcm = { @@ -2764,8 +1399,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, }, }, - .slaves = omap3_sr2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), .dev_attr = &sr2_dev_attr, .mpu_irqs = omap3_smartreflex_core_irqs, }; @@ -2791,34 +1424,11 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { .sysc = &omap3xxx_mailbox_sysc, }; -static struct omap_hwmod omap3xxx_mailbox_hwmod; static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { { .irq = 26 }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { - { - .pa_start = 0x48094000, - .pa_end = 0x480941ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -/* l4_core -> mailbox */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_mailbox_hwmod, - .addr = omap3xxx_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mailbox slave ports */ -static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { - &omap3xxx_l4_core__mailbox, -}; - static struct omap_hwmod omap3xxx_mailbox_hwmod = { .name = "mailbox", .class = &omap3xxx_mailbox_hwmod_class, @@ -2833,53 +1443,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = { .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, }, }, - .slaves = omap3xxx_mailbox_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), -}; - -/* l4 core -> mcspi1 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi1, - .clk = "mcspi1_ick", - .addr = omap2_mcspi1_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi2 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi2, - .clk = "mcspi2_ick", - .addr = omap2_mcspi2_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi3 interface */ -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi3, - .clk = "mcspi3_ick", - .addr = omap2430_mcspi3_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 core -> mcspi4 interface */ -static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { - { - .pa_start = 0x480ba000, - .pa_end = 0x480ba0ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - -static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap34xx_mcspi4, - .clk = "mcspi4_ick", - .addr = omap34xx_mcspi4_addr_space, - .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* @@ -2906,10 +1469,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = { }; /* mcspi1 */ -static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { - &omap34xx_l4_core__mcspi1, -}; - static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { .num_chipselect = 4, }; @@ -2928,17 +1487,11 @@ static struct omap_hwmod omap34xx_mcspi1 = { .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, }, }, - .slaves = omap34xx_mcspi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi1_dev_attr, }; /* mcspi2 */ -static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { - &omap34xx_l4_core__mcspi2, -}; - static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { .num_chipselect = 2, }; @@ -2957,8 +1510,6 @@ static struct omap_hwmod omap34xx_mcspi2 = { .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, }, }, - .slaves = omap34xx_mcspi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi2_dev_attr, }; @@ -2977,10 +1528,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { - &omap34xx_l4_core__mcspi3, -}; - static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { .num_chipselect = 2, }; @@ -2999,13 +1546,11 @@ static struct omap_hwmod omap34xx_mcspi3 = { .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, }, }, - .slaves = omap34xx_mcspi3_slaves, - .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi3_dev_attr, }; -/* SPI4 */ +/* mcspi4 */ static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ { .irq = -1 } @@ -3017,10 +1562,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { - &omap34xx_l4_core__mcspi4, -}; - static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { .num_chipselect = 1, }; @@ -3039,15 +1580,11 @@ static struct omap_hwmod omap34xx_mcspi4 = { .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, }, }, - .slaves = omap34xx_mcspi4_slaves, - .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), .class = &omap34xx_mcspi_class, .dev_attr = &omap_mcspi4_dev_attr, }; -/* - * usbhsotg - */ +/* usbhsotg */ static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { .rev_offs = 0x0400, .sysc_offs = 0x0404, @@ -3064,6 +1601,7 @@ static struct omap_hwmod_class usbotg_class = { .name = "usbotg", .sysc = &omap3xxx_usbhsotg_sysc, }; + /* usb_otg_hs */ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { @@ -3086,10 +1624,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT }, }, - .masters = omap3xxx_usbhsotg_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), - .slaves = omap3xxx_usbhsotg_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), .class = &usbotg_class, /* @@ -3121,15 +1655,10 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = { .omap2 = { }, }, - .masters = am35xx_usbhsotg_masters, - .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), - .slaves = am35xx_usbhsotg_slaves, - .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), .class = &am35xx_usbotg_class, }; /* MMC/SD/SDIO common */ - static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { .rev_offs = 0x1fc, .sysc_offs = 0x10, @@ -3163,10 +1692,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { - &omap3xxx_l4_core__mmc1, -}; - static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; @@ -3194,8 +1719,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { }, }, .dev_attr = &mmc1_pre_es3_dev_attr, - .slaves = omap3xxx_mmc1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), .class = &omap34xx_mmc_class, }; @@ -3216,8 +1739,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { }, }, .dev_attr = &mmc1_dev_attr, - .slaves = omap3xxx_mmc1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), .class = &omap34xx_mmc_class, }; @@ -3238,10 +1759,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { - &omap3xxx_l4_core__mmc2, -}; - /* See 35xx errata 2.1.1.128 in SPRZ278F */ static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, @@ -3264,8 +1781,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { }, }, .dev_attr = &mmc2_pre_es3_dev_attr, - .slaves = omap3xxx_mmc2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), .class = &omap34xx_mmc_class, }; @@ -3285,8 +1800,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, }, }, - .slaves = omap3xxx_mmc2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), .class = &omap34xx_mmc_class, }; @@ -3307,10 +1820,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { { .role = "dbck", .clk = "omap_32k_fck", }, }; -static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { - &omap3xxx_l4_core__mmc3, -}; - static struct omap_hwmod omap3xxx_mmc3_hwmod = { .name = "mmc3", .mpu_irqs = omap34xx_mmc3_mpu_irqs, @@ -3326,8 +1835,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, }, }, - .slaves = omap3xxx_mmc3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), .class = &omap34xx_mmc_class, }; @@ -3335,12 +1842,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = { * 'usb_host_hs' class * high-speed multi-port usb host controller */ -static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { - .master = &omap3xxx_usb_host_hs_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, -}; static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { .rev_offs = 0x0000, @@ -3359,42 +1860,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { .sysc = &omap3xxx_usb_host_hs_sysc, }; -static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = { - &omap3xxx_usb_host_hs__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { - { - .name = "uhh", - .pa_start = 0x48064000, - .pa_end = 0x480643ff, - .flags = ADDR_TYPE_RT - }, - { - .name = "ohci", - .pa_start = 0x48064400, - .pa_end = 0x480647ff, - }, - { - .name = "ehci", - .pa_start = 0x48064800, - .pa_end = 0x48064cff, - }, - {} -}; - -static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_usb_host_hs_hwmod, - .clk = "usbhost_ick", - .addr = omap3xxx_usb_host_hs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = { - &omap3xxx_l4_core__usb_host_hs, -}; - static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, }; @@ -3423,10 +1888,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { }, .opt_clks = omap3xxx_usb_host_hs_opt_clks, .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), - .slaves = omap3xxx_usb_host_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves), - .masters = omap3xxx_usb_host_hs_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters), /* * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock @@ -3502,6 +1963,1084 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { { .irq = -1 } }; +static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap3xxx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap3xxx_usb_tll_hs_irqs, + .main_clk = "usbtll_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 3, + .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .idlest_reg_id = 3, + .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, + }, + }, +}; + +/* + * interfaces + */ + +/* L3 -> L4_CORE interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_l4_core_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L3 -> L4_PER interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_l4_per_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { + { + .pa_start = 0x68000000, + .pa_end = 0x6800ffff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* MPU -> L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { + .master = &omap3xxx_mpu_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .addr = omap3xxx_l3_main_addrs, + .user = OCP_USER_MPU, +}; + +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { + .master = &omap3430es1_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { + .master = &omap3xxx_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { + .master = &omap3xxx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + +/* l3_core -> am35xx_usbhsotg interface */ +static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { + .master = &am35xx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; +/* L4_CORE -> L4_WKUP interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_l4_wkup_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_pre_es3_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_es3plus_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_pre_es3_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_es3plus_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap2430_mmc2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +/* L4 CORE -> MMC3 interface */ +static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad1ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc3_hwmod, + .clk = "mmchs3_ick", + .addr = omap3xxx_mmc3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { + { + .pa_start = OMAP3_UART1_BASE, + .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap3xxx_uart1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { + { + .pa_start = OMAP3_UART2_BASE, + .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap3xxx_uart2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { + { + .pa_start = OMAP3_UART3_BASE, + .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap3xxx_uart3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART4 interface */ +static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_BASE, + .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap36xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = omap36xx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* AM35xx: L4 CORE -> UART4 interface */ +static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_AM35XX_BASE, + .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_uart4_hwmod, + .clk = "uart4_ick", + .addr = am35xx_uart4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2_i2c1_addr_space, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2_i2c2_addr_space, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C3 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x48060000 + SZ_128 - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c3_hwmod, + .clk = "i2c3_ick", + .addr = omap3xxx_i2c3_addr_space, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { + { + .pa_start = OMAP34XX_SR1_BASE, + .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap36xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .user = OCP_USER_MPU, +}; + +/* L4 CORE -> SR1 interface */ +static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { + { + .pa_start = OMAP34XX_SR2_BASE, + .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap36xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { + { + .pa_start = OMAP34XX_HSUSB_OTG_BASE, + .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = omap3xxx_usbhsotg_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { + { + .pa_start = AM35XX_IPSS_USBOTGSS_BASE, + .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = am35xx_usbhsotg_addrs, + .user = OCP_USER_MPU, +}; + +/* L4_WKUP -> L4_SEC interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_l4_sec_hwmod, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_iva_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { + { + .pa_start = 0x48318000, + .pa_end = 0x48318000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap3xxx_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x49032000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap3xxx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { + { + .pa_start = 0x49034000, + .pa_end = 0x49034000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap3xxx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { + { + .pa_start = 0x49036000, + .pa_end = 0x49036000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap3xxx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x49038000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap3xxx_timer5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { + { + .pa_start = 0x4903A000, + .pa_end = 0x4903A000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer6 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap3xxx_timer6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { + { + .pa_start = 0x4903C000, + .pa_end = 0x4903C000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer7 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap3xxx_timer7_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { + { + .pa_start = 0x4903E000, + .pa_end = 0x4903E000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer8 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap3xxx_timer8_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { + { + .pa_start = 0x49040000, + .pa_end = 0x49040000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap3xxx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { + .master = &omap3xxx_l4_sec_hwmod, + .slave = &omap3xxx_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap3xxx_timer12_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { + { + .pa_start = 0x48314000, + .pa_end = 0x4831407f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_wd_timer2_hwmod, + .clk = "wdt2_ick", + .addr = omap3xxx_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3430es1_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_dispc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { + { + .pa_start = 0x4804FC00, + .pa_end = 0x4804FFFF, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dsi1_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_dsi1_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_rfbi_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_venc_hwmod, + .clk = "dss_ick", + .addr = omap2_dss_venc_addrs, + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .flags = OCPIF_SWSUP_IDLE, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { + { + .pa_start = 0x48310000, + .pa_end = 0x483101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_gpio1_hwmod, + .addr = omap3xxx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { + { + .pa_start = 0x49050000, + .pa_end = 0x490501ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio2_hwmod, + .addr = omap3xxx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { + { + .pa_start = 0x49052000, + .pa_end = 0x490521ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio3_hwmod, + .addr = omap3xxx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { + { + .pa_start = 0x49054000, + .pa_end = 0x490541ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio4_hwmod, + .addr = omap3xxx_gpio4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { + { + .pa_start = 0x49056000, + .pa_end = 0x490561ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio5_hwmod, + .addr = omap3xxx_gpio5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { + { + .pa_start = 0x49058000, + .pa_end = 0x490581ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_gpio6_hwmod, + .addr = omap3xxx_gpio6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dma_system -> L3 */ +static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { + .master = &omap3xxx_dma_system_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { + { + .pa_start = 0x48056000, + .pa_end = 0x48056fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dma_system_hwmod, + .clk = "core_l4_ick", + .addr = omap3xxx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap3xxx_mcbsp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap3xxx_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap3xxx_mcbsp5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x49028000, + .pa_end = 0x490280ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp2_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_sidetone_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_sidetone_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x4902A000, + .pa_end = 0x4902A0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp3_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_sidetone_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_sidetone_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { + { + .pa_start = 0x48094000, + .pa_end = 0x480941ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mailbox_hwmod, + .addr = omap3xxx_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi1, + .clk = "mcspi1_ick", + .addr = omap2_mcspi1_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi2, + .clk = "mcspi2_ick", + .addr = omap2_mcspi2_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi3, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi4 interface */ +static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba0ff, + .flags = ADDR_TYPE_RT, + }, + { } +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi4, + .clk = "mcspi4_ick", + .addr = omap34xx_mcspi4_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { + .master = &omap3xxx_usb_host_hs_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { + { + .name = "uhh", + .pa_start = 0x48064000, + .pa_end = 0x480643ff, + .flags = ADDR_TYPE_RT + }, + { + .name = "ohci", + .pa_start = 0x48064400, + .pa_end = 0x480647ff, + }, + { + .name = "ehci", + .pa_start = 0x48064800, + .pa_end = 0x48064cff, + }, + {} +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usb_host_hs_hwmod, + .clk = "usbhost_ick", + .addr = omap3xxx_usb_host_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { { .name = "tll", @@ -3520,183 +3059,156 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { - &omap3xxx_l4_core__usb_tll_hs, -}; - -static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap3xxx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .mpu_irqs = omap3xxx_usb_tll_hs_irqs, - .main_clk = "usbtll_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .prcm_reg_id = 3, - .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .idlest_reg_id = 3, - .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, - }, - }, - .slaves = omap3xxx_usb_tll_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), -}; - -static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { - &omap3xxx_l3_main_hwmod, - &omap3xxx_l4_core_hwmod, - &omap3xxx_l4_per_hwmod, - &omap3xxx_l4_wkup_hwmod, - &omap3xxx_mmc3_hwmod, - &omap3xxx_mpu_hwmod, - - &omap3xxx_timer1_hwmod, - &omap3xxx_timer2_hwmod, - &omap3xxx_timer3_hwmod, - &omap3xxx_timer4_hwmod, - &omap3xxx_timer5_hwmod, - &omap3xxx_timer6_hwmod, - &omap3xxx_timer7_hwmod, - &omap3xxx_timer8_hwmod, - &omap3xxx_timer9_hwmod, - &omap3xxx_timer10_hwmod, - &omap3xxx_timer11_hwmod, - - &omap3xxx_wd_timer2_hwmod, - &omap3xxx_uart1_hwmod, - &omap3xxx_uart2_hwmod, - &omap3xxx_uart3_hwmod, - - /* i2c class */ - &omap3xxx_i2c1_hwmod, - &omap3xxx_i2c2_hwmod, - &omap3xxx_i2c3_hwmod, - - /* gpio class */ - &omap3xxx_gpio1_hwmod, - &omap3xxx_gpio2_hwmod, - &omap3xxx_gpio3_hwmod, - &omap3xxx_gpio4_hwmod, - &omap3xxx_gpio5_hwmod, - &omap3xxx_gpio6_hwmod, - - /* dma_system class*/ - &omap3xxx_dma_system_hwmod, - - /* mcbsp class */ - &omap3xxx_mcbsp1_hwmod, - &omap3xxx_mcbsp2_hwmod, - &omap3xxx_mcbsp3_hwmod, - &omap3xxx_mcbsp4_hwmod, - &omap3xxx_mcbsp5_hwmod, - &omap3xxx_mcbsp2_sidetone_hwmod, - &omap3xxx_mcbsp3_sidetone_hwmod, - - - /* mcspi class */ - &omap34xx_mcspi1, - &omap34xx_mcspi2, - &omap34xx_mcspi3, - &omap34xx_mcspi4, - +static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l3_main__l4_core, + &omap3xxx_l3_main__l4_per, + &omap3xxx_mpu__l3_main, + &omap3xxx_l4_core__l4_wkup, + &omap3xxx_l4_core__mmc3, + &omap3_l4_core__uart1, + &omap3_l4_core__uart2, + &omap3_l4_per__uart3, + &omap3_l4_core__i2c1, + &omap3_l4_core__i2c2, + &omap3_l4_core__i2c3, + &omap3xxx_l4_wkup__l4_sec, + &omap3xxx_l4_wkup__timer1, + &omap3xxx_l4_per__timer2, + &omap3xxx_l4_per__timer3, + &omap3xxx_l4_per__timer4, + &omap3xxx_l4_per__timer5, + &omap3xxx_l4_per__timer6, + &omap3xxx_l4_per__timer7, + &omap3xxx_l4_per__timer8, + &omap3xxx_l4_per__timer9, + &omap3xxx_l4_core__timer10, + &omap3xxx_l4_core__timer11, + &omap3xxx_l4_wkup__wd_timer2, + &omap3xxx_l4_wkup__gpio1, + &omap3xxx_l4_per__gpio2, + &omap3xxx_l4_per__gpio3, + &omap3xxx_l4_per__gpio4, + &omap3xxx_l4_per__gpio5, + &omap3xxx_l4_per__gpio6, + &omap3xxx_dma_system__l3, + &omap3xxx_l4_core__dma_system, + &omap3xxx_l4_core__mcbsp1, + &omap3xxx_l4_per__mcbsp2, + &omap3xxx_l4_per__mcbsp3, + &omap3xxx_l4_per__mcbsp4, + &omap3xxx_l4_core__mcbsp5, + &omap3xxx_l4_per__mcbsp2_sidetone, + &omap3xxx_l4_per__mcbsp3_sidetone, + &omap34xx_l4_core__mcspi1, + &omap34xx_l4_core__mcspi2, + &omap34xx_l4_core__mcspi3, + &omap34xx_l4_core__mcspi4, NULL, }; -/* GP-only hwmods */ -static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { - &omap3xxx_timer12_hwmod, +/* GP-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_sec__timer12, NULL }; -/* 3430ES1-only hwmods */ -static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { - &omap3430es1_dss_core_hwmod, +/* 3430ES1-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { + &omap3430es1_dss__l3, + &omap3430es1_l4_core__dss, NULL }; -/* 3430ES2+-only hwmods */ -static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { - &omap3xxx_dss_core_hwmod, - &omap3xxx_usbhsotg_hwmod, - &omap3xxx_usb_host_hs_hwmod, - &omap3xxx_usb_tll_hs_hwmod, +/* 3430ES2+-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_dss__l3, + &omap3xxx_l4_core__dss, + &omap3xxx_usbhsotg__l3, + &omap3xxx_l4_core__usbhsotg, + &omap3xxx_usb_host_hs__l3_main_2, + &omap3xxx_l4_core__usb_host_hs, + &omap3xxx_l4_core__usb_tll_hs, NULL }; -/* <= 3430ES3-only hwmods */ -static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { - &omap3xxx_pre_es3_mmc1_hwmod, - &omap3xxx_pre_es3_mmc2_hwmod, +/* <= 3430ES3-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_core__pre_es3_mmc1, + &omap3xxx_l4_core__pre_es3_mmc2, NULL }; -/* 3430ES3+-only hwmods */ -static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { - &omap3xxx_es3plus_mmc1_hwmod, - &omap3xxx_es3plus_mmc2_hwmod, +/* 3430ES3+-only hwmod links */ +static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_core__es3plus_mmc1, + &omap3xxx_l4_core__es3plus_mmc2, NULL }; -/* 34xx-only hwmods (all ES revisions) */ -static __initdata struct omap_hwmod *omap34xx_hwmods[] = { - &omap3xxx_iva_hwmod, - &omap34xx_sr1_hwmod, - &omap34xx_sr2_hwmod, - &omap3xxx_mailbox_hwmod, +/* 34xx-only hwmod links (all ES revisions) */ +static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l3__iva, + &omap34xx_l4_core__sr1, + &omap34xx_l4_core__sr2, + &omap3xxx_l4_core__mailbox, NULL }; -/* 36xx-only hwmods (all ES revisions) */ -static __initdata struct omap_hwmod *omap36xx_hwmods[] = { - &omap3xxx_iva_hwmod, - &omap3xxx_uart4_hwmod, - &omap3xxx_dss_core_hwmod, - &omap36xx_sr1_hwmod, - &omap36xx_sr2_hwmod, - &omap3xxx_usbhsotg_hwmod, - &omap3xxx_mailbox_hwmod, - &omap3xxx_usb_host_hs_hwmod, - &omap3xxx_usb_tll_hs_hwmod, - &omap3xxx_es3plus_mmc1_hwmod, - &omap3xxx_es3plus_mmc2_hwmod, +/* 36xx-only hwmod links (all ES revisions) */ +static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l3__iva, + &omap36xx_l4_per__uart4, + &omap3xxx_dss__l3, + &omap3xxx_l4_core__dss, + &omap36xx_l4_core__sr1, + &omap36xx_l4_core__sr2, + &omap3xxx_usbhsotg__l3, + &omap3xxx_l4_core__usbhsotg, + &omap3xxx_l4_core__mailbox, + &omap3xxx_usb_host_hs__l3_main_2, + &omap3xxx_l4_core__usb_host_hs, + &omap3xxx_l4_core__usb_tll_hs, + &omap3xxx_l4_core__es3plus_mmc1, + &omap3xxx_l4_core__es3plus_mmc2, NULL }; -static __initdata struct omap_hwmod *am35xx_hwmods[] = { - &omap3xxx_dss_core_hwmod, /* XXX ??? */ - &am35xx_usbhsotg_hwmod, - &am35xx_uart4_hwmod, - &omap3xxx_usb_host_hs_hwmod, - &omap3xxx_usb_tll_hs_hwmod, - &omap3xxx_es3plus_mmc1_hwmod, - &omap3xxx_es3plus_mmc2_hwmod, +static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_dss__l3, + &omap3xxx_l4_core__dss, + &am35xx_usbhsotg__l3, + &am35xx_l4_core__usbhsotg, + &am35xx_l4_core__uart4, + &omap3xxx_usb_host_hs__l3_main_2, + &omap3xxx_l4_core__usb_host_hs, + &omap3xxx_l4_core__usb_tll_hs, + &omap3xxx_l4_core__es3plus_mmc1, + &omap3xxx_l4_core__es3plus_mmc2, NULL }; -static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { - /* dss class */ - &omap3xxx_dss_dispc_hwmod, - &omap3xxx_dss_dsi1_hwmod, - &omap3xxx_dss_rfbi_hwmod, - &omap3xxx_dss_venc_hwmod, +static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { + &omap3xxx_l4_core__dss_dispc, + &omap3xxx_l4_core__dss_dsi1, + &omap3xxx_l4_core__dss_rfbi, + &omap3xxx_l4_core__dss_venc, NULL }; int __init omap3xxx_hwmod_init(void) { int r; - struct omap_hwmod **h = NULL; + struct omap_hwmod_ocp_if **h = NULL; unsigned int rev; - /* Register hwmods common to all OMAP3 */ - r = omap_hwmod_register(omap3xxx_hwmods); + /* Register hwmod links common to all OMAP3 */ + r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); if (r < 0) return r; - /* Register GP-only hwmods. */ + /* Register GP-only hwmod links. */ if (omap_type() == OMAP2_DEVICE_TYPE_GP) { - r = omap_hwmod_register(omap3xxx_gp_hwmods); + r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); if (r < 0) return r; } @@ -3704,43 +3216,43 @@ int __init omap3xxx_hwmod_init(void) rev = omap_rev(); /* - * Register hwmods common to individual OMAP3 families, all + * Register hwmod links common to individual OMAP3 families, all * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) * All possible revisions should be included in this conditional. */ if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap34xx_hwmods; + h = omap34xx_hwmod_ocp_ifs; } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { - h = am35xx_hwmods; + h = am35xx_hwmod_ocp_ifs; } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) { - h = omap36xx_hwmods; + h = omap36xx_hwmod_ocp_ifs; } else { WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); return -EINVAL; }; - r = omap_hwmod_register(h); + r = omap_hwmod_register_links(h); if (r < 0) return r; /* - * Register hwmods specific to certain ES levels of a + * Register hwmod links specific to certain ES levels of a * particular family of silicon (e.g., 34xx ES1.0) */ h = NULL; if (rev == OMAP3430_REV_ES1_0) { - h = omap3430es1_hwmods; + h = omap3430es1_hwmod_ocp_ifs; } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap3430es2plus_hwmods; + h = omap3430es2plus_hwmod_ocp_ifs; }; if (h) { - r = omap_hwmod_register(h); + r = omap_hwmod_register_links(h); if (r < 0) return r; } @@ -3748,29 +3260,29 @@ int __init omap3xxx_hwmod_init(void) h = NULL; if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1) { - h = omap3430_pre_es3_hwmods; + h = omap3430_pre_es3_hwmod_ocp_ifs; } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { - h = omap3430_es3plus_hwmods; + h = omap3430_es3plus_hwmod_ocp_ifs; }; if (h) - r = omap_hwmod_register(h); + r = omap_hwmod_register_links(h); if (r < 0) return r; /* * DSS code presumes that dss_core hwmod is handled first, * _before_ any other DSS related hwmods so register common - * DSS hwmods last to ensure that dss_core is already registered. - * Otherwise some change things may happen, for ex. if dispc - * is handled before dss_core and DSS is enabled in bootloader - * DIPSC will be reset with outputs enabled which sometimes leads - * to unrecoverable L3 error. - * XXX The long-term fix to this is to ensure modules are set up - * in dependency order in the hwmod core code. + * DSS hwmod links last to ensure that dss_core is already + * registered. Otherwise some change things may happen, for + * ex. if dispc is handled before dss_core and DSS is enabled + * in bootloader DISPC will be reset with outputs enabled + * which sometimes leads to unrecoverable L3 error. XXX The + * long-term fix to this is to ensure hwmods are set up in + * dependency order in the hwmod core code. */ - r = omap_hwmod_register(omap3xxx_dss_hwmods); + r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); return r; } diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index cc9bd106a854..0d91dec5b4bc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1,7 +1,7 @@ /* * Hardware modules present on the OMAP44xx chips * - * Copyright (C) 2009-2011 Texas Instruments, Inc. + * Copyright (C) 2009-2012 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley @@ -44,38 +44,10 @@ #define OMAP44XX_IRQ_GIC_START 32 /* Base offset for all OMAP4 dma requests */ -#define OMAP44XX_DMA_REQ_START 1 - -/* Backward references (IPs with Bus Master capability) */ -static struct omap_hwmod omap44xx_aess_hwmod; -static struct omap_hwmod omap44xx_dma_system_hwmod; -static struct omap_hwmod omap44xx_dmm_hwmod; -static struct omap_hwmod omap44xx_dsp_hwmod; -static struct omap_hwmod omap44xx_dss_hwmod; -static struct omap_hwmod omap44xx_emif_fw_hwmod; -static struct omap_hwmod omap44xx_hsi_hwmod; -static struct omap_hwmod omap44xx_ipu_hwmod; -static struct omap_hwmod omap44xx_iss_hwmod; -static struct omap_hwmod omap44xx_iva_hwmod; -static struct omap_hwmod omap44xx_l3_instr_hwmod; -static struct omap_hwmod omap44xx_l3_main_1_hwmod; -static struct omap_hwmod omap44xx_l3_main_2_hwmod; -static struct omap_hwmod omap44xx_l3_main_3_hwmod; -static struct omap_hwmod omap44xx_l4_abe_hwmod; -static struct omap_hwmod omap44xx_l4_cfg_hwmod; -static struct omap_hwmod omap44xx_l4_per_hwmod; -static struct omap_hwmod omap44xx_l4_wkup_hwmod; -static struct omap_hwmod omap44xx_mmc1_hwmod; -static struct omap_hwmod omap44xx_mmc2_hwmod; -static struct omap_hwmod omap44xx_mpu_hwmod; -static struct omap_hwmod omap44xx_mpu_private_hwmod; -static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; -static struct omap_hwmod omap44xx_usb_host_hs_hwmod; -static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; +#define OMAP44XX_DMA_REQ_START 1 /* - * Interconnects omap_hwmod structures - * hwmods that compose the global OMAP interconnect + * IP blocks */ /* @@ -92,51 +64,17 @@ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { { .irq = -1 } }; -/* l3_main_1 -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { - { - .pa_start = 0x4e000000, - .pa_end = 0x4e0007ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* mpu -> dmm */ -static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_dmm_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_dmm_addrs, - .user = OCP_USER_MPU, -}; - -/* dmm slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { - &omap44xx_l3_main_1__dmm, - &omap44xx_mpu__dmm, -}; - static struct omap_hwmod omap44xx_dmm_hwmod = { .name = "dmm", .class = &omap44xx_dmm_hwmod_class, .clkdm_name = "l3_emif_clkdm", + .mpu_irqs = omap44xx_dmm_irqs, .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_dmm_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), - .mpu_irqs = omap44xx_dmm_irqs, }; /* @@ -148,38 +86,6 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { }; /* emif_fw */ -/* dmm -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { - .master = &omap44xx_dmm_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { - { - .pa_start = 0x4a20c000, - .pa_end = 0x4a20c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> emif_fw */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_emif_fw_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_emif_fw_addrs, - .user = OCP_USER_MPU, -}; - -/* emif_fw slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { - &omap44xx_dmm__emif_fw, - &omap44xx_l4_cfg__emif_fw, -}; - static struct omap_hwmod omap44xx_emif_fw_hwmod = { .name = "emif_fw", .class = &omap44xx_emif_fw_hwmod_class, @@ -190,8 +96,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = { .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_emif_fw_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), }; /* @@ -203,28 +107,6 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = { }; /* l3_instr */ -/* iva -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_3 -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { - .master = &omap44xx_l3_main_3_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_instr slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { - &omap44xx_iva__l3_instr, - &omap44xx_l3_main_3__l3_instr, -}; - static struct omap_hwmod omap44xx_l3_instr_hwmod = { .name = "l3_instr", .class = &omap44xx_l3_hwmod_class, @@ -236,8 +118,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_l3_instr_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), }; /* l3_main_1 */ @@ -247,83 +127,6 @@ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { { .irq = -1 } }; -/* dsp -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dss -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { - .master = &omap44xx_dss_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc1 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { - .master = &omap44xx_mmc1_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc2 -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { - .master = &omap44xx_mmc2_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { - { - .pa_start = 0x44000000, - .pa_end = 0x44000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* mpu -> l3_main_1 */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l3_main_1_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_1_addrs, - .user = OCP_USER_MPU, -}; - -/* l3_main_1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { - &omap44xx_dsp__l3_main_1, - &omap44xx_dss__l3_main_1, - &omap44xx_l3_main_2__l3_main_1, - &omap44xx_l4_cfg__l3_main_1, - &omap44xx_mmc1__l3_main_1, - &omap44xx_mmc2__l3_main_1, - &omap44xx_mpu__l3_main_1, -}; - static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .name = "l3_main_1", .class = &omap44xx_l3_hwmod_class, @@ -335,97 +138,9 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l3_main_1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), }; /* l3_main_2 */ -/* dma_system -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { - .master = &omap44xx_dma_system_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* hsi -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { - .master = &omap44xx_hsi_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* ipu -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { - .master = &omap44xx_ipu_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iss -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { - .master = &omap44xx_iss_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iva -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { - { - .pa_start = 0x44800000, - .pa_end = 0x44801fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_1 -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_2_addrs, - .user = OCP_USER_MPU, -}; - -/* l4_cfg -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_otg_hs -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { - .master = &omap44xx_usb_otg_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { - &omap44xx_dma_system__l3_main_2, - &omap44xx_hsi__l3_main_2, - &omap44xx_ipu__l3_main_2, - &omap44xx_iss__l3_main_2, - &omap44xx_iva__l3_main_2, - &omap44xx_l3_main_1__l3_main_2, - &omap44xx_l4_cfg__l3_main_2, - &omap44xx_usb_otg_hs__l3_main_2, -}; - static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .name = "l3_main_2", .class = &omap44xx_l3_hwmod_class, @@ -436,52 +151,9 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l3_main_2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), }; /* l3_main_3 */ -static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { - { - .pa_start = 0x45000000, - .pa_end = 0x45000fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_1 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_l3_main_3_addrs, - .user = OCP_USER_MPU, -}; - -/* l3_main_2 -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> l3_main_3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l3_main_3_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { - &omap44xx_l3_main_1__l3_main_3, - &omap44xx_l3_main_2__l3_main_3, - &omap44xx_l4_cfg__l3_main_3, -}; - static struct omap_hwmod omap44xx_l3_main_3_hwmod = { .name = "l3_main_3", .class = &omap44xx_l3_hwmod_class, @@ -493,8 +165,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_l3_main_3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), }; /* @@ -506,46 +176,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = { }; /* l4_abe */ -/* aess -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { - .master = &omap44xx_aess_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dsp -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3_main_1 -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_abe slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { - &omap44xx_aess__l4_abe, - &omap44xx_dsp__l4_abe, - &omap44xx_l3_main_1__l4_abe, - &omap44xx_mpu__l4_abe, -}; - static struct omap_hwmod omap44xx_l4_abe_hwmod = { .name = "l4_abe", .class = &omap44xx_l4_hwmod_class, @@ -555,24 +185,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = { .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, }, }, - .slaves = omap44xx_l4_abe_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), }; /* l4_cfg */ -/* l3_main_1 -> l4_cfg */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_cfg_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { - &omap44xx_l3_main_1__l4_cfg, -}; - static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .name = "l4_cfg", .class = &omap44xx_l4_hwmod_class, @@ -583,24 +198,9 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l4_cfg_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), }; /* l4_per */ -/* l3_main_2 -> l4_per */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_l4_per_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { - &omap44xx_l3_main_2__l4_per, -}; - static struct omap_hwmod omap44xx_l4_per_hwmod = { .name = "l4_per", .class = &omap44xx_l4_hwmod_class, @@ -611,24 +211,9 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = { .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l4_per_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), }; /* l4_wkup */ -/* l4_cfg -> l4_wkup */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_l4_wkup_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_wkup slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { - &omap44xx_l4_cfg__l4_wkup, -}; - static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .name = "l4_wkup", .class = &omap44xx_l4_hwmod_class, @@ -639,8 +224,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_l4_wkup_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), }; /* @@ -652,25 +235,10 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { }; /* mpu_private */ -/* mpu -> mpu_private */ -static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_mpu_private_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu_private slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { - &omap44xx_mpu__mpu_private, -}; - static struct omap_hwmod omap44xx_mpu_private_hwmod = { .name = "mpu_private", .class = &omap44xx_mpu_bus_hwmod_class, .clkdm_name = "mpuss_clkdm", - .slaves = omap44xx_mpu_private_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), }; /* @@ -756,53 +324,6 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { { .dma_req = -1 } }; -/* aess master ports */ -static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { - &omap44xx_aess__l4_abe, -}; - -static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { - { - .pa_start = 0x401f1000, - .pa_end = 0x401f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> aess */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { - { - .pa_start = 0x490f1000, - .pa_end = 0x490f13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> aess (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_aess_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_aess_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* aess slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { - &omap44xx_l4_abe__aess, - &omap44xx_l4_abe__aess_dma, -}; - static struct omap_hwmod omap44xx_aess_hwmod = { .name = "aess", .class = &omap44xx_aess_hwmod_class, @@ -817,37 +338,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_aess_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), - .masters = omap44xx_aess_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), -}; - -/* - * 'bandgap' class - * bangap reference for ldo regulators - */ - -static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { - .name = "bandgap", -}; - -/* bandgap */ -static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { - { .role = "fclk", .clk = "bandgap_fclk" }, -}; - -static struct omap_hwmod omap44xx_bandgap_hwmod = { - .name = "bandgap", - .class = &omap44xx_bandgap_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, - }, - }, - .opt_clks = bandgap_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), }; /* @@ -870,30 +360,6 @@ static struct omap_hwmod_class omap44xx_counter_hwmod_class = { }; /* counter_32k */ -static struct omap_hwmod omap44xx_counter_32k_hwmod; -static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { - { - .pa_start = 0x4a304000, - .pa_end = 0x4a30401f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_counter_32k_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_counter_32k_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* counter_32k slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { - &omap44xx_l4_wkup__counter_32k, -}; - static struct omap_hwmod omap44xx_counter_32k_hwmod = { .name = "counter_32k", .class = &omap44xx_counter_hwmod_class, @@ -906,8 +372,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = { .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_counter_32k_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), }; /* @@ -950,34 +414,6 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { { .irq = -1 } }; -/* dma_system master ports */ -static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { - &omap44xx_dma_system__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { - { - .pa_start = 0x4a056000, - .pa_end = 0x4a056fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> dma_system */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dma_system_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dma_system_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dma_system slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { - &omap44xx_l4_cfg__dma_system, -}; - static struct omap_hwmod omap44xx_dma_system_hwmod = { .name = "dma_system", .class = &omap44xx_dma_hwmod_class, @@ -991,10 +427,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { }, }, .dev_attr = &dma_dev_attr, - .slaves = omap44xx_dma_system_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), - .masters = omap44xx_dma_system_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), }; /* @@ -1018,7 +450,6 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { }; /* dmic */ -static struct omap_hwmod omap44xx_dmic_hwmod; static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { { .irq = 114 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1029,50 +460,6 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { - { - .name = "mpu", - .pa_start = 0x4012e000, - .pa_end = 0x4012e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> dmic */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x4902e000, - .pa_end = 0x4902e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> dmic (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_dmic_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_dmic_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* dmic slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { - &omap44xx_l4_abe__dmic, - &omap44xx_l4_abe__dmic_dma, -}; - static struct omap_hwmod omap44xx_dmic_hwmod = { .name = "dmic", .class = &omap44xx_dmic_hwmod_class, @@ -1087,8 +474,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_dmic_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), }; /* @@ -1107,53 +492,8 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { }; static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { - { .name = "mmu_cache", .rst_shift = 1 }, -}; - -static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { { .name = "dsp", .rst_shift = 0 }, -}; - -/* dsp -> iva */ -static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { - .master = &omap44xx_dsp_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "dpll_iva_m5x2_ck", -}; - -/* dsp master ports */ -static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { - &omap44xx_dsp__l3_main_1, - &omap44xx_dsp__l4_abe, - &omap44xx_dsp__iva, -}; - -/* l4_cfg -> dsp */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_dsp_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* dsp slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { - &omap44xx_l4_cfg__dsp, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_dsp_c0_hwmod = { - .name = "dsp_c0", - .class = &omap44xx_dsp_hwmod_class, - .clkdm_name = "tesla_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_dsp_c0_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, - }, - }, + { .name = "mmu_cache", .rst_shift = 1 }, }; static struct omap_hwmod omap44xx_dsp_hwmod = { @@ -1172,10 +512,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_dsp_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), - .masters = omap44xx_dsp_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), }; /* @@ -1196,53 +532,6 @@ static struct omap_hwmod_class omap44xx_dss_hwmod_class = { }; /* dss */ -/* dss master ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { - &omap44xx_dss__l3_main_1, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { - { - .pa_start = 0x58000000, - .pa_end = 0x5800007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { - { - .pa_start = 0x48040000, - .pa_end = 0x4804007f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_addrs, - .user = OCP_USER_MPU, -}; - -/* dss slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { - &omap44xx_l3_main_2__dss, - &omap44xx_l4_per__dss, -}; - static struct omap_hwmod_opt_clk dss_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, { .role = "tv_clk", .clk = "dss_tv_clk" }, @@ -1263,10 +552,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = { }, .opt_clks = dss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), - .slaves = omap44xx_dss_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), - .masters = omap44xx_dss_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), }; /* @@ -1293,7 +578,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { }; /* dss_dispc */ -static struct omap_hwmod omap44xx_dss_dispc_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { { .irq = 25 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1304,53 +588,11 @@ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { - { - .pa_start = 0x58001000, - .pa_end = 0x58001fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dispc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dispc_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dispc_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { - { - .pa_start = 0x48041000, - .pa_end = 0x48041fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { .manager_count = 3, .has_framedonetv_irq = 1 }; -/* l4_per -> dss_dispc */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dispc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dispc_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_dispc slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { - &omap44xx_l3_main_2__dss_dispc, - &omap44xx_l4_per__dss_dispc, -}; - static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .name = "dss_dispc", .class = &omap44xx_dispc_hwmod_class, @@ -1364,8 +606,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_dss_dispc_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), .dev_attr = &omap44xx_dss_dispc_dev_attr }; @@ -1391,7 +631,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { }; /* dss_dsi1 */ -static struct omap_hwmod omap44xx_dss_dsi1_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { { .irq = 53 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1402,48 +641,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { - { - .pa_start = 0x58004000, - .pa_end = 0x580041ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dsi1_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { - { - .pa_start = 0x48044000, - .pa_end = 0x480441ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dsi1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dsi1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi1_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_dsi1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { - &omap44xx_l3_main_2__dss_dsi1, - &omap44xx_l4_per__dss_dsi1, -}; - static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1463,12 +660,9 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { }, .opt_clks = dss_dsi1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), - .slaves = omap44xx_dss_dsi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), }; /* dss_dsi2 */ -static struct omap_hwmod omap44xx_dss_dsi2_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { { .irq = 84 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1479,48 +673,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { - { - .pa_start = 0x58005000, - .pa_end = 0x580051ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_dsi2 */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_dsi2_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { - { - .pa_start = 0x48045000, - .pa_end = 0x480451ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_dsi2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_dsi2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_dsi2_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_dsi2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { - &omap44xx_l3_main_2__dss_dsi2, - &omap44xx_l4_per__dss_dsi2, -}; - static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1540,8 +692,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { }, .opt_clks = dss_dsi2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), - .slaves = omap44xx_dss_dsi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), }; /* @@ -1565,7 +715,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { }; /* dss_hdmi */ -static struct omap_hwmod omap44xx_dss_hdmi_hwmod; static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { { .irq = 101 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -1576,48 +725,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { - { - .pa_start = 0x58006000, - .pa_end = 0x58006fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_hdmi */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_hdmi_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { - { - .pa_start = 0x48046000, - .pa_end = 0x48046fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_hdmi */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_hdmi_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_hdmi slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { - &omap44xx_l3_main_2__dss_hdmi, - &omap44xx_l4_per__dss_hdmi, -}; - static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { { .role = "sys_clk", .clk = "dss_sys_clk" }, }; @@ -1637,8 +744,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { }, .opt_clks = dss_hdmi_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), - .slaves = omap44xx_dss_hdmi_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), }; /* @@ -1662,54 +767,11 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { }; /* dss_rfbi */ -static struct omap_hwmod omap44xx_dss_rfbi_hwmod; static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { - { - .pa_start = 0x58002000, - .pa_end = 0x580020ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_rfbi_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { - { - .pa_start = 0x48042000, - .pa_end = 0x480420ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_rfbi */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_rfbi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_rfbi_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_rfbi slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { - &omap44xx_l3_main_2__dss_rfbi, - &omap44xx_l4_per__dss_rfbi, -}; - static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { { .role = "ick", .clk = "dss_fck" }, }; @@ -1728,8 +790,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { }, .opt_clks = dss_rfbi_opt_clks, .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), - .slaves = omap44xx_dss_rfbi_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), }; /* @@ -1742,49 +802,6 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = { }; /* dss_venc */ -static struct omap_hwmod omap44xx_dss_venc_hwmod; -static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { - { - .pa_start = 0x58003000, - .pa_end = 0x580030ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> dss_venc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_dss_venc_hwmod, - .clk = "dss_fck", - .addr = omap44xx_dss_venc_dma_addrs, - .user = OCP_USER_SDMA, -}; - -static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { - { - .pa_start = 0x48043000, - .pa_end = 0x480430ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> dss_venc */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_dss_venc_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_dss_venc_addrs, - .user = OCP_USER_MPU, -}; - -/* dss_venc slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { - &omap44xx_l3_main_2__dss_venc, - &omap44xx_l4_per__dss_venc, -}; - static struct omap_hwmod omap44xx_dss_venc_hwmod = { .name = "dss_venc", .class = &omap44xx_venc_hwmod_class, @@ -1796,8 +813,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_dss_venc_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), }; /* @@ -1830,35 +845,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { }; /* gpio1 */ -static struct omap_hwmod omap44xx_gpio1_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { { .irq = 29 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { - { - .pa_start = 0x4a310000, - .pa_end = 0x4a3101ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> gpio1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_gpio1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_gpio1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { - &omap44xx_l4_wkup__gpio1, -}; - static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { { .role = "dbclk", .clk = "gpio1_dbclk" }, }; @@ -1879,40 +870,14 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { .opt_clks = gpio1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), }; /* gpio2 */ -static struct omap_hwmod omap44xx_gpio2_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { { .irq = 30 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { - { - .pa_start = 0x48055000, - .pa_end = 0x480551ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { - &omap44xx_l4_per__gpio2, -}; - static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { { .role = "dbclk", .clk = "gpio2_dbclk" }, }; @@ -1934,40 +899,14 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { .opt_clks = gpio2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), }; /* gpio3 */ -static struct omap_hwmod omap44xx_gpio3_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { { .irq = 31 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { - { - .pa_start = 0x48057000, - .pa_end = 0x480571ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { - &omap44xx_l4_per__gpio3, -}; - static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { { .role = "dbclk", .clk = "gpio3_dbclk" }, }; @@ -1989,40 +928,14 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { .opt_clks = gpio3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), }; /* gpio4 */ -static struct omap_hwmod omap44xx_gpio4_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { { .irq = 32 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { - { - .pa_start = 0x48059000, - .pa_end = 0x480591ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { - &omap44xx_l4_per__gpio4, -}; - static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { { .role = "dbclk", .clk = "gpio4_dbclk" }, }; @@ -2044,40 +957,14 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { .opt_clks = gpio4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), }; /* gpio5 */ -static struct omap_hwmod omap44xx_gpio5_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { { .irq = 33 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { - { - .pa_start = 0x4805b000, - .pa_end = 0x4805b1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio5_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio5 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { - &omap44xx_l4_per__gpio5, -}; - static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { { .role = "dbclk", .clk = "gpio5_dbclk" }, }; @@ -2099,40 +986,14 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { .opt_clks = gpio5_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio5_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), }; /* gpio6 */ -static struct omap_hwmod omap44xx_gpio6_hwmod; static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { { .irq = 34 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { - { - .pa_start = 0x4805d000, - .pa_end = 0x4805d1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> gpio6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_gpio6_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_gpio6_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* gpio6 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { - &omap44xx_l4_per__gpio6, -}; - static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { { .role = "dbclk", .clk = "gpio6_dbclk" }, }; @@ -2154,8 +1015,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .opt_clks = gpio6_opt_clks, .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), .dev_attr = &gpio_dev_attr, - .slaves = omap44xx_gpio6_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), }; /* @@ -2190,34 +1049,6 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { { .irq = -1 } }; -/* hsi master ports */ -static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { - &omap44xx_hsi__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { - { - .pa_start = 0x4a058000, - .pa_end = 0x4a05bfff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> hsi */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_hsi_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_hsi_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* hsi slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { - &omap44xx_l4_cfg__hsi, -}; - static struct omap_hwmod omap44xx_hsi_hwmod = { .name = "hsi", .class = &omap44xx_hsi_hwmod_class, @@ -2231,10 +1062,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_hsi_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), - .masters = omap44xx_hsi_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), }; /* @@ -2266,7 +1093,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = { }; /* i2c1 */ -static struct omap_hwmod omap44xx_i2c1_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { { .irq = 56 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2278,29 +1104,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { - { - .pa_start = 0x48070000, - .pa_end = 0x480700ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* i2c1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { - &omap44xx_l4_per__i2c1, -}; - static struct omap_hwmod omap44xx_i2c1_hwmod = { .name = "i2c1", .class = &omap44xx_i2c_hwmod_class, @@ -2316,13 +1119,10 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_i2c1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), .dev_attr = &i2c_dev_attr, }; /* i2c2 */ -static struct omap_hwmod omap44xx_i2c2_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { { .irq = 57 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2334,29 +1134,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { - { - .pa_start = 0x48072000, - .pa_end = 0x480720ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* i2c2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { - &omap44xx_l4_per__i2c2, -}; - static struct omap_hwmod omap44xx_i2c2_hwmod = { .name = "i2c2", .class = &omap44xx_i2c_hwmod_class, @@ -2372,13 +1149,10 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_i2c2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), .dev_attr = &i2c_dev_attr, }; /* i2c3 */ -static struct omap_hwmod omap44xx_i2c3_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { { .irq = 61 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2390,29 +1164,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { - { - .pa_start = 0x48060000, - .pa_end = 0x480600ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* i2c3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { - &omap44xx_l4_per__i2c3, -}; - static struct omap_hwmod omap44xx_i2c3_hwmod = { .name = "i2c3", .class = &omap44xx_i2c_hwmod_class, @@ -2428,13 +1179,10 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_i2c3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), .dev_attr = &i2c_dev_attr, }; /* i2c4 */ -static struct omap_hwmod omap44xx_i2c4_hwmod; static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { { .irq = 62 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2446,29 +1194,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { - { - .pa_start = 0x48350000, - .pa_end = 0x483500ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> i2c4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_i2c4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_i2c4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* i2c4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { - &omap44xx_l4_per__i2c4, -}; - static struct omap_hwmod omap44xx_i2c4_hwmod = { .name = "i2c4", .class = &omap44xx_i2c_hwmod_class, @@ -2484,8 +1209,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_i2c4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), .dev_attr = &i2c_dev_attr, }; @@ -2504,66 +1227,12 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { { .irq = -1 } }; -static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { +static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "cpu0", .rst_shift = 0 }, -}; - -static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { { .name = "cpu1", .rst_shift = 1 }, -}; - -static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { { .name = "mmu_cache", .rst_shift = 2 }, }; -/* ipu master ports */ -static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { - &omap44xx_ipu__l3_main_2, -}; - -/* l3_main_2 -> ipu */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_ipu_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* ipu slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { - &omap44xx_l3_main_2__ipu, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_ipu_c0_hwmod = { - .name = "ipu_c0", - .class = &omap44xx_ipu_hwmod_class, - .clkdm_name = "ducati_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_ipu_c0_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, - }, - }, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_ipu_c1_hwmod = { - .name = "ipu_c1", - .class = &omap44xx_ipu_hwmod_class, - .clkdm_name = "ducati_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_ipu_c1_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, - }, - }, -}; - static struct omap_hwmod omap44xx_ipu_hwmod = { .name = "ipu", .class = &omap44xx_ipu_hwmod_class, @@ -2580,10 +1249,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_ipu_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), - .masters = omap44xx_ipu_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), }; /* @@ -2594,6 +1259,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, + /* + * ISS needs 100 OCP clk cycles delay after a softreset before + * accessing sysconfig again. + * The lowest frequency at the moment for L3 bus is 100 MHz, so + * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). + * + * TODO: Indicate errata when available. + */ + .srst_udelay = 2, .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | @@ -2621,34 +1295,6 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { { .dma_req = -1 } }; -/* iss master ports */ -static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { - &omap44xx_iss__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { - { - .pa_start = 0x52000000, - .pa_end = 0x520000ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> iss */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iss_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_iss_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* iss slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { - &omap44xx_l3_main_2__iss, -}; - static struct omap_hwmod_opt_clk iss_opt_clks[] = { { .role = "ctrlclk", .clk = "iss_ctrlclk" }, }; @@ -2669,10 +1315,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = { }, .opt_clks = iss_opt_clks, .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), - .slaves = omap44xx_iss_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), - .masters = omap44xx_iss_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), }; /* @@ -2693,75 +1335,9 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { }; static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { - { .name = "logic", .rst_shift = 2 }, -}; - -static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { { .name = "seq0", .rst_shift = 0 }, -}; - -static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { { .name = "seq1", .rst_shift = 1 }, -}; - -/* iva master ports */ -static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { - &omap44xx_iva__l3_main_2, - &omap44xx_iva__l3_instr, -}; - -static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { - { - .pa_start = 0x5a000000, - .pa_end = 0x5a07ffff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l3_main_2 -> iva */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "l3_div_ck", - .addr = omap44xx_iva_addrs, - .user = OCP_USER_MPU, -}; - -/* iva slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { - &omap44xx_dsp__iva, - &omap44xx_l3_main_2__iva, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_iva_seq0_hwmod = { - .name = "iva_seq0", - .class = &omap44xx_iva_hwmod_class, - .clkdm_name = "ivahd_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_iva_seq0_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, - }, - }, -}; - -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod omap44xx_iva_seq1_hwmod = { - .name = "iva_seq1", - .class = &omap44xx_iva_hwmod_class, - .clkdm_name = "ivahd_clkdm", - .flags = HWMOD_INIT_NO_RESET, - .rst_lines = omap44xx_iva_seq1_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), - .prcm = { - .omap4 = { - .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, - }, - }, + { .name = "logic", .rst_shift = 2 }, }; static struct omap_hwmod omap44xx_iva_hwmod = { @@ -2780,10 +1356,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .modulemode = MODULEMODE_HWCTRL, }, }, - .slaves = omap44xx_iva_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), - .masters = omap44xx_iva_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), }; /* @@ -2809,35 +1381,11 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { }; /* kbd */ -static struct omap_hwmod omap44xx_kbd_hwmod; static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { { .irq = 120 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { - { - .pa_start = 0x4a31c000, - .pa_end = 0x4a31c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> kbd */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_kbd_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_kbd_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* kbd slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { - &omap44xx_l4_wkup__kbd, -}; - static struct omap_hwmod omap44xx_kbd_hwmod = { .name = "kbd", .class = &omap44xx_kbd_hwmod_class, @@ -2851,8 +1399,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_kbd_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), }; /* @@ -2876,35 +1422,11 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { }; /* mailbox */ -static struct omap_hwmod omap44xx_mailbox_hwmod; static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { { .irq = 26 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { - { - .pa_start = 0x4a0f4000, - .pa_end = 0x4a0f41ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> mailbox */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_mailbox_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mailbox_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mailbox slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { - &omap44xx_l4_cfg__mailbox, -}; - static struct omap_hwmod omap44xx_mailbox_hwmod = { .name = "mailbox", .class = &omap44xx_mailbox_hwmod_class, @@ -2916,8 +1438,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_mailbox_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), }; /* @@ -2940,7 +1460,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { }; /* mcbsp1 */ -static struct omap_hwmod omap44xx_mcbsp1_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { { .irq = 17 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -2952,50 +1471,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40122000, - .pa_end = 0x401220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49022000, - .pa_end = 0x490220ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp1 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp1_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp1_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* mcbsp1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { - &omap44xx_l4_abe__mcbsp1, - &omap44xx_l4_abe__mcbsp1_dma, -}; - static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, @@ -3015,14 +1490,11 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcbsp1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), .opt_clks = mcbsp1_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), }; /* mcbsp2 */ -static struct omap_hwmod omap44xx_mcbsp2_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { { .irq = 22 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3034,50 +1506,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40124000, - .pa_end = 0x401240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49024000, - .pa_end = 0x490240ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp2 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp2_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp2_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* mcbsp2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { - &omap44xx_l4_abe__mcbsp2, - &omap44xx_l4_abe__mcbsp2_dma, -}; - static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, @@ -3097,14 +1525,11 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcbsp2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), .opt_clks = mcbsp2_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), }; /* mcbsp3 */ -static struct omap_hwmod omap44xx_mcbsp3_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { { .irq = 23 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3116,50 +1541,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { - { - .name = "mpu", - .pa_start = 0x40126000, - .pa_end = 0x401260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { - { - .name = "dma", - .pa_start = 0x49026000, - .pa_end = 0x490260ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcbsp3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcbsp3_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcbsp3_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* mcbsp3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { - &omap44xx_l4_abe__mcbsp3, - &omap44xx_l4_abe__mcbsp3_dma, -}; - static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, @@ -3179,14 +1560,11 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcbsp3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), .opt_clks = mcbsp3_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), }; /* mcbsp4 */ -static struct omap_hwmod omap44xx_mcbsp4_hwmod; static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { { .irq = 16 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3198,29 +1576,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { - { - .pa_start = 0x48096000, - .pa_end = 0x480960ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcbsp4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcbsp4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcbsp4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcbsp4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { - &omap44xx_l4_per__mcbsp4, -}; - static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { { .role = "pad_fck", .clk = "pad_clks_ck" }, { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, @@ -3240,8 +1595,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcbsp4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), .opt_clks = mcbsp4_opt_clks, .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), }; @@ -3268,7 +1621,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { }; /* mcpdm */ -static struct omap_hwmod omap44xx_mcpdm_hwmod; static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { { .irq = 112 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3280,48 +1632,6 @@ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { - { - .pa_start = 0x40132000, - .pa_end = 0x4013207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcpdm */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { - { - .pa_start = 0x49032000, - .pa_end = 0x4903207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> mcpdm (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_mcpdm_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_mcpdm_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* mcpdm slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { - &omap44xx_l4_abe__mcpdm, - &omap44xx_l4_abe__mcpdm_dma, -}; - static struct omap_hwmod omap44xx_mcpdm_hwmod = { .name = "mcpdm", .class = &omap44xx_mcpdm_hwmod_class, @@ -3336,8 +1646,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mcpdm_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), }; /* @@ -3363,7 +1671,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { }; /* mcspi1 */ -static struct omap_hwmod omap44xx_mcspi1_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { { .irq = 65 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3381,29 +1688,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { - { - .pa_start = 0x48098000, - .pa_end = 0x480981ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcspi1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { - &omap44xx_l4_per__mcspi1, -}; - /* mcspi1 dev_attr */ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { .num_chipselect = 4, @@ -3424,12 +1708,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { }, }, .dev_attr = &mcspi1_dev_attr, - .slaves = omap44xx_mcspi1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), }; /* mcspi2 */ -static struct omap_hwmod omap44xx_mcspi2_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { { .irq = 66 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3443,29 +1724,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { - { - .pa_start = 0x4809a000, - .pa_end = 0x4809a1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcspi2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { - &omap44xx_l4_per__mcspi2, -}; - /* mcspi2 dev_attr */ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { .num_chipselect = 2, @@ -3486,12 +1744,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { }, }, .dev_attr = &mcspi2_dev_attr, - .slaves = omap44xx_mcspi2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), }; /* mcspi3 */ -static struct omap_hwmod omap44xx_mcspi3_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { { .irq = 91 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3505,29 +1760,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { - { - .pa_start = 0x480b8000, - .pa_end = 0x480b81ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcspi3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { - &omap44xx_l4_per__mcspi3, -}; - /* mcspi3 dev_attr */ static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { .num_chipselect = 2, @@ -3548,12 +1780,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { }, }, .dev_attr = &mcspi3_dev_attr, - .slaves = omap44xx_mcspi3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), }; /* mcspi4 */ -static struct omap_hwmod omap44xx_mcspi4_hwmod; static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { { .irq = 48 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3565,29 +1794,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { - { - .pa_start = 0x480ba000, - .pa_end = 0x480ba1ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mcspi4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mcspi4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mcspi4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mcspi4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { - &omap44xx_l4_per__mcspi4, -}; - /* mcspi4 dev_attr */ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { .num_chipselect = 1, @@ -3608,8 +1814,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { }, }, .dev_attr = &mcspi4_dev_attr, - .slaves = omap44xx_mcspi4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), }; /* @@ -3646,34 +1850,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { { .dma_req = -1 } }; -/* mmc1 master ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { - &omap44xx_mmc1__l3_main_1, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { - { - .pa_start = 0x4809c000, - .pa_end = 0x4809c3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { - &omap44xx_l4_per__mmc1, -}; - /* mmc1 dev_attr */ static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, @@ -3694,10 +1870,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { }, }, .dev_attr = &mmc1_dev_attr, - .slaves = omap44xx_mmc1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), - .masters = omap44xx_mmc1_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), }; /* mmc2 */ @@ -3712,34 +1884,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { { .dma_req = -1 } }; -/* mmc2 master ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { - &omap44xx_mmc2__l3_main_1, -}; - -static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { - { - .pa_start = 0x480b4000, - .pa_end = 0x480b43ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { - &omap44xx_l4_per__mmc2, -}; - static struct omap_hwmod omap44xx_mmc2_hwmod = { .name = "mmc2", .class = &omap44xx_mmc_hwmod_class, @@ -3754,14 +1898,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mmc2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), - .masters = omap44xx_mmc2_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), }; /* mmc3 */ -static struct omap_hwmod omap44xx_mmc3_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { { .irq = 94 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3773,29 +1912,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { - { - .pa_start = 0x480ad000, - .pa_end = 0x480ad3ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { - &omap44xx_l4_per__mmc3, -}; - static struct omap_hwmod omap44xx_mmc3_hwmod = { .name = "mmc3", .class = &omap44xx_mmc_hwmod_class, @@ -3810,12 +1926,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mmc3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), }; /* mmc4 */ -static struct omap_hwmod omap44xx_mmc4_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { { .irq = 96 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3827,35 +1940,11 @@ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { - { - .pa_start = 0x480d1000, - .pa_end = 0x480d13ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { - &omap44xx_l4_per__mmc4, -}; - static struct omap_hwmod omap44xx_mmc4_hwmod = { .name = "mmc4", .class = &omap44xx_mmc_hwmod_class, .clkdm_name = "l4_per_clkdm", .mpu_irqs = omap44xx_mmc4_irqs, - .sdma_reqs = omap44xx_mmc4_sdma_reqs, .main_clk = "mmc4_fck", .prcm = { @@ -3865,12 +1954,9 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mmc4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), }; /* mmc5 */ -static struct omap_hwmod omap44xx_mmc5_hwmod; static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { { .irq = 59 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -3882,29 +1968,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { - { - .pa_start = 0x480d5000, - .pa_end = 0x480d53ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> mmc5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_mmc5_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_mmc5_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mmc5 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { - &omap44xx_l4_per__mmc5, -}; - static struct omap_hwmod omap44xx_mmc5_hwmod = { .name = "mmc5", .class = &omap44xx_mmc_hwmod_class, @@ -3919,8 +1982,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_mmc5_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), }; /* @@ -3940,13 +2001,6 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { { .irq = -1 } }; -/* mpu master ports */ -static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { - &omap44xx_mpu__l3_main_1, - &omap44xx_mpu__l4_abe, - &omap44xx_mpu__dmm, -}; - static struct omap_hwmod omap44xx_mpu_hwmod = { .name = "mpu", .class = &omap44xx_mpu_hwmod_class, @@ -3960,8 +2014,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, }, }, - .masters = omap44xx_mpu_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), }; /* @@ -3995,35 +2047,11 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { .sensor_voltdm_name = "core", }; -static struct omap_hwmod omap44xx_smartreflex_core_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { { .irq = 19 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { - { - .pa_start = 0x4a0dd000, - .pa_end = 0x4a0dd03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_core */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_core_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_core_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* smartreflex_core slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { - &omap44xx_l4_cfg__smartreflex_core, -}; - static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { .name = "smartreflex_core", .class = &omap44xx_smartreflex_hwmod_class, @@ -4038,8 +2066,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_smartreflex_core_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), .dev_attr = &smartreflex_core_dev_attr, }; @@ -4048,35 +2074,11 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { .sensor_voltdm_name = "iva", }; -static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { { .irq = 102 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { - { - .pa_start = 0x4a0db000, - .pa_end = 0x4a0db03f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_iva */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_iva_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_iva_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* smartreflex_iva slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { - &omap44xx_l4_cfg__smartreflex_iva, -}; - static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .name = "smartreflex_iva", .class = &omap44xx_smartreflex_hwmod_class, @@ -4090,8 +2092,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_smartreflex_iva_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), .dev_attr = &smartreflex_iva_dev_attr, }; @@ -4100,35 +2100,11 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { .sensor_voltdm_name = "mpu", }; -static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { { .irq = 18 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { - { - .pa_start = 0x4a0d9000, - .pa_end = 0x4a0d903f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> smartreflex_mpu */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_smartreflex_mpu_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_smartreflex_mpu_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* smartreflex_mpu slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { - &omap44xx_l4_cfg__smartreflex_mpu, -}; - static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .name = "smartreflex_mpu", .class = &omap44xx_smartreflex_hwmod_class, @@ -4142,8 +2118,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_smartreflex_mpu_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), .dev_attr = &smartreflex_mpu_dev_attr, }; @@ -4171,30 +2145,6 @@ static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { }; /* spinlock */ -static struct omap_hwmod omap44xx_spinlock_hwmod; -static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { - { - .pa_start = 0x4a0f6000, - .pa_end = 0x4a0f6fff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> spinlock */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_spinlock_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_spinlock_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* spinlock slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { - &omap44xx_l4_cfg__spinlock, -}; - static struct omap_hwmod omap44xx_spinlock_hwmod = { .name = "spinlock", .class = &omap44xx_spinlock_hwmod_class, @@ -4205,8 +2155,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = { .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, }, }, - .slaves = omap44xx_spinlock_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), }; /* @@ -4258,35 +2206,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { }; /* timer1 */ -static struct omap_hwmod omap44xx_timer1_hwmod; static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { { .irq = 37 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { - { - .pa_start = 0x4a318000, - .pa_end = 0x4a31807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_timer1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_timer1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { - &omap44xx_l4_wkup__timer1, -}; - static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", .class = &omap44xx_timer_1ms_hwmod_class, @@ -4301,40 +2225,14 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), }; /* timer2 */ -static struct omap_hwmod omap44xx_timer2_hwmod; static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { { .irq = 38 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { - { - .pa_start = 0x48032000, - .pa_end = 0x4803207f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { - &omap44xx_l4_per__timer2, -}; - static struct omap_hwmod omap44xx_timer2_hwmod = { .name = "timer2", .class = &omap44xx_timer_1ms_hwmod_class, @@ -4349,40 +2247,14 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), }; /* timer3 */ -static struct omap_hwmod omap44xx_timer3_hwmod; static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { { .irq = 39 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { - { - .pa_start = 0x48034000, - .pa_end = 0x4803407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { - &omap44xx_l4_per__timer3, -}; - static struct omap_hwmod omap44xx_timer3_hwmod = { .name = "timer3", .class = &omap44xx_timer_hwmod_class, @@ -4397,40 +2269,14 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), }; /* timer4 */ -static struct omap_hwmod omap44xx_timer4_hwmod; static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { { .irq = 40 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { - { - .pa_start = 0x48036000, - .pa_end = 0x4803607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { - &omap44xx_l4_per__timer4, -}; - static struct omap_hwmod omap44xx_timer4_hwmod = { .name = "timer4", .class = &omap44xx_timer_hwmod_class, @@ -4445,59 +2291,14 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), }; /* timer5 */ -static struct omap_hwmod omap44xx_timer5_hwmod; static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { { .irq = 41 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { - { - .pa_start = 0x40138000, - .pa_end = 0x4013807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer5 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { - { - .pa_start = 0x49038000, - .pa_end = 0x4903807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer5 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer5_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer5_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* timer5 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { - &omap44xx_l4_abe__timer5, - &omap44xx_l4_abe__timer5_dma, -}; - static struct omap_hwmod omap44xx_timer5_hwmod = { .name = "timer5", .class = &omap44xx_timer_hwmod_class, @@ -4512,59 +2313,14 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer5_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), }; /* timer6 */ -static struct omap_hwmod omap44xx_timer6_hwmod; static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { { .irq = 42 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { - { - .pa_start = 0x4013a000, - .pa_end = 0x4013a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer6 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { - { - .pa_start = 0x4903a000, - .pa_end = 0x4903a07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer6 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer6_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer6_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* timer6 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { - &omap44xx_l4_abe__timer6, - &omap44xx_l4_abe__timer6_dma, -}; - static struct omap_hwmod omap44xx_timer6_hwmod = { .name = "timer6", .class = &omap44xx_timer_hwmod_class, @@ -4580,59 +2336,14 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer6_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), }; /* timer7 */ -static struct omap_hwmod omap44xx_timer7_hwmod; static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { { .irq = 43 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { - { - .pa_start = 0x4013c000, - .pa_end = 0x4013c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer7 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { - { - .pa_start = 0x4903c000, - .pa_end = 0x4903c07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer7 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer7_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer7_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* timer7 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { - &omap44xx_l4_abe__timer7, - &omap44xx_l4_abe__timer7_dma, -}; - static struct omap_hwmod omap44xx_timer7_hwmod = { .name = "timer7", .class = &omap44xx_timer_hwmod_class, @@ -4647,59 +2358,14 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { }, }, .dev_attr = &capability_alwon_dev_attr, - .slaves = omap44xx_timer7_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), }; /* timer8 */ -static struct omap_hwmod omap44xx_timer8_hwmod; static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { { .irq = 44 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { - { - .pa_start = 0x4013e000, - .pa_end = 0x4013e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer8 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_addrs, - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { - { - .pa_start = 0x4903e000, - .pa_end = 0x4903e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_abe -> timer8 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { - .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_timer8_hwmod, - .clk = "ocp_abe_iclk", - .addr = omap44xx_timer8_dma_addrs, - .user = OCP_USER_SDMA, -}; - -/* timer8 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { - &omap44xx_l4_abe__timer8, - &omap44xx_l4_abe__timer8_dma, -}; - static struct omap_hwmod omap44xx_timer8_hwmod = { .name = "timer8", .class = &omap44xx_timer_hwmod_class, @@ -4714,40 +2380,14 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap44xx_timer8_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), }; /* timer9 */ -static struct omap_hwmod omap44xx_timer9_hwmod; static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { { .irq = 45 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { - { - .pa_start = 0x4803e000, - .pa_end = 0x4803e07f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer9 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer9_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer9_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer9 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { - &omap44xx_l4_per__timer9, -}; - static struct omap_hwmod omap44xx_timer9_hwmod = { .name = "timer9", .class = &omap44xx_timer_hwmod_class, @@ -4762,40 +2402,14 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap44xx_timer9_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), }; /* timer10 */ -static struct omap_hwmod omap44xx_timer10_hwmod; static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { { .irq = 46 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { - { - .pa_start = 0x48086000, - .pa_end = 0x4808607f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer10 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer10_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer10_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer10 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { - &omap44xx_l4_per__timer10, -}; - static struct omap_hwmod omap44xx_timer10_hwmod = { .name = "timer10", .class = &omap44xx_timer_1ms_hwmod_class, @@ -4810,40 +2424,14 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap44xx_timer10_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), }; /* timer11 */ -static struct omap_hwmod omap44xx_timer11_hwmod; static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { { .irq = 47 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { - { - .pa_start = 0x48088000, - .pa_end = 0x4808807f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> timer11 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_timer11_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_timer11_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* timer11 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { - &omap44xx_l4_per__timer11, -}; - static struct omap_hwmod omap44xx_timer11_hwmod = { .name = "timer11", .class = &omap44xx_timer_hwmod_class, @@ -4858,8 +2446,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { }, }, .dev_attr = &capability_pwm_dev_attr, - .slaves = omap44xx_timer11_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), }; /* @@ -4885,7 +2471,6 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = { }; /* uart1 */ -static struct omap_hwmod omap44xx_uart1_hwmod; static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { { .irq = 72 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -4897,29 +2482,6 @@ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { - { - .pa_start = 0x4806a000, - .pa_end = 0x4806a0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart1_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart1_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart1 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { - &omap44xx_l4_per__uart1, -}; - static struct omap_hwmod omap44xx_uart1_hwmod = { .name = "uart1", .class = &omap44xx_uart_hwmod_class, @@ -4934,12 +2496,9 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_uart1_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), }; /* uart2 */ -static struct omap_hwmod omap44xx_uart2_hwmod; static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { { .irq = 73 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -4951,29 +2510,6 @@ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { - { - .pa_start = 0x4806c000, - .pa_end = 0x4806c0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart2_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { - &omap44xx_l4_per__uart2, -}; - static struct omap_hwmod omap44xx_uart2_hwmod = { .name = "uart2", .class = &omap44xx_uart_hwmod_class, @@ -4988,12 +2524,9 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_uart2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), }; /* uart3 */ -static struct omap_hwmod omap44xx_uart3_hwmod; static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { { .irq = 74 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -5005,29 +2538,6 @@ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { - { - .pa_start = 0x48020000, - .pa_end = 0x480200ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart3_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart3_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { - &omap44xx_l4_per__uart3, -}; - static struct omap_hwmod omap44xx_uart3_hwmod = { .name = "uart3", .class = &omap44xx_uart_hwmod_class, @@ -5043,12 +2553,9 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_uart3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), }; /* uart4 */ -static struct omap_hwmod omap44xx_uart4_hwmod; static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { { .irq = 70 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } @@ -5060,29 +2567,6 @@ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { { .dma_req = -1 } }; -static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { - { - .pa_start = 0x4806e000, - .pa_end = 0x4806e0ff, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_per -> uart4 */ -static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { - .master = &omap44xx_l4_per_hwmod, - .slave = &omap44xx_uart4_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_uart4_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* uart4 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { - &omap44xx_l4_per__uart4, -}; - static struct omap_hwmod omap44xx_uart4_hwmod = { .name = "uart4", .class = &omap44xx_uart_hwmod_class, @@ -5097,8 +2581,98 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_uart4_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), +}; + +/* + * 'usb_host_hs' class + * high-speed multi-port usb host controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { + .name = "usb_host_hs", + .sysc = &omap44xx_usb_host_hs_sysc, +}; + +/* usb_host_hs */ +static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { + { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, + { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap44xx_usb_host_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .main_clk = "usb_host_hs_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .mpu_irqs = omap44xx_usb_host_hs_irqs, + + /* + * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * id: i660 + * + * Description: + * In the following configuration : + * - USBHOST module is set to smart-idle mode + * - PRCM asserts idle_req to the USBHOST module ( This typically + * happens when the system is going to a low power mode : all ports + * have been suspended, the master part of the USBHOST module has + * entered the standby state, and SW has cut the functional clocks) + * - an USBHOST interrupt occurs before the module is able to answer + * idle_ack, typically a remote wakeup IRQ. + * Then the USB HOST module will enter a deadlock situation where it + * is no more accessible nor functional. + * + * Workaround: + * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE + */ + + /* + * Errata: USB host EHCI may stall when entering smart-standby mode + * Id: i571 + * + * Description: + * When the USBHOST module is set to smart-standby mode, and when it is + * ready to enter the standby state (i.e. all ports are suspended and + * all attached devices are in suspend mode), then it can wrongly assert + * the Mstandby signal too early while there are still some residual OCP + * transactions ongoing. If this condition occurs, the internal state + * machine may go to an undefined state and the USB link may be stuck + * upon the next resume. + * + * Workaround: + * Don't use smart standby; use only force standby, + * hence HWMOD_SWSUP_MSTANDBY + */ + + /* + * During system boot; If the hwmod framework resets the module + * the module will have smart idle settings; which can lead to deadlock + * (above Errata Id:i660); so, dont reset the module during boot; + * Use HWMOD_INIT_NO_RESET. + */ + + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_INIT_NO_RESET, }; /* @@ -5131,34 +2705,6 @@ static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { { .irq = -1 } }; -/* usb_otg_hs master ports */ -static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { - &omap44xx_usb_otg_hs__l3_main_2, -}; - -static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { - { - .pa_start = 0x4a0ab000, - .pa_end = 0x4a0ab003, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_cfg -> usb_otg_hs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_otg_hs_hwmod, - .clk = "l4_div_ck", - .addr = omap44xx_usb_otg_hs_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_otg_hs slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { - &omap44xx_l4_cfg__usb_otg_hs, -}; - static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { { .role = "xclk", .clk = "usb_otg_hs_xclk" }, }; @@ -5179,10 +2725,47 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { }, .opt_clks = usb_otg_hs_opt_clks, .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), - .slaves = omap44xx_usb_otg_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), - .masters = omap44xx_usb_otg_hs_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), +}; + +/* + * 'usb_tll_hs' class + * usb_tll_hs module is the adapter on the usb_host_hs ports + */ + +static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { + .name = "usb_tll_hs", + .sysc = &omap44xx_usb_tll_hs_sysc, +}; + +static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { + { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap44xx_usb_tll_hs_hwmod_class, + .clkdm_name = "l3_init_clkdm", + .mpu_irqs = omap44xx_usb_tll_hs_irqs, + .main_clk = "usb_tll_hs_ick", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, }; /* @@ -5209,35 +2792,11 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { }; /* wd_timer2 */ -static struct omap_hwmod omap44xx_wd_timer2_hwmod; static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { { .irq = 80 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { - { - .pa_start = 0x4a314000, - .pa_end = 0x4a31407f, - .flags = ADDR_TYPE_RT - }, - { } -}; - -/* l4_wkup -> wd_timer2 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_wd_timer2_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .addr = omap44xx_wd_timer2_addrs, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* wd_timer2 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { - &omap44xx_l4_wkup__wd_timer2, -}; - static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .name = "wd_timer2", .class = &omap44xx_wd_timer_hwmod_class, @@ -5251,106 +2810,1746 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .slaves = omap44xx_wd_timer2_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), }; /* wd_timer3 */ -static struct omap_hwmod omap44xx_wd_timer3_hwmod; static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { { .irq = 36 + OMAP44XX_IRQ_GIC_START }, { .irq = -1 } }; -static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { +static struct omap_hwmod omap44xx_wd_timer3_hwmod = { + .name = "wd_timer3", + .class = &omap44xx_wd_timer_hwmod_class, + .clkdm_name = "abe_clkdm", + .mpu_irqs = omap44xx_wd_timer3_irqs, + .main_clk = "wd_timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* + * interfaces + */ + +/* l3_main_1 -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { { - .pa_start = 0x40130000, - .pa_end = 0x4013007f, + .pa_start = 0x4e000000, + .pa_end = 0x4e0007ff, .flags = ADDR_TYPE_RT }, { } }; -/* l4_abe -> wd_timer3 */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { +/* mpu -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dmm_addrs, + .user = OCP_USER_MPU, +}; + +/* dmm -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { + .master = &omap44xx_dmm_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { + { + .pa_start = 0x4a20c000, + .pa_end = 0x4a20c0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_emif_fw_addrs, + .user = OCP_USER_MPU, +}; + +/* iva -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_3 -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { + .master = &omap44xx_l3_main_3_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { + .master = &omap44xx_dss_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { + .master = &omap44xx_mmc1_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { + .master = &omap44xx_mmc2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { + { + .pa_start = 0x44000000, + .pa_end = 0x44000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_1_addrs, + .user = OCP_USER_MPU, +}; + +/* dma_system -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { + .master = &omap44xx_dma_system_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* hsi -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { + .master = &omap44xx_hsi_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { + .master = &omap44xx_ipu_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iss -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { + .master = &omap44xx_iss_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iva -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { + .master = &omap44xx_iva_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { + { + .pa_start = 0x44800000, + .pa_end = 0x44801fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_2_addrs, + .user = OCP_USER_MPU, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_host_hs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { + .master = &omap44xx_usb_host_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_otg_hs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { + .master = &omap44xx_usb_otg_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { + { + .pa_start = 0x45000000, + .pa_end = 0x45000fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_l3_main_3_addrs, + .user = OCP_USER_MPU, +}; + +/* l3_main_2 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* aess -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { + .master = &omap44xx_aess_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_cfg_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l4_per */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l4_per_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l4_wkup */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l4_wkup_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> mpu_private */ +static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_mpu_private_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { + { + .pa_start = 0x401f1000, + .pa_end = 0x401f13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> aess */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, + .slave = &omap44xx_aess_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_addrs, + .addr = omap44xx_aess_addrs, .user = OCP_USER_MPU, }; -static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { +static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { { - .pa_start = 0x49030000, - .pa_end = 0x4903007f, + .pa_start = 0x490f1000, + .pa_end = 0x490f13ff, .flags = ADDR_TYPE_RT }, { } }; -/* l4_abe -> wd_timer3 (dma) */ -static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { +/* l4_abe -> aess (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { .master = &omap44xx_l4_abe_hwmod, - .slave = &omap44xx_wd_timer3_hwmod, + .slave = &omap44xx_aess_hwmod, .clk = "ocp_abe_iclk", - .addr = omap44xx_wd_timer3_dma_addrs, + .addr = omap44xx_aess_dma_addrs, .user = OCP_USER_SDMA, }; -/* wd_timer3 slave ports */ -static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { - &omap44xx_l4_abe__wd_timer3, - &omap44xx_l4_abe__wd_timer3_dma, +static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { + { + .pa_start = 0x4a304000, + .pa_end = 0x4a30401f, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap44xx_wd_timer3_hwmod = { - .name = "wd_timer3", - .class = &omap44xx_wd_timer_hwmod_class, - .clkdm_name = "abe_clkdm", - .mpu_irqs = omap44xx_wd_timer3_irqs, - .main_clk = "wd_timer3_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, +/* l4_wkup -> counter_32k */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_counter_32k_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_counter_32k_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { + { + .pa_start = 0x4a056000, + .pa_end = 0x4a056fff, + .flags = ADDR_TYPE_RT }, - .slaves = omap44xx_wd_timer3_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), + { } }; -/* - * 'usb_host_hs' class - * high-speed multi-port usb host controller - */ -static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { - .master = &omap44xx_usb_host_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dma_system_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4012e000, + .pa_end = 0x4012e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> dmic */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x4902e000, + .pa_end = 0x4902e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> dmic (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_dma_addrs, + .user = OCP_USER_SDMA, +}; + +/* dsp -> iva */ +static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { + .master = &omap44xx_dsp_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "dpll_iva_m5x2_ck", + .user = OCP_USER_DSP, +}; + +/* l4_cfg -> dsp */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_dsp_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { + { + .pa_start = 0x58000000, + .pa_end = 0x5800007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { + { + .pa_start = 0x48040000, + .pa_end = 0x4804007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { + { + .pa_start = 0x58001000, + .pa_end = 0x58001fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dispc_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { + { + .pa_start = 0x48041000, + .pa_end = 0x48041fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dispc_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { + { + .pa_start = 0x58004000, + .pa_end = 0x580041ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dsi1_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { + { + .pa_start = 0x48044000, + .pa_end = 0x480441ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi1_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { + { + .pa_start = 0x58005000, + .pa_end = 0x580051ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_dsi2_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { + { + .pa_start = 0x48045000, + .pa_end = 0x480451ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi2_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { + { + .pa_start = 0x58006000, + .pa_end = 0x58006fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_hdmi_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { + { + .pa_start = 0x48046000, + .pa_end = 0x48046fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_hdmi_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { + { + .pa_start = 0x58002000, + .pa_end = 0x580020ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_rfbi_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { + { + .pa_start = 0x48042000, + .pa_end = 0x480420ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_rfbi_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { + { + .pa_start = 0x58003000, + .pa_end = 0x580030ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "dss_fck", + .addr = omap44xx_dss_venc_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { + { + .pa_start = 0x48043000, + .pa_end = 0x480430ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_venc_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { + { + .pa_start = 0x4a310000, + .pa_end = 0x4a3101ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_gpio1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_gpio1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { + { + .pa_start = 0x48055000, + .pa_end = 0x480551ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { + { + .pa_start = 0x48057000, + .pa_end = 0x480571ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { + { + .pa_start = 0x48059000, + .pa_end = 0x480591ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { + { + .pa_start = 0x4805b000, + .pa_end = 0x4805b1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { + { + .pa_start = 0x4805d000, + .pa_end = 0x4805d1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> gpio6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_gpio6_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_gpio6_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { + { + .pa_start = 0x4a058000, + .pa_end = 0x4a05bfff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> hsi */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_hsi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_hsi_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x480700ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x480720ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x480600ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { + { + .pa_start = 0x48350000, + .pa_end = 0x483500ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> i2c4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> ipu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_ipu_hwmod, .clk = "l3_div_ck", .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, +static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { + { + .pa_start = 0x52000000, + .pa_end = 0x520000ff, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap44xx_usb_host_hs_sysc, +/* l3_main_2 -> iss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iss_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { - &omap44xx_usb_host_hs__l3_main_2, +static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { + { + .pa_start = 0x5a000000, + .pa_end = 0x5a07ffff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_2 -> iva */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iva_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iva_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { + { + .pa_start = 0x4a31c000, + .pa_end = 0x4a31c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> kbd */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_kbd_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_kbd_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { + { + .pa_start = 0x4a0f4000, + .pa_end = 0x4a0f41ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> mailbox */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_mailbox_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mailbox_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40122000, + .pa_end = 0x401220ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp1 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40124000, + .pa_end = 0x401240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp2 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x40126000, + .pa_end = 0x401260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { + { + .name = "dma", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcbsp3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { + { + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcbsp4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcbsp4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { + { + .pa_start = 0x40132000, + .pa_end = 0x4013207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcpdm */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x4903207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> mcpdm (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480981ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { + { + .pa_start = 0x480b8000, + .pa_end = 0x480b81ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba1ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mcspi4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { + { + .pa_start = 0x480b4000, + .pa_end = 0x480b43ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad3ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { + { + .pa_start = 0x480d1000, + .pa_end = 0x480d13ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { + { + .pa_start = 0x480d5000, + .pa_end = 0x480d53ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> mmc5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc5_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { + { + .pa_start = 0x4a0dd000, + .pa_end = 0x4a0dd03f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_core */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_core_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_core_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { + { + .pa_start = 0x4a0db000, + .pa_end = 0x4a0db03f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_iva */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_iva_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_iva_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { + { + .pa_start = 0x4a0d9000, + .pa_end = 0x4a0d903f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_mpu */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_smartreflex_mpu_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_smartreflex_mpu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { + { + .pa_start = 0x4a0f6000, + .pa_end = 0x4a0f6fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> spinlock */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_spinlock_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_spinlock_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { + { + .pa_start = 0x4a318000, + .pa_end = 0x4a31807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_timer1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_timer1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { + { + .pa_start = 0x48032000, + .pa_end = 0x4803207f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { + { + .pa_start = 0x48034000, + .pa_end = 0x4803407f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { + { + .pa_start = 0x48036000, + .pa_end = 0x4803607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { + { + .pa_start = 0x40138000, + .pa_end = 0x4013807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x4903807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer5 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { + { + .pa_start = 0x4013a000, + .pa_end = 0x4013a07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { + { + .pa_start = 0x4903a000, + .pa_end = 0x4903a07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer6 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { + { + .pa_start = 0x4013c000, + .pa_end = 0x4013c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer7 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { + { + .pa_start = 0x4903c000, + .pa_end = 0x4903c07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer7 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { + { + .pa_start = 0x4013e000, + .pa_end = 0x4013e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer8 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { + { + .pa_start = 0x4903e000, + .pa_end = 0x4903e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> timer8 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { + { + .pa_start = 0x4803e000, + .pa_end = 0x4803e07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer9_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer9_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x4808607f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer10 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer10_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer10_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x4808807f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> timer11 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer11_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer11_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { + { + .pa_start = 0x4806a000, + .pa_end = 0x4806a0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { + { + .pa_start = 0x4806c000, + .pa_end = 0x4806c0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { + { + .pa_start = 0x48020000, + .pa_end = 0x480200ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart3_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { + { + .pa_start = 0x4806e000, + .pa_end = 0x4806e0ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per -> uart4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart4_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { @@ -5373,12 +4572,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { {} }; -static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { - { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, - { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } -}; - +/* l4_cfg -> usb_host_hs */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_host_hs_hwmod, @@ -5387,100 +4581,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { - &omap44xx_l4_cfg__usb_host_hs, -}; - -static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap44xx_usb_host_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_host_hs_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, +static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { + { + .pa_start = 0x4a0ab000, + .pa_end = 0x4a0ab003, + .flags = ADDR_TYPE_RT }, - .mpu_irqs = omap44xx_usb_host_hs_irqs, - .slaves = omap44xx_usb_host_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), - .masters = omap44xx_usb_host_hs_masters, - .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), - - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ - - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ - - /* - * During system boot; If the hwmod framework resets the module - * the module will have smart idle settings; which can lead to deadlock - * (above Errata Id:i660); so, dont reset the module during boot; - * Use HWMOD_INIT_NO_RESET. - */ - - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | - HWMOD_INIT_NO_RESET, -}; - -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ -static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap44xx_usb_tll_hs_sysc, + { } }; -static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { - { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, - { .irq = -1 } +/* l4_cfg -> usb_otg_hs */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_otg_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_otg_hs_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { @@ -5493,6 +4609,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { {} }; +/* l4_cfg -> usb_tll_hs */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_usb_tll_hs_hwmod, @@ -5501,181 +4618,184 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { - &omap44xx_l4_cfg__usb_tll_hs, +static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { + { + .pa_start = 0x4a314000, + .pa_end = 0x4a31407f, + .flags = ADDR_TYPE_RT + }, + { } }; -static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap44xx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_tll_hs_ick", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_wd_timer2_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_wd_timer2_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { + { + .pa_start = 0x40130000, + .pa_end = 0x4013007f, + .flags = ADDR_TYPE_RT }, - .mpu_irqs = omap44xx_usb_tll_hs_irqs, - .slaves = omap44xx_usb_tll_hs_slaves, - .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), + { } +}; + +/* l4_abe -> wd_timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_addrs, + .user = OCP_USER_MPU, }; -static __initdata struct omap_hwmod *omap44xx_hwmods[] = { - - /* dmm class */ - &omap44xx_dmm_hwmod, - - /* emif_fw class */ - &omap44xx_emif_fw_hwmod, - - /* l3 class */ - &omap44xx_l3_instr_hwmod, - &omap44xx_l3_main_1_hwmod, - &omap44xx_l3_main_2_hwmod, - &omap44xx_l3_main_3_hwmod, - - /* l4 class */ - &omap44xx_l4_abe_hwmod, - &omap44xx_l4_cfg_hwmod, - &omap44xx_l4_per_hwmod, - &omap44xx_l4_wkup_hwmod, - - /* mpu_bus class */ - &omap44xx_mpu_private_hwmod, - - /* aess class */ -/* &omap44xx_aess_hwmod, */ - - /* bandgap class */ - &omap44xx_bandgap_hwmod, - - /* counter class */ -/* &omap44xx_counter_32k_hwmod, */ - - /* dma class */ - &omap44xx_dma_system_hwmod, - - /* dmic class */ - &omap44xx_dmic_hwmod, - - /* dsp class */ - &omap44xx_dsp_hwmod, - &omap44xx_dsp_c0_hwmod, - - /* dss class */ - &omap44xx_dss_hwmod, - &omap44xx_dss_dispc_hwmod, - &omap44xx_dss_dsi1_hwmod, - &omap44xx_dss_dsi2_hwmod, - &omap44xx_dss_hdmi_hwmod, - &omap44xx_dss_rfbi_hwmod, - &omap44xx_dss_venc_hwmod, - - /* gpio class */ - &omap44xx_gpio1_hwmod, - &omap44xx_gpio2_hwmod, - &omap44xx_gpio3_hwmod, - &omap44xx_gpio4_hwmod, - &omap44xx_gpio5_hwmod, - &omap44xx_gpio6_hwmod, - - /* hsi class */ -/* &omap44xx_hsi_hwmod, */ - - /* i2c class */ - &omap44xx_i2c1_hwmod, - &omap44xx_i2c2_hwmod, - &omap44xx_i2c3_hwmod, - &omap44xx_i2c4_hwmod, - - /* ipu class */ - &omap44xx_ipu_hwmod, - &omap44xx_ipu_c0_hwmod, - &omap44xx_ipu_c1_hwmod, - - /* iss class */ -/* &omap44xx_iss_hwmod, */ - - /* iva class */ - &omap44xx_iva_hwmod, - &omap44xx_iva_seq0_hwmod, - &omap44xx_iva_seq1_hwmod, - - /* kbd class */ - &omap44xx_kbd_hwmod, - - /* mailbox class */ - &omap44xx_mailbox_hwmod, - - /* mcbsp class */ - &omap44xx_mcbsp1_hwmod, - &omap44xx_mcbsp2_hwmod, - &omap44xx_mcbsp3_hwmod, - &omap44xx_mcbsp4_hwmod, - - /* mcpdm class */ - &omap44xx_mcpdm_hwmod, - - /* mcspi class */ - &omap44xx_mcspi1_hwmod, - &omap44xx_mcspi2_hwmod, - &omap44xx_mcspi3_hwmod, - &omap44xx_mcspi4_hwmod, - - /* mmc class */ - &omap44xx_mmc1_hwmod, - &omap44xx_mmc2_hwmod, - &omap44xx_mmc3_hwmod, - &omap44xx_mmc4_hwmod, - &omap44xx_mmc5_hwmod, - - /* mpu class */ - &omap44xx_mpu_hwmod, - - /* smartreflex class */ - &omap44xx_smartreflex_core_hwmod, - &omap44xx_smartreflex_iva_hwmod, - &omap44xx_smartreflex_mpu_hwmod, - - /* spinlock class */ - &omap44xx_spinlock_hwmod, - - /* timer class */ - &omap44xx_timer1_hwmod, - &omap44xx_timer2_hwmod, - &omap44xx_timer3_hwmod, - &omap44xx_timer4_hwmod, - &omap44xx_timer5_hwmod, - &omap44xx_timer6_hwmod, - &omap44xx_timer7_hwmod, - &omap44xx_timer8_hwmod, - &omap44xx_timer9_hwmod, - &omap44xx_timer10_hwmod, - &omap44xx_timer11_hwmod, - - /* uart class */ - &omap44xx_uart1_hwmod, - &omap44xx_uart2_hwmod, - &omap44xx_uart3_hwmod, - &omap44xx_uart4_hwmod, - - /* usb host class */ - &omap44xx_usb_host_hs_hwmod, - &omap44xx_usb_tll_hs_hwmod, - - /* usb_otg_hs class */ - &omap44xx_usb_otg_hs_hwmod, - - /* wd_timer class */ - &omap44xx_wd_timer2_hwmod, - &omap44xx_wd_timer3_hwmod, +static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { + { + .pa_start = 0x49030000, + .pa_end = 0x4903007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_abe -> wd_timer3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_dma_addrs, + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { + &omap44xx_l3_main_1__dmm, + &omap44xx_mpu__dmm, + &omap44xx_dmm__emif_fw, + &omap44xx_l4_cfg__emif_fw, + &omap44xx_iva__l3_instr, + &omap44xx_l3_main_3__l3_instr, + &omap44xx_dsp__l3_main_1, + &omap44xx_dss__l3_main_1, + &omap44xx_l3_main_2__l3_main_1, + &omap44xx_l4_cfg__l3_main_1, + &omap44xx_mmc1__l3_main_1, + &omap44xx_mmc2__l3_main_1, + &omap44xx_mpu__l3_main_1, + &omap44xx_dma_system__l3_main_2, + &omap44xx_hsi__l3_main_2, + &omap44xx_ipu__l3_main_2, + &omap44xx_iss__l3_main_2, + &omap44xx_iva__l3_main_2, + &omap44xx_l3_main_1__l3_main_2, + &omap44xx_l4_cfg__l3_main_2, + &omap44xx_usb_host_hs__l3_main_2, + &omap44xx_usb_otg_hs__l3_main_2, + &omap44xx_l3_main_1__l3_main_3, + &omap44xx_l3_main_2__l3_main_3, + &omap44xx_l4_cfg__l3_main_3, + &omap44xx_aess__l4_abe, + &omap44xx_dsp__l4_abe, + &omap44xx_l3_main_1__l4_abe, + &omap44xx_mpu__l4_abe, + &omap44xx_l3_main_1__l4_cfg, + &omap44xx_l3_main_2__l4_per, + &omap44xx_l4_cfg__l4_wkup, + &omap44xx_mpu__mpu_private, + &omap44xx_l4_abe__aess, + &omap44xx_l4_abe__aess_dma, + &omap44xx_l4_wkup__counter_32k, + &omap44xx_l4_cfg__dma_system, + &omap44xx_l4_abe__dmic, + &omap44xx_l4_abe__dmic_dma, + &omap44xx_dsp__iva, + &omap44xx_l4_cfg__dsp, + &omap44xx_l3_main_2__dss, + &omap44xx_l4_per__dss, + &omap44xx_l3_main_2__dss_dispc, + &omap44xx_l4_per__dss_dispc, + &omap44xx_l3_main_2__dss_dsi1, + &omap44xx_l4_per__dss_dsi1, + &omap44xx_l3_main_2__dss_dsi2, + &omap44xx_l4_per__dss_dsi2, + &omap44xx_l3_main_2__dss_hdmi, + &omap44xx_l4_per__dss_hdmi, + &omap44xx_l3_main_2__dss_rfbi, + &omap44xx_l4_per__dss_rfbi, + &omap44xx_l3_main_2__dss_venc, + &omap44xx_l4_per__dss_venc, + &omap44xx_l4_wkup__gpio1, + &omap44xx_l4_per__gpio2, + &omap44xx_l4_per__gpio3, + &omap44xx_l4_per__gpio4, + &omap44xx_l4_per__gpio5, + &omap44xx_l4_per__gpio6, + &omap44xx_l4_cfg__hsi, + &omap44xx_l4_per__i2c1, + &omap44xx_l4_per__i2c2, + &omap44xx_l4_per__i2c3, + &omap44xx_l4_per__i2c4, + &omap44xx_l3_main_2__ipu, + &omap44xx_l3_main_2__iss, + &omap44xx_l3_main_2__iva, + &omap44xx_l4_wkup__kbd, + &omap44xx_l4_cfg__mailbox, + &omap44xx_l4_abe__mcbsp1, + &omap44xx_l4_abe__mcbsp1_dma, + &omap44xx_l4_abe__mcbsp2, + &omap44xx_l4_abe__mcbsp2_dma, + &omap44xx_l4_abe__mcbsp3, + &omap44xx_l4_abe__mcbsp3_dma, + &omap44xx_l4_per__mcbsp4, + &omap44xx_l4_abe__mcpdm, + &omap44xx_l4_abe__mcpdm_dma, + &omap44xx_l4_per__mcspi1, + &omap44xx_l4_per__mcspi2, + &omap44xx_l4_per__mcspi3, + &omap44xx_l4_per__mcspi4, + &omap44xx_l4_per__mmc1, + &omap44xx_l4_per__mmc2, + &omap44xx_l4_per__mmc3, + &omap44xx_l4_per__mmc4, + &omap44xx_l4_per__mmc5, + &omap44xx_l4_cfg__smartreflex_core, + &omap44xx_l4_cfg__smartreflex_iva, + &omap44xx_l4_cfg__smartreflex_mpu, + &omap44xx_l4_cfg__spinlock, + &omap44xx_l4_wkup__timer1, + &omap44xx_l4_per__timer2, + &omap44xx_l4_per__timer3, + &omap44xx_l4_per__timer4, + &omap44xx_l4_abe__timer5, + &omap44xx_l4_abe__timer5_dma, + &omap44xx_l4_abe__timer6, + &omap44xx_l4_abe__timer6_dma, + &omap44xx_l4_abe__timer7, + &omap44xx_l4_abe__timer7_dma, + &omap44xx_l4_abe__timer8, + &omap44xx_l4_abe__timer8_dma, + &omap44xx_l4_per__timer9, + &omap44xx_l4_per__timer10, + &omap44xx_l4_per__timer11, + &omap44xx_l4_per__uart1, + &omap44xx_l4_per__uart2, + &omap44xx_l4_per__uart3, + &omap44xx_l4_per__uart4, + &omap44xx_l4_cfg__usb_host_hs, + &omap44xx_l4_cfg__usb_otg_hs, + &omap44xx_l4_cfg__usb_tll_hs, + &omap44xx_l4_wkup__wd_timer2, + &omap44xx_l4_abe__wd_timer3, + &omap44xx_l4_abe__wd_timer3_dma, NULL, }; int __init omap44xx_hwmod_init(void) { - return omap_hwmod_register(omap44xx_hwmods); + return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index ad5d8f04c0b8..7aa9156d50ab 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -19,18 +19,6 @@ #include "display.h" /* Common address space across OMAP2xxx */ -extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[]; -extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[]; -extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[]; -extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[]; -extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[]; /* Common address space across OMAP2xxx/3xxx */ @@ -54,6 +42,64 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; /* Common IP block data across OMAP2xxx */ extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[]; +extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; +extern struct omap_hwmod omap2xxx_l3_main_hwmod; +extern struct omap_hwmod omap2xxx_l4_core_hwmod; +extern struct omap_hwmod omap2xxx_l4_wkup_hwmod; +extern struct omap_hwmod omap2xxx_mpu_hwmod; +extern struct omap_hwmod omap2xxx_iva_hwmod; +extern struct omap_hwmod omap2xxx_timer1_hwmod; +extern struct omap_hwmod omap2xxx_timer2_hwmod; +extern struct omap_hwmod omap2xxx_timer3_hwmod; +extern struct omap_hwmod omap2xxx_timer4_hwmod; +extern struct omap_hwmod omap2xxx_timer5_hwmod; +extern struct omap_hwmod omap2xxx_timer6_hwmod; +extern struct omap_hwmod omap2xxx_timer7_hwmod; +extern struct omap_hwmod omap2xxx_timer8_hwmod; +extern struct omap_hwmod omap2xxx_timer9_hwmod; +extern struct omap_hwmod omap2xxx_timer10_hwmod; +extern struct omap_hwmod omap2xxx_timer11_hwmod; +extern struct omap_hwmod omap2xxx_timer12_hwmod; +extern struct omap_hwmod omap2xxx_wd_timer2_hwmod; +extern struct omap_hwmod omap2xxx_uart1_hwmod; +extern struct omap_hwmod omap2xxx_uart2_hwmod; +extern struct omap_hwmod omap2xxx_uart3_hwmod; +extern struct omap_hwmod omap2xxx_dss_core_hwmod; +extern struct omap_hwmod omap2xxx_dss_dispc_hwmod; +extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod; +extern struct omap_hwmod omap2xxx_dss_venc_hwmod; +extern struct omap_hwmod omap2xxx_gpio1_hwmod; +extern struct omap_hwmod omap2xxx_gpio2_hwmod; +extern struct omap_hwmod omap2xxx_gpio3_hwmod; +extern struct omap_hwmod omap2xxx_gpio4_hwmod; +extern struct omap_hwmod omap2xxx_mcspi1_hwmod; +extern struct omap_hwmod omap2xxx_mcspi2_hwmod; + +/* Common interface data across OMAP2xxx */ +extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; +extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main; +extern struct omap_hwmod_ocp_if omap2xxx_dss__l3; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup; +extern struct omap_hwmod_ocp_if omap2_l4_core__uart1; +extern struct omap_hwmod_ocp_if omap2_l4_core__uart2; +extern struct omap_hwmod_ocp_if omap2_l4_core__uart3; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi; +extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc; /* Common IP block data */ extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; @@ -94,6 +140,7 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[]; extern struct omap_hwmod_irq_info omap2_dma_system_irqs[]; extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[]; extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[]; +extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; /* OMAP hwmod classes - forward declarations */ extern struct omap_hwmod_class l3_hwmod_class; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 36fa90b6ece8..78564895e914 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -38,27 +38,6 @@ static inline int omap4_opp_init(void) } #endif -/* - * cpuidle mach specific parameters - * - * The board code can override the default C-states definition using - * omap3_pm_init_cpuidle - */ -struct cpuidle_params { - u32 exit_latency; /* exit_latency = sleep + wake-up latencies */ - u32 target_residency; - u8 valid; /* validates the C-state */ -}; - -#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE) -extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params); -#else -static -inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) -{ -} -#endif - extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 95442b69ae27..facfffca9eac 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -171,8 +171,6 @@ static int omap2_allow_mpu_retention(void) static void omap2_enter_mpu_retention(void) { - int only_idle = 0; - /* Putting MPU into the WFI state while a transfer is active * seems to cause the I2C block to timeout. Why? Good question. */ if (omap2_i2c_active()) @@ -195,7 +193,6 @@ static void omap2_enter_mpu_retention(void) omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); - only_idle = 1; } omap2_sram_idle(); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 703bd1099259..8b43aefba0ea 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -273,7 +273,7 @@ void omap_sram_idle(void) int per_next_state = PWRDM_POWER_ON; int core_next_state = PWRDM_POWER_ON; int per_going_off; - int core_prev_state, per_prev_state; + int core_prev_state; u32 sdrc_pwr = 0; mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); @@ -375,10 +375,8 @@ void omap_sram_idle(void) pwrdm_post_transition(); /* PER */ - if (per_next_state < PWRDM_POWER_ON) { - per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); + if (per_next_state < PWRDM_POWER_ON) omap2_gpio_resume_after_idle(); - } /* Disable IO-PAD and IO-CHAIN wakeup */ if (omap3_has_io_wakeup() && @@ -702,7 +700,7 @@ static void __init pm_errata_configure(void) static int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; - struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; + struct clockdomain *neon_clkdm, *mpu_clkdm; int ret; if (!cpu_is_omap34xx()) @@ -757,8 +755,6 @@ static int __init omap3_pm_init(void) neon_clkdm = clkdm_lookup("neon_clkdm"); mpu_clkdm = clkdm_lookup("mpu_clkdm"); - per_clkdm = clkdm_lookup("per_clkdm"); - core_clkdm = clkdm_lookup("core_clkdm"); #ifdef CONFIG_SUSPEND omap_pm_suspend = omap3_pm_suspend; diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index d28f848897d6..dfe00ddb5c60 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -237,7 +237,7 @@ void omap_prcm_irq_complete(void) */ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) { - int nr_regs = irq_setup->nr_regs; + int nr_regs; u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; int offset, i; struct irq_chip_generic *gc; @@ -246,6 +246,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) if (!irq_setup) return -EINVAL; + nr_regs = irq_setup->nr_regs; + if (prcm_irq_setup) { pr_err("PRCM: already initialized; won't reinitialize\n"); return -EINVAL; diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 0cdd359a128e..678dd1d612e5 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev) static void omap_uart_set_smartidle(struct platform_device *pdev) { struct omap_device *od = to_omap_device(pdev); + u8 idlemode; - omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART); + if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP) + idlemode = HWMOD_IDLEMODE_SMART_WKUP; + else + idlemode = HWMOD_IDLEMODE_SMART; + + omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode); } #else @@ -120,130 +126,14 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {} #endif /* CONFIG_PM */ #ifdef CONFIG_OMAP_MUX -static struct omap_device_pad default_uart1_pads[] __initdata = { - { - .name = "uart1_cts.uart1_cts", - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, - { - .name = "uart1_rts.uart1_rts", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart1_tx.uart1_tx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart1_rx.uart1_rx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, -}; - -static struct omap_device_pad default_uart2_pads[] __initdata = { - { - .name = "uart2_cts.uart2_cts", - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, - { - .name = "uart2_rts.uart2_rts", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart2_tx.uart2_tx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart2_rx.uart2_rx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, -}; - -static struct omap_device_pad default_uart3_pads[] __initdata = { - { - .name = "uart3_cts_rctx.uart3_cts_rctx", - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, - }, - { - .name = "uart3_rts_sd.uart3_rts_sd", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart3_tx_irtx.uart3_tx_irtx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart3_rx_irrx.uart3_rx_irrx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, - }, -}; - -static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = { - { - .name = "gpmc_wait2.uart4_tx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "gpmc_wait3.uart4_rx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2, - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2, - }, -}; - -static struct omap_device_pad default_omap4_uart4_pads[] __initdata = { - { - .name = "uart4_tx.uart4_tx", - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, - }, - { - .name = "uart4_rx.uart4_rx", - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, - }, -}; - static void omap_serial_fill_default_pads(struct omap_board_data *bdata) { - switch (bdata->id) { - case 0: - bdata->pads = default_uart1_pads; - bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads); - break; - case 1: - bdata->pads = default_uart2_pads; - bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads); - break; - case 2: - bdata->pads = default_uart3_pads; - bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads); - break; - case 3: - if (cpu_is_omap44xx()) { - bdata->pads = default_omap4_uart4_pads; - bdata->pads_cnt = - ARRAY_SIZE(default_omap4_uart4_pads); - } else if (cpu_is_omap3630()) { - bdata->pads = default_omap36xx_uart4_pads; - bdata->pads_cnt = - ARRAY_SIZE(default_omap36xx_uart4_pads); - } - break; - default: - break; - } } #else static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} #endif -char *cmdline_find_option(char *str) +static char *cmdline_find_option(char *str) { extern char *saved_command_line; diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index c512bac69ec5..ecec873e78cd 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -145,8 +145,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ struct omap_hwmod *oh; + struct resource irq_rsrc, mem_rsrc; size_t size; int res = 0; + int r; sprintf(name, "timer%d", gptimer_id); omap_hwmod_setup_one(name); @@ -154,9 +156,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, if (!oh) return -ENODEV; - timer->irq = oh->mpu_irqs[0].irq; - timer->phys_base = oh->slaves[0]->addr->pa_start; - size = oh->slaves[0]->addr->pa_end - timer->phys_base; + r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); + if (r) + return -ENXIO; + timer->irq = irq_rsrc.start; + + r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); + if (r) + return -ENXIO; + timer->phys_base = mem_rsrc.start; + size = mem_rsrc.end - mem_rsrc.start; /* Static mapping, never released */ timer->io_base = ioremap(timer->phys_base, size); diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 4b57757bf9d1..7a7b89304c48 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -37,6 +37,16 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = { .flags = I2C_CLIENT_WAKE, }; +static struct i2c_board_info __initdata omap4_i2c1_board_info[] = { + { + .addr = 0x48, + .flags = I2C_CLIENT_WAKE, + }, + { + I2C_BOARD_INFO("twl6040", 0x4b), + }, +}; + void __init omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data) @@ -49,14 +59,31 @@ void __init omap_pmic_init(int bus, u32 clkrate, omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1); } +void __init omap4_pmic_init(const char *pmic_type, + struct twl4030_platform_data *pmic_data, + struct twl6040_platform_data *twl6040_data, int twl6040_irq) +{ + /* PMIC part*/ + strncpy(omap4_i2c1_board_info[0].type, pmic_type, + sizeof(omap4_i2c1_board_info[0].type)); + omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N; + omap4_i2c1_board_info[0].platform_data = pmic_data; + + /* TWL6040 audio IC part */ + omap4_i2c1_board_info[1].irq = twl6040_irq; + omap4_i2c1_board_info[1].platform_data = twl6040_data; + + omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2); + +} + void __init omap_pmic_late_init(void) { /* Init the OMAP TWL parameters (if PMIC has been registerd) */ - if (!pmic_i2c_board_info.irq) - return; - - omap3_twl_init(); - omap4_twl_init(); + if (pmic_i2c_board_info.irq) + omap3_twl_init(); + if (omap4_i2c1_board_info[0].irq) + omap4_twl_init(); } #if defined(CONFIG_ARCH_OMAP3) diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h index 275dde8cb27a..09627483a57f 100644 --- a/arch/arm/mach-omap2/twl-common.h +++ b/arch/arm/mach-omap2/twl-common.h @@ -29,6 +29,7 @@ struct twl4030_platform_data; +struct twl6040_platform_data; void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data); @@ -46,12 +47,9 @@ static inline void omap3_pmic_init(const char *pmic_type, omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data); } -static inline void omap4_pmic_init(const char *pmic_type, - struct twl4030_platform_data *pmic_data) -{ - /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */ - omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data); -} +void omap4_pmic_init(const char *pmic_type, + struct twl4030_platform_data *pmic_data, + struct twl6040_platform_data *audio_data, int twl6040_irq); void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags); diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 994d8f591a1d..db84a46ce7fd 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps) tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps; if (tmp > 4) return -ERANGE; - if (tmp <= 0) + if (tmp == 0) tmp = 1; t.page_burst_access = (fclk_ps * tmp) / 1000; diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h index c54cef25895c..cbf51ae81855 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h @@ -17,6 +17,7 @@ * * bit 23 - Input/Output (PXA2xx specific) * bit 24 - Wakeup Enable(PXA2xx specific) + * bit 25 - Keep Output (PXA2xx specific) */ #define MFP_DIR_IN (0x0 << 23) @@ -25,6 +26,12 @@ #define MFP_DIR(x) (((x) >> 23) & 0x1) #define MFP_LPM_CAN_WAKEUP (0x1 << 24) + +/* + * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to + * retain their last output level (low or high). + * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input. + */ #define MFP_LPM_KEEP_OUTPUT (0x1 << 25) #define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index b0a842887780..ef0426a159d4 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -33,6 +33,8 @@ #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5)) #define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c) +#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18) +#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24) #define PWER_WE35 (1 << 24) @@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {} #ifdef CONFIG_PM static unsigned long saved_gafr[2][4]; static unsigned long saved_gpdr[4]; +static unsigned long saved_gplr[4]; static unsigned long saved_pgsr[4]; static int pxa2xx_mfp_suspend(void) @@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void) } for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { - saved_gafr[0][i] = GAFR_L(i); saved_gafr[1][i] = GAFR_U(i); saved_gpdr[i] = GPDR(i * 32); + saved_gplr[i] = GPLR(i * 32); saved_pgsr[i] = PGSR(i); - GPDR(i * 32) = gpdr_lpm[i]; + GPSR(i * 32) = PGSR(i); + GPCR(i * 32) = ~PGSR(i); + } + + /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */ + for (i = 0; i < pxa_last_gpio; i++) { + if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) || + ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) && + (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i)))) + GPDR(i) |= GPIO_bit(i); + else + GPDR(i) &= ~GPIO_bit(i); } + return 0; } @@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void) for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { GAFR_L(i) = saved_gafr[0][i]; GAFR_U(i) = saved_gafr[1][i]; + GPSR(i * 32) = saved_gplr[i]; + GPCR(i * 32) = ~saved_gplr[i]; GPDR(i * 32) = saved_gpdr[i]; PGSR(i) = saved_pgsr[i]; } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 6bce78edce7a..4726c246dcdc 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) pxa_register_device(&pxa27x_device_i2c_power, info); } +static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { + .gpio_set_wake = gpio_set_wake, +}; + static struct platform_device *devices[] __initdata = { - &pxa_device_gpio, &pxa27x_device_udc, &pxa_device_pmu, &pxa_device_i2s, @@ -458,6 +461,7 @@ static int __init pxa27x_init(void) register_syscore_ops(&pxa2xx_mfp_syscore_ops); register_syscore_ops(&pxa2xx_clock_syscore_ops); + pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 0f3a327ebcaa..b34287ab5afd 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS help Compile in platform device definition for Samsung TouchScreen. -# cpu-specific sections - -if CPU_S3C2410 - config S3C2410_DMA bool depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) @@ -127,6 +123,10 @@ config S3C2410_PM help Power Management code common to S3C2410 and better +# cpu-specific sections + +if CPU_S3C2410 + config S3C24XX_SIMTEC_NOR bool help diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index 86ce62f66190..b8337e248b09 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c @@ -33,8 +33,6 @@ #include <mach/irqs.h> #include <mach/dma.h> -static u64 dma_dmamask = DMA_BIT_MASK(32); - static u8 pdma0_peri[] = { DMACH_UART0_RX, DMACH_UART0_TX, diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index a9ea64e0da0d..48d018f2332b 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c @@ -484,8 +484,8 @@ static struct wm8994_pdata wm8994_platform_data = { .gpio_defaults[8] = 0x0100, .gpio_defaults[9] = 0x0100, .gpio_defaults[10] = 0x0100, - .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */ - .ldo[1] = { 0, NULL, &wm8994_ldo2_data }, + .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */ + .ldo[1] = { 0, &wm8994_ldo2_data }, }; /* GPIO I2C PMIC */ diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 2cf5ed75f390..32395664e879 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -25,6 +25,7 @@ #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/gpio.h> +#include <linux/mmc/host.h> #include <linux/interrupt.h> #include <asm/hardware/vic.h> @@ -674,8 +675,8 @@ static struct wm8994_pdata wm8994_platform_data = { .gpio_defaults[8] = 0x0100, .gpio_defaults[9] = 0x0100, .gpio_defaults[10] = 0x0100, - .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */ - .ldo[1] = { 0, NULL, &wm8994_ldo2_data }, + .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */ + .ldo[1] = { 0, &wm8994_ldo2_data }, }; /* GPIO I2C PMIC */ @@ -765,6 +766,7 @@ static void __init goni_pmic_init(void) /* MoviNAND */ static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = { .max_width = 4, + .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE, .cd_type = S3C_SDHCI_CD_PERMANENT, }; diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 7c524b4e415d..16be4c56abe3 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda) } static struct resource sa1100_rtc_resources[] = { - DEFINE_RES_MEM(0x90010000, 0x9001003f), + DEFINE_RES_MEM(0x90010000, 0x40), DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"), DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"), }; diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 0952494f481a..72ae62003520 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -37,7 +37,6 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/setup.h> -#include <asm/hardware/gic.h> #include <mach/iomap.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h index 3c9339058bec..9077092812c0 100644 --- a/arch/arm/mach-tegra/include/mach/dma.h +++ b/arch/arm/mach-tegra/include/mach/dma.h @@ -51,8 +51,6 @@ #define TEGRA_DMA_REQ_SEL_OWR 25 #define TEGRA_DMA_REQ_SEL_INVALID 31 -#if defined(CONFIG_TEGRA_SYSTEM_DMA) - struct tegra_dma_req; struct tegra_dma_channel; @@ -151,5 +149,3 @@ void tegra_dma_free_channel(struct tegra_dma_channel *ch); int __init tegra_dma_init(void); #endif - -#endif diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 1621ad07d284..33339745d432 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -1667,8 +1667,10 @@ void __init u300_init_irq(void) for (i = 0; i < U300_VIC_IRQS_END; i++) set_bit(i, (unsigned long *) &mask[0]); - vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); - vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); + vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START, + mask[0], mask[0]); + vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START, + mask[1], mask[1]); } diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c index a38f80238ea9..cb04bd6ab3e7 100644 --- a/arch/arm/mach-u300/i2c.c +++ b/arch/arm/mach-u300/i2c.c @@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = { .min_uV = 1800000, .max_uV = 1800000, .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, .always_on = 1, .boot_on = 1, }, @@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = { .min_uV = 2500000, .max_uV = 2500000, .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, .always_on = 1, .boot_on = 1, }, @@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = { .max_uV = 1800000, .valid_modes_mask = REGULATOR_MODE_NORMAL, .valid_ops_mask = - REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, + REGULATOR_CHANGE_VOLTAGE, .always_on = 1, .boot_on = 1, }, diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h index ee78a26707eb..ec09c1e07b1a 100644 --- a/arch/arm/mach-u300/include/mach/irqs.h +++ b/arch/arm/mach-u300/include/mach/irqs.h @@ -12,101 +12,101 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H -#define IRQ_U300_INTCON0_START 0 -#define IRQ_U300_INTCON1_START 32 +#define IRQ_U300_INTCON0_START 1 +#define IRQ_U300_INTCON1_START 33 /* These are on INTCON0 - 30 lines */ -#define IRQ_U300_IRQ0_EXT 0 -#define IRQ_U300_IRQ1_EXT 1 -#define IRQ_U300_DMA 2 -#define IRQ_U300_VIDEO_ENC_0 3 -#define IRQ_U300_VIDEO_ENC_1 4 -#define IRQ_U300_AAIF_RX 5 -#define IRQ_U300_AAIF_TX 6 -#define IRQ_U300_AAIF_VGPIO 7 -#define IRQ_U300_AAIF_WAKEUP 8 -#define IRQ_U300_PCM_I2S0_FRAME 9 -#define IRQ_U300_PCM_I2S0_FIFO 10 -#define IRQ_U300_PCM_I2S1_FRAME 11 -#define IRQ_U300_PCM_I2S1_FIFO 12 -#define IRQ_U300_XGAM_GAMCON 13 -#define IRQ_U300_XGAM_CDI 14 -#define IRQ_U300_XGAM_CDICON 15 +#define IRQ_U300_IRQ0_EXT 1 +#define IRQ_U300_IRQ1_EXT 2 +#define IRQ_U300_DMA 3 +#define IRQ_U300_VIDEO_ENC_0 4 +#define IRQ_U300_VIDEO_ENC_1 5 +#define IRQ_U300_AAIF_RX 6 +#define IRQ_U300_AAIF_TX 7 +#define IRQ_U300_AAIF_VGPIO 8 +#define IRQ_U300_AAIF_WAKEUP 9 +#define IRQ_U300_PCM_I2S0_FRAME 10 +#define IRQ_U300_PCM_I2S0_FIFO 11 +#define IRQ_U300_PCM_I2S1_FRAME 12 +#define IRQ_U300_PCM_I2S1_FIFO 13 +#define IRQ_U300_XGAM_GAMCON 14 +#define IRQ_U300_XGAM_CDI 15 +#define IRQ_U300_XGAM_CDICON 16 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) /* MMIACC not used on the DB3210 or DB3350 chips */ -#define IRQ_U300_XGAM_MMIACC 16 +#define IRQ_U300_XGAM_MMIACC 17 #endif -#define IRQ_U300_XGAM_PDI 17 -#define IRQ_U300_XGAM_PDICON 18 -#define IRQ_U300_XGAM_GAMEACC 19 -#define IRQ_U300_XGAM_MCIDCT 20 -#define IRQ_U300_APEX 21 -#define IRQ_U300_UART0 22 -#define IRQ_U300_SPI 23 -#define IRQ_U300_TIMER_APP_OS 24 -#define IRQ_U300_TIMER_APP_DD 25 -#define IRQ_U300_TIMER_APP_GP1 26 -#define IRQ_U300_TIMER_APP_GP2 27 -#define IRQ_U300_TIMER_OS 28 -#define IRQ_U300_TIMER_MS 29 -#define IRQ_U300_KEYPAD_KEYBF 30 -#define IRQ_U300_KEYPAD_KEYBR 31 +#define IRQ_U300_XGAM_PDI 18 +#define IRQ_U300_XGAM_PDICON 19 +#define IRQ_U300_XGAM_GAMEACC 20 +#define IRQ_U300_XGAM_MCIDCT 21 +#define IRQ_U300_APEX 22 +#define IRQ_U300_UART0 23 +#define IRQ_U300_SPI 24 +#define IRQ_U300_TIMER_APP_OS 25 +#define IRQ_U300_TIMER_APP_DD 26 +#define IRQ_U300_TIMER_APP_GP1 27 +#define IRQ_U300_TIMER_APP_GP2 28 +#define IRQ_U300_TIMER_OS 29 +#define IRQ_U300_TIMER_MS 30 +#define IRQ_U300_KEYPAD_KEYBF 31 +#define IRQ_U300_KEYPAD_KEYBR 32 /* These are on INTCON1 - 32 lines */ -#define IRQ_U300_GPIO_PORT0 32 -#define IRQ_U300_GPIO_PORT1 33 -#define IRQ_U300_GPIO_PORT2 34 +#define IRQ_U300_GPIO_PORT0 33 +#define IRQ_U300_GPIO_PORT1 34 +#define IRQ_U300_GPIO_PORT2 35 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ defined(CONFIG_MACH_U300_BS335) /* These are for DB3150, DB3200 and DB3350 */ -#define IRQ_U300_WDOG 35 -#define IRQ_U300_EVHIST 36 -#define IRQ_U300_MSPRO 37 -#define IRQ_U300_MMCSD_MCIINTR0 38 -#define IRQ_U300_MMCSD_MCIINTR1 39 -#define IRQ_U300_I2C0 40 -#define IRQ_U300_I2C1 41 -#define IRQ_U300_RTC 42 -#define IRQ_U300_NFIF 43 -#define IRQ_U300_NFIF2 44 +#define IRQ_U300_WDOG 36 +#define IRQ_U300_EVHIST 37 +#define IRQ_U300_MSPRO 38 +#define IRQ_U300_MMCSD_MCIINTR0 39 +#define IRQ_U300_MMCSD_MCIINTR1 40 +#define IRQ_U300_I2C0 41 +#define IRQ_U300_I2C1 42 +#define IRQ_U300_RTC 43 +#define IRQ_U300_NFIF 44 +#define IRQ_U300_NFIF2 45 #endif /* DB3150 and DB3200 have only 45 IRQs */ #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) -#define U300_VIC_IRQS_END 45 +#define U300_VIC_IRQS_END 46 #endif /* The DB3350-specific interrupt lines */ #ifdef CONFIG_MACH_U300_BS335 -#define IRQ_U300_ISP_F0 45 -#define IRQ_U300_ISP_F1 46 -#define IRQ_U300_ISP_F2 47 -#define IRQ_U300_ISP_F3 48 -#define IRQ_U300_ISP_F4 49 -#define IRQ_U300_GPIO_PORT3 50 -#define IRQ_U300_SYSCON_PLL_LOCK 51 -#define IRQ_U300_UART1 52 -#define IRQ_U300_GPIO_PORT4 53 -#define IRQ_U300_GPIO_PORT5 54 -#define IRQ_U300_GPIO_PORT6 55 -#define U300_VIC_IRQS_END 56 +#define IRQ_U300_ISP_F0 46 +#define IRQ_U300_ISP_F1 47 +#define IRQ_U300_ISP_F2 48 +#define IRQ_U300_ISP_F3 49 +#define IRQ_U300_ISP_F4 50 +#define IRQ_U300_GPIO_PORT3 51 +#define IRQ_U300_SYSCON_PLL_LOCK 52 +#define IRQ_U300_UART1 53 +#define IRQ_U300_GPIO_PORT4 54 +#define IRQ_U300_GPIO_PORT5 55 +#define IRQ_U300_GPIO_PORT6 56 +#define U300_VIC_IRQS_END 57 #endif /* The DB3210-specific interrupt lines */ #ifdef CONFIG_MACH_U300_BS365 -#define IRQ_U300_GPIO_PORT3 35 -#define IRQ_U300_GPIO_PORT4 36 -#define IRQ_U300_WDOG 37 -#define IRQ_U300_EVHIST 38 -#define IRQ_U300_MSPRO 39 -#define IRQ_U300_MMCSD_MCIINTR0 40 -#define IRQ_U300_MMCSD_MCIINTR1 41 -#define IRQ_U300_I2C0 42 -#define IRQ_U300_I2C1 43 -#define IRQ_U300_RTC 44 -#define IRQ_U300_NFIF 45 -#define IRQ_U300_NFIF2 46 -#define IRQ_U300_SYSCON_PLL_LOCK 47 -#define U300_VIC_IRQS_END 48 +#define IRQ_U300_GPIO_PORT3 36 +#define IRQ_U300_GPIO_PORT4 37 +#define IRQ_U300_WDOG 38 +#define IRQ_U300_EVHIST 39 +#define IRQ_U300_MSPRO 40 +#define IRQ_U300_MMCSD_MCIINTR0 41 +#define IRQ_U300_MMCSD_MCIINTR1 42 +#define IRQ_U300_I2C0 43 +#define IRQ_U300_I2C1 44 +#define IRQ_U300_RTC 45 +#define IRQ_U300_NFIF 46 +#define IRQ_U300_NFIF2 47 +#define IRQ_U300_SYSCON_PLL_LOCK 48 +#define U300_VIC_IRQS_END 49 #endif /* Maximum 8*7 GPIO lines */ @@ -117,6 +117,6 @@ #define IRQ_U300_GPIO_END (U300_VIC_IRQS_END) #endif -#define NR_IRQS (IRQ_U300_GPIO_END) +#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START) #endif diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 880d02ec89d4..0e8470a3fbeb 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -10,13 +10,10 @@ config UX500_SOC_COMMON select ARM_ERRATA_764369 select CACHE_L2X0 -config UX500_SOC_DB5500 - bool - select MFD_DB5500_PRCMU - config UX500_SOC_DB8500 bool select MFD_DB8500_PRCMU + select REGULATOR select REGULATOR_DB8500_PRCMU select CPU_FREQ_TABLE if CPU_FREQ @@ -44,15 +41,8 @@ config MACH_SNOWBALL help Include support for the snowball development platform. -config MACH_U5500 - bool "U5500 Development platform" - select UX500_SOC_DB5500 - help - Include support for the U5500 development platform. - config UX500_AUTO_PLATFORM def_bool y - depends on !MACH_U5500 select MACH_MOP500 help At least one platform needs to be selected in order to build @@ -73,18 +63,4 @@ config UX500_DEBUG_UART Choose the UART on which kernel low-level debug messages should be output. -config U5500_MODEM_IRQ - bool "Modem IRQ support" - depends on UX500_SOC_DB5500 - default y - help - Add support for handling IRQ:s from modem side - -config U5500_MBOX - bool "Mailbox support" - depends on U5500_MODEM_IRQ - default y - help - Add support for U5500 mailbox communication with modem side - endif diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 465b9ec9510a..fc7db5df970b 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -5,16 +5,11 @@ obj-y := clock.o cpu.o devices.o devices-common.o \ id.o usb.o timer.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o -obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ board-mop500-regulators.o \ board-mop500-uib.o board-mop500-stuib.o \ board-mop500-u8500uib.o \ board-mop500-pins.o -obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o -obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o - diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c deleted file mode 100644 index 836112eedde7..000000000000 --- a/arch/arm/mach-ux500/board-u5500-sdi.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Hanumath Prasad <ulf.hansson@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/amba/mmci.h> -#include <linux/mmc/host.h> - -#include <plat/pincfg.h> -#include <plat/gpio-nomadik.h> -#include <mach/db5500-regs.h> -#include <plat/ste_dma40.h> - -#include "pins-db5500.h" -#include "devices-db5500.h" -#include "ste-dma40-db5500.h" - -static pin_cfg_t u5500_sdi_pins[] = { - /* SDI0 (POP eMMC) */ - GPIO5_MC0_DAT0 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO6_MC0_DAT1 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO7_MC0_DAT2 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO8_MC0_DAT3 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO9_MC0_DAT4 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO10_MC0_DAT5 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO11_MC0_DAT6 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO12_MC0_DAT7 | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO13_MC0_CMD | PIN_DIR_INPUT | PIN_PULL_UP, - GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW, -}; - -#ifdef CONFIG_STE_DMA40 -struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_PERIPH_TO_MEM, - .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX, - .dst_dev_type = STEDMA40_DEV_DST_MEMORY, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; - -static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = STEDMA40_MEM_TO_PERIPH, - .src_dev_type = STEDMA40_DEV_SRC_MEMORY, - .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX, - .src_info.data_width = STEDMA40_WORD_WIDTH, - .dst_info.data_width = STEDMA40_WORD_WIDTH, -}; -#endif - -static struct mmci_platform_data u5500_sdi0_data = { - .ocr_mask = MMC_VDD_165_195, - .f_max = 50000000, - .capabilities = MMC_CAP_4_BIT_DATA | - MMC_CAP_8_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED, - .gpio_cd = -1, - .gpio_wp = -1, -#ifdef CONFIG_STE_DMA40 - .dma_filter = stedma40_filter, - .dma_rx_param = &u5500_sdi0_dma_cfg_rx, - .dma_tx_param = &u5500_sdi0_dma_cfg_tx, -#endif -}; - -void __init u5500_sdi_init(struct device *parent) -{ - nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins)); - - db5500_add_sdi0(parent, &u5500_sdi0_data); -} diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c deleted file mode 100644 index 0ff4be72a809..000000000000 --- a/arch/arm/mach-ux500/board-u5500.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <linux/irq.h> -#include <linux/i2c.h> -#include <linux/mfd/abx500/ab5500.h> - -#include <asm/hardware/gic.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <plat/pincfg.h> -#include <plat/i2c.h> -#include <plat/gpio-nomadik.h> - -#include <mach/hardware.h> -#include <mach/devices.h> -#include <mach/setup.h> - -#include "pins-db5500.h" -#include "devices-db5500.h" -#include <linux/led-lm3530.h> - -/* - * GPIO - */ - -static pin_cfg_t u5500_pins[] = { - /* I2C */ - GPIO218_I2C2_SCL | PIN_INPUT_PULLUP, - GPIO219_I2C2_SDA | PIN_INPUT_PULLUP, - - /* DISPLAY_ENABLE */ - GPIO226_GPIO | PIN_OUTPUT_LOW, - - /* Backlight Enbale */ - GPIO224_GPIO | PIN_OUTPUT_HIGH, -}; -/* - * I2C - */ - -#define U5500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ -static struct nmk_i2c_controller u5500_i2c##id##_data = { \ - /* \ - * slave data setup time, which is \ - * 250 ns,100ns,10ns which is 14,6,2 \ - * respectively for a 48 Mhz \ - * i2c clock \ - */ \ - .slsu = _slsu, \ - /* Tx FIFO threshold */ \ - .tft = _tft, \ - /* Rx FIFO threshold */ \ - .rft = _rft, \ - /* std. mode operation */ \ - .clk_freq = clk, \ - .sm = _sm, \ -} -/* - * The board uses TODO <3> i2c controllers, initialize all of - * them with slave data setup time of 250 ns, - * Tx & Rx FIFO threshold values as 1 and standard - * mode of operation - */ - -U5500_I2C_CONTROLLER(2, 0xe, 1, 1, 400000, I2C_FREQ_MODE_FAST); - -static struct lm3530_platform_data u5500_als_platform_data = { - .mode = LM3530_BL_MODE_MANUAL, - .als_input_mode = LM3530_INPUT_ALS1, - .max_current = LM3530_FS_CURR_26mA, - .pwm_pol_hi = true, - .als_avrg_time = LM3530_ALS_AVRG_TIME_512ms, - .brt_ramp_law = 1, /* Linear */ - .brt_ramp_fall = LM3530_RAMP_TIME_8s, - .brt_ramp_rise = LM3530_RAMP_TIME_8s, - .als1_resistor_sel = LM3530_ALS_IMPD_13_53kOhm, - .als2_resistor_sel = LM3530_ALS_IMPD_Z, - .als_vmin = 730, /* mV */ - .als_vmax = 1020, /* mV */ - .brt_val = 0x7F, /* Max brightness */ -}; - -static struct i2c_board_info __initdata u5500_i2c2_devices[] = { - { - /* Backlight */ - I2C_BOARD_INFO("lm3530-led", 0x36), - .platform_data = &u5500_als_platform_data, - }, -}; - -static void __init u5500_i2c_init(struct device *parent) -{ - db5500_add_i2c2(parent, &u5500_i2c2_data); - i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices)); -} - -static struct ab5500_platform_data ab5500_plf_data = { - .irq = { - .base = 0, - .count = 0, - }, - .init_settings = NULL, - .init_settings_sz = 0, - .pm_power_off = false, -}; - -static struct platform_device ab5500_device = { - .name = "ab5500-core", - .id = 0, - .dev = { - .platform_data = &ab5500_plf_data, - }, - .num_resources = 0, -}; - -static struct platform_device *u5500_platform_devices[] __initdata = { - &ab5500_device, -}; - -static void __init u5500_uart_init(struct device *parent) -{ - db5500_add_uart0(parent, NULL); - db5500_add_uart1(parent, NULL); - db5500_add_uart2(parent, NULL); -} - -static void __init u5500_init_machine(void) -{ - struct device *parent = NULL; - int i; - - parent = u5500_init_devices(); - nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins)); - - u5500_i2c_init(parent); - u5500_sdi_init(parent); - u5500_uart_init(parent); - - for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++) - u5500_platform_devices[i]->dev.parent = parent; - - platform_add_devices(u5500_platform_devices, - ARRAY_SIZE(u5500_platform_devices)); -} - -MACHINE_START(U5500, "ST-Ericsson U5500 Platform") - .atag_offset = 0x100, - .map_io = u5500_map_io, - .init_irq = ux500_init_irq, - .timer = &ux500_timer, - .handle_irq = gic_handle_irq, - .init_machine = u5500_init_machine, -MACHINE_END diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 77a75ed0df67..df91344aa2db 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -36,9 +36,7 @@ static int __init ux500_l2x0_unlock(void) static int __init ux500_l2x0_init(void) { - if (cpu_is_u5500()) - l2x0_base = __io_address(U5500_L2CC_BASE); - else if (cpu_is_u8500()) + if (cpu_is_u8500()) l2x0_base = __io_address(U8500_L2CC_BASE); else ux500_unknown_soc(); diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index ec35f0aa5665..9feb6bc7f20e 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -149,9 +149,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) unsigned long mturate; unsigned long retclk; - if (cpu_is_u5500()) - addr = __io_address(U5500_PRCMU_BASE); - else if (cpu_is_u8500()) + if (cpu_is_u8500()) addr = __io_address(U8500_PRCMU_BASE); else ux500_unknown_soc(); @@ -705,14 +703,6 @@ late_initcall(clk_init_smp_twd_cpufreq); int __init clk_init(void) { - if (cpu_is_u5500()) { - /* Clock tree for U5500 not implemented yet */ - clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; - clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; - clk_uartclk.rate = 36360000; - clk_sdmmcclk.rate = 99900000; - } - clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); clkdev_add(&clk_smp_twd_lookup); diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c deleted file mode 100644 index bca47f32082f..000000000000 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <linux/io.h> -#include <linux/irq.h> - -#include <asm/mach/map.h> -#include <asm/pmu.h> - -#include <plat/gpio-nomadik.h> - -#include <mach/hardware.h> -#include <mach/devices.h> -#include <mach/setup.h> -#include <mach/irqs.h> -#include <mach/usb.h> - -#include "devices-db5500.h" -#include "ste-dma40-db5500.h" - -static struct map_desc u5500_uart_io_desc[] __initdata = { - __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K), -}; - -static struct map_desc u5500_io_desc[] __initdata = { - /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ - __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K), - __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K), - __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K), - - __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K), - __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K), - __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), - __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K), -}; - -static struct resource mbox0_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX0_PEER_START, - .end = U5500_MBOX0_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX0_LOCAL_START, - .end = U5500_MBOX0_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR0_VIRT_IRQ, - .end = MBOX_PAIR0_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource mbox1_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX1_PEER_START, - .end = U5500_MBOX1_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX1_LOCAL_START, - .end = U5500_MBOX1_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR1_VIRT_IRQ, - .end = MBOX_PAIR1_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource mbox2_resources[] = { - { - .name = "mbox_peer", - .start = U5500_MBOX2_PEER_START, - .end = U5500_MBOX2_PEER_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_local", - .start = U5500_MBOX2_LOCAL_START, - .end = U5500_MBOX2_LOCAL_END, - .flags = IORESOURCE_MEM, - }, - { - .name = "mbox_irq", - .start = MBOX_PAIR2_VIRT_IRQ, - .end = MBOX_PAIR2_VIRT_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device mbox0_device = { - .id = 0, - .name = "mbox", - .resource = mbox0_resources, - .num_resources = ARRAY_SIZE(mbox0_resources), -}; - -static struct platform_device mbox1_device = { - .id = 1, - .name = "mbox", - .resource = mbox1_resources, - .num_resources = ARRAY_SIZE(mbox1_resources), -}; - -static struct platform_device mbox2_device = { - .id = 2, - .name = "mbox", - .resource = mbox2_resources, - .num_resources = ARRAY_SIZE(mbox2_resources), -}; - -static struct platform_device *db5500_platform_devs[] __initdata = { - &mbox0_device, - &mbox1_device, - &mbox2_device, -}; - -static resource_size_t __initdata db5500_gpio_base[] = { - U5500_GPIOBANK0_BASE, - U5500_GPIOBANK1_BASE, - U5500_GPIOBANK2_BASE, - U5500_GPIOBANK3_BASE, - U5500_GPIOBANK4_BASE, - U5500_GPIOBANK5_BASE, - U5500_GPIOBANK6_BASE, - U5500_GPIOBANK7_BASE, -}; - -static void __init db5500_add_gpios(struct device *parent) -{ - struct nmk_gpio_platform_data pdata = { - /* No custom data yet */ - }; - - dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base), - IRQ_DB5500_GPIO0, &pdata); -} - -void __init u5500_map_io(void) -{ - /* - * Map the UARTs early so that the DEBUG_LL stuff continues to work. - */ - iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc)); - - ux500_map_io(); - - iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); - - _PRCMU_BASE = __io_address(U5500_PRCMU_BASE); -} - -static void __init db5500_pmu_init(void) -{ - struct resource res[] = { - [0] = { - .start = IRQ_DB5500_PMU0, - .end = IRQ_DB5500_PMU0, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = IRQ_DB5500_PMU1, - .end = IRQ_DB5500_PMU1, - .flags = IORESOURCE_IRQ, - }, - }; - - platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU, - res, ARRAY_SIZE(res)); -} - -static int usb_db5500_rx_dma_cfg[] = { - DB5500_DMA_DEV4_USB_OTG_IEP_1_9, - DB5500_DMA_DEV5_USB_OTG_IEP_2_10, - DB5500_DMA_DEV6_USB_OTG_IEP_3_11, - DB5500_DMA_DEV20_USB_OTG_IEP_4_12, - DB5500_DMA_DEV21_USB_OTG_IEP_5_13, - DB5500_DMA_DEV22_USB_OTG_IEP_6_14, - DB5500_DMA_DEV23_USB_OTG_IEP_7_15, - DB5500_DMA_DEV38_USB_OTG_IEP_8 -}; - -static int usb_db5500_tx_dma_cfg[] = { - DB5500_DMA_DEV4_USB_OTG_OEP_1_9, - DB5500_DMA_DEV5_USB_OTG_OEP_2_10, - DB5500_DMA_DEV6_USB_OTG_OEP_3_11, - DB5500_DMA_DEV20_USB_OTG_OEP_4_12, - DB5500_DMA_DEV21_USB_OTG_OEP_5_13, - DB5500_DMA_DEV22_USB_OTG_OEP_6_14, - DB5500_DMA_DEV23_USB_OTG_OEP_7_15, - DB5500_DMA_DEV38_USB_OTG_OEP_8 -}; - -static const char *db5500_read_soc_id(void) -{ - return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n"); -} - -static struct device * __init db5500_soc_device_init(void) -{ - const char *soc_id = db5500_read_soc_id(); - - return ux500_soc_device_init(soc_id); -} - -struct device * __init u5500_init_devices(void) -{ - struct device *parent; - int i; - - parent = db5500_soc_device_init(); - - db5500_add_gpios(parent); - db5500_pmu_init(); - db5500_dma_init(parent); - db5500_add_rtc(parent); - db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); - - for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++) - db5500_platform_devs[i]->dev.parent = parent; - - platform_add_devices(db5500_platform_devs, - ARRAY_SIZE(db5500_platform_devs)); - - return parent; -} diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index d11f3892a27d..4b4e59b30d81 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -10,7 +10,6 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/mfd/db8500-prcmu.h> -#include <linux/mfd/db5500-prcmu.h> #include <linux/clksrc-dbx500-prcmu.h> #include <linux/sys_soc.h> #include <linux/err.h> @@ -40,10 +39,7 @@ void __init ux500_init_irq(void) void __iomem *dist_base; void __iomem *cpu_base; - if (cpu_is_u5500()) { - dist_base = __io_address(U5500_GIC_DIST_BASE); - cpu_base = __io_address(U5500_GIC_CPU_BASE); - } else if (cpu_is_u8500()) { + if (cpu_is_u8500()) { dist_base = __io_address(U8500_GIC_DIST_BASE); cpu_base = __io_address(U8500_GIC_CPU_BASE); } else @@ -60,8 +56,6 @@ void __init ux500_init_irq(void) * Init clocks here so that they are available for system timer * initialization. */ - if (cpu_is_u5500()) - db5500_prcmu_early_init(); if (cpu_is_u8500()) db8500_prcmu_early_init(); clk_init(); diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h deleted file mode 100644 index e70955502c35..000000000000 --- a/arch/arm/mach-ux500/devices-db5500.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __DEVICES_DB5500_H -#define __DEVICES_DB5500_H - -#include "devices-common.h" - -#define db5500_add_i2c1(parent, pdata) \ - dbx500_add_i2c(parent, 1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata) -#define db5500_add_i2c2(parent, pdata) \ - dbx500_add_i2c(parent, 2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata) -#define db5500_add_i2c3(parent, pdata) \ - dbx500_add_i2c(parent, 3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata) - -#define db5500_add_msp0_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \ - IRQ_DB5500_MSP0, pdata) -#define db5500_add_msp1_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \ - IRQ_DB5500_MSP1, pdata) -#define db5500_add_msp2_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \ - IRQ_DB5500_MSP2, pdata) - -#define db5500_add_msp0_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \ - IRQ_DB5500_MSP0, pdata) -#define db5500_add_msp1_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \ - IRQ_DB5500_MSP1, pdata) -#define db5500_add_msp2_spi(parent, pdata) \ - dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \ - IRQ_DB5500_MSP2, pdata) - -#define db5500_add_rtc(parent) \ - dbx500_add_rtc(parent, U5500_RTC_BASE, IRQ_DB5500_RTC); - -#define db5500_add_usb(parent, rx_cfg, tx_cfg) \ - ux500_add_usb(parent, U5500_USBOTG_BASE, \ - IRQ_DB5500_USBOTG, rx_cfg, tx_cfg) - -#define db5500_add_sdi0(parent, pdata) \ - dbx500_add_sdi(parent, "sdi0", U5500_SDI0_BASE, \ - IRQ_DB5500_SDMMC0, pdata, \ - 0x10480180) -#define db5500_add_sdi1(parent, pdata) \ - dbx500_add_sdi(parent, "sdi1", U5500_SDI1_BASE, \ - IRQ_DB5500_SDMMC1, pdata, \ - 0x10480180) -#define db5500_add_sdi2(parent, pdata) \ - dbx500_add_sdi(parent, "sdi2", U5500_SDI2_BASE, \ - IRQ_DB5500_SDMMC2, pdata \ - 0x10480180) -#define db5500_add_sdi3(parent, pdata) \ - dbx500_add_sdi(parent, "sdi3", U5500_SDI3_BASE, \ - IRQ_DB5500_SDMMC3, pdata \ - 0x10480180) -#define db5500_add_sdi4(parent, pdata) \ - dbx500_add_sdi(parent, "sdi4", U5500_SDI4_BASE, \ - IRQ_DB5500_SDMMC4, pdata \ - 0x10480180) - -/* This one has a bad peripheral ID in the U5500 silicon */ -#define db5500_add_spi0(parent, pdata) \ - dbx500_add_spi(parent, "spi0", U5500_SPI0_BASE, \ - IRQ_DB5500_SPI0, pdata, \ - 0x10080023) -#define db5500_add_spi1(parent, pdata) \ - dbx500_add_spi(parent, "spi1", U5500_SPI1_BASE, \ - IRQ_DB5500_SPI1, pdata, \ - 0x10080023) -#define db5500_add_spi2(parent, pdata) \ - dbx500_add_spi(parent, "spi2", U5500_SPI2_BASE, \ - IRQ_DB5500_SPI2, pdata \ - 0x10080023) -#define db5500_add_spi3(parent, pdata) \ - dbx500_add_spi(parent, "spi3", U5500_SPI3_BASE, \ - IRQ_DB5500_SPI3, pdata \ - 0x10080023) - -#define db5500_add_uart0(parent, plat) \ - dbx500_add_uart(parent, "uart0", U5500_UART0_BASE, \ - IRQ_DB5500_UART0, plat) -#define db5500_add_uart1(parent, plat) \ - dbx500_add_uart(parent, "uart1", U5500_UART1_BASE, \ - IRQ_DB5500_UART1, plat) -#define db5500_add_uart2(parent, plat) \ - dbx500_add_uart(parent, "uart2", U5500_UART2_BASE, \ - IRQ_DB5500_UART2, plat) -#define db5500_add_uart3(parent, plat) \ - dbx500_add_uart(parent, "uart3", U5500_UART3_BASE, \ - IRQ_DB5500_UART3, plat) - -#endif diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c deleted file mode 100644 index 41e9470fa0e6..000000000000 --- a/arch/arm/mach-ux500/dma-db5500.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson - * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson - * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson - * - * License terms: GNU General Public License (GPL), version 2 - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <plat/ste_dma40.h> -#include <mach/setup.h> -#include <mach/hardware.h> - -#include "ste-dma40-db5500.h" - -static struct resource dma40_resources[] = { - [0] = { - .start = U5500_DMA_BASE, - .end = U5500_DMA_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - .name = "base", - }, - [1] = { - .start = U5500_DMA_LCPA_BASE, - .end = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - .name = "lcpa", - }, - [2] = { - .start = IRQ_DB5500_DMA, - .end = IRQ_DB5500_DMA, - .flags = IORESOURCE_IRQ - } -}; - -/* Default configuration for physical memcpy */ -static struct stedma40_chan_cfg dma40_memcpy_conf_phy = { - .mode = STEDMA40_MODE_PHYSICAL, - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_PHY_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_PHY_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; - -/* Default configuration for logical memcpy */ -static struct stedma40_chan_cfg dma40_memcpy_conf_log = { - .dir = STEDMA40_MEM_TO_MEM, - - .src_info.data_width = STEDMA40_BYTE_WIDTH, - .src_info.psize = STEDMA40_PSIZE_LOG_1, - .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, - - .dst_info.data_width = STEDMA40_BYTE_WIDTH, - .dst_info.psize = STEDMA40_PSIZE_LOG_1, - .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, -}; - -/* - * Mapping between soruce event lines and physical device address This was - * created assuming that the event line is tied to a device and therefore the - * address is constant, however this is not true for at least USB, and the - * values are just placeholders for USB. This table is preserved and used for - * now. - */ -static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = { - [DB5500_DMA_DEV24_SDMMC0_RX] = -1, - [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1, - [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1, - [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1, - [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1, - [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1, - [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1, - [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1, - [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1, -}; - -/* Mapping between destination event lines and physical device address */ -static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = { - [DB5500_DMA_DEV24_SDMMC0_TX] = -1, - [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1, - [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1, - [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1, - [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1, - [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1, - [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1, - [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1, - [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1, -}; - -static int dma40_memcpy_event[] = { - DB5500_DMA_MEMCPY_TX_1, - DB5500_DMA_MEMCPY_TX_2, - DB5500_DMA_MEMCPY_TX_3, - DB5500_DMA_MEMCPY_TX_4, - DB5500_DMA_MEMCPY_TX_5, -}; - -static struct stedma40_platform_data dma40_plat_data = { - .dev_len = ARRAY_SIZE(dma40_rx_map), - .dev_rx = dma40_rx_map, - .dev_tx = dma40_tx_map, - .memcpy = dma40_memcpy_event, - .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), - .memcpy_conf_phy = &dma40_memcpy_conf_phy, - .memcpy_conf_log = &dma40_memcpy_conf_log, - .disabled_channels = {-1}, -}; - -static struct platform_device dma40_device = { - .dev = { - .platform_data = &dma40_plat_data, - }, - .name = "dma40", - .id = 0, - .num_resources = ARRAY_SIZE(dma40_resources), - .resource = dma40_resources -}; - -void __init db5500_dma_init(struct device *parent) -{ - int ret; - - dma40_device.dev.parent = parent; - ret = platform_device_register(&dma40_device); - if (ret) - dev_err(&dma40_device.dev, "unable to register device: %d\n", ret); - -} diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h deleted file mode 100644 index 8e714bcb099f..000000000000 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_DB5500_REGS_H -#define __MACH_DB5500_REGS_H - -#define U5500_PER1_BASE 0xA0020000 -#define U5500_PER2_BASE 0xA0010000 -#define U5500_PER3_BASE 0x80140000 -#define U5500_PER4_BASE 0x80150000 -#define U5500_PER5_BASE 0x80100000 -#define U5500_PER6_BASE 0x80120000 - -#define U5500_GIC_DIST_BASE 0xA0411000 -#define U5500_GIC_CPU_BASE 0xA0410100 -#define U5500_DMA_BASE 0x90030000 -#define U5500_STM_BASE 0x90020000 -#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000) -#define U5500_MCDE_BASE 0xA0400000 -#define U5500_MODEM_BASE 0xB0000000 -#define U5500_L2CC_BASE 0xA0412000 -#define U5500_SCU_BASE 0xA0410000 -#define U5500_DSI1_BASE 0xA0401000 -#define U5500_DSI2_BASE 0xA0402000 -#define U5500_SIA_BASE 0xA0100000 -#define U5500_SVA_BASE 0x80200000 -#define U5500_HSEM_BASE 0xA0000000 -#define U5500_NAND0_BASE 0x60000000 -#define U5500_NAND1_BASE 0x70000000 -#define U5500_TWD_BASE 0xa0410600 -#define U5500_ICN_BASE 0xA0040000 -#define U5500_B2R2_BASE 0xa0200000 -#define U5500_BOOT_ROM_BASE 0x90000000 - -#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) -#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) -#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000) -#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000) -#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000) -#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000) -#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000) -#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000) - -#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000) -#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000) -#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000) - -#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000) -#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000) -#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000) -#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000) - -#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000) -#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000) -#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000) -#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000) -#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000) -#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) -#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) -#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) -#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338) -#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) -#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) -#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) -#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000) -#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) -#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000) -#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000) -#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000) - -#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) -#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) -#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000) -#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000) -#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000) -#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000) -#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000) -#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000) -#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000) -#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000) -#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000) -#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000) -#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000) -#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000) -#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000) -#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000) -#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000) - -#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000) -#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) -#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) -#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) -#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100) -#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) -#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) -#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) -#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000) -#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000) -#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000) - -#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE -#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80) -#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE -#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE -#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE -#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE -#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) -#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) - -#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000) -#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40) -#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F) -#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60) -#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F) -#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80) -#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F) -#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0) -#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF) -#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00) -#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F) -#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) -#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) - -#define U5500_ACCCON_BASE_SEC (0xBFFF0000) -#define U5500_ACCCON_BASE (0xBFFF1000) -#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020) -#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC) -#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4) - -#define U5500_ESRAM_BASE 0x40000000 -#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 -#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) - -#define U5500_MCDE_SIZE 0x1000 -#define U5500_DSI_LINK_SIZE 0x1000 -#define U5500_DSI_LINK_COUNT 0x2 -#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE) -#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE) - -#endif diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index 8d74d927d4e2..67035223334a 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S @@ -20,10 +20,6 @@ * built, so that there's some hint during the build that something is wrong. */ -#ifdef CONFIG_UX500_SOC_DB5500 -#define __UX500_UART(n) U5500_UART##n##_BASE -#endif - #ifdef CONFIG_UX500_SOC_DB8500 #define __UX500_UART(n) U8500_UART##n##_BASE #endif diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index 5f6cb71fc62d..9b5eb69a0154 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -10,7 +10,6 @@ struct platform_device; struct amba_device; -extern struct platform_device u5500_gpio_devs[]; extern struct platform_device u8500_gpio_devs[]; extern struct amba_device ux500_pl031_device; diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index f84698936d36..cf6fac3d1eeb 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -28,7 +28,6 @@ #define io_p2v(n) __io_address(n) #include <mach/db8500-regs.h> -#include <mach/db5500-regs.h> #define MSP_TX_RX_REG_OFFSET 0 diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h deleted file mode 100644 index 29d972c7717b..000000000000 --- a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_BOARD_U5500_H -#define __MACH_IRQS_BOARD_U5500_H - -#define AB5500_NR_IRQS 5 -#define IRQ_AB5500_BASE IRQ_BOARD_START -#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS) - -#define U5500_IRQ_END IRQ_AB5500_END - -#if IRQ_BOARD_END < U5500_IRQ_END -#undef IRQ_BOARD_END -#define IRQ_BOARD_END U5500_IRQ_END -#endif - -#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h deleted file mode 100644 index 77239776a6f2..000000000000 --- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_IRQS_DB5500_H -#define __MACH_IRQS_DB5500_H - -#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4) -#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6) -#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7) -#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8) -#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9) -#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10) -#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11) -#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12) -#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13) -#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14) -#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15) -#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16) -#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17) -#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18) -#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19) -#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20) -#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21) -#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22) -#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23) -#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24) -#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25) -#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26) -#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27) -#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28) -#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29) -#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30) -#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31) -#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33) -#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34) -#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35) -#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36) -#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37) -#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38) -#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39) -#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40) -#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41) -#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42) -#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43) -#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44) -#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45) -#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46) -#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47) -#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48) -#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50) -#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52) -#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53) -#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55) -#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56) -#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57) -#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59) -#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) -#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) -#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) -#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65) -#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) -#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) -#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) -#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108) -#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109) -#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110) -#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112) -#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113) -#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114) -#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115) -#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116) -#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118) -#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119) -#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120) -#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121) -#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122) -#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123) -#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124) -#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125) -#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126) - -#ifdef CONFIG_UX500_SOC_DB5500 - -/* - * After the GPIO ones we reserve a range of IRQ:s in which virtual - * IRQ:s representing modem IRQ:s can be allocated - */ -#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START -#define IRQ_MODEM_EVENTS_NBR 72 -#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR) - -/* List of virtual IRQ:s that are allocated from the range above */ -#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43) -#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45) -#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41) - -/* - * We may have several SoCs, but only one will run at a - * time, so the one with most IRQs will bump this ahead, - * but the IRQ_SOC_START remains the same for either SoC. - */ -#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END -#undef IRQ_SOC_END -#define IRQ_SOC_END IRQ_MODEM_EVENTS_END -#endif - -#endif /* CONFIG_UX500_SOC_DB5500 */ - -#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index c23a6b5f0c4e..d06dcf6208fa 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -36,7 +36,6 @@ /* This will be overridden by SoC-specific irq headers */ #define IRQ_SOC_END IRQ_SOC_START -#include <mach/irqs-db5500.h> #include <mach/irqs-db8500.h> #define IRQ_BOARD_START IRQ_SOC_END @@ -47,10 +46,6 @@ #include <mach/irqs-board-mop500.h> #endif -#ifdef CONFIG_MACH_U5500 -#include <mach/irqs-board-u5500.h> -#endif - #define NR_IRQS IRQ_BOARD_END #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h deleted file mode 100644 index 7f9da4d2fbda..000000000000 --- a/arch/arm/mach-ux500/include/mach/mbox-db5500.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __INC_STE_MBOX_H -#define __INC_STE_MBOX_H - -#define MBOX_BUF_SIZE 16 -#define MBOX_NAME_SIZE 8 - -/** - * mbox_recv_cb_t - Definition of the mailbox callback. - * @mbox_msg: The mailbox message. - * @priv: The clients private data as specified in the call to mbox_setup. - * - * This function will be called upon reception of new mailbox messages. - */ -typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv); - -/** - * struct mbox - Mailbox instance struct - * @list: Linked list head. - * @pdev: Pointer to device struct. - * @cb: Callback function. Will be called - * when new data is received. - * @client_data: Clients private data. Will be sent back - * in the callback function. - * @virtbase_peer: Virtual address for outgoing mailbox. - * @virtbase_local: Virtual address for incoming mailbox. - * @buffer: Then internal queue for outgoing messages. - * @name: Name of this mailbox. - * @buffer_available: Completion variable to achieve "blocking send". - * This variable will be signaled when there is - * internal buffer space available. - * @client_blocked: To keep track if any client is currently - * blocked. - * @lock: Spinlock to protect this mailbox instance. - * @write_index: Index in internal buffer to write to. - * @read_index: Index in internal buffer to read from. - * @allocated: Indicates whether this particular mailbox - * id has been allocated by someone. - */ -struct mbox { - struct list_head list; - struct platform_device *pdev; - mbox_recv_cb_t *cb; - void *client_data; - void __iomem *virtbase_peer; - void __iomem *virtbase_local; - u32 buffer[MBOX_BUF_SIZE]; - char name[MBOX_NAME_SIZE]; - struct completion buffer_available; - u8 client_blocked; - spinlock_t lock; - u8 write_index; - u8 read_index; - bool allocated; -}; - -/** - * mbox_setup - Set up a mailbox and return its instance. - * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU, - * 2 for modem DSP. - * @mbox_cb: Pointer to the callback function to be called when a new message - * is received. - * @priv: Client user data which will be returned in the callback. - * - * Returns a mailbox instance to be specified in subsequent calls to mbox_send. - */ -struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv); - -/** - * mbox_send - Send a mailbox message. - * @mbox: Mailbox instance (returned by mbox_setup) - * @mbox_msg: The mailbox message to send. - * @block: Specifies whether this call will block until send is possible, - * or return an error if the mailbox buffer is full. - * - * Returns 0 on success or a negative error code on error. -ENOMEM indicates - * that the internal buffer is full and you have to try again later (or - * specify "block" in order to block until send is possible). - */ -int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block); - -#endif /*INC_STE_MBOX_H*/ diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index 3dc00ffa7bfa..4e369f1645ec 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -15,18 +15,12 @@ #include <linux/init.h> void __init ux500_map_io(void); -extern void __init u5500_map_io(void); extern void __init u8500_map_io(void); -extern struct device * __init u5500_init_devices(void); extern struct device * __init u8500_init_devices(void); extern void __init ux500_init_irq(void); -extern void __init u5500_sdi_init(struct device *parent); - -extern void __init db5500_dma_init(struct device *parent); - extern struct device *ux500_soc_device_init(const char *soc_id); struct amba_device; diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 6fb3c4b0105d..34775baadaea 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -50,11 +50,8 @@ static void flush(void) static inline void arch_decomp_setup(void) { - /* Check in run time if we run on an U8500 or U5500 */ - if (machine_is_u5500()) - ux500_uart_base = U5500_UART0_BASE; - else - ux500_uart_base = U8500_UART2_BASE; + /* Use machine_is_foo() macro if you need to switch base someday */ + ux500_uart_base = U8500_UART2_BASE; } #define arch_decomp_wdog() /* nothing to do here */ diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c deleted file mode 100644 index 2b2d51caf9d8..000000000000 --- a/arch/arm/mach-ux500/mbox-db5500.c +++ /dev/null @@ -1,565 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -/* - * Mailbox nomenclature: - * - * APE MODEM - * mbox pairX - * .......................... - * . . - * . peer . - * . send ---- . - * . --> | | . - * . | | . - * . ---- . - * . . - * . local . - * . rec ---- . - * . | | <-- . - * . | | . - * . ---- . - * ......................... - */ - -#include <linux/init.h> -#include <linux/module.h> -#include <linux/device.h> -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <linux/completion.h> -#include <mach/mbox-db5500.h> - -#define MBOX_NAME "mbox" - -#define MBOX_FIFO_DATA 0x000 -#define MBOX_FIFO_ADD 0x004 -#define MBOX_FIFO_REMOVE 0x008 -#define MBOX_FIFO_THRES_FREE 0x00C -#define MBOX_FIFO_THRES_OCCUP 0x010 -#define MBOX_FIFO_STATUS 0x014 - -#define MBOX_DISABLE_IRQ 0x4 -#define MBOX_ENABLE_IRQ 0x0 -#define MBOX_LATCH 1 - -/* Global list of all mailboxes */ -static struct list_head mboxs = LIST_HEAD_INIT(mboxs); - -static struct mbox *get_mbox_with_id(u8 id) -{ - u8 i; - struct list_head *pos = &mboxs; - for (i = 0; i <= id; i++) - pos = pos->next; - - return (struct mbox *) list_entry(pos, struct mbox, list); -} - -int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block) -{ - int res = 0; - - spin_lock(&mbox->lock); - - dev_dbg(&(mbox->pdev->dev), - "About to buffer 0x%X to mailbox 0x%X." - " ri = %d, wi = %d\n", - mbox_msg, (u32)mbox, mbox->read_index, - mbox->write_index); - - /* Check if write buffer is full */ - while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) { - if (!block) { - dev_dbg(&(mbox->pdev->dev), - "Buffer full in non-blocking call! " - "Returning -ENOMEM!\n"); - res = -ENOMEM; - goto exit; - } - spin_unlock(&mbox->lock); - dev_dbg(&(mbox->pdev->dev), - "Buffer full in blocking call! Sleeping...\n"); - mbox->client_blocked = 1; - wait_for_completion(&mbox->buffer_available); - dev_dbg(&(mbox->pdev->dev), - "Blocking send was woken up! Trying again...\n"); - spin_lock(&mbox->lock); - } - - mbox->buffer[mbox->write_index] = mbox_msg; - mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE; - - /* - * Indicate that we want an IRQ as soon as there is a slot - * in the FIFO - */ - writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - -exit: - spin_unlock(&mbox->lock); - return res; -} -EXPORT_SYMBOL(mbox_send); - -#if defined(CONFIG_DEBUG_FS) -/* - * Expected input: <value> <nbr sends> - * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times - */ -static ssize_t mbox_write_fifo(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t count) -{ - unsigned long mbox_mess; - unsigned long nbr_sends; - unsigned long i; - char int_buf[16]; - char *token; - char *val; - - struct mbox *mbox = (struct mbox *) dev->platform_data; - - strncpy((char *) &int_buf, buf, sizeof(int_buf)); - token = (char *) &int_buf; - - /* Parse message */ - val = strsep(&token, " "); - if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0)) - mbox_mess = 0xDEADBEEF; - - val = strsep(&token, " "); - if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0)) - nbr_sends = 1; - - dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n", - mbox_mess, nbr_sends, (u32) mbox); - - for (i = 0; i < nbr_sends; i++) - mbox_send(mbox, mbox_mess, true); - - return count; -} - -static ssize_t mbox_read_fifo(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - int mbox_value; - struct mbox *mbox = (struct mbox *) dev->platform_data; - - if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0) - return sprintf(buf, "Mailbox is empty\n"); - - mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA); - writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE)); - - return sprintf(buf, "0x%X\n", mbox_value); -} - -static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo); - -static int mbox_show(struct seq_file *s, void *data) -{ - struct list_head *pos; - u8 mbox_index = 0; - - list_for_each(pos, &mboxs) { - struct mbox *m = - (struct mbox *) list_entry(pos, struct mbox, list); - if (m == NULL) { - seq_printf(s, - "Unable to retrieve mailbox %d\n", - mbox_index); - continue; - } - - spin_lock(&m->lock); - if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) { - seq_printf(s, "MAILBOX %d not setup or corrupt\n", - mbox_index); - spin_unlock(&m->lock); - continue; - } - - seq_printf(s, - "===========================\n" - " MAILBOX %d\n" - " PEER MAILBOX DUMP\n" - "---------------------------\n" - "FIFO: 0x%X (%d)\n" - "Free Threshold: 0x%.2X (%d)\n" - "Occupied Threshold: 0x%.2X (%d)\n" - "Status: 0x%.2X (%d)\n" - " Free spaces (ot): %d (%d)\n" - " Occup spaces (ot): %d (%d)\n" - "===========================\n" - " LOCAL MAILBOX DUMP\n" - "---------------------------\n" - "FIFO: 0x%.X (%d)\n" - "Free Threshold: 0x%.2X (%d)\n" - "Occupied Threshold: 0x%.2X (%d)\n" - "Status: 0x%.2X (%d)\n" - " Free spaces (ot): %d (%d)\n" - " Occup spaces (ot): %d (%d)\n" - "===========================\n" - "write_index: %d\n" - "read_index : %d\n" - "===========================\n" - "\n", - mbox_index, - readl(m->virtbase_peer + MBOX_FIFO_DATA), - readl(m->virtbase_peer + MBOX_FIFO_DATA), - readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_peer + MBOX_FIFO_STATUS), - readl(m->virtbase_peer + MBOX_FIFO_STATUS), - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7, - (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1, - readl(m->virtbase_local + MBOX_FIFO_DATA), - readl(m->virtbase_local + MBOX_FIFO_DATA), - readl(m->virtbase_local + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_local + MBOX_FIFO_THRES_FREE), - readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP), - readl(m->virtbase_local + MBOX_FIFO_STATUS), - readl(m->virtbase_local + MBOX_FIFO_STATUS), - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7, - (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1, - m->write_index, m->read_index); - mbox_index++; - spin_unlock(&m->lock); - } - - return 0; -} - -static int mbox_open(struct inode *inode, struct file *file) -{ - return single_open(file, mbox_show, NULL); -} - -static const struct file_operations mbox_operations = { - .owner = THIS_MODULE, - .open = mbox_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; -#endif - -static irqreturn_t mbox_irq(int irq, void *arg) -{ - u32 mbox_value; - int nbr_occup; - int nbr_free; - struct mbox *mbox = (struct mbox *) arg; - - spin_lock(&mbox->lock); - - dev_dbg(&(mbox->pdev->dev), - "mbox IRQ [%d] received. ri = %d, wi = %d\n", - irq, mbox->read_index, mbox->write_index); - - /* - * Check if we have any outgoing messages, and if there is space for - * them in the FIFO. - */ - if (mbox->read_index != mbox->write_index) { - /* - * Check by reading FREE for LOCAL since that indicates - * OCCUP for PEER - */ - nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS) - >> 4) & 0x7; - dev_dbg(&(mbox->pdev->dev), - "Status indicates %d empty spaces in the FIFO!\n", - nbr_free); - - while ((nbr_free > 0) && - (mbox->read_index != mbox->write_index)) { - /* Write the message and latch it into the FIFO */ - writel(mbox->buffer[mbox->read_index], - (mbox->virtbase_peer + MBOX_FIFO_DATA)); - writel(MBOX_LATCH, - (mbox->virtbase_peer + MBOX_FIFO_ADD)); - dev_dbg(&(mbox->pdev->dev), - "Wrote message 0x%X to addr 0x%X\n", - mbox->buffer[mbox->read_index], - (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA)); - - nbr_free--; - mbox->read_index = - (mbox->read_index + 1) % MBOX_BUF_SIZE; - } - - /* - * Check if we still want IRQ:s when there is free - * space to send - */ - if (mbox->read_index != mbox->write_index) { - dev_dbg(&(mbox->pdev->dev), - "Still have messages to send, but FIFO full. " - "Request IRQ again!\n"); - writel(MBOX_ENABLE_IRQ, - mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - } else { - dev_dbg(&(mbox->pdev->dev), - "No more messages to send. " - "Do not request IRQ again!\n"); - writel(MBOX_DISABLE_IRQ, - mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - } - - /* - * Check if we can signal any blocked clients that it is OK to - * start buffering again - */ - if (mbox->client_blocked && - (((mbox->write_index + 1) % MBOX_BUF_SIZE) - != mbox->read_index)) { - dev_dbg(&(mbox->pdev->dev), - "Waking up blocked client\n"); - complete(&mbox->buffer_available); - mbox->client_blocked = 0; - } - } - - /* Check if we have any incoming messages */ - nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7; - if (nbr_occup == 0) - goto exit; - - if (mbox->cb == NULL) { - dev_dbg(&(mbox->pdev->dev), "No receive callback registered, " - "leaving %d incoming messages in fifo!\n", nbr_occup); - goto exit; - } - - /* Read and acknowledge the message */ - mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA); - writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE)); - - /* Notify consumer of new mailbox message */ - dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n", - mbox_value); - mbox->cb(mbox_value, mbox->client_data); - -exit: - dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n", - mbox->read_index, mbox->write_index); - spin_unlock(&mbox->lock); - - return IRQ_HANDLED; -} - -/* Setup is executed once for each mbox pair */ -struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv) -{ - struct resource *resource; - int irq; - int res; - struct mbox *mbox; - - mbox = get_mbox_with_id(mbox_id); - if (mbox == NULL) { - dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n", - mbox_id); - goto exit; - } - - /* - * Check if mailbox has been allocated to someone else, - * otherwise allocate it - */ - if (mbox->allocated) { - dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n", - mbox_id); - mbox = NULL; - goto exit; - } - mbox->allocated = true; - - dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n", - mbox_id, (u32)mbox); - - mbox->client_data = priv; - mbox->cb = mbox_cb; - - /* Get addr for peer mailbox and ioremap it */ - resource = platform_get_resource_byname(mbox->pdev, - IORESOURCE_MEM, - "mbox_peer"); - if (resource == NULL) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox peer resource\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "Resource name: %s start: 0x%X, end: 0x%X\n", - resource->name, resource->start, resource->end); - mbox->virtbase_peer = ioremap(resource->start, resource_size(resource)); - if (!mbox->virtbase_peer) { - dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n", - resource->start, resource->end, (u32) mbox->virtbase_peer); - - /* Get addr for local mailbox and ioremap it */ - resource = platform_get_resource_byname(mbox->pdev, - IORESOURCE_MEM, - "mbox_local"); - if (resource == NULL) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox local resource\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "Resource name: %s start: 0x%X, end: 0x%X\n", - resource->name, resource->start, resource->end); - mbox->virtbase_local = ioremap(resource->start, resource_size(resource)); - if (!mbox->virtbase_local) { - dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n"); - mbox = NULL; - goto exit; - } - dev_dbg(&(mbox->pdev->dev), - "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n", - resource->start, resource->end, (u32) mbox->virtbase_peer); - - init_completion(&mbox->buffer_available); - mbox->client_blocked = 0; - - /* Get IRQ for mailbox and allocate it */ - irq = platform_get_irq_byname(mbox->pdev, "mbox_irq"); - if (irq < 0) { - dev_err(&(mbox->pdev->dev), - "Unable to retrieve mbox irq resource\n"); - mbox = NULL; - goto exit; - } - - dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq); - res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox); - if (res < 0) { - dev_err(&(mbox->pdev->dev), - "Unable to allocate mbox irq %d\n", irq); - mbox = NULL; - goto exit; - } - - /* Set up mailbox to not launch IRQ on free space in mailbox */ - writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); - - /* - * Set up mailbox to launch IRQ on new message if we have - * a callback set. If not, do not raise IRQ, but keep message - * in FIFO for manual retrieval - */ - if (mbox_cb != NULL) - writel(MBOX_ENABLE_IRQ, - mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP); - else - writel(MBOX_DISABLE_IRQ, - mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP); - -#if defined(CONFIG_DEBUG_FS) - res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo); - if (res != 0) - dev_warn(&(mbox->pdev->dev), - "Unable to create mbox sysfs entry"); - - (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL, - NULL, &mbox_operations); -#endif - - dev_info(&(mbox->pdev->dev), - "Mailbox driver with index %d initiated!\n", mbox_id); - -exit: - return mbox; -} -EXPORT_SYMBOL(mbox_setup); - - -int __init mbox_probe(struct platform_device *pdev) -{ - struct mbox local_mbox; - struct mbox *mbox; - int res = 0; - dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev); - - memset(&local_mbox, 0x0, sizeof(struct mbox)); - - /* Associate our mbox data with the platform device */ - res = platform_device_add_data(pdev, - (void *) &local_mbox, - sizeof(struct mbox)); - if (res != 0) { - dev_err(&(pdev->dev), - "Unable to allocate driver platform data!\n"); - goto exit; - } - - mbox = (struct mbox *) pdev->dev.platform_data; - mbox->pdev = pdev; - mbox->write_index = 0; - mbox->read_index = 0; - - INIT_LIST_HEAD(&(mbox->list)); - list_add_tail(&(mbox->list), &mboxs); - - sprintf(mbox->name, "%s", MBOX_NAME); - spin_lock_init(&mbox->lock); - - dev_info(&(pdev->dev), "Mailbox driver loaded\n"); - -exit: - return res; -} - -static struct platform_driver mbox_driver = { - .driver = { - .name = MBOX_NAME, - .owner = THIS_MODULE, - }, -}; - -static int __init mbox_init(void) -{ - return platform_driver_probe(&mbox_driver, mbox_probe); -} - -module_init(mbox_init); - -void __exit mbox_exit(void) -{ - platform_driver_unregister(&mbox_driver); -} - -module_exit(mbox_exit); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("MBOX driver"); diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c deleted file mode 100644 index 6b86416c94c9..000000000000 --- a/arch/arm/mach-ux500/modem-irq-db5500.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson. - * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson. - * License terms: GNU General Public License (GPL), version 2. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/slab.h> - -#include <mach/id.h> - -#define MODEM_INTCON_BASE_ADDR 0xBFFD3000 -#define MODEM_INTCON_SIZE 0xFFF - -#define DEST_IRQ41_OFFSET 0x2A4 -#define DEST_IRQ43_OFFSET 0x2AC -#define DEST_IRQ45_OFFSET 0x2B4 - -#define PRIO_IRQ41_OFFSET 0x6A4 -#define PRIO_IRQ43_OFFSET 0x6AC -#define PRIO_IRQ45_OFFSET 0x6B4 - -#define ALLOW_IRQ_OFFSET 0x104 - -#define MODEM_INTCON_CPU_NBR 0x1 -#define MODEM_INTCON_PRIO_HIGH 0x0 - -#define MODEM_INTCON_ALLOW_IRQ41 0x0200 -#define MODEM_INTCON_ALLOW_IRQ43 0x0800 -#define MODEM_INTCON_ALLOW_IRQ45 0x2000 - -#define MODEM_IRQ_REG_OFFSET 0x4 - -struct modem_irq { - void __iomem *modem_intcon_base; -}; - - -static void setup_modem_intcon(void __iomem *modem_intcon_base) -{ - /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */ - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET); - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET); - writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET); - - /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */ - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET); - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET); - writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET); - - /* IC_ALLOW_ARRAY - IRQ enable */ - writel(MODEM_INTCON_ALLOW_IRQ41 | - MODEM_INTCON_ALLOW_IRQ43 | - MODEM_INTCON_ALLOW_IRQ45, - modem_intcon_base + ALLOW_IRQ_OFFSET); -} - -static irqreturn_t modem_cpu_irq_handler(int irq, void *data) -{ - int real_irq; - int virt_irq; - struct modem_irq *mi = (struct modem_irq *)data; - - /* Read modem side IRQ number from modem IRQ controller */ - real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF; - virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq; - - pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X " - "which will be 0x%X (%d) which translates to " - "virtual IRQ 0x%X (%d)!\n", - (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET, - real_irq, - real_irq & 0xFF, - real_irq & 0xFF, - virt_irq, - virt_irq); - - if (virt_irq != 0) - generic_handle_irq(virt_irq); - - pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq); - - return IRQ_HANDLED; -} - -static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) -{ - irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); - - pr_debug("modem_irq: Created virtual IRQ %d\n", irq); -} - -static int modem_irq_init(void) -{ - int err; - static struct irq_chip modem_irq_chip; - struct modem_irq *mi; - - if (!cpu_is_u5500()) - return -ENODEV; - - pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n", - IRQ_DB5500_MODEM); - - mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL); - if (!mi) { - pr_err("modem_irq: Could not allocate device\n"); - return -ENOMEM; - } - - mi->modem_intcon_base = - ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE); - pr_debug("modem_irq: ioremapped modem_intcon_base from " - "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR, - (u32)mi->modem_intcon_base); - - setup_modem_intcon(mi->modem_intcon_base); - - modem_irq_chip = dummy_irq_chip; - modem_irq_chip.name = "modem_irq"; - - /* Create the virtual IRQ:s needed */ - create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip); - create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip); - create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip); - - err = request_threaded_irq(IRQ_DB5500_MODEM, NULL, - modem_cpu_irq_handler, IRQF_ONESHOT, - "modem_irq", mi); - if (err) - pr_err("modem_irq: Could not register IRQ %d\n", - IRQ_DB5500_MODEM); - - return 0; -} - -arch_initcall(modem_irq_init); diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h deleted file mode 100644 index bf50c21fe69d..000000000000 --- a/arch/arm/mach-ux500/pins-db5500.h +++ /dev/null @@ -1,620 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License, version 2 - * Author: Rabin Vincent <rabin.vincent@stericsson.com> - */ - -#ifndef __MACH_DB5500_PINS_H -#define __MACH_DB5500_PINS_H - -#define GPIO0_GPIO PIN_CFG(0, GPIO) -#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A) - -#define GPIO1_GPIO PIN_CFG(1, GPIO) -#define GPIO1_SM_A3 PIN_CFG(1, ALT_A) - -#define GPIO2_GPIO PIN_CFG(2, GPIO) -#define GPIO2_SM_A4 PIN_CFG(2, ALT_A) -#define GPIO2_SM_AVD PIN_CFG(2, ALT_B) - -#define GPIO3_GPIO PIN_CFG(3, GPIO) -#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A) - -#define GPIO4_GPIO PIN_CFG(4, GPIO) -#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A) - -#define GPIO5_GPIO PIN_CFG(5, GPIO) -#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A) -#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B) - -#define GPIO6_GPIO PIN_CFG(6, GPIO) -#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A) -#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B) - -#define GPIO7_GPIO PIN_CFG(7, GPIO) -#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A) -#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B) - -#define GPIO8_GPIO PIN_CFG(8, GPIO) -#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A) -#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B) - -#define GPIO9_GPIO PIN_CFG(9, GPIO) -#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A) -#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B) - -#define GPIO10_GPIO PIN_CFG(10, GPIO) -#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A) -#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B) - -#define GPIO11_GPIO PIN_CFG(11, GPIO) -#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A) -#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B) - -#define GPIO12_GPIO PIN_CFG(12, GPIO) -#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A) -#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B) - -#define GPIO13_GPIO PIN_CFG(13, GPIO) -#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A) -#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B) -#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C) - -#define GPIO14_GPIO PIN_CFG(14, GPIO) -#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A) -#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B) -#define GPIO14_SM_CKO PIN_CFG(14, ALT_C) - -#define GPIO15_GPIO PIN_CFG(15, GPIO) -#define GPIO15_SM_A5 PIN_CFG(15, ALT_A) -#define GPIO15_SM_CLE PIN_CFG(15, ALT_B) - -#define GPIO16_GPIO PIN_CFG(16, GPIO) -#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A) -#define GPIO16_SM_OEn PIN_CFG(16, ALT_B) - -#define GPIO17_GPIO PIN_CFG(17, GPIO) -#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A) -#define GPIO17_SM_WEn PIN_CFG(17, ALT_B) - -#define GPIO18_GPIO PIN_CFG(18, GPIO) -#define GPIO18_SM_A6 PIN_CFG(18, ALT_A) -#define GPIO18_SM_ALE PIN_CFG(18, ALT_B) -#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C) - -#define GPIO19_GPIO PIN_CFG(19, GPIO) -#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A) -#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B) - -#define GPIO20_GPIO PIN_CFG(20, GPIO) -#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A) -#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B) - -#define GPIO21_GPIO PIN_CFG(21, GPIO) -#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A) -#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B) - -#define GPIO22_GPIO PIN_CFG(22, GPIO) -#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A) -#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B) - -#define GPIO23_GPIO PIN_CFG(23, GPIO) -#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A) -#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B) -#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C) - -#define GPIO24_GPIO PIN_CFG(24, GPIO) -#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A) -#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B) -#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C) - -#define GPIO25_GPIO PIN_CFG(25, GPIO) -#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A) -#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B) -#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C) - -#define GPIO26_GPIO PIN_CFG(26, GPIO) -#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A) -#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B) - -#define GPIO27_GPIO PIN_CFG(27, GPIO) -#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A) -#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B) - -#define GPIO28_GPIO PIN_CFG(28, GPIO) -#define GPIO28_U0_TXD PIN_CFG(28, ALT_A) -#define GPIO28_SM_A0 PIN_CFG(28, ALT_B) - -#define GPIO29_GPIO PIN_CFG(29, GPIO) -#define GPIO29_U0_RXD PIN_CFG(29, ALT_A) -#define GPIO29_SM_A1 PIN_CFG(29, ALT_B) -#define GPIO29_PWM_0 PIN_CFG(29, ALT_C) - -#define GPIO30_GPIO PIN_CFG(30, GPIO) -#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) -#define GPIO30_SM_A2 PIN_CFG(30, ALT_B) -#define GPIO30_PWM_1 PIN_CFG(30, ALT_C) - -#define GPIO31_GPIO PIN_CFG(31, GPIO) -#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A) -#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B) -#define GPIO31_PWM_2 PIN_CFG(31, ALT_C) - -#define GPIO32_GPIO PIN_CFG(32, GPIO) -#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A) -#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B) - -#define GPIO33_GPIO PIN_CFG(33, GPIO) -#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A) -#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B) - -#define GPIO34_GPIO PIN_CFG(34, GPIO) -#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A) -#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B) - -#define GPIO35_GPIO PIN_CFG(35, GPIO) -#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A) -#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B) - -#define GPIO64_GPIO PIN_CFG(64, GPIO) -#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A) -#define GPIO64_U0_TXD PIN_CFG(64, ALT_B) - -#define GPIO65_GPIO PIN_CFG(65, GPIO) -#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A) -#define GPIO65_U0_RXD PIN_CFG(65, ALT_B) - -#define GPIO66_GPIO PIN_CFG(66, GPIO) -#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A) - -#define GPIO67_GPIO PIN_CFG(67, GPIO) -#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A) - -#define GPIO68_GPIO PIN_CFG(68, GPIO) -#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A) - -#define GPIO69_GPIO PIN_CFG(69, GPIO) -#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A) - -#define GPIO70_GPIO PIN_CFG(70, GPIO) -#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A) - -#define GPIO71_GPIO PIN_CFG(71, GPIO) -#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A) - -#define GPIO72_GPIO PIN_CFG(72, GPIO) -#define GPIO72_USB_STP PIN_CFG(72, ALT_A) - -#define GPIO73_GPIO PIN_CFG(73, GPIO) -#define GPIO73_USB_DIR PIN_CFG(73, ALT_A) - -#define GPIO74_GPIO PIN_CFG(74, GPIO) -#define GPIO74_USB_NXT PIN_CFG(74, ALT_A) - -#define GPIO75_GPIO PIN_CFG(75, GPIO) -#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A) - -#define GPIO76_GPIO PIN_CFG(76, GPIO) - -#define GPIO77_GPIO PIN_CFG(77, GPIO) -#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A) - -#define GPIO78_GPIO PIN_CFG(78, GPIO) -#define GPIO78_IRQn PIN_CFG(78, ALT_A) - -#define GPIO79_GPIO PIN_CFG(79, GPIO) -#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A) - -#define GPIO80_GPIO PIN_CFG(80, GPIO) -#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A) - -#define GPIO81_GPIO PIN_CFG(81, GPIO) -#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A) - -#define GPIO82_GPIO PIN_CFG(82, GPIO) -#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A) - -#define GPIO96_GPIO PIN_CFG(96, GPIO) -#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A) -#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B) -#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C) - -#define GPIO97_GPIO PIN_CFG(97, GPIO) -#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A) -#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B) -#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C) - -#define GPIO98_GPIO PIN_CFG(98, GPIO) -#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A) -#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B) -#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C) - -#define GPIO99_GPIO PIN_CFG(99, GPIO) -#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A) -#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B) -#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C) - -#define GPIO100_GPIO PIN_CFG(100, GPIO) -#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A) - -#define GPIO101_GPIO PIN_CFG(101, GPIO) -#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A) - -#define GPIO128_GPIO PIN_CFG(128, GPIO) -#define GPIO128_KP_I0 PIN_CFG(128, ALT_A) -#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B) - -#define GPIO129_GPIO PIN_CFG(129, GPIO) -#define GPIO129_KP_O0 PIN_CFG(129, ALT_A) -#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B) - -#define GPIO130_GPIO PIN_CFG(130, GPIO) -#define GPIO130_KP_I1 PIN_CFG(130, ALT_A) -#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B) - -#define GPIO131_GPIO PIN_CFG(131, GPIO) -#define GPIO131_KP_O1 PIN_CFG(131, ALT_A) -#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B) - -#define GPIO132_GPIO PIN_CFG(132, GPIO) -#define GPIO132_KP_I2 PIN_CFG(132, ALT_A) -#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B) -#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C) - -#define GPIO133_GPIO PIN_CFG(133, GPIO) -#define GPIO133_KP_O2 PIN_CFG(133, ALT_A) -#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B) -#define GPIO133_U0_RXD PIN_CFG(133, ALT_C) - -#define GPIO134_GPIO PIN_CFG(134, GPIO) -#define GPIO134_KP_I3 PIN_CFG(134, ALT_A) -#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B) -#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C) - -#define GPIO135_GPIO PIN_CFG(135, GPIO) -#define GPIO135_KP_O3 PIN_CFG(135, ALT_A) -#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B) -#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C) - -#define GPIO136_GPIO PIN_CFG(136, GPIO) -#define GPIO136_KP_I4 PIN_CFG(136, ALT_A) -#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B) -#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C) - -#define GPIO137_GPIO PIN_CFG(137, GPIO) -#define GPIO137_KP_O4 PIN_CFG(137, ALT_A) -#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B) -#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C) - -#define GPIO138_GPIO PIN_CFG(138, GPIO) -#define GPIO138_KP_I5 PIN_CFG(138, ALT_A) -#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B) -#define GPIO138_U0_TXD PIN_CFG(138, ALT_C) - -#define GPIO139_GPIO PIN_CFG(139, GPIO) -#define GPIO139_KP_O5 PIN_CFG(139, ALT_A) -#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B) -#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C) - -#define GPIO140_GPIO PIN_CFG(140, GPIO) -#define GPIO140_KP_I6 PIN_CFG(140, ALT_A) -#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B) -#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C) - -#define GPIO141_GPIO PIN_CFG(141, GPIO) -#define GPIO141_KP_O6 PIN_CFG(141, ALT_A) -#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B) -#define GPIO141_U0_RXD PIN_CFG(141, ALT_C) - -#define GPIO142_GPIO PIN_CFG(142, GPIO) -#define GPIO142_KP_I7 PIN_CFG(142, ALT_A) -#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B) -#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C) - -#define GPIO143_GPIO PIN_CFG(143, GPIO) -#define GPIO143_KP_O7 PIN_CFG(143, ALT_A) -#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B) -#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C) - -#define GPIO144_GPIO PIN_CFG(144, GPIO) -#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A) -#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B) -#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C) - -#define GPIO145_GPIO PIN_CFG(145, GPIO) -#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A) -#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B) -#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C) - -#define GPIO146_GPIO PIN_CFG(146, GPIO) -#define GPIO146_PWM_0 PIN_CFG(146, ALT_A) -#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B) - -#define GPIO147_GPIO PIN_CFG(147, GPIO) -#define GPIO147_PWM_1 PIN_CFG(147, ALT_A) -#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B) - -#define GPIO148_GPIO PIN_CFG(148, GPIO) -#define GPIO148_PWM_2 PIN_CFG(148, ALT_A) -#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B) - -#define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A) - -#define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A) - -#define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A) - -#define GPIO163_GPIO PIN_CFG(163, GPIO) - -#define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_GPS_START PIN_CFG(164, ALT_A) - -#define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A) -#define GPIO165_U3_RXD PIN_CFG(165, ALT_B) -#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C) - -#define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A) -#define GPIO166_U3_TXD PIN_CFG(166, ALT_B) -#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C) - -#define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A) -#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B) -#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C) - -#define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A) -#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B) -#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C) - -#define GPIO169_GPIO PIN_CFG(169, GPIO) -#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A) -#define GPIO169_DDR_RC PIN_CFG(169, ALT_B) -#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C) - -#define GPIO170_GPIO PIN_CFG(170, GPIO) -#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A) - -#define GPIO171_GPIO PIN_CFG(171, GPIO) -#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A) -#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B) -#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C) - -#define GPIO172_GPIO PIN_CFG(172, GPIO) -#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A) -#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B) -#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C) - -#define GPIO173_GPIO PIN_CFG(173, GPIO) -#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A) -#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B) -#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C) - -#define GPIO174_GPIO PIN_CFG(174, GPIO) -#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A) -#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B) -#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C) - -#define GPIO175_GPIO PIN_CFG(175, GPIO) -#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A) -#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B) -#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C) - -#define GPIO176_GPIO PIN_CFG(176, GPIO) -#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A) -#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B) - -#define GPIO177_GPIO PIN_CFG(177, GPIO) -#define GPIO177_U2_RXD PIN_CFG(177, ALT_A) -#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B) -#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C) - -#define GPIO178_GPIO PIN_CFG(178, GPIO) -#define GPIO178_U2_TXD PIN_CFG(178, ALT_A) -#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B) -#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C) - -#define GPIO179_GPIO PIN_CFG(179, GPIO) -#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A) -#define GPIO179_U3_RXD PIN_CFG(179, ALT_B) -#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C) - -#define GPIO180_GPIO PIN_CFG(180, GPIO) -#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A) -#define GPIO180_U3_TXD PIN_CFG(180, ALT_B) -#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C) - -#define GPIO185_GPIO PIN_CFG(185, GPIO) -#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A) -#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B) - -#define GPIO186_GPIO PIN_CFG(186, GPIO) -#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A) -#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B) - -#define GPIO187_GPIO PIN_CFG(187, GPIO) -#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A) -#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B) - -#define GPIO188_GPIO PIN_CFG(188, GPIO) -#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A) -#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B) - -#define GPIO189_GPIO PIN_CFG(189, GPIO) -#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A) -#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B) - -#define GPIO190_GPIO PIN_CFG(190, GPIO) -#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A) -#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B) - -#define GPIO191_GPIO PIN_CFG(191, GPIO) -#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A) -#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B) -#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C) - -#define GPIO192_GPIO PIN_CFG(192, GPIO) -#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A) -#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B) -#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C) - -#define GPIO193_GPIO PIN_CFG(193, GPIO) -#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A) -#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B) -#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C) - -#define GPIO194_GPIO PIN_CFG(194, GPIO) -#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A) -#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B) -#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C) - -#define GPIO195_GPIO PIN_CFG(195, GPIO) -#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A) -#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B) -#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C) - -#define GPIO196_GPIO PIN_CFG(196, GPIO) -#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A) -#define GPIO196_U0_RXD PIN_CFG(196, ALT_B) -#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C) - -#define GPIO197_GPIO PIN_CFG(197, GPIO) -#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A) -#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B) - -#define GPIO198_GPIO PIN_CFG(198, GPIO) -#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A) - -#define GPIO199_GPIO PIN_CFG(199, GPIO) -#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A) -#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B) - -#define GPIO200_GPIO PIN_CFG(200, GPIO) -#define GPIO200_U1_TXD PIN_CFG(200, ALT_A) -#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B) - -#define GPIO201_GPIO PIN_CFG(201, GPIO) -#define GPIO201_U1_RXD PIN_CFG(201, ALT_A) -#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B) - -#define GPIO202_GPIO PIN_CFG(202, GPIO) -#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A) -#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B) - -#define GPIO203_GPIO PIN_CFG(203, GPIO) -#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A) -#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B) - -#define GPIO204_GPIO PIN_CFG(204, GPIO) -#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A) -#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B) -#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C) - -#define GPIO205_GPIO PIN_CFG(205, GPIO) -#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A) -#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B) -#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C) - -#define GPIO206_GPIO PIN_CFG(206, GPIO) -#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A) -#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B) -#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C) - -#define GPIO207_GPIO PIN_CFG(207, GPIO) -#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A) -#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B) -#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C) - -#define GPIO208_GPIO PIN_CFG(208, GPIO) -#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A) -#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B) -#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C) - -#define GPIO209_GPIO PIN_CFG(209, GPIO) -#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A) -#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B) -#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C) - -#define GPIO210_GPIO PIN_CFG(210, GPIO) -#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A) -#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B) - -#define GPIO211_GPIO PIN_CFG(211, GPIO) -#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A) -#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B) - -#define GPIO212_GPIO PIN_CFG(212, GPIO) -#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A) -#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B) - -#define GPIO213_GPIO PIN_CFG(213, GPIO) -#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A) -#define GPIO213_LCD_DE PIN_CFG(213, ALT_B) -#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C) - -#define GPIO214_GPIO PIN_CFG(214, GPIO) -#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A) -#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B) -#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C) - -#define GPIO215_GPIO PIN_CFG(215, GPIO) -#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A) -#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B) -#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C) - -#define GPIO216_GPIO PIN_CFG(216, GPIO) -#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A) -#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B) - -#define GPIO217_GPIO PIN_CFG(217, GPIO) -#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A) -#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B) -#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C) - -#define GPIO218_GPIO PIN_CFG(218, GPIO) -#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A) -#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B) - -#define GPIO219_GPIO PIN_CFG(219, GPIO) -#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A) -#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B) - -#define GPIO220_GPIO PIN_CFG(220, GPIO) -#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A) -#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B) - -#define GPIO221_GPIO PIN_CFG(221, GPIO) -#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A) -#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B) - -#define GPIO222_GPIO PIN_CFG(222, GPIO) -#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A) -#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B) - -#define GPIO223_GPIO PIN_CFG(223, GPIO) -#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A) -#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B) - -#define GPIO224_GPIO PIN_CFG(224, GPIO) -#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A) -#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B) - -#define GPIO225_GPIO PIN_CFG(225, GPIO) -#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A) -#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B) - -#define GPIO226_GPIO PIN_CFG(226, GPIO) -#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A) -#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B) - -#define GPIO227_GPIO PIN_CFG(227, GPIO) -#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A) -#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B) - -#endif diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index d2058ef8345f..e8cd51aa61e4 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -48,9 +48,7 @@ static void write_pen_release(int val) static void __iomem *scu_base_addr(void) { - if (cpu_is_u5500()) - return __io_address(U5500_SCU_BASE); - else if (cpu_is_u8500()) + if (cpu_is_u8500()) return __io_address(U8500_SCU_BASE); else ux500_unknown_soc(); @@ -99,7 +97,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) */ write_pen_release(cpu_logical_map(cpu)); - gic_raise_softirq(cpumask_of(cpu), 1); + smp_send_reschedule(cpu); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -120,9 +118,7 @@ static void __init wakeup_secondary(void) { void __iomem *backupram; - if (cpu_is_u5500()) - backupram = __io_address(U5500_BACKUPRAM0_BASE); - else if (cpu_is_u8500()) + if (cpu_is_u8500()) backupram = __io_address(U8500_BACKUPRAM0_BASE); else ux500_unknown_soc(); diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h deleted file mode 100644 index cb2110c32858..000000000000 --- a/arch/arm/mach-ux500/ste-dma40-db5500.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - * - * DB5500-SoC-specific configuration for DMA40 - */ - -#ifndef STE_DMA40_DB5500_H -#define STE_DMA40_DB5500_H - -#define DB5500_DMA_NR_DEV 64 - -enum dma_src_dev_type { - DB5500_DMA_DEV0_SPI0_RX = 0, - DB5500_DMA_DEV1_SPI1_RX = 1, - DB5500_DMA_DEV2_SPI2_RX = 2, - DB5500_DMA_DEV3_SPI3_RX = 3, - DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4, - DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5, - DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6, - DB5500_DMA_DEV7_IRDA_RFS = 7, - DB5500_DMA_DEV8_IRDA_FIFO_RX = 8, - DB5500_DMA_DEV9_MSP0_RX = 9, - DB5500_DMA_DEV10_MSP1_RX = 10, - DB5500_DMA_DEV11_MSP2_RX = 11, - DB5500_DMA_DEV12_UART0_RX = 12, - DB5500_DMA_DEV13_UART1_RX = 13, - DB5500_DMA_DEV14_UART2_RX = 14, - DB5500_DMA_DEV15_UART3_RX = 15, - DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16, - DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17, - DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18, - DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19, - DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20, - DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21, - DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22, - DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23, - DB5500_DMA_DEV24_SDMMC0_RX = 24, - DB5500_DMA_DEV25_SDMMC1_RX = 25, - DB5500_DMA_DEV26_SDMMC2_RX = 26, - DB5500_DMA_DEV27_SDMMC3_RX = 27, - DB5500_DMA_DEV28_SDMMC4_RX = 28, - /* 29 - 32 not used */ - DB5500_DMA_DEV33_SDMMC0_RX = 33, - DB5500_DMA_DEV34_SDMMC1_RX = 34, - DB5500_DMA_DEV35_SDMMC2_RX = 35, - DB5500_DMA_DEV36_SDMMC3_RX = 36, - DB5500_DMA_DEV37_SDMMC4_RX = 37, - DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38, - DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39, - DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40, - DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41, - DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42, - DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43, - DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44, - DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45, - /* 46 not used */ - DB5500_DMA_DEV47_MCDE_RX = 47, - DB5500_DMA_DEV48_CRYPTO1_RX = 48, - /* 49, 50 not used */ - DB5500_DMA_DEV49_I2C1_RX = 51, - DB5500_DMA_DEV50_I2C3_RX = 52, - DB5500_DMA_DEV51_I2C2_RX = 53, - /* 54 - 60 not used */ - DB5500_DMA_DEV61_CRYPTO0_RX = 61, - /* 62, 63 not used */ -}; - -enum dma_dest_dev_type { - DB5500_DMA_DEV0_SPI0_TX = 0, - DB5500_DMA_DEV1_SPI1_TX = 1, - DB5500_DMA_DEV2_SPI2_TX = 2, - DB5500_DMA_DEV3_SPI3_TX = 3, - DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4, - DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5, - DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6, - DB5500_DMA_DEV7_IRRC_TX = 7, - DB5500_DMA_DEV8_IRDA_FIFO_TX = 8, - DB5500_DMA_DEV9_MSP0_TX = 9, - DB5500_DMA_DEV10_MSP1_TX = 10, - DB5500_DMA_DEV11_MSP2_TX = 11, - DB5500_DMA_DEV12_UART0_TX = 12, - DB5500_DMA_DEV13_UART1_TX = 13, - DB5500_DMA_DEV14_UART2_TX = 14, - DB5500_DMA_DEV15_UART3_TX = 15, - DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16, - DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17, - DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18, - DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19, - DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20, - DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21, - DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22, - DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23, - DB5500_DMA_DEV24_SDMMC0_TX = 24, - DB5500_DMA_DEV25_SDMMC1_TX = 25, - DB5500_DMA_DEV26_SDMMC2_TX = 26, - DB5500_DMA_DEV27_SDMMC3_TX = 27, - DB5500_DMA_DEV28_SDMMC4_TX = 28, - /* 29 - 31 not used */ - DB5500_DMA_DEV32_FSMC_TX = 32, - DB5500_DMA_DEV33_SDMMC0_TX = 33, - DB5500_DMA_DEV34_SDMMC1_TX = 34, - DB5500_DMA_DEV35_SDMMC2_TX = 35, - DB5500_DMA_DEV36_SDMMC3_TX = 36, - DB5500_DMA_DEV37_SDMMC4_TX = 37, - DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38, - DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39, - DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40, - DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41, - DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42, - DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43, - DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44, - DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45, - /* 46 not used */ - DB5500_DMA_DEV47_STM_TX = 47, - DB5500_DMA_DEV48_CRYPTO1_TX = 48, - DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49, - DB5500_DMA_DEV50_HASH1_TX = 50, - DB5500_DMA_DEV51_I2C1_TX = 51, - DB5500_DMA_DEV52_I2C3_TX = 52, - DB5500_DMA_DEV53_I2C2_TX = 53, - /* 54, 55 not used */ - DB5500_DMA_MEMCPY_TX_1 = 56, - DB5500_DMA_MEMCPY_TX_2 = 57, - DB5500_DMA_MEMCPY_TX_3 = 58, - DB5500_DMA_MEMCPY_TX_4 = 59, - DB5500_DMA_MEMCPY_TX_5 = 60, - DB5500_DMA_DEV61_CRYPTO0_TX = 61, - DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62, - DB5500_DMA_DEV63_HASH0_TX = 63, -}; - -#endif diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index d37df98b5c32..52e55337aa9b 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -18,8 +18,6 @@ #include <mach/irqs.h> #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer, - U5500_TWD_BASE, IRQ_LOCALTIMER); static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, U8500_TWD_BASE, IRQ_LOCALTIMER); @@ -28,8 +26,8 @@ static void __init ux500_twd_init(void) struct twd_local_timer *twd_local_timer; int err; - twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer : - &u8500_twd_local_timer; + /* Use this to switch local timer base if changed in new ASICs */ + twd_local_timer = &u8500_twd_local_timer; if (of_have_populated_dt()) twd_local_timer_of_register(); @@ -48,10 +46,7 @@ static void __init ux500_timer_init(void) void __iomem *mtu_timer_base; void __iomem *prcmu_timer_base; - if (cpu_is_u5500()) { - mtu_timer_base = __io_address(U5500_MTU0_BASE); - prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); - } else if (cpu_is_u8500()) { + if (cpu_is_u8500()) { mtu_timer_base = __io_address(U8500_MTU0_BASE); prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); } else { @@ -70,7 +65,7 @@ static void __init ux500_timer_init(void) * depending on delay which is not yet calibrated. RTC-RTT is in the * always-on powerdomain and is used as clockevent instead of twd when * sleeping. - * The PRCMU timer 4(3 for DB5500) register a clocksource and + * The PRCMU timer 4 register a clocksource and * sched_clock with higher rating then MTU since is always-on. * */ diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7edef9121632..7c8a7d8467bf 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -723,7 +723,7 @@ config CPU_HIGH_VECTOR bool "Select the High exception vector" help Say Y here to select high exception vector(0xFFFF0000~). - The exception vector can be vary depending on the platform + The exception vector can vary depending on the platform design in nommu mode. If your platform needs to select high exception vector, say Y. Otherwise or if you are unsure, say N, and the low exception diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index ff1f7cc11f87..80741992a9fc 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -26,18 +26,23 @@ ENTRY(v6_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR /* - * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). - * The test below covers all the write situations, including Java bytecodes + * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. */ - bic r1, r1, #1 << 11 @ clear bit 11 of FSR +#ifdef CONFIG_ARM_ERRATA_326103 + ldr ip, =0x4107b36 + mrc p15, 0, r3, c0, c0, 0 @ get processor id + teq ip, r3, lsr #4 @ r0 ARM1136? + bne do_DataAbort tst r5, #PSR_J_BIT @ Java? + tsteq r5, #PSR_T_BIT @ Thumb? bne do_DataAbort - do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 - ldreq r3, [r4] @ read aborted ARM instruction + bic r1, r1, #1 << 11 @ clear bit 11 of FSR + ldr r3, [r4] @ read aborted ARM instruction #ifdef CONFIG_CPU_ENDIAN_BE8 - reveq r3, r3 + rev r3, r3 #endif do_ldrd_abort tmp=ip, insn=r3 tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. +#endif b do_DataAbort diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index a53fd2aaa2f4..2a8e380501e8 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -32,6 +32,7 @@ static void __iomem *l2x0_base; static DEFINE_RAW_SPINLOCK(l2x0_lock); static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; +static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; struct l2x0_regs l2x0_saved_regs; @@ -61,12 +62,7 @@ static inline void cache_sync(void) { void __iomem *base = l2x0_base; -#ifdef CONFIG_PL310_ERRATA_753970 - /* write to an unmmapped register */ - writel_relaxed(0, base + L2X0_DUMMY_REG); -#else - writel_relaxed(0, base + L2X0_CACHE_SYNC); -#endif + writel_relaxed(0, base + sync_reg_offset); cache_wait(base + L2X0_CACHE_SYNC, 1); } @@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr) } #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) +static inline void debug_writel(unsigned long val) +{ + if (outer_cache.set_debug) + outer_cache.set_debug(val); +} -#define debug_writel(val) outer_cache.set_debug(val) - -static void l2x0_set_debug(unsigned long val) +static void pl310_set_debug(unsigned long val) { writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); } @@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val) { } -#define l2x0_set_debug NULL +#define pl310_set_debug NULL #endif #ifdef CONFIG_PL310_ERRATA_588369 @@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) else ways = 8; type = "L310"; +#ifdef CONFIG_PL310_ERRATA_753970 + /* Unmapped register. */ + sync_reg_offset = L2X0_DUMMY_REG; +#endif + outer_cache.set_debug = pl310_set_debug; break; case L2X0_CACHE_ID_PART_L210: ways = (aux >> 13) & 0xf; @@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) outer_cache.flush_all = l2x0_flush_all; outer_cache.inv_all = l2x0_inv_all; outer_cache.disable = l2x0_disable; - outer_cache.set_debug = l2x0_set_debug; printk(KERN_INFO "%s cache controller enabled\n", type); printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 9055b5a84ec5..f07467533365 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -320,7 +320,7 @@ retry: */ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); - if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (!(fault & VM_FAULT_ERROR) && flags & FAULT_FLAG_ALLOW_RETRY) { if (fault & VM_FAULT_MAJOR) { tsk->maj_flt++; perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 595079fa9d1d..8f5813bbffb5 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -293,11 +293,11 @@ EXPORT_SYMBOL(pfn_valid); #endif #ifndef CONFIG_SPARSEMEM -static void arm_memory_present(void) +static void __init arm_memory_present(void) { } #else -static void arm_memory_present(void) +static void __init arm_memory_present(void) { struct memblock_region *reg; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index b86f8933ff91..2c7cf2f9c837 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -618,8 +618,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr, } } -static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, - unsigned long phys, const struct mem_type *type) +static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, + unsigned long end, unsigned long phys, const struct mem_type *type) { pud_t *pud = pud_offset(pgd, addr); unsigned long next; diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 6486d2f253cd..d51225f90ae2 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -13,6 +13,7 @@ #include <asm/sections.h> #include <asm/page.h> #include <asm/setup.h> +#include <asm/traps.h> #include <asm/mach/arch.h> #include "mm.h" @@ -39,6 +40,7 @@ void __init sanity_check_meminfo(void) */ void __init paging_init(struct machine_desc *mdesc) { + early_trap_init((void *)CONFIG_VECTORS_BASE); bootmem_init(); } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index f1c8486f7501..c2e2b66f72b5 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -255,6 +255,18 @@ __v7_setup: mcr p15, 0, r5, c10, c2, 0 @ write PRRR mcr p15, 0, r6, c10, c2, 1 @ write NMRR #endif +#ifndef CONFIG_ARM_THUMBEE + mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE + and r0, r0, #(0xf << 12) @ ThumbEE enabled field + teq r0, #(1 << 12) @ check if ThumbEE is present + bne 1f + mov r5, #0 + mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 + mrc p14, 6, r0, c0, c0, 0 @ load TEECR + orr r0, r0, #1 @ set the 1st bit in order to + mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access +1: +#endif adr r5, v7_crval ldmia r5, {r5, r6} #ifdef CONFIG_CPU_ENDIAN_BE8 diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index c7f5169a6a54..36c8989d9de6 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -256,13 +256,13 @@ #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) @@ -270,7 +270,7 @@ #define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) @@ -283,13 +283,13 @@ #define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) @@ -316,7 +316,7 @@ #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) @@ -672,23 +672,23 @@ #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) @@ -698,7 +698,7 @@ #define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) @@ -746,16 +746,16 @@ #define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) +#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) #define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) @@ -766,19 +766,19 @@ #define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) #define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) @@ -786,27 +786,27 @@ #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index 527f8fe3e31b..9761e003bde2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -573,7 +573,7 @@ #define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) #define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) -#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C) +#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL) #define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) @@ -1187,7 +1187,7 @@ #define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) #define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) #define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) -#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL) #define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) #define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) #define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index c0fe2757b695..ed8605f01155 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -9,9 +9,6 @@ obj-m := obj-n := obj- := -# OCPI interconnect support for 1710, 1610 and 5912 -obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o - # omap_device support (OMAP2+ only at the moment) obj-$(CONFIG_ARCH_OMAP2) += omap_device.o obj-$(CONFIG_ARCH_OMAP3) += omap_device.o diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 8506cbb7fea4..62ec5c452792 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -398,32 +398,6 @@ struct clk dummy_ck = { .ops = &clkops_null, }; -#ifdef CONFIG_CPU_FREQ -void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) -{ - unsigned long flags; - - if (!arch_clock || !arch_clock->clk_init_cpufreq_table) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - arch_clock->clk_init_cpufreq_table(table); - spin_unlock_irqrestore(&clockfw_lock, flags); -} - -void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) -{ - unsigned long flags; - - if (!arch_clock || !arch_clock->clk_exit_cpufreq_table) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - arch_clock->clk_exit_cpufreq_table(table); - spin_unlock_irqrestore(&clockfw_lock, flags); -} -#endif - /* * */ diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index f1e46ea6b81d..0a9b9a970113 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -20,6 +20,7 @@ #include <plat/board.h> #include <plat/vram.h> #include <plat/dsp.h> +#include <plat/dma.h> #include <plat/omap-secure.h> diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index ecdb3da0dea9..987e6101267d 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -41,6 +41,15 @@ #include <plat/tc.h> +/* + * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA + * channels that an instance of the SDMA IP block can support. Used + * to size arrays. (The actual maximum on a particular SoC may be less + * than this -- for example, OMAP1 SDMA instances only support 17 logical + * DMA channels.) + */ +#define MAX_LOGICAL_DMA_CH_COUNT 32 + #undef DEBUG #ifndef CONFIG_ARCH_OMAP1 @@ -883,7 +892,7 @@ void omap_start_dma(int lch) if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; - char dma_chan_link_map[dma_lch_count]; + char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ @@ -916,6 +925,13 @@ void omap_start_dma(int lch) l |= OMAP_DMA_CCR_BUFFERING_DISABLE; l |= OMAP_DMA_CCR_EN; + /* + * As dma_write() uses IO accessors which are weakly ordered, there + * is no guarantee that data in coherent DMA memory will be visible + * to the DMA device. Add a memory barrier here to ensure that any + * such data is visible prior to enabling DMA. + */ + mb(); p->dma_write(l, CCR, lch); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; @@ -965,9 +981,16 @@ void omap_stop_dma(int lch) p->dma_write(l, CCR, lch); } + /* + * Ensure that data transferred by DMA is visible to any access + * after DMA has been disabled. This is important for coherent + * DMA regions. + */ + mb(); + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; - char dma_chan_link_map[dma_lch_count]; + char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); do { diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 652139c0339e..c4ed35e89fbd 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -349,11 +349,12 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start); int omap_dm_timer_stop(struct omap_dm_timer *timer) { unsigned long rate = 0; - struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; + struct dmtimer_platform_data *pdata; if (unlikely(!timer)) return -EINVAL; + pdata = timer->pdev->dev.platform_data; if (!pdata->needs_manual_reset) rate = clk_get_rate(timer->fclk); diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index d5eb4c87db9d..4814c5b65306 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h @@ -91,6 +91,8 @@ struct omap_usb_config { u32 (*usb0_init)(unsigned nwires, unsigned is_device); u32 (*usb1_init)(unsigned nwires); u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); + + int (*ocpi_enable)(void); }; struct omap_lcd_config { diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 240a7b9fd946..d0ef57c1d71b 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -272,8 +272,6 @@ struct clk { #endif }; -struct cpufreq_frequency_table; - struct clk_functions { int (*clk_enable)(struct clk *clk); void (*clk_disable)(struct clk *clk); @@ -283,10 +281,6 @@ struct clk_functions { void (*clk_allow_idle)(struct clk *clk); void (*clk_deny_idle)(struct clk *clk); void (*clk_disable_unused)(struct clk *clk); -#ifdef CONFIG_CPU_FREQ - void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **); - void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **); -#endif }; extern int mpurate; @@ -301,10 +295,6 @@ extern void recalculate_root_clocks(void); extern unsigned long followparent_recalc(struct clk *clk); extern void clk_enable_init_clocks(void); unsigned long omap_fixed_divisor_recalc(struct clk *clk); -#ifdef CONFIG_CPU_FREQ -extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); -extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); -#endif extern struct clk *omap_clk_get_by_name(const char *name); extern int omap_clk_enable_autoidle_all(void); extern int omap_clk_disable_autoidle_all(void); diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index b4d7ec3fbfbe..a557b8484e6c 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -32,6 +32,8 @@ extern int __init omap_init_clocksource_32k(void); +extern void __init omap_check_revision(void); + extern void omap_reserve(void); extern int omap_dss_reset(struct omap_hwmod *); diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index dc562a5c0a8a..42afb4c45517 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -442,6 +442,7 @@ struct omap_system_dma_plat_info { u32 (*dma_read)(int reg, int lch); }; +extern void __init omap_init_consistent_dma_size(void); extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 9418f00b6c38..230ff91be491 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -316,12 +316,12 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) OMAP_TIMER_V1_SYS_STAT_OFFSET; timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; - timer->irq_dis = 0; + timer->irq_dis = NULL; timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; timer->func_base = timer->io_base; } else { timer->revision = 2; - timer->sys_stat = 0; + timer->sys_stat = NULL; timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 8070145ccb98..14dde32cd406 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -213,11 +213,16 @@ struct omap_hwmod_addr_space { */ #define OCP_USER_MPU (1 << 0) #define OCP_USER_SDMA (1 << 1) +#define OCP_USER_DSP (1 << 2) /* omap_hwmod_ocp_if.flags bits */ #define OCPIF_SWSUP_IDLE (1 << 0) #define OCPIF_CAN_BURST (1 << 1) +/* omap_hwmod_ocp_if._int_flags possibilities */ +#define _OCPIF_INT_FLAGS_REGISTERED (1 << 0) + + /** * struct omap_hwmod_ocp_if - OCP interface data * @master: struct omap_hwmod that initiates OCP transactions on this link @@ -229,6 +234,7 @@ struct omap_hwmod_addr_space { * @width: OCP data width * @user: initiators using this interface (see OCP_USER_* macros above) * @flags: OCP interface flags (see OCPIF_* macros above) + * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above) * * It may also be useful to add a tag_cnt field for OCP2.x devices. * @@ -247,6 +253,7 @@ struct omap_hwmod_ocp_if { u8 width; u8 user; u8 flags; + u8 _int_flags; }; @@ -305,6 +312,7 @@ struct omap_hwmod_sysc_fields { * @rev_offs: IP block revision register offset (from module base addr) * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) + * @srst_udelay: Delay needed after doing a softreset in usecs * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported * @clockact: the default value of the module CLOCKACTIVITY bits @@ -326,13 +334,14 @@ struct omap_hwmod_sysc_fields { * then this field has to be populated with the correct offset structure. */ struct omap_hwmod_class_sysconfig { - u16 rev_offs; - u16 sysc_offs; - u16 syss_offs; + u32 rev_offs; + u32 sysc_offs; + u32 syss_offs; u16 sysc_flags; + struct omap_hwmod_sysc_fields *sysc_fields; + u8 srst_udelay; u8 idlemodes; u8 clockact; - struct omap_hwmod_sysc_fields *sysc_fields; }; /** @@ -474,6 +483,16 @@ struct omap_hwmod_class { }; /** + * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs + * @ocp_if: OCP interface structure record pointer + * @node: list_head pointing to next struct omap_hwmod_link in a list + */ +struct omap_hwmod_link { + struct omap_hwmod_ocp_if *ocp_if; + struct list_head node; +}; + +/** * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) * @name: name of the hwmod * @class: struct omap_hwmod_class * to the class of this hwmod @@ -485,12 +504,10 @@ struct omap_hwmod_class { * @_clk: pointer to the main struct clk (filled in at runtime) * @opt_clks: other device clocks that drivers can request (0..*) * @voltdm: pointer to voltage domain (filled in at runtime) - * @masters: ptr to array of OCP ifs that this hwmod can initiate on - * @slaves: ptr to array of OCP ifs that this hwmod can respond on * @dev_attr: arbitrary device attributes that can be passed to the driver * @_sysc_cache: internal-use hwmod flags * @_mpu_rt_va: cached register target start address (internal use) - * @_mpu_port_index: cached MPU register target slave ID (internal use) + * @_mpu_port: cached MPU register target slave (internal use) * @opt_clks_cnt: number of @opt_clks * @master_cnt: number of @master entries * @slaves_cnt: number of @slave entries @@ -509,6 +526,8 @@ struct omap_hwmod_class { * * Parameter names beginning with an underscore are managed internally by * the omap_hwmod code and should not be set during initialization. + * + * @masters and @slaves are now deprecated. */ struct omap_hwmod { const char *name; @@ -527,15 +546,15 @@ struct omap_hwmod { struct omap_hwmod_opt_clk *opt_clks; char *clkdm_name; struct clockdomain *clkdm; - struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ - struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ + struct list_head master_ports; /* connect to *_IA */ + struct list_head slave_ports; /* connect to *_TA */ void *dev_attr; u32 _sysc_cache; void __iomem *_mpu_rt_va; spinlock_t _lock; struct list_head node; + struct omap_hwmod_ocp_if *_mpu_port; u16 flags; - u8 _mpu_port_index; u8 response_lat; u8 rst_lines_cnt; u8 opt_clks_cnt; @@ -547,7 +566,6 @@ struct omap_hwmod { u8 _postsetup_state; }; -int omap_hwmod_register(struct omap_hwmod **ohs); struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); @@ -579,6 +597,8 @@ int omap_hwmod_softreset(struct omap_hwmod *oh); int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); +int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, + const char *name, struct resource *res); struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); @@ -617,4 +637,6 @@ extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); +extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); + #endif diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index d50cbc6385bd..c490240bb82c 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -475,13 +475,11 @@ static int omap_device_count_resources(struct omap_device *od) static int omap_device_fill_resources(struct omap_device *od, struct resource *res) { - int c = 0; int i, r; for (i = 0; i < od->hwmods_cnt; i++) { r = omap_hwmod_fill_resources(od->hwmods[i], res); res += r; - c += r; } return 0; diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index eec98afa0f83..477363c163ec 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -196,8 +196,8 @@ static void __init omap_map_sram(void) * Looks like we need to preserve some bootloader code at the * beginning of SRAM for jumping to flash for reboot to work... */ - memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0, - omap_sram_size - SRAM_BOOTLOADER_SZ); + memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0, + omap_sram_size - SRAM_BOOTLOADER_SZ); } /* @@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, sdrc_actim_ctrl_b_1, sdrc_mr_1); } -#ifdef CONFIG_PM void omap3_sram_restore_context(void) { omap_sram_ceil = omap_sram_base + omap_sram_size; @@ -358,17 +357,18 @@ void omap3_sram_restore_context(void) omap3_sram_configure_core_dpll_sz); omap_push_sram_idle(); } -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_OMAP3 */ static inline int omap34xx_sram_init(void) { -#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) omap3_sram_restore_context(); -#endif return 0; } +#else +static inline int omap34xx_sram_init(void) +{ + return 0; +} +#endif /* CONFIG_ARCH_OMAP3 */ static inline int am33xx_sram_init(void) { diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index d2bbfd1cb0b5..daa0327381b5 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -31,15 +31,12 @@ #include <mach/hardware.h> -#include "../mach-omap2/common.h" - #ifdef CONFIG_ARCH_OMAP_OTG void __init omap_otg_init(struct omap_usb_config *config) { u32 syscon; - int status; int alt_pingroup = 0; /* NOTE: no bus or clock setup (yet?) */ @@ -104,6 +101,7 @@ omap_otg_init(struct omap_usb_config *config) #ifdef CONFIG_USB_GADGET_OMAP if (config->otg || config->register_dev) { struct platform_device *udc_device = config->udc_device; + int status; syscon &= ~DEV_IDLE_EN; udc_device->dev.platform_data = config; @@ -116,6 +114,7 @@ omap_otg_init(struct omap_usb_config *config) #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) if (config->otg || config->register_host) { struct platform_device *ohci_device = config->ohci_device; + int status; syscon &= ~HST_IDLE_EN; ohci_device->dev.platform_data = config; @@ -128,6 +127,7 @@ omap_otg_init(struct omap_usb_config *config) #ifdef CONFIG_USB_OTG if (config->otg) { struct platform_device *otg_device = config->otg_device; + int status; syscon &= ~OTG_IDLE_EN; otg_device->dev.platform_data = config; @@ -138,8 +138,6 @@ omap_otg_init(struct omap_usb_config *config) #endif pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); omap_writel(syscon, OTG_SYSCON_1); - - status = 0; } #else diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 71553f410016..a0ffc77da809 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -302,6 +302,7 @@ comment "Power management" config SAMSUNG_PM_DEBUG bool "S3C2410 PM Suspend debug" depends on PM + select DEBUG_LL help Say Y here if you want verbose debugging from the PM Suspend and Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 317e246ffc56..e834c5ef437c 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -18,6 +18,8 @@ #ifndef __PLAT_S3C_SDHCI_H #define __PLAT_S3C_SDHCI_H __FILE__ +#include <plat/devs.h> + struct platform_device; struct mmc_host; struct mmc_card; @@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { } #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ +static inline void s3c_sdhci_setname(int id, char *name) +{ + switch (id) { +#ifdef CONFIG_S3C_DEV_HSMMC + case 0: + s3c_device_hsmmc0.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + case 1: + s3c_device_hsmmc1.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + case 2: + s3c_device_hsmmc2.name = name; + break; +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + case 3: + s3c_device_hsmmc3.name = name; + break; +#endif + } +} + #endif /* __PLAT_S3C_SDHCI_H */ diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 858748eaa144..bc683b8219b5 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -17,6 +17,8 @@ #include <linux/sched.h> #include <linux/smp.h> #include <linux/init.h> +#include <linux/uaccess.h> +#include <linux/user.h> #include <asm/cp15.h> #include <asm/cputype.h> @@ -529,6 +531,103 @@ void vfp_flush_hwstate(struct thread_info *thread) } /* + * Save the current VFP state into the provided structures and prepare + * for entry into a new function (signal handler). + */ +int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp, + struct user_vfp_exc __user *ufp_exc) +{ + struct thread_info *thread = current_thread_info(); + struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; + int err = 0; + + /* Ensure that the saved hwstate is up-to-date. */ + vfp_sync_hwstate(thread); + + /* + * Copy the floating point registers. There can be unused + * registers see asm/hwcap.h for details. + */ + err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs, + sizeof(hwstate->fpregs)); + /* + * Copy the status and control register. + */ + __put_user_error(hwstate->fpscr, &ufp->fpscr, err); + + /* + * Copy the exception registers. + */ + __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err); + __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); + __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); + + if (err) + return -EFAULT; + + /* Ensure that VFP is disabled. */ + vfp_flush_hwstate(thread); + + /* + * As per the PCS, clear the length and stride bits for function + * entry. + */ + hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK); + + /* + * Disable VFP in the hwstate so that we can detect if it gets + * used. + */ + hwstate->fpexc &= ~FPEXC_EN; + return 0; +} + +/* Sanitise and restore the current VFP state from the provided structures. */ +int vfp_restore_user_hwstate(struct user_vfp __user *ufp, + struct user_vfp_exc __user *ufp_exc) +{ + struct thread_info *thread = current_thread_info(); + struct vfp_hard_struct *hwstate = &thread->vfpstate.hard; + unsigned long fpexc; + int err = 0; + + /* + * If VFP has been used, then disable it to avoid corrupting + * the new thread state. + */ + if (hwstate->fpexc & FPEXC_EN) + vfp_flush_hwstate(thread); + + /* + * Copy the floating point registers. There can be unused + * registers see asm/hwcap.h for details. + */ + err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs, + sizeof(hwstate->fpregs)); + /* + * Copy the status and control register. + */ + __get_user_error(hwstate->fpscr, &ufp->fpscr, err); + + /* + * Sanitise and restore the exception registers. + */ + __get_user_error(fpexc, &ufp_exc->fpexc, err); + + /* Ensure the VFP is enabled. */ + fpexc |= FPEXC_EN; + + /* Ensure FPINST2 is invalid and the exception flag is cleared. */ + fpexc &= ~(FPEXC_EX | FPEXC_FP2V); + hwstate->fpexc = fpexc; + + __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err); + __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err); + + return err ? -EFAULT : 0; +} + +/* * VFP hardware can lose all context when a CPU goes offline. * As we will be running in SMP mode with CPU hotplug, we will save the * hardware state at every thread switch. We clear our held state when diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c index 1633a6f306c0..85038f54354d 100644 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/arch/blackfin/mach-bf538/boards/ezkit.c @@ -38,7 +38,7 @@ static struct platform_device rtc_device = { .name = "rtc-bfin", .id = -1, }; -#endif +#endif /* CONFIG_RTC_DRV_BFIN */ #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) #ifdef CONFIG_SERIAL_BFIN_UART0 @@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = { .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_UART0 */ #ifdef CONFIG_SERIAL_BFIN_UART1 static struct resource bfin_uart1_resources[] = { { @@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = { .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_UART1 */ #ifdef CONFIG_SERIAL_BFIN_UART2 static struct resource bfin_uart2_resources[] = { { @@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = { .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ }, }; -#endif -#endif +#endif /* CONFIG_SERIAL_BFIN_UART2 */ +#endif /* CONFIG_SERIAL_BFIN */ #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) #ifdef CONFIG_BFIN_SIR0 @@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = { .num_resources = ARRAY_SIZE(bfin_sir0_resources), .resource = bfin_sir0_resources, }; -#endif +#endif /* CONFIG_BFIN_SIR0 */ #ifdef CONFIG_BFIN_SIR1 static struct resource bfin_sir1_resources[] = { { @@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = { .num_resources = ARRAY_SIZE(bfin_sir1_resources), .resource = bfin_sir1_resources, }; -#endif +#endif /* CONFIG_BFIN_SIR1 */ #ifdef CONFIG_BFIN_SIR2 static struct resource bfin_sir2_resources[] = { { @@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = { .num_resources = ARRAY_SIZE(bfin_sir2_resources), .resource = bfin_sir2_resources, }; -#endif -#endif +#endif /* CONFIG_BFIN_SIR2 */ +#endif /* CONFIG_BFIN_SIR */ #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART @@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = { .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */ #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART static struct resource bfin_sport1_uart_resources[] = { { @@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = { .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */ #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART static struct resource bfin_sport2_uart_resources[] = { { @@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = { .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */ #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART static struct resource bfin_sport3_uart_resources[] = { { @@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = { .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ }, }; -#endif -#endif +#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */ +#endif /* CONFIG_SERIAL_BFIN_SPORT */ #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) static unsigned short bfin_can_peripherals[] = { @@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = { .platform_data = &bfin_can_peripherals, /* Passed to driver */ }, }; -#endif +#endif /* CONFIG_CAN_BFIN */ /* * USB-LAN EzExtender board @@ -488,7 +488,7 @@ static struct platform_device smc91x_device = { .platform_data = &smc91x_info, }, }; -#endif +#endif /* CONFIG_SMC91X */ #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE) /* all SPI peripherals info goes here */ @@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = { static struct bfin5xx_spi_chip spi_flash_chip_info = { .enable_dma = 0, /* use dma transfer with this chip*/ }; -#endif +#endif /* CONFIG_MTD_M25P80 */ +#endif /* CONFIG_SPI_BFIN5XX */ #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) #include <linux/spi/ad7879.h> @@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { .gpio_export = 1, /* Export GPIO to gpiolib */ .gpio_base = -1, /* Dynamic allocation */ }; -#endif +#endif /* CONFIG_TOUCHSCREEN_AD7879 */ #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) #include <asm/bfin-lq035q1.h> @@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = { .platform_data = &bfin_lq035q1_data, }, }; -#endif +#endif /* CONFIG_FB_BFIN_LQ035Q1 */ static struct spi_board_info bf538_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ @@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .controller_data = &spi_flash_chip_info, .mode = SPI_MODE_3, }, -#endif +#endif /* CONFIG_MTD_M25P80 */ #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) { .modalias = "ad7879", @@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .chip_select = 1, .mode = SPI_CPHA | SPI_CPOL, }, -#endif +#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */ #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) { .modalias = "bfin-lq035q1-spi", @@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .chip_select = 2, .mode = SPI_CPHA | SPI_CPOL, }, -#endif +#endif /* CONFIG_FB_BFIN_LQ035Q1 */ #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) { .modalias = "spidev", @@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = { .bus_num = 0, .chip_select = 1, }, -#endif +#endif /* CONFIG_SPI_SPIDEV */ }; /* SPI (0) */ @@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = { }, }; -#endif /* spi master and devices */ - #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { [0] = { @@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = { .num_resources = ARRAY_SIZE(bfin_twi1_resource), .resource = bfin_twi1_resource, }; -#endif -#endif +#endif /* CONFIG_BF542 */ +#endif /* CONFIG_I2C_BLACKFIN_TWI */ #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) #include <linux/gpio_keys.h> diff --git a/arch/c6x/include/asm/irq.h b/arch/c6x/include/asm/irq.h index f13b78d5e1ca..ab4577f93d96 100644 --- a/arch/c6x/include/asm/irq.h +++ b/arch/c6x/include/asm/irq.h @@ -42,10 +42,6 @@ /* This number is used when no interrupt has been assigned */ #define NO_IRQ 0 -struct irq_data; -extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d); -extern irq_hw_number_t virq_to_hw(unsigned int virq); - extern void __init init_pic_c64xplus(void); extern void init_IRQ(void); diff --git a/arch/c6x/kernel/irq.c b/arch/c6x/kernel/irq.c index 65b8ddf54b44..c90fb5e82ad7 100644 --- a/arch/c6x/kernel/irq.c +++ b/arch/c6x/kernel/irq.c @@ -130,16 +130,3 @@ int arch_show_interrupts(struct seq_file *p, int prec) seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); return 0; } - -irq_hw_number_t irqd_to_hwirq(struct irq_data *d) -{ - return d->hwirq; -} -EXPORT_SYMBOL_GPL(irqd_to_hwirq); - -irq_hw_number_t virq_to_hw(unsigned int virq) -{ - struct irq_data *irq_data = irq_get_irq_data(virq); - return WARN_ON(!irq_data) ? 0 : irq_data->hwirq; -} -EXPORT_SYMBOL_GPL(virq_to_hw); diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c index 37302218ca4a..0f2367cc5493 100644 --- a/arch/hexagon/kernel/dma.c +++ b/arch/hexagon/kernel/dma.c @@ -22,6 +22,7 @@ #include <linux/bootmem.h> #include <linux/genalloc.h> #include <asm/dma-mapping.h> +#include <linux/module.h> struct dma_map_ops *dma_ops; EXPORT_SYMBOL(dma_ops); diff --git a/arch/hexagon/kernel/process.c b/arch/hexagon/kernel/process.c index 18c4f0b0f4ba..ff02821bfb7e 100644 --- a/arch/hexagon/kernel/process.c +++ b/arch/hexagon/kernel/process.c @@ -1,7 +1,7 @@ /* * Process creation support for Hexagon * - * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle; void cpu_idle(void) { while (1) { - tick_nohz_stop_sched_tick(1); + tick_nohz_idle_enter(); local_irq_disable(); while (!need_resched()) { idle_sleep(); @@ -97,7 +97,7 @@ void cpu_idle(void) local_irq_disable(); } local_irq_enable(); - tick_nohz_restart_sched_tick(); + tick_nohz_idle_exit(); schedule(); } } diff --git a/arch/hexagon/kernel/ptrace.c b/arch/hexagon/kernel/ptrace.c index 32342de1a79c..96c3b2c4dbad 100644 --- a/arch/hexagon/kernel/ptrace.c +++ b/arch/hexagon/kernel/ptrace.c @@ -28,6 +28,7 @@ #include <linux/ptrace.h> #include <linux/regset.h> #include <linux/user.h> +#include <linux/elf.h> #include <asm/user.h> diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c index 9b44a9e2d05a..1298141874a3 100644 --- a/arch/hexagon/kernel/smp.c +++ b/arch/hexagon/kernel/smp.c @@ -1,7 +1,7 @@ /* * SMP support for Hexagon * - * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. + * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,6 +28,7 @@ #include <linux/sched.h> #include <linux/smp.h> #include <linux/spinlock.h> +#include <linux/cpu.h> #include <asm/time.h> /* timer_interrupt */ #include <asm/hexagon_vm.h> @@ -177,7 +178,12 @@ void __cpuinit start_secondary(void) printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu); + notify_cpu_starting(cpu); + + ipi_call_lock(); set_cpu_online(cpu, true); + ipi_call_unlock(); + local_irq_enable(); cpu_idle(); diff --git a/arch/hexagon/kernel/time.c b/arch/hexagon/kernel/time.c index 6bee15c9c113..5d9b33b67935 100644 --- a/arch/hexagon/kernel/time.c +++ b/arch/hexagon/kernel/time.c @@ -28,6 +28,7 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/module.h> #include <asm/timer-regs.h> #include <asm/hexagon_vm.h> diff --git a/arch/hexagon/kernel/vdso.c b/arch/hexagon/kernel/vdso.c index f212a453b527..5d39f42f7085 100644 --- a/arch/hexagon/kernel/vdso.c +++ b/arch/hexagon/kernel/vdso.c @@ -21,6 +21,7 @@ #include <linux/err.h> #include <linux/mm.h> #include <linux/vmalloc.h> +#include <linux/binfmts.h> #include <asm/vdso.h> diff --git a/arch/ia64/include/asm/cmpxchg.h b/arch/ia64/include/asm/cmpxchg.h index 4c96187e2049..4f37dbbb8640 100644 --- a/arch/ia64/include/asm/cmpxchg.h +++ b/arch/ia64/include/asm/cmpxchg.h @@ -1 +1,147 @@ -#include <asm/intrinsics.h> +#ifndef _ASM_IA64_CMPXCHG_H +#define _ASM_IA64_CMPXCHG_H + +/* + * Compare/Exchange, forked from asm/intrinsics.h + * which was: + * + * Copyright (C) 2002-2003 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> + */ + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> +/* include compiler specific intrinsics */ +#include <asm/ia64regs.h> +#ifdef __INTEL_COMPILER +# include <asm/intel_intrin.h> +#else +# include <asm/gcc_intrin.h> +#endif + +/* + * This function doesn't exist, so you'll get a linker error if + * something tries to do an invalid xchg(). + */ +extern void ia64_xchg_called_with_bad_pointer(void); + +#define __xchg(x, ptr, size) \ +({ \ + unsigned long __xchg_result; \ + \ + switch (size) { \ + case 1: \ + __xchg_result = ia64_xchg1((__u8 *)ptr, x); \ + break; \ + \ + case 2: \ + __xchg_result = ia64_xchg2((__u16 *)ptr, x); \ + break; \ + \ + case 4: \ + __xchg_result = ia64_xchg4((__u32 *)ptr, x); \ + break; \ + \ + case 8: \ + __xchg_result = ia64_xchg8((__u64 *)ptr, x); \ + break; \ + default: \ + ia64_xchg_called_with_bad_pointer(); \ + } \ + __xchg_result; \ +}) + +#define xchg(ptr, x) \ +((__typeof__(*(ptr))) __xchg((unsigned long) (x), (ptr), sizeof(*(ptr)))) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ + +#define __HAVE_ARCH_CMPXCHG 1 + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid cmpxchg(). + */ +extern long ia64_cmpxchg_called_with_bad_pointer(void); + +#define ia64_cmpxchg(sem, ptr, old, new, size) \ +({ \ + __u64 _o_, _r_; \ + \ + switch (size) { \ + case 1: \ + _o_ = (__u8) (long) (old); \ + break; \ + case 2: \ + _o_ = (__u16) (long) (old); \ + break; \ + case 4: \ + _o_ = (__u32) (long) (old); \ + break; \ + case 8: \ + _o_ = (__u64) (long) (old); \ + break; \ + default: \ + break; \ + } \ + switch (size) { \ + case 1: \ + _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_); \ + break; \ + \ + case 2: \ + _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_); \ + break; \ + \ + case 4: \ + _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_); \ + break; \ + \ + case 8: \ + _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_); \ + break; \ + \ + default: \ + _r_ = ia64_cmpxchg_called_with_bad_pointer(); \ + break; \ + } \ + (__typeof__(old)) _r_; \ +}) + +#define cmpxchg_acq(ptr, o, n) \ + ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr))) +#define cmpxchg_rel(ptr, o, n) \ + ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr))) + +/* for compatibility with other platforms: */ +#define cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) +#define cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) + +#define cmpxchg_local cmpxchg +#define cmpxchg64_local cmpxchg64 + +#ifdef CONFIG_IA64_DEBUG_CMPXCHG +# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; +# define CMPXCHG_BUGCHECK(v) \ +do { \ + if (_cmpxchg_bugcheck_count-- <= 0) { \ + void *ip; \ + extern int printk(const char *fmt, ...); \ + ip = (void *) ia64_getreg(_IA64_REG_IP); \ + printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v));\ + break; \ + } \ +} while (0) +#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ +# define CMPXCHG_BUGCHECK_DECL +# define CMPXCHG_BUGCHECK(v) +#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_IA64_CMPXCHG_H */ diff --git a/arch/ia64/include/asm/futex.h b/arch/ia64/include/asm/futex.h index 0ab82cc2dc8f..d2bf1fd5e44f 100644 --- a/arch/ia64/include/asm/futex.h +++ b/arch/ia64/include/asm/futex.h @@ -106,15 +106,16 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, return -EFAULT; { - register unsigned long r8 __asm ("r8") = 0; + register unsigned long r8 __asm ("r8"); unsigned long prev; __asm__ __volatile__( " mf;; \n" - " mov ar.ccv=%3;; \n" - "[1:] cmpxchg4.acq %0=[%1],%2,ar.ccv \n" + " mov %0=r0 \n" + " mov ar.ccv=%4;; \n" + "[1:] cmpxchg4.acq %1=[%2],%3,ar.ccv \n" " .xdata4 \"__ex_table\", 1b-., 2f-. \n" "[2:]" - : "=r" (prev) + : "=r" (r8), "=r" (prev) : "r" (uaddr), "r" (newval), "rO" ((long) (unsigned) oldval) : "memory"); diff --git a/arch/ia64/include/asm/intrinsics.h b/arch/ia64/include/asm/intrinsics.h index e4076b511829..d129e367e764 100644 --- a/arch/ia64/include/asm/intrinsics.h +++ b/arch/ia64/include/asm/intrinsics.h @@ -18,6 +18,7 @@ #else # include <asm/gcc_intrin.h> #endif +#include <asm/cmpxchg.h> #define ia64_native_get_psr_i() (ia64_native_getreg(_IA64_REG_PSR) & IA64_PSR_I) @@ -81,119 +82,6 @@ extern unsigned long __bad_increment_for_ia64_fetch_and_add (void); #define ia64_fetch_and_add(i,v) (ia64_fetchadd(i, v, rel) + (i)) /* return new value */ -/* - * This function doesn't exist, so you'll get a linker error if - * something tries to do an invalid xchg(). - */ -extern void ia64_xchg_called_with_bad_pointer (void); - -#define __xchg(x,ptr,size) \ -({ \ - unsigned long __xchg_result; \ - \ - switch (size) { \ - case 1: \ - __xchg_result = ia64_xchg1((__u8 *)ptr, x); \ - break; \ - \ - case 2: \ - __xchg_result = ia64_xchg2((__u16 *)ptr, x); \ - break; \ - \ - case 4: \ - __xchg_result = ia64_xchg4((__u32 *)ptr, x); \ - break; \ - \ - case 8: \ - __xchg_result = ia64_xchg8((__u64 *)ptr, x); \ - break; \ - default: \ - ia64_xchg_called_with_bad_pointer(); \ - } \ - __xchg_result; \ -}) - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr)))) - -/* - * Atomic compare and exchange. Compare OLD with MEM, if identical, - * store NEW in MEM. Return the initial value in MEM. Success is - * indicated by comparing RETURN with OLD. - */ - -#define __HAVE_ARCH_CMPXCHG 1 - -/* - * This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid cmpxchg(). - */ -extern long ia64_cmpxchg_called_with_bad_pointer (void); - -#define ia64_cmpxchg(sem,ptr,old,new,size) \ -({ \ - __u64 _o_, _r_; \ - \ - switch (size) { \ - case 1: _o_ = (__u8 ) (long) (old); break; \ - case 2: _o_ = (__u16) (long) (old); break; \ - case 4: _o_ = (__u32) (long) (old); break; \ - case 8: _o_ = (__u64) (long) (old); break; \ - default: break; \ - } \ - switch (size) { \ - case 1: \ - _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_); \ - break; \ - \ - case 2: \ - _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_); \ - break; \ - \ - case 4: \ - _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_); \ - break; \ - \ - case 8: \ - _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_); \ - break; \ - \ - default: \ - _r_ = ia64_cmpxchg_called_with_bad_pointer(); \ - break; \ - } \ - (__typeof__(old)) _r_; \ -}) - -#define cmpxchg_acq(ptr, o, n) \ - ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr))) -#define cmpxchg_rel(ptr, o, n) \ - ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr))) - -/* for compatibility with other platforms: */ -#define cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) -#define cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) - -#define cmpxchg_local cmpxchg -#define cmpxchg64_local cmpxchg64 - -#ifdef CONFIG_IA64_DEBUG_CMPXCHG -# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; -# define CMPXCHG_BUGCHECK(v) \ - do { \ - if (_cmpxchg_bugcheck_count-- <= 0) { \ - void *ip; \ - extern int printk(const char *fmt, ...); \ - ip = (void *) ia64_getreg(_IA64_REG_IP); \ - printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v)); \ - break; \ - } \ - } while (0) -#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ -# define CMPXCHG_BUGCHECK_DECL -# define CMPXCHG_BUGCHECK(v) -#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ - #endif #ifdef __KERNEL__ diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index 9d0fd7d5bb82..f00ba025375d 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -604,12 +604,6 @@ pfm_unprotect_ctx_ctxsw(pfm_context_t *x, unsigned long f) spin_unlock(&(x)->ctx_lock); } -static inline unsigned int -pfm_do_munmap(struct mm_struct *mm, unsigned long addr, size_t len, int acct) -{ - return do_munmap(mm, addr, len); -} - static inline unsigned long pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len, unsigned long pgoff, unsigned long flags, unsigned long exec) { @@ -1458,8 +1452,9 @@ pfm_unreserve_session(pfm_context_t *ctx, int is_syswide, unsigned int cpu) * a PROTECT_CTX() section. */ static int -pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long size) +pfm_remove_smpl_mapping(void *vaddr, unsigned long size) { + struct task_struct *task = current; int r; /* sanity checks */ @@ -1473,13 +1468,8 @@ pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long siz /* * does the actual unmapping */ - down_write(&task->mm->mmap_sem); + r = vm_munmap((unsigned long)vaddr, size); - DPRINT(("down_write done smpl_vaddr=%p size=%lu\n", vaddr, size)); - - r = pfm_do_munmap(task->mm, (unsigned long)vaddr, size, 0); - - up_write(&task->mm->mmap_sem); if (r !=0) { printk(KERN_ERR "perfmon: [%d] unable to unmap sampling buffer @%p size=%lu\n", task_pid_nr(task), vaddr, size); } @@ -1945,7 +1935,7 @@ pfm_flush(struct file *filp, fl_owner_t id) * because some VM function reenables interrupts. * */ - if (smpl_buf_vaddr) pfm_remove_smpl_mapping(current, smpl_buf_vaddr, smpl_buf_size); + if (smpl_buf_vaddr) pfm_remove_smpl_mapping(smpl_buf_vaddr, smpl_buf_size); return 0; } diff --git a/arch/m68k/configs/m5275evb_defconfig b/arch/m68k/configs/m5275evb_defconfig index 33c32aeca12b..a1230e82bb1e 100644 --- a/arch/m68k/configs/m5275evb_defconfig +++ b/arch/m68k/configs/m5275evb_defconfig @@ -49,7 +49,6 @@ CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_FEC=y -CONFIG_FEC2=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set CONFIG_PPP=y diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c index 7ed848c3b848..f91a53294c35 100644 --- a/arch/m68k/platform/527x/config.c +++ b/arch/m68k/platform/527x/config.c @@ -74,9 +74,7 @@ static void __init m527x_fec_init(void) writew(par | 0xf00, MCF_IPSBAR + 0x100082); v = readb(MCF_IPSBAR + 0x100078); writeb(v | 0xc0, MCF_IPSBAR + 0x100078); -#endif -#ifdef CONFIG_FEC2 /* Set multi-function pins to ethernet mode for fec1 */ par = readw(MCF_IPSBAR + 0x100082); writew(par | 0xa0, MCF_IPSBAR + 0x100082); diff --git a/arch/m68k/platform/68EZ328/Makefile b/arch/m68k/platform/68EZ328/Makefile index ee97735a242c..b44d799b1115 100644 --- a/arch/m68k/platform/68EZ328/Makefile +++ b/arch/m68k/platform/68EZ328/Makefile @@ -3,9 +3,3 @@ # obj-y := config.o - -extra-y := bootlogo.rh - -$(obj)/bootlogo.rh: $(src)/bootlogo.h - perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \ - > $(obj)/bootlogo.rh diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile index 447ffa0fd7c7..a49d75e65489 100644 --- a/arch/m68k/platform/68VZ328/Makefile +++ b/arch/m68k/platform/68VZ328/Makefile @@ -3,14 +3,9 @@ # obj-y := config.o -logo-$(UCDIMM) := bootlogo.rh -logo-$(DRAGEN2) := screen.h -extra-y := $(logo-y) - -$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h - perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh +extra-$(DRAGEN2):= screen.h $(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h -clean-files := $(obj)/screen.h $(obj)/bootlogo.rh +clean-files := $(obj)/screen.h diff --git a/arch/m68k/platform/68EZ328/bootlogo.h b/arch/m68k/platform/68VZ328/bootlogo.h index e842bdae5839..b38e2b255142 100644 --- a/arch/m68k/platform/68EZ328/bootlogo.h +++ b/arch/m68k/platform/68VZ328/bootlogo.h @@ -1,6 +1,6 @@ #define splash_width 640 #define splash_height 480 -static unsigned char splash_bits[] = { +unsigned char __attribute__ ((aligned(16))) bootlogo_bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c index fa50c48292ff..7af97362b95c 100644 --- a/arch/m68k/platform/coldfire/device.c +++ b/arch/m68k/platform/coldfire/device.c @@ -114,7 +114,7 @@ static struct resource mcf_fec1_resources[] = { static struct platform_device mcf_fec1 = { .name = "fec", - .id = 0, + .id = 1, .num_resources = ARRAY_SIZE(mcf_fec1_resources), .resource = mcf_fec1_resources, }; diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c index e21507052066..9c717bf98ffe 100644 --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c @@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void) static int ar933x_wmac_reset(void) { - ath79_device_reset_clear(AR933X_RESET_WMAC); ath79_device_reset_set(AR933X_RESET_WMAC); + ath79_device_reset_clear(AR933X_RESET_WMAC); return 0; } diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h index a865c983c70a..5ad1a9c113c6 100644 --- a/arch/mips/include/asm/mach-jz4740/irq.h +++ b/arch/mips/include/asm/mach-jz4740/irq.h @@ -45,7 +45,7 @@ #define JZ4740_IRQ_LCD JZ4740_IRQ(30) /* 2nd-level interrupts */ -#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X)) +#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (x)) #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x)) #define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x)) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 73c0d45798de..9b02cfba7449 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -37,12 +37,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd); write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ } while (0) - -static inline unsigned long get_current_pgd(void) -{ - return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL); -} - #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ /* diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 185ca00c4c84..d5a338a1739c 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -257,11 +257,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -286,11 +283,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -362,10 +356,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&blocked); sig = restore_sigcontext(®s, &frame->sf_sc); if (sig < 0) @@ -401,10 +392,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) @@ -580,12 +568,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info, if (ret) return ret; - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked, sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + block_sigmask(ka, sig); return ret; } diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 06b5da392e24..ac3b8d89aae5 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&blocked); sig = restore_sigcontext32(®s, &frame->sf_sc); if (sig < 0) @@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext32(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index ae29e894ab8d..86eb4b04631c 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -93,11 +93,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) sigset_from_compat(&newset, &uset); sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); current->saved_sigmask = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&newset); current->state = TASK_INTERRUPTIBLE; schedule(); @@ -121,10 +118,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sighand->siglock); - current->blocked = set; - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + set_current_blocked(&set); sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext); if (sig < 0) diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c index 4f004596a6e7..0b3393381a81 100644 --- a/arch/parisc/kernel/pdc_cons.c +++ b/arch/parisc/kernel/pdc_cons.c @@ -104,7 +104,7 @@ static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp) static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp) { - if (!tty->count) { + if (tty->count == 1) { del_timer_sync(&pdc_console_timer); tty_port_tty_set(&tty_port, NULL); } diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi new file mode 100644 index 000000000000..1cf0b77b1efe --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi @@ -0,0 +1,43 @@ +/* + * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ] + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +message@42400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x42400 0x200>; + interrupts = < + 0xb4 2 0 0 + 0xb5 2 0 0 + 0xb6 2 0 0 + 0xb7 2 0 0>; +}; diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi index fdedf7b1fe0f..71c30eb10056 100644 --- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi +++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi @@ -53,6 +53,16 @@ timer@41100 { 3 0 3 0>; }; +message@41400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x41400 0x200>; + interrupts = < + 0xb0 2 0 0 + 0xb1 2 0 0 + 0xb2 2 0 0 + 0xb3 2 0 0>; +}; + msi@41600 { compatible = "fsl,mpic-msi"; reg = <0x41600 0x80>; diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h index cf417e510736..0e40843a1c6e 100644 --- a/arch/powerpc/include/asm/irq.h +++ b/arch/powerpc/include/asm/irq.h @@ -18,10 +18,6 @@ #include <linux/atomic.h> -/* Define a way to iterate across irqs. */ -#define for_each_irq(i) \ - for ((i) = 0; (i) < NR_IRQS; ++(i)) - extern atomic_t ppc_n_lost_interrupts; /* This number is used when no interrupt has been assigned */ @@ -33,8 +29,6 @@ extern atomic_t ppc_n_lost_interrupts; /* Same thing, used by the generic IRQ code */ #define NR_IRQS_LEGACY NUM_ISA_INTERRUPTS -struct irq_data; -extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d); extern irq_hw_number_t virq_to_hw(unsigned int virq); /** diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index c65b9294376e..c9f698a994be 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -275,9 +275,6 @@ struct mpic unsigned int isu_mask; /* Number of sources */ unsigned int num_sources; - /* default senses array */ - unsigned char *senses; - unsigned int senses_count; /* vector numbers used for internal sources (ipi/timers) */ unsigned int ipi_vecs[4]; @@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node, extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, phys_addr_t phys_addr); -/* Set default sense codes - * - * @mpic: controller - * @senses: array of sense codes - * @count: size of above array - * - * Optionally provide an array (indexed on hardware interrupt numbers - * for this MPIC) of default sense codes for the chip. Those are linux - * sense codes IRQ_TYPE_* - * - * The driver gets ownership of the pointer, don't dispose of it or - * anything like that. __init only. - */ -extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count); - /* Initialize the controller. After this has been called, none of the above * should be called again for this mpic diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h index 3ec37dc9003e..326d33ca55cd 100644 --- a/arch/powerpc/include/asm/mpic_msgr.h +++ b/arch/powerpc/include/asm/mpic_msgr.h @@ -13,6 +13,7 @@ #include <linux/types.h> #include <linux/spinlock.h> +#include <asm/smp.h> struct mpic_msgr { u32 __iomem *base; diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index b86faa9107da..8a97aa7289d3 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -15,11 +15,6 @@ #ifndef __ASM_POWERPC_REG_BOOKE_H__ #define __ASM_POWERPC_REG_BOOKE_H__ -#ifdef CONFIG_BOOKE_WDT -extern u32 booke_wdt_enabled; -extern u32 booke_wdt_period; -#endif /* CONFIG_BOOKE_WDT */ - /* Machine State Register (MSR) Fields */ #define MSR_GS (1<<28) /* Guest state */ #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 3e57a00b8cba..ba3aeb4bc06a 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -206,40 +206,43 @@ reenable_mmu: /* re-enable mmu so we can */ andi. r10,r10,MSR_EE /* Did EE change? */ beq 1f - /* Save handler and return address into the 2 unused words - * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything - * else can be recovered from the pt_regs except r3 which for - * normal interrupts has been set to pt_regs and for syscalls - * is an argument, so we temporarily use ORIG_GPR3 to save it - */ - stw r9,8(r1) - stw r11,12(r1) - stw r3,ORIG_GPR3(r1) /* * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1. * If from user mode there is only one stack frame on the stack, and * accessing CALLER_ADDR1 will cause oops. So we need create a dummy * stack frame to make trace_hardirqs_off happy. + * + * This is handy because we also need to save a bunch of GPRs, + * r3 can be different from GPR3(r1) at this point, r9 and r11 + * contains the old MSR and handler address respectively, + * r4 & r5 can contain page fault arguments that need to be passed + * along as well. r12, CCR, CTR, XER etc... are left clobbered as + * they aren't useful past this point (aren't syscall arguments), + * the rest is restored from the exception frame. */ + stwu r1,-32(r1) + stw r9,8(r1) + stw r11,12(r1) + stw r3,16(r1) + stw r4,20(r1) + stw r5,24(r1) andi. r12,r12,MSR_PR - beq 11f - stwu r1,-16(r1) + b 11f bl trace_hardirqs_off - addi r1,r1,16 b 12f - 11: bl trace_hardirqs_off 12: + lwz r5,24(r1) + lwz r4,20(r1) + lwz r3,16(r1) + lwz r11,12(r1) + lwz r9,8(r1) + addi r1,r1,32 lwz r0,GPR0(r1) - lwz r3,ORIG_GPR3(r1) - lwz r4,GPR4(r1) - lwz r5,GPR5(r1) lwz r6,GPR6(r1) lwz r7,GPR7(r1) lwz r8,GPR8(r1) - lwz r9,8(r1) - lwz r11,12(r1) 1: mtctr r11 mtlr r9 bctr /* jump to handler */ diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 243dbabfe74d..43eb74fcedde 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -330,14 +330,10 @@ void migrate_irqs(void) alloc_cpumask_var(&mask, GFP_KERNEL); - for_each_irq(irq) { + for_each_irq_desc(irq, desc) { struct irq_data *data; struct irq_chip *chip; - desc = irq_to_desc(irq); - if (!desc) - continue; - data = irq_desc_get_irq_data(desc); if (irqd_is_per_cpu(data)) continue; @@ -560,12 +556,6 @@ void do_softirq(void) local_irq_restore(flags); } -irq_hw_number_t irqd_to_hwirq(struct irq_data *d) -{ - return d->hwirq; -} -EXPORT_SYMBOL_GPL(irqd_to_hwirq); - irq_hw_number_t virq_to_hw(unsigned int virq) { struct irq_data *irq_data = irq_get_irq_data(virq); diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index c957b1202bdc..5df777794403 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c @@ -23,14 +23,11 @@ void machine_kexec_mask_interrupts(void) { unsigned int i; + struct irq_desc *desc; - for_each_irq(i) { - struct irq_desc *desc = irq_to_desc(i); + for_each_irq_desc(i, desc) { struct irq_chip *chip; - if (!desc) - continue; - chip = irq_desc_get_chip(desc); if (!chip) continue; diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index f88698c0f332..4937c9690090 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1235,7 +1235,7 @@ void __ppc64_runlatch_on(void) ctrl |= CTRL_RUNLATCH; mtspr(SPRN_CTRLT, ctrl); - ti->local_flags |= TLF_RUNLATCH; + ti->local_flags |= _TLF_RUNLATCH; } /* Called with hard IRQs off */ @@ -1244,7 +1244,7 @@ void __ppc64_runlatch_off(void) struct thread_info *ti = current_thread_info(); unsigned long ctrl; - ti->local_flags &= ~TLF_RUNLATCH; + ti->local_flags &= ~_TLF_RUNLATCH; ctrl = mfspr(SPRN_CTRLF); ctrl &= ~CTRL_RUNLATCH; diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 9825f29d1faf..ec8a53fa9e8f 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c @@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr) } #ifdef CONFIG_BOOKE_WDT +extern u32 booke_wdt_enabled; +extern u32 booke_wdt_period; + /* Checks wdt=x and wdt_period=xx command-line option */ notrace int __init early_parse_wdt(char *p) { diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h index af1ab5e9a691..5c3cf2d04e41 100644 --- a/arch/powerpc/net/bpf_jit.h +++ b/arch/powerpc/net/bpf_jit.h @@ -48,7 +48,13 @@ /* * Assembly helpers from arch/powerpc/net/bpf_jit.S: */ -extern u8 sk_load_word[], sk_load_half[], sk_load_byte[], sk_load_byte_msh[]; +#define DECLARE_LOAD_FUNC(func) \ + extern u8 func[], func##_negative_offset[], func##_positive_offset[] + +DECLARE_LOAD_FUNC(sk_load_word); +DECLARE_LOAD_FUNC(sk_load_half); +DECLARE_LOAD_FUNC(sk_load_byte); +DECLARE_LOAD_FUNC(sk_load_byte_msh); #define FUNCTION_DESCR_SIZE 24 diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S index ff4506e85cce..55ba3855a97f 100644 --- a/arch/powerpc/net/bpf_jit_64.S +++ b/arch/powerpc/net/bpf_jit_64.S @@ -31,14 +31,13 @@ * then branch directly to slow_path_XXX if required. (In fact, could * load a spare GPR with the address of slow_path_generic and pass size * as an argument, making the call site a mtlr, li and bllr.) - * - * Technically, the "is addr < 0" check is unnecessary & slowing down - * the ABS path, as it's statically checked on generation. */ .globl sk_load_word sk_load_word: cmpdi r_addr, 0 - blt bpf_error + blt bpf_slow_path_word_neg + .globl sk_load_word_positive_offset +sk_load_word_positive_offset: /* Are we accessing past headlen? */ subi r_scratch1, r_HL, 4 cmpd r_scratch1, r_addr @@ -51,7 +50,9 @@ sk_load_word: .globl sk_load_half sk_load_half: cmpdi r_addr, 0 - blt bpf_error + blt bpf_slow_path_half_neg + .globl sk_load_half_positive_offset +sk_load_half_positive_offset: subi r_scratch1, r_HL, 2 cmpd r_scratch1, r_addr blt bpf_slow_path_half @@ -61,7 +62,9 @@ sk_load_half: .globl sk_load_byte sk_load_byte: cmpdi r_addr, 0 - blt bpf_error + blt bpf_slow_path_byte_neg + .globl sk_load_byte_positive_offset +sk_load_byte_positive_offset: cmpd r_HL, r_addr ble bpf_slow_path_byte lbzx r_A, r_D, r_addr @@ -69,22 +72,20 @@ sk_load_byte: /* * BPF_S_LDX_B_MSH: ldxb 4*([offset]&0xf) - * r_addr is the offset value, already known positive + * r_addr is the offset value */ .globl sk_load_byte_msh sk_load_byte_msh: + cmpdi r_addr, 0 + blt bpf_slow_path_byte_msh_neg + .globl sk_load_byte_msh_positive_offset +sk_load_byte_msh_positive_offset: cmpd r_HL, r_addr ble bpf_slow_path_byte_msh lbzx r_X, r_D, r_addr rlwinm r_X, r_X, 2, 32-4-2, 31-2 blr -bpf_error: - /* Entered with cr0 = lt */ - li r3, 0 - /* Generated code will 'blt epilogue', returning 0. */ - blr - /* Call out to skb_copy_bits: * We'll need to back up our volatile regs first; we have * local variable space at r1+(BPF_PPC_STACK_BASIC). @@ -136,3 +137,84 @@ bpf_slow_path_byte_msh: lbz r_X, BPF_PPC_STACK_BASIC+(2*8)(r1) rlwinm r_X, r_X, 2, 32-4-2, 31-2 blr + +/* Call out to bpf_internal_load_pointer_neg_helper: + * We'll need to back up our volatile regs first; we have + * local variable space at r1+(BPF_PPC_STACK_BASIC). + * Allocate a new stack frame here to remain ABI-compliant in + * stashing LR. + */ +#define sk_negative_common(SIZE) \ + mflr r0; \ + std r0, 16(r1); \ + /* R3 goes in parameter space of caller's frame */ \ + std r_skb, (BPF_PPC_STACKFRAME+48)(r1); \ + std r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1); \ + std r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1); \ + stdu r1, -BPF_PPC_SLOWPATH_FRAME(r1); \ + /* R3 = r_skb, as passed */ \ + mr r4, r_addr; \ + li r5, SIZE; \ + bl bpf_internal_load_pointer_neg_helper; \ + /* R3 != 0 on success */ \ + addi r1, r1, BPF_PPC_SLOWPATH_FRAME; \ + ld r0, 16(r1); \ + ld r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1); \ + ld r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1); \ + mtlr r0; \ + cmpldi r3, 0; \ + beq bpf_error_slow; /* cr0 = EQ */ \ + mr r_addr, r3; \ + ld r_skb, (BPF_PPC_STACKFRAME+48)(r1); \ + /* Great success! */ + +bpf_slow_path_word_neg: + lis r_scratch1,-32 /* SKF_LL_OFF */ + cmpd r_addr, r_scratch1 /* addr < SKF_* */ + blt bpf_error /* cr0 = LT */ + .globl sk_load_word_negative_offset +sk_load_word_negative_offset: + sk_negative_common(4) + lwz r_A, 0(r_addr) + blr + +bpf_slow_path_half_neg: + lis r_scratch1,-32 /* SKF_LL_OFF */ + cmpd r_addr, r_scratch1 /* addr < SKF_* */ + blt bpf_error /* cr0 = LT */ + .globl sk_load_half_negative_offset +sk_load_half_negative_offset: + sk_negative_common(2) + lhz r_A, 0(r_addr) + blr + +bpf_slow_path_byte_neg: + lis r_scratch1,-32 /* SKF_LL_OFF */ + cmpd r_addr, r_scratch1 /* addr < SKF_* */ + blt bpf_error /* cr0 = LT */ + .globl sk_load_byte_negative_offset +sk_load_byte_negative_offset: + sk_negative_common(1) + lbz r_A, 0(r_addr) + blr + +bpf_slow_path_byte_msh_neg: + lis r_scratch1,-32 /* SKF_LL_OFF */ + cmpd r_addr, r_scratch1 /* addr < SKF_* */ + blt bpf_error /* cr0 = LT */ + .globl sk_load_byte_msh_negative_offset +sk_load_byte_msh_negative_offset: + sk_negative_common(1) + lbz r_X, 0(r_addr) + rlwinm r_X, r_X, 2, 32-4-2, 31-2 + blr + +bpf_error_slow: + /* fabricate a cr0 = lt */ + li r_scratch1, -1 + cmpdi r_scratch1, 0 +bpf_error: + /* Entered with cr0 = lt */ + li r3, 0 + /* Generated code will 'blt epilogue', returning 0. */ + blr diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c index 73619d3aeb6c..2dc8b1484845 100644 --- a/arch/powerpc/net/bpf_jit_comp.c +++ b/arch/powerpc/net/bpf_jit_comp.c @@ -127,6 +127,9 @@ static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx) PPC_BLR(); } +#define CHOOSE_LOAD_FUNC(K, func) \ + ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset) + /* Assemble the body code between the prologue & epilogue. */ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image, struct codegen_context *ctx, @@ -391,21 +394,16 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image, /*** Absolute loads from packet header/data ***/ case BPF_S_LD_W_ABS: - func = sk_load_word; + func = CHOOSE_LOAD_FUNC(K, sk_load_word); goto common_load; case BPF_S_LD_H_ABS: - func = sk_load_half; + func = CHOOSE_LOAD_FUNC(K, sk_load_half); goto common_load; case BPF_S_LD_B_ABS: - func = sk_load_byte; + func = CHOOSE_LOAD_FUNC(K, sk_load_byte); common_load: - /* - * Load from [K]. Reference with the (negative) - * SKF_NET_OFF/SKF_LL_OFF offsets is unsupported. - */ + /* Load from [K]. */ ctx->seen |= SEEN_DATAREF; - if ((int)K < 0) - return -ENOTSUPP; PPC_LI64(r_scratch1, func); PPC_MTLR(r_scratch1); PPC_LI32(r_addr, K); @@ -429,7 +427,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image, common_load_ind: /* * Load from [X + K]. Negative offsets are tested for - * in the helper functions, and result in a 'ret 0'. + * in the helper functions. */ ctx->seen |= SEEN_DATAREF | SEEN_XREG; PPC_LI64(r_scratch1, func); @@ -443,13 +441,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image, break; case BPF_S_LDX_B_MSH: - /* - * x86 version drops packet (RET 0) when K<0, whereas - * interpreter does allow K<0 (__load_pointer, special - * ancillary data). common_load returns ENOTSUPP if K<0, - * so we fall back to interpreter & filter works. - */ - func = sk_load_byte_msh; + func = CHOOSE_LOAD_FUNC(K, sk_load_byte_msh); goto common_load; break; diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c index 9fef5302adc1..67dac22b4363 100644 --- a/arch/powerpc/platforms/85xx/common.c +++ b/arch/powerpc/platforms/85xx/common.c @@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = { { .compatible = "fsl,qe", }, { .compatible = "fsl,cpm2", }, { .compatible = "fsl,srio", }, + /* So that the DMA channel nodes can be probed individually: */ + { .compatible = "fsl,eloplus-dma", }, + /* For the PMC driver */ + { .compatible = "fsl,mpc8548-guts", }, + /* Probably unnecessary? */ + { .compatible = "gpio-leds", }, {}, }; diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 9a6f04406e0d..d208ebccb91c 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -399,12 +399,6 @@ static int __init board_fixups(void) machine_arch_initcall(mpc8568_mds, board_fixups); machine_arch_initcall(mpc8569_mds, board_fixups); -static struct of_device_id mpc85xx_ids[] = { - { .compatible = "fsl,mpc8548-guts", }, - { .compatible = "gpio-leds", }, - {}, -}; - static int __init mpc85xx_publish_devices(void) { if (machine_is(mpc8568_mds)) @@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void) if (machine_is(mpc8569_mds)) simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio"); - mpc85xx_common_publish_devices(); - of_platform_bus_probe(NULL, mpc85xx_ids, NULL); - - return 0; + return mpc85xx_common_publish_devices(); } machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index e74b7cde9aee..f700c81a1321 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c @@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void) pr_info("Freescale P1022 DS reference board\n"); } -static struct of_device_id __initdata p1022_ds_ids[] = { - /* So that the DMA channel nodes can be probed individually: */ - { .compatible = "fsl,eloplus-dma", }, - {}, -}; - -static int __init p1022_ds_publish_devices(void) -{ - mpc85xx_common_publish_devices(); - return of_platform_bus_probe(NULL, p1022_ds_ids, NULL); -} -machine_device_initcall(p1022_ds, p1022_ds_publish_devices); +machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices); machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier); diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index db360fc4cf0e..85825b5401e5 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c @@ -114,7 +114,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) pr_devel("axon_msi: woff %x roff %x msi %x\n", write_offset, msic->read_offset, msi); - if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) { + if (msi < nr_irqs && irq_get_chip_data(msi) == msic) { generic_handle_irq(msi); msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); } else { @@ -276,9 +276,6 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) if (rc) return rc; - /* We rely on being able to stash a virq in a u16 */ - BUILD_BUG_ON(NR_IRQS > 65536); - list_for_each_entry(entry, &dev->msi_list, list) { virq = irq_create_direct_mapping(msic->irq_domain); if (virq == NO_IRQ) { @@ -392,7 +389,8 @@ static int axon_msi_probe(struct platform_device *device) } memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES); - msic->irq_domain = irq_domain_add_nomap(dn, &msic_host_ops, msic); + /* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */ + msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic); if (!msic->irq_domain) { printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n", dn->full_name); diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c index e5c3a2c6090d..8c6dc42ecf65 100644 --- a/arch/powerpc/platforms/cell/beat_interrupt.c +++ b/arch/powerpc/platforms/cell/beat_interrupt.c @@ -239,7 +239,7 @@ void __init beatic_init_IRQ(void) ppc_md.get_irq = beatic_get_irq; /* Allocate an irq host */ - beatic_host = irq_domain_add_nomap(NULL, &beatic_pic_host_ops, NULL); + beatic_host = irq_domain_add_nomap(NULL, 0, &beatic_pic_host_ops, NULL); BUG_ON(beatic_host == NULL); irq_set_default_host(beatic_host); } @@ -248,6 +248,6 @@ void beatic_deinit_IRQ(void) { int i; - for (i = 1; i < NR_IRQS; i++) + for (i = 1; i < nr_irqs; i++) beat_destruct_irq_plug(i); } diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c index 996c5ff7824b..03685a329d7d 100644 --- a/arch/powerpc/platforms/powermac/low_i2c.c +++ b/arch/powerpc/platforms/powermac/low_i2c.c @@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data) unsigned long flags; spin_lock_irqsave(&host->lock, flags); + + /* + * If the timer is pending, that means we raced with the + * irq, in which case we just return + */ + if (timer_pending(&host->timeout_timer)) + goto skip; + kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr)); if (host->state != state_idle) { host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT; add_timer(&host->timeout_timer); } + skip: spin_unlock_irqrestore(&host->lock, flags); } diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index 66ad93de1d55..c4e630576ff2 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c @@ -57,9 +57,9 @@ static int max_real_irqs; static DEFINE_RAW_SPINLOCK(pmac_pic_lock); -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) -static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; -static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; +/* The max irq number this driver deals with is 128; see max_irqs */ +static DECLARE_BITMAP(ppc_lost_interrupts, 128); +static DECLARE_BITMAP(ppc_cached_irq_mask, 128); static int pmac_irq_cascade = -1; static struct irq_domain *pmac_pic_host; diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index a81e5a88fbdf..b4ddaa3fbb29 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -192,7 +192,7 @@ static int psurge_secondary_ipi_init(void) { int rc = -ENOMEM; - psurge_host = irq_domain_add_nomap(NULL, &psurge_host_ops, NULL); + psurge_host = irq_domain_add_nomap(NULL, 0, &psurge_host_ops, NULL); if (psurge_host) psurge_secondary_virq = irq_create_direct_mapping(psurge_host); diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c index 2a4ff86cc21f..5f3b23220b8e 100644 --- a/arch/powerpc/platforms/ps3/interrupt.c +++ b/arch/powerpc/platforms/ps3/interrupt.c @@ -753,9 +753,8 @@ void __init ps3_init_IRQ(void) unsigned cpu; struct irq_domain *host; - host = irq_domain_add_nomap(NULL, &ps3_host_ops, NULL); + host = irq_domain_add_nomap(NULL, PS3_PLUG_MAX + 1, &ps3_host_ops, NULL); irq_set_default_host(host); - irq_set_virq_count(PS3_PLUG_MAX + 1); for_each_possible_cpu(cpu) { struct ps3_private *pd = &per_cpu(ps3_private, cpu); diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig index aadbe4f6d537..178a5f300bc9 100644 --- a/arch/powerpc/platforms/pseries/Kconfig +++ b/arch/powerpc/platforms/pseries/Kconfig @@ -30,9 +30,9 @@ config PPC_SPLPAR two or more partitions. config EEH - bool "PCI Extended Error Handling (EEH)" if EXPERT + bool depends on PPC_PSERIES && PCI - default y if !EXPERT + default y config PSERIES_MSI bool diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c index 309d38ef7322..a75e37dc41aa 100644 --- a/arch/powerpc/platforms/pseries/eeh.c +++ b/arch/powerpc/platforms/pseries/eeh.c @@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev) pr_debug("EEH: Adding device %s\n", pci_name(dev)); dn = pci_device_to_OF_node(dev); - edev = pci_dev_to_eeh_dev(dev); + edev = of_node_to_eeh_dev(dn); if (edev->pdev == dev) { pr_debug("EEH: Already referenced !\n"); return; diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c index d3be961e2ae7..10386b676d87 100644 --- a/arch/powerpc/sysdev/cpm2_pic.c +++ b/arch/powerpc/sysdev/cpm2_pic.c @@ -51,8 +51,7 @@ static intctl_cpm2_t __iomem *cpm2_intctl; static struct irq_domain *cpm2_pic_host; -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) -static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; +static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */ static const u_char irq_to_siureg[] = { 1, 1, 1, 1, 1, 1, 1, 1, diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c index d5f5416be310..b724622c3a0b 100644 --- a/arch/powerpc/sysdev/mpc8xx_pic.c +++ b/arch/powerpc/sysdev/mpc8xx_pic.c @@ -18,69 +18,45 @@ extern int cpm_get_irq(struct pt_regs *regs); static struct irq_domain *mpc8xx_pic_host; -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) -static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; +static unsigned long mpc8xx_cached_irq_mask; static sysconf8xx_t __iomem *siu_reg; -int cpm_get_irq(struct pt_regs *regs); +static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d) +{ + return 0x80000000 >> irqd_to_hwirq(d); +} static void mpc8xx_unmask_irq(struct irq_data *d) { - int bit, word; - unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] |= (1 << (31-bit)); - out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); + mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); + out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); } static void mpc8xx_mask_irq(struct irq_data *d) { - int bit, word; - unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] &= ~(1 << (31-bit)); - out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); + mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d); + out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); } static void mpc8xx_ack(struct irq_data *d) { - int bit; - unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); - - bit = irq_nr & 0x1f; - out_be32(&siu_reg->sc_sipend, 1 << (31-bit)); + out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d)); } static void mpc8xx_end_irq(struct irq_data *d) { - int bit, word; - unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d); - - bit = irq_nr & 0x1f; - word = irq_nr >> 5; - - ppc_cached_irq_mask[word] |= (1 << (31-bit)); - out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); + mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d); + out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask); } static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) { - if (flow_type & IRQ_TYPE_EDGE_FALLING) { - irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d); + /* only external IRQ senses are programmable */ + if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) { unsigned int siel = in_be32(&siu_reg->sc_siel); - - /* only external IRQ senses are programmable */ - if ((hw & 1) == 0) { - siel |= (0x80000000 >> hw); - out_be32(&siu_reg->sc_siel, siel); - __irq_set_handler_locked(d->irq, handle_edge_irq); - } + siel |= mpc8xx_irqd_to_bit(d); + out_be32(&siu_reg->sc_siel, siel); + __irq_set_handler_locked(d->irq, handle_edge_irq); } return 0; } @@ -132,6 +108,9 @@ static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct, IRQ_TYPE_EDGE_FALLING, }; + if (intspec[0] > 0x1f) + return 0; + *out_hwirq = intspec[0]; if (intsize > 1 && intspec[1] < 4) *out_flags = map_pic_senses[intspec[1]]; diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 9ac71ebd2c40..395af1347749 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq) } /* Determine if the linux irq is an IPI */ -static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) +static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src) { - unsigned int src = virq_to_hw(irq); - return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); } /* Determine if the linux irq is a timer */ -static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq) +static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src) { - unsigned int src = virq_to_hw(irq); - return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); } @@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) if (src >= mpic->num_sources) return -EINVAL; + vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); + + /* We don't support "none" type */ if (flow_type == IRQ_TYPE_NONE) - if (mpic->senses && src < mpic->senses_count) - flow_type = mpic->senses[src]; - if (flow_type == IRQ_TYPE_NONE) - flow_type = IRQ_TYPE_LEVEL_LOW; + flow_type = IRQ_TYPE_DEFAULT; + + /* Default: read HW settings */ + if (flow_type == IRQ_TYPE_DEFAULT) { + switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) | + MPIC_INFO(VECPRI_SENSE_MASK))) { + case MPIC_INFO(VECPRI_SENSE_EDGE) | + MPIC_INFO(VECPRI_POLARITY_POSITIVE): + flow_type = IRQ_TYPE_EDGE_RISING; + break; + case MPIC_INFO(VECPRI_SENSE_EDGE) | + MPIC_INFO(VECPRI_POLARITY_NEGATIVE): + flow_type = IRQ_TYPE_EDGE_FALLING; + break; + case MPIC_INFO(VECPRI_SENSE_LEVEL) | + MPIC_INFO(VECPRI_POLARITY_POSITIVE): + flow_type = IRQ_TYPE_LEVEL_HIGH; + break; + case MPIC_INFO(VECPRI_SENSE_LEVEL) | + MPIC_INFO(VECPRI_POLARITY_NEGATIVE): + flow_type = IRQ_TYPE_LEVEL_LOW; + break; + } + } + /* Apply to irq desc */ irqd_set_trigger_type(d, flow_type); + /* Apply to HW */ if (mpic_is_ht_interrupt(mpic, src)) vecpri = MPIC_VECPRI_POLARITY_POSITIVE | MPIC_VECPRI_SENSE_EDGE; else vecpri = mpic_type_to_vecpri(mpic, flow_type); - vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | MPIC_INFO(VECPRI_SENSE_MASK)); vnew |= vecpri; @@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq, irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); /* Set default irq type */ - irq_set_irq_type(virq, IRQ_TYPE_NONE); + irq_set_irq_type(virq, IRQ_TYPE_DEFAULT); /* If the MPIC was reset, then all vectors have already been * initialized. Otherwise, a per source lazy initialization @@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, mpic->num_sources = isu_first + mpic->isu_size; } -void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count) -{ - mpic->senses = senses; - mpic->senses_count = count; -} - void __init mpic_init(struct mpic *mpic) { int i, cpu; @@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri) return; raw_spin_lock_irqsave(&mpic_lock, flags); - if (mpic_is_ipi(mpic, irq)) { + if (mpic_is_ipi(mpic, src)) { reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & ~MPIC_VECPRI_PRIORITY_MASK; mpic_ipi_write(src - mpic->ipi_vecs[0], reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); - } else if (mpic_is_tm(mpic, irq)) { + } else if (mpic_is_tm(mpic, src)) { reg = mpic_tm_read(src - mpic->timer_vecs[0]) & ~MPIC_VECPRI_PRIORITY_MASK; mpic_tm_write(src - mpic->timer_vecs[0], diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c index 6e7fa386e76a..483d8fa72e8b 100644 --- a/arch/powerpc/sysdev/mpic_msgr.c +++ b/arch/powerpc/sysdev/mpic_msgr.c @@ -27,6 +27,7 @@ static struct mpic_msgr **mpic_msgrs; static unsigned int mpic_msgr_count; +static DEFINE_RAW_SPINLOCK(msgrs_lock); static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value) { @@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num) if (reg_num >= mpic_msgr_count) return ERR_PTR(-ENODEV); - raw_spin_lock_irqsave(&msgr->lock, flags); - if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) { - msgr = mpic_msgrs[reg_num]; + raw_spin_lock_irqsave(&msgrs_lock, flags); + msgr = mpic_msgrs[reg_num]; + if (msgr->in_use == MSGR_FREE) msgr->in_use = MSGR_INUSE; - } - raw_spin_unlock_irqrestore(&msgr->lock, flags); + raw_spin_unlock_irqrestore(&msgrs_lock, flags); return msgr; } @@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev) reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i; msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE; - msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET; + msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET); msgr->in_use = MSGR_FREE; msgr->num = i; raw_spin_lock_init(&msgr->lock); diff --git a/arch/powerpc/sysdev/scom.c b/arch/powerpc/sysdev/scom.c index 49a3ece1c6b3..702256a1ca11 100644 --- a/arch/powerpc/sysdev/scom.c +++ b/arch/powerpc/sysdev/scom.c @@ -22,6 +22,7 @@ #include <linux/debugfs.h> #include <linux/slab.h> #include <linux/export.h> +#include <asm/debug.h> #include <asm/prom.h> #include <asm/scom.h> diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c index ea5e204e3450..cd1d18db92c6 100644 --- a/arch/powerpc/sysdev/xics/xics-common.c +++ b/arch/powerpc/sysdev/xics/xics-common.c @@ -188,6 +188,7 @@ void xics_migrate_irqs_away(void) { int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); unsigned int irq, virq; + struct irq_desc *desc; /* If we used to be the default server, move to the new "boot_cpuid" */ if (hw_cpu == xics_default_server) @@ -202,8 +203,7 @@ void xics_migrate_irqs_away(void) /* Allow IPIs again... */ icp_ops->set_priority(DEFAULT_PRIORITY); - for_each_irq(virq) { - struct irq_desc *desc; + for_each_irq_desc(virq, desc) { struct irq_chip *chip; long server; unsigned long flags; @@ -212,9 +212,8 @@ void xics_migrate_irqs_away(void) /* We can't set affinity on ISA interrupts */ if (virq < NUM_ISA_INTERRUPTS) continue; - desc = irq_to_desc(virq); /* We only need to migrate enabled IRQS */ - if (!desc || !desc->action) + if (!desc->action) continue; if (desc->irq_data.domain != xics_host) continue; diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 2b7c0fbe578e..9015060919a0 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -90,7 +90,6 @@ config S390 select HAVE_KERNEL_XZ select HAVE_ARCH_MUTEX_CPU_RELAX select HAVE_ARCH_JUMP_LABEL if !MARCH_G5 - select HAVE_RCU_TABLE_FREE if SMP select ARCH_SAVE_PAGE_KEYS if HIBERNATION select HAVE_MEMBLOCK select HAVE_MEMBLOCK_NODE_MAP diff --git a/arch/s390/defconfig b/arch/s390/defconfig index 6cf8e26b3137..1957a9dd256d 100644 --- a/arch/s390/defconfig +++ b/arch/s390/defconfig @@ -1,8 +1,12 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y CONFIG_AUDIT=y -CONFIG_RCU_TRACE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y @@ -14,16 +18,22 @@ CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y CONFIG_BLK_CGROUP=y +CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_EXPERT=y # CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_OPROFILE=y CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_IBM_PARTITION=y CONFIG_DEFAULT_DEADLINE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -34,18 +44,15 @@ CONFIG_KSM=y CONFIG_BINFMT_MISC=m CONFIG_CMM=m CONFIG_HZ_100=y -CONFIG_KEXEC=y -CONFIG_PM=y +CONFIG_CRASH_DUMP=y CONFIG_HIBERNATION=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_NET_KEY=y -CONFIG_AFIUCV=m CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_INET_LRO is not set CONFIG_IPV6=y -CONFIG_NET_SCTPPROBE=m CONFIG_L2TP=m CONFIG_L2TP_DEBUGFS=m CONFIG_VLAN_8021Q=y @@ -84,15 +91,14 @@ CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_ZFCP=y -CONFIG_ZFCP_DIF=y CONFIG_NETDEVICES=y -CONFIG_DUMMY=m CONFIG_BONDING=m +CONFIG_DUMMY=m CONFIG_EQUALIZER=m CONFIG_TUN=m -CONFIG_NET_ETHERNET=y CONFIG_VIRTIO_NET=y CONFIG_RAW_DRIVER=m +CONFIG_VIRTIO_BALLOON=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set @@ -103,27 +109,21 @@ CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_IBM_PARTITION=y -CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y CONFIG_PROVE_RCU=y CONFIG_LOCK_STAT=y CONFIG_DEBUG_LOCKDEP=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_LIST=y CONFIG_DEBUG_NOTIFIERS=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_RCU_TRACE=y CONFIG_KPROBES_SANITY_TEST=y CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y CONFIG_CPU_NOTIFIER_ERROR_INJECT=m CONFIG_LATENCYTOP=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_PAGEALLOC=y -# CONFIG_FTRACE is not set +CONFIG_BLK_DEV_IO_TRACE=y # CONFIG_STRICT_DEVMEM is not set CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m @@ -173,4 +173,3 @@ CONFIG_CRYPTO_SHA512_S390=m CONFIG_CRYPTO_DES_S390=m CONFIG_CRYPTO_AES_S390=m CONFIG_CRC7=m -CONFIG_VIRTIO_BALLOON=y diff --git a/arch/s390/include/asm/facility.h b/arch/s390/include/asm/facility.h index 1e5b27edc0c9..2ee66a65f2d4 100644 --- a/arch/s390/include/asm/facility.h +++ b/arch/s390/include/asm/facility.h @@ -38,12 +38,11 @@ static inline void stfle(u64 *stfle_fac_list, int size) unsigned long nr; preempt_disable(); - S390_lowcore.stfl_fac_list = 0; asm volatile( " .insn s,0xb2b10000,0(0)\n" /* stfl */ "0:\n" EX_TABLE(0b, 0b) - : "=m" (S390_lowcore.stfl_fac_list)); + : "+m" (S390_lowcore.stfl_fac_list)); nr = 4; /* bytes stored by stfl */ memcpy(stfle_fac_list, &S390_lowcore.stfl_fac_list, 4); if (S390_lowcore.stfl_fac_list & 0x01000000) { diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h index 8eef9b5b3cf4..78e3041919de 100644 --- a/arch/s390/include/asm/pgalloc.h +++ b/arch/s390/include/asm/pgalloc.h @@ -22,10 +22,7 @@ void crst_table_free(struct mm_struct *, unsigned long *); unsigned long *page_table_alloc(struct mm_struct *, unsigned long); void page_table_free(struct mm_struct *, unsigned long *); -#ifdef CONFIG_HAVE_RCU_TABLE_FREE void page_table_free_rcu(struct mmu_gather *, unsigned long *); -void __tlb_remove_table(void *_table); -#endif static inline void clear_table(unsigned long *s, unsigned long val, size_t n) { diff --git a/arch/s390/include/asm/swab.h b/arch/s390/include/asm/swab.h index 6bdee21c077e..a3e4ebb32090 100644 --- a/arch/s390/include/asm/swab.h +++ b/arch/s390/include/asm/swab.h @@ -77,7 +77,7 @@ static inline __u16 __arch_swab16p(const __u16 *x) asm volatile( #ifndef __s390x__ - " icm %0,2,%O+1(%R1)\n" + " icm %0,2,%O1+1(%R1)\n" " ic %0,%1\n" : "=&d" (result) : "Q" (*x) : "cc"); #else /* __s390x__ */ diff --git a/arch/s390/include/asm/tlb.h b/arch/s390/include/asm/tlb.h index c687a2c83462..775a5eea8f9e 100644 --- a/arch/s390/include/asm/tlb.h +++ b/arch/s390/include/asm/tlb.h @@ -30,14 +30,10 @@ struct mmu_gather { struct mm_struct *mm; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE struct mmu_table_batch *batch; -#endif unsigned int fullmm; - unsigned int need_flush; }; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE struct mmu_table_batch { struct rcu_head rcu; unsigned int nr; @@ -49,7 +45,6 @@ struct mmu_table_batch { extern void tlb_table_flush(struct mmu_gather *tlb); extern void tlb_remove_table(struct mmu_gather *tlb, void *table); -#endif static inline void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, @@ -57,29 +52,20 @@ static inline void tlb_gather_mmu(struct mmu_gather *tlb, { tlb->mm = mm; tlb->fullmm = full_mm_flush; - tlb->need_flush = 0; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE tlb->batch = NULL; -#endif if (tlb->fullmm) __tlb_flush_mm(mm); } static inline void tlb_flush_mmu(struct mmu_gather *tlb) { - if (!tlb->need_flush) - return; - tlb->need_flush = 0; - __tlb_flush_mm(tlb->mm); -#ifdef CONFIG_HAVE_RCU_TABLE_FREE tlb_table_flush(tlb); -#endif } static inline void tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end) { - tlb_flush_mmu(tlb); + tlb_table_flush(tlb); } /* @@ -105,10 +91,8 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page) static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long address) { -#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return page_table_free_rcu(tlb, (unsigned long *) pte); -#endif page_table_free(tlb->mm, (unsigned long *) pte); } @@ -125,10 +109,8 @@ static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd, #ifdef __s390x__ if (tlb->mm->context.asce_limit <= (1UL << 31)) return; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return tlb_remove_table(tlb, pmd); -#endif crst_table_free(tlb->mm, (unsigned long *) pmd); #endif } @@ -146,10 +128,8 @@ static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud, #ifdef __s390x__ if (tlb->mm->context.asce_limit <= (1UL << 42)) return; -#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return tlb_remove_table(tlb, pud); -#endif crst_table_free(tlb->mm, (unsigned long *) pud); #endif } diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S index c27a0727f930..adccd908ebc7 100644 --- a/arch/s390/kernel/head.S +++ b/arch/s390/kernel/head.S @@ -474,9 +474,9 @@ ENTRY(startup_kdump) stck __LC_LAST_UPDATE_CLOCK spt 5f-.LPG0(%r13) mvc __LC_LAST_UPDATE_TIMER(8),5f-.LPG0(%r13) + xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST #ifndef CONFIG_MARCH_G5 # check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10} - xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST .insn s,0xb2b10000,__LC_STFL_FAC_LIST # store facility list tm __LC_STFL_FAC_LIST,0x01 # stfle available ? jz 0f diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c index 1c2cdd59ccd0..8a22c27219dd 100644 --- a/arch/s390/kernel/irq.c +++ b/arch/s390/kernel/irq.c @@ -118,9 +118,10 @@ asmlinkage void do_softirq(void) "a" (__do_softirq) : "0", "1", "2", "3", "4", "5", "14", "cc", "memory" ); - } else + } else { /* We are already on the async stack. */ __do_softirq(); + } } local_irq_restore(flags); @@ -192,11 +193,12 @@ int unregister_external_interrupt(u16 code, ext_int_handler_t handler) int index = ext_hash(code); spin_lock_irqsave(&ext_int_hash_lock, flags); - list_for_each_entry_rcu(p, &ext_int_hash[index], entry) + list_for_each_entry_rcu(p, &ext_int_hash[index], entry) { if (p->code == code && p->handler == handler) { list_del_rcu(&p->entry); kfree_rcu(p, rcu); } + } spin_unlock_irqrestore(&ext_int_hash_lock, flags); return 0; } @@ -211,9 +213,10 @@ void __irq_entry do_extint(struct pt_regs *regs, struct ext_code ext_code, old_regs = set_irq_regs(regs); irq_enter(); - if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) + if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) { /* Serve timer interrupts first. */ clock_comparator_work(); + } kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++; if (ext_code.code != 0x1004) __get_cpu_var(s390_idle).nohz_delay = 1; diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c index 46405086479c..cb019f429e88 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -178,7 +178,7 @@ static void cpumf_pmu_enable(struct pmu *pmu) err = lcctl(cpuhw->state); if (err) { pr_err("Enabling the performance measuring unit " - "failed with rc=%lx\n", err); + "failed with rc=%x\n", err); return; } @@ -203,7 +203,7 @@ static void cpumf_pmu_disable(struct pmu *pmu) err = lcctl(inactive); if (err) { pr_err("Disabling the performance measuring unit " - "failed with rc=%lx\n", err); + "failed with rc=%x\n", err); return; } diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c index 7bb15fcca75e..e1335dc2b1b7 100644 --- a/arch/s390/mm/maccess.c +++ b/arch/s390/mm/maccess.c @@ -61,21 +61,14 @@ long probe_kernel_write(void *dst, const void *src, size_t size) return copied < 0 ? -EFAULT : 0; } -/* - * Copy memory in real mode (kernel to kernel) - */ -int memcpy_real(void *dest, void *src, size_t count) +static int __memcpy_real(void *dest, void *src, size_t count) { register unsigned long _dest asm("2") = (unsigned long) dest; register unsigned long _len1 asm("3") = (unsigned long) count; register unsigned long _src asm("4") = (unsigned long) src; register unsigned long _len2 asm("5") = (unsigned long) count; - unsigned long flags; int rc = -EFAULT; - if (!count) - return 0; - flags = __arch_local_irq_stnsm(0xf8UL); asm volatile ( "0: mvcle %1,%2,0x0\n" "1: jo 0b\n" @@ -86,7 +79,23 @@ int memcpy_real(void *dest, void *src, size_t count) "+d" (_len2), "=m" (*((long *) dest)) : "m" (*((long *) src)) : "cc", "memory"); - arch_local_irq_restore(flags); + return rc; +} + +/* + * Copy memory in real mode (kernel to kernel) + */ +int memcpy_real(void *dest, void *src, size_t count) +{ + unsigned long flags; + int rc; + + if (!count) + return 0; + local_irq_save(flags); + __arch_local_irq_stnsm(0xfbUL); + rc = __memcpy_real(dest, src, count); + local_irq_restore(flags); return rc; } diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 373adf69b01c..6e765bf00670 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -678,8 +678,6 @@ void page_table_free(struct mm_struct *mm, unsigned long *table) } } -#ifdef CONFIG_HAVE_RCU_TABLE_FREE - static void __page_table_free_rcu(void *table, unsigned bit) { struct page *page; @@ -733,7 +731,66 @@ void __tlb_remove_table(void *_table) free_pages((unsigned long) table, ALLOC_ORDER); } -#endif +static void tlb_remove_table_smp_sync(void *arg) +{ + /* Simply deliver the interrupt */ +} + +static void tlb_remove_table_one(void *table) +{ + /* + * This isn't an RCU grace period and hence the page-tables cannot be + * assumed to be actually RCU-freed. + * + * It is however sufficient for software page-table walkers that rely + * on IRQ disabling. See the comment near struct mmu_table_batch. + */ + smp_call_function(tlb_remove_table_smp_sync, NULL, 1); + __tlb_remove_table(table); +} + +static void tlb_remove_table_rcu(struct rcu_head *head) +{ + struct mmu_table_batch *batch; + int i; + + batch = container_of(head, struct mmu_table_batch, rcu); + + for (i = 0; i < batch->nr; i++) + __tlb_remove_table(batch->tables[i]); + + free_page((unsigned long)batch); +} + +void tlb_table_flush(struct mmu_gather *tlb) +{ + struct mmu_table_batch **batch = &tlb->batch; + + if (*batch) { + __tlb_flush_mm(tlb->mm); + call_rcu_sched(&(*batch)->rcu, tlb_remove_table_rcu); + *batch = NULL; + } +} + +void tlb_remove_table(struct mmu_gather *tlb, void *table) +{ + struct mmu_table_batch **batch = &tlb->batch; + + if (*batch == NULL) { + *batch = (struct mmu_table_batch *) + __get_free_page(GFP_NOWAIT | __GFP_NOWARN); + if (*batch == NULL) { + __tlb_flush_mm(tlb->mm); + tlb_remove_table_one(table); + return; + } + (*batch)->nr = 0; + } + (*batch)->tables[(*batch)->nr++] = table; + if ((*batch)->nr == MAX_TABLE_BATCH) + tlb_table_flush(tlb); +} /* * switch on pgstes for its userspace process (for kvm) diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h index 37f2f4a55231..f4c1c20bcdf6 100644 --- a/arch/sh/include/asm/atomic.h +++ b/arch/sh/include/asm/atomic.h @@ -11,7 +11,7 @@ #include <linux/types.h> #include <asm/cmpxchg.h> -#define ATOMIC_INIT(i) ( (atomic_t) { (i) } ) +#define ATOMIC_INIT(i) { (i) } #define atomic_read(v) (*(volatile int *)&(v)->counter) #define atomic_set(v,i) ((v)->counter = (i)) diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 324eef93c900..e99b104d967a 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -86,7 +86,7 @@ static noinline int vmalloc_fault(unsigned long address) pte_t *pte_k; /* Make sure we are in vmalloc/module/P3 area: */ - if (!(address >= VMALLOC_START && address < P3_ADDR_MAX)) + if (!(address >= P3SEG && address < P3_ADDR_MAX)) return -1; /* diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c index fea13c7b1aee..b93c2c9ccb1d 100644 --- a/arch/sparc/kernel/ds.c +++ b/arch/sparc/kernel/ds.c @@ -1264,4 +1264,4 @@ static int __init ds_init(void) return vio_register_driver(&ds_driver); } -subsys_initcall(ds_init); +fs_initcall(ds_init); diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c index aba6b958b2a5..19f56058742b 100644 --- a/arch/sparc/kernel/leon_pci.c +++ b/arch/sparc/kernel/leon_pci.c @@ -45,7 +45,6 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info) void __devinit pcibios_fixup_bus(struct pci_bus *pbus) { - struct leon_pci_info *info = pbus->sysdata; struct pci_dev *dev; int i, has_io, has_mem; u16 cmd; @@ -111,18 +110,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pci_enable_resources(dev, mask); } -struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) -{ - /* - * Currently the OpenBoot nodes are not connected with the PCI device, - * this is because the LEON PROM does not create PCI nodes. Eventually - * this will change and the same approach as pcic.c can be used to - * match PROM nodes with pci devices. - */ - return NULL; -} -EXPORT_SYMBOL(pci_device_to_OF_node); - void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) { #ifdef CONFIG_PCI_DEBUG diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c index 1210fde18740..160cac9c4036 100644 --- a/arch/sparc/kernel/leon_smp.c +++ b/arch/sparc/kernel/leon_smp.c @@ -23,6 +23,7 @@ #include <linux/pm.h> #include <linux/delay.h> #include <linux/gfp.h> +#include <linux/cpu.h> #include <asm/cacheflush.h> #include <asm/tlbflush.h> @@ -78,6 +79,8 @@ void __cpuinit leon_callin(void) local_flush_tlb_all(); leon_configure_cache_smp(); + notify_cpu_starting(cpuid); + /* Get our local ticker going. */ smp_setup_percpu_timer(); diff --git a/arch/sparc/kernel/rtrap_64.S b/arch/sparc/kernel/rtrap_64.S index 77f1b95e0806..9171fc238def 100644 --- a/arch/sparc/kernel/rtrap_64.S +++ b/arch/sparc/kernel/rtrap_64.S @@ -20,11 +20,6 @@ .text .align 32 -__handle_softirq: - call do_softirq - nop - ba,a,pt %xcc, __handle_softirq_continue - nop __handle_preemption: call schedule wrpr %g0, RTRAP_PSTATE, %pstate @@ -89,9 +84,7 @@ rtrap: cmp %l1, 0 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */ - bne,pn %icc, __handle_softirq ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 -__handle_softirq_continue: rtrap_xcall: sethi %hi(0xf << 20), %l4 and %l1, %l4, %l4 diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c index 232df9949530..3ee51f189a55 100644 --- a/arch/sparc/kernel/sys_sparc_64.c +++ b/arch/sparc/kernel/sys_sparc_64.c @@ -566,15 +566,10 @@ out: SYSCALL_DEFINE2(64_munmap, unsigned long, addr, size_t, len) { - long ret; - if (invalid_64bit_range(addr, len)) return -EINVAL; - down_write(¤t->mm->mmap_sem); - ret = do_munmap(current->mm, addr, len); - up_write(¤t->mm->mmap_sem); - return ret; + return vm_munmap(addr, len); } extern unsigned long do_mremap(unsigned long addr, diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c index 7705c6731e28..df3155a17991 100644 --- a/arch/sparc/mm/fault_32.c +++ b/arch/sparc/mm/fault_32.c @@ -225,6 +225,8 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write, unsigned long g2; int from_user = !(regs->psr & PSR_PS); int fault, code; + unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | + (write ? FAULT_FLAG_WRITE : 0)); if(text_fault) address = regs->pc; @@ -251,6 +253,7 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write, perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address); +retry: down_read(&mm->mmap_sem); /* @@ -289,7 +292,11 @@ good_area: * make sure we exit gracefully rather than endlessly redo * the fault. */ - fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0); + fault = handle_mm_fault(mm, vma, address, flags); + + if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) + return; + if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -297,13 +304,29 @@ good_area: goto do_sigbus; BUG(); } - if (fault & VM_FAULT_MAJOR) { - current->maj_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address); - } else { - current->min_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address); + + if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (fault & VM_FAULT_MAJOR) { + current->maj_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, + 1, regs, address); + } else { + current->min_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, + 1, regs, address); + } + if (fault & VM_FAULT_RETRY) { + flags &= ~FAULT_FLAG_ALLOW_RETRY; + + /* No need to up_read(&mm->mmap_sem) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; + } } + up_read(&mm->mmap_sem); return; diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c index 504c0622f729..1fe0429b6314 100644 --- a/arch/sparc/mm/fault_64.c +++ b/arch/sparc/mm/fault_64.c @@ -279,6 +279,7 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs) unsigned int insn = 0; int si_code, fault_code, fault; unsigned long address, mm_rss; + unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; fault_code = get_thread_fault_code(); @@ -333,6 +334,8 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs) insn = get_fault_insn(regs, insn); goto handle_kernel_fault; } + +retry: down_read(&mm->mmap_sem); } @@ -423,7 +426,12 @@ good_area: goto bad_area; } - fault = handle_mm_fault(mm, vma, address, (fault_code & FAULT_CODE_WRITE) ? FAULT_FLAG_WRITE : 0); + flags |= ((fault_code & FAULT_CODE_WRITE) ? FAULT_FLAG_WRITE : 0); + fault = handle_mm_fault(mm, vma, address, flags); + + if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) + return; + if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -431,12 +439,27 @@ good_area: goto do_sigbus; BUG(); } - if (fault & VM_FAULT_MAJOR) { - current->maj_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address); - } else { - current->min_flt++; - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address); + + if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (fault & VM_FAULT_MAJOR) { + current->maj_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, + 1, regs, address); + } else { + current->min_flt++; + perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, + 1, regs, address); + } + if (fault & VM_FAULT_RETRY) { + flags &= ~FAULT_FLAG_ALLOW_RETRY; + + /* No need to up_read(&mm->mmap_sem) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; + } } up_read(&mm->mmap_sem); diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h index 5d5a635530bd..32e6cbe8dff3 100644 --- a/arch/tile/include/asm/pci.h +++ b/arch/tile/include/asm/pci.h @@ -47,8 +47,8 @@ struct pci_controller { */ #define PCI_DMA_BUS_IS_PHYS 1 -int __devinit tile_pci_init(void); -int __devinit pcibios_init(void); +int __init tile_pci_init(void); +int __init pcibios_init(void); static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index a1bb59eecc18..b56d12bf5900 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -141,7 +141,7 @@ static int __devinit tile_init_irqs(int controller_id, * * Returns the number of controllers discovered. */ -int __devinit tile_pci_init(void) +int __init tile_pci_init(void) { int i; @@ -287,7 +287,7 @@ static void __devinit fixup_read_and_payload_sizes(void) * The controllers have been set up by the time we get here, by a call to * tile_pci_init. */ -int __devinit pcibios_init(void) +int __init pcibios_init(void) { int i; diff --git a/arch/tile/kernel/proc.c b/arch/tile/kernel/proc.c index 7a9327046404..446a7f52cc11 100644 --- a/arch/tile/kernel/proc.c +++ b/arch/tile/kernel/proc.c @@ -146,7 +146,6 @@ static ctl_table unaligned_table[] = { }, {} }; -#endif static struct ctl_path tile_path[] = { { .procname = "tile" }, @@ -155,10 +154,9 @@ static struct ctl_path tile_path[] = { static int __init proc_sys_tile_init(void) { -#ifndef __tilegx__ /* FIXME: GX: no support for unaligned access yet */ register_sysctl_paths(tile_path, unaligned_table); -#endif return 0; } arch_initcall(proc_sys_tile_init); +#endif diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c index 9efbc1391b3c..89529c9f0605 100644 --- a/arch/tile/kernel/single_step.c +++ b/arch/tile/kernel/single_step.c @@ -346,12 +346,10 @@ void single_step_once(struct pt_regs *regs) } /* allocate a cache line of writable, executable memory */ - down_write(¤t->mm->mmap_sem); - buffer = (void __user *) do_mmap(NULL, 0, 64, + buffer = (void __user *) vm_mmap(NULL, 0, 64, PROT_EXEC | PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, 0); - up_write(¤t->mm->mmap_sem); if (IS_ERR((void __force *)buffer)) { kfree(state); diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c index b949edcec200..172aef7d3159 100644 --- a/arch/tile/kernel/smpboot.c +++ b/arch/tile/kernel/smpboot.c @@ -196,6 +196,8 @@ void __cpuinit online_secondary(void) /* This must be done before setting cpu_online_mask */ wmb(); + notify_cpu_starting(smp_processor_id()); + /* * We need to hold call_lock, so there is no inconsistency * between the time smp_call_function() determines number of diff --git a/arch/um/drivers/cow.h b/arch/um/drivers/cow.h index dc36b222100b..6673508f3426 100644 --- a/arch/um/drivers/cow.h +++ b/arch/um/drivers/cow.h @@ -3,41 +3,6 @@ #include <asm/types.h> -#if defined(__KERNEL__) - -# include <asm/byteorder.h> - -# if defined(__BIG_ENDIAN) -# define ntohll(x) (x) -# define htonll(x) (x) -# elif defined(__LITTLE_ENDIAN) -# define ntohll(x) be64_to_cpu(x) -# define htonll(x) cpu_to_be64(x) -# else -# error "Could not determine byte order" -# endif - -#else -/* For the definition of ntohl, htonl and __BYTE_ORDER */ -#include <endian.h> -#include <netinet/in.h> -#if defined(__BYTE_ORDER) - -# if __BYTE_ORDER == __BIG_ENDIAN -# define ntohll(x) (x) -# define htonll(x) (x) -# elif __BYTE_ORDER == __LITTLE_ENDIAN -# define ntohll(x) bswap_64(x) -# define htonll(x) bswap_64(x) -# else -# error "Could not determine byte order: __BYTE_ORDER uncorrectly defined" -# endif - -#else /* ! defined(__BYTE_ORDER) */ -# error "Could not determine byte order: __BYTE_ORDER not defined" -#endif -#endif /* ! defined(__KERNEL__) */ - extern int init_cow_file(int fd, char *cow_file, char *backing_file, int sectorsize, int alignment, int *bitmap_offset_out, unsigned long *bitmap_len_out, int *data_offset_out); diff --git a/arch/um/drivers/cow_user.c b/arch/um/drivers/cow_user.c index 9cbb426c0b91..0ee9cc6cc4c7 100644 --- a/arch/um/drivers/cow_user.c +++ b/arch/um/drivers/cow_user.c @@ -8,11 +8,10 @@ * that. */ #include <unistd.h> -#include <byteswap.h> #include <errno.h> #include <string.h> #include <arpa/inet.h> -#include <asm/types.h> +#include <endian.h> #include "cow.h" #include "cow_sys.h" @@ -214,8 +213,8 @@ int write_cow_header(char *cow_file, int fd, char *backing_file, "header\n"); goto out; } - header->magic = htonl(COW_MAGIC); - header->version = htonl(COW_VERSION); + header->magic = htobe32(COW_MAGIC); + header->version = htobe32(COW_VERSION); err = -EINVAL; if (strlen(backing_file) > sizeof(header->backing_file) - 1) { @@ -246,10 +245,10 @@ int write_cow_header(char *cow_file, int fd, char *backing_file, goto out_free; } - header->mtime = htonl(modtime); - header->size = htonll(*size); - header->sectorsize = htonl(sectorsize); - header->alignment = htonl(alignment); + header->mtime = htobe32(modtime); + header->size = htobe64(*size); + header->sectorsize = htobe32(sectorsize); + header->alignment = htobe32(alignment); header->cow_format = COW_BITMAP; err = cow_write_file(fd, header, sizeof(*header)); @@ -301,8 +300,8 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg, magic = header->v1.magic; if (magic == COW_MAGIC) version = header->v1.version; - else if (magic == ntohl(COW_MAGIC)) - version = ntohl(header->v1.version); + else if (magic == be32toh(COW_MAGIC)) + version = be32toh(header->v1.version); /* No error printed because the non-COW case comes through here */ else goto out; @@ -327,9 +326,9 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg, "header\n"); goto out; } - *mtime_out = ntohl(header->v2.mtime); - *size_out = ntohll(header->v2.size); - *sectorsize_out = ntohl(header->v2.sectorsize); + *mtime_out = be32toh(header->v2.mtime); + *size_out = be64toh(header->v2.size); + *sectorsize_out = be32toh(header->v2.sectorsize); *bitmap_offset_out = sizeof(header->v2); *align_out = *sectorsize_out; file = header->v2.backing_file; @@ -341,10 +340,10 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg, "header\n"); goto out; } - *mtime_out = ntohl(header->v3.mtime); - *size_out = ntohll(header->v3.size); - *sectorsize_out = ntohl(header->v3.sectorsize); - *align_out = ntohl(header->v3.alignment); + *mtime_out = be32toh(header->v3.mtime); + *size_out = be64toh(header->v3.size); + *sectorsize_out = be32toh(header->v3.sectorsize); + *align_out = be32toh(header->v3.alignment); if (*align_out == 0) { cow_printf("read_cow_header - invalid COW header, " "align == 0\n"); @@ -366,16 +365,16 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg, * this was used until Dec2005 - 64bits are needed to represent * 2038+. I.e. we can safely do this truncating cast. * - * Additionally, we must use ntohl() instead of ntohll(), since + * Additionally, we must use be32toh() instead of be64toh(), since * the program used to use the former (tested - I got mtime * mismatch "0 vs whatever"). * * Ever heard about bug-to-bug-compatibility ? ;-) */ - *mtime_out = (time32_t) ntohl(header->v3_b.mtime); + *mtime_out = (time32_t) be32toh(header->v3_b.mtime); - *size_out = ntohll(header->v3_b.size); - *sectorsize_out = ntohl(header->v3_b.sectorsize); - *align_out = ntohl(header->v3_b.alignment); + *size_out = be64toh(header->v3_b.size); + *sectorsize_out = be32toh(header->v3_b.sectorsize); + *align_out = be32toh(header->v3_b.alignment); if (*align_out == 0) { cow_printf("read_cow_header - invalid COW header, " "align == 0\n"); diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c index e672bd6d43e3..43b39d61b538 100644 --- a/arch/um/drivers/mconsole_kern.c +++ b/arch/um/drivers/mconsole_kern.c @@ -22,6 +22,7 @@ #include <linux/workqueue.h> #include <linux/mutex.h> #include <asm/uaccess.h> +#include <asm/switch_to.h> #include "init.h" #include "irq_kern.h" diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild index 8419f5cf2ac7..fff24352255d 100644 --- a/arch/um/include/asm/Kbuild +++ b/arch/um/include/asm/Kbuild @@ -1,3 +1,4 @@ generic-y += bug.h cputime.h device.h emergency-restart.h futex.h hardirq.h generic-y += hw_irq.h irq_regs.h kdebug.h percpu.h sections.h topology.h xor.h -generic-y += ftrace.h pci.h io.h param.h delay.h mutex.h current.h +generic-y += ftrace.h pci.h io.h param.h delay.h mutex.h current.h exec.h +generic-y += switch_to.h diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile index 492bc4c1b62b..65a1c3d690ea 100644 --- a/arch/um/kernel/Makefile +++ b/arch/um/kernel/Makefile @@ -3,9 +3,10 @@ # Licensed under the GPL # -CPPFLAGS_vmlinux.lds := -DSTART=$(LDS_START) \ - -DELF_ARCH=$(LDS_ELF_ARCH) \ - -DELF_FORMAT=$(LDS_ELF_FORMAT) +CPPFLAGS_vmlinux.lds := -DSTART=$(LDS_START) \ + -DELF_ARCH=$(LDS_ELF_ARCH) \ + -DELF_FORMAT=$(LDS_ELF_FORMAT) \ + $(LDS_EXTRA) extra-y := vmlinux.lds clean-files := diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c index f386d04a84a5..2b73dedb44ca 100644 --- a/arch/um/kernel/process.c +++ b/arch/um/kernel/process.c @@ -88,11 +88,8 @@ static inline void set_current(struct task_struct *task) extern void arch_switch_to(struct task_struct *to); -void *_switch_to(void *prev, void *next, void *last) +void *__switch_to(struct task_struct *from, struct task_struct *to) { - struct task_struct *from = prev; - struct task_struct *to = next; - to->thread.prev_sched = from; set_current(to); @@ -111,7 +108,6 @@ void *_switch_to(void *prev, void *next, void *last) } while (current->thread.saved_task); return current->thread.prev_sched; - } void interrupt_end(void) diff --git a/arch/um/kernel/skas/mmu.c b/arch/um/kernel/skas/mmu.c index 4947b319f53a..0a49ef0c2bf4 100644 --- a/arch/um/kernel/skas/mmu.c +++ b/arch/um/kernel/skas/mmu.c @@ -103,7 +103,6 @@ int init_new_context(struct task_struct *task, struct mm_struct *mm) void uml_setup_stubs(struct mm_struct *mm) { - struct page **pages; int err, ret; if (!skas_needs_stub) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 1d14cc6b79ad..c9866b0b77d8 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -81,7 +81,7 @@ config X86 select CLKEVT_I8253 select ARCH_HAVE_NMI_SAFE_CMPXCHG select GENERIC_IOMAP - select DCACHE_WORD_ACCESS if !DEBUG_PAGEALLOC + select DCACHE_WORD_ACCESS config INSTRUCTION_DECODER def_bool (KPROBES || PERF_EVENTS) diff --git a/arch/x86/Makefile.um b/arch/x86/Makefile.um index 4be406abeefd..36b62bc52638 100644 --- a/arch/x86/Makefile.um +++ b/arch/x86/Makefile.um @@ -14,6 +14,9 @@ LINK-y += $(call cc-option,-m32) export LDFLAGS +LDS_EXTRA := -Ui386 +export LDS_EXTRA + # First of all, tune CFLAGS for the specific CPU. This actually sets cflags-y. include $(srctree)/arch/x86/Makefile_32.cpu diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S index a0559930a180..c85e3ac99bba 100644 --- a/arch/x86/boot/compressed/head_32.S +++ b/arch/x86/boot/compressed/head_32.S @@ -33,6 +33,9 @@ __HEAD ENTRY(startup_32) #ifdef CONFIG_EFI_STUB + jmp preferred_addr + + .balign 0x10 /* * We don't need the return address, so set up the stack so * efi_main() can find its arugments. @@ -41,12 +44,17 @@ ENTRY(startup_32) call efi_main cmpl $0, %eax - je preferred_addr movl %eax, %esi - call 1f + jne 2f 1: + /* EFI init failed, so hang. */ + hlt + jmp 1b +2: + call 3f +3: popl %eax - subl $1b, %eax + subl $3b, %eax subl BP_pref_address(%esi), %eax add BP_code32_start(%esi), %eax leal preferred_addr(%eax), %eax diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 558d76ce23bc..87e03a13d8e3 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -200,18 +200,28 @@ ENTRY(startup_64) * entire text+data+bss and hopefully all of memory. */ #ifdef CONFIG_EFI_STUB - pushq %rsi + /* + * The entry point for the PE/COFF executable is 0x210, so only + * legacy boot loaders will execute this jmp. + */ + jmp preferred_addr + + .org 0x210 mov %rcx, %rdi mov %rdx, %rsi call efi_main - popq %rsi - cmpq $0,%rax - je preferred_addr movq %rax,%rsi - call 1f + cmpq $0,%rax + jne 2f 1: + /* EFI init failed, so hang. */ + hlt + jmp 1b +2: + call 3f +3: popq %rax - subq $1b, %rax + subq $3b, %rax subq BP_pref_address(%rsi), %rax add BP_code32_start(%esi), %eax leaq preferred_addr(%rax), %rax diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/boot/compressed/relocs.c index d3c0b0277666..fb7117a4ade1 100644 --- a/arch/x86/boot/compressed/relocs.c +++ b/arch/x86/boot/compressed/relocs.c @@ -403,13 +403,11 @@ static void print_absolute_symbols(void) for (i = 0; i < ehdr.e_shnum; i++) { struct section *sec = &secs[i]; char *sym_strtab; - Elf32_Sym *sh_symtab; int j; if (sec->shdr.sh_type != SHT_SYMTAB) { continue; } - sh_symtab = sec->symtab; sym_strtab = sec->link->strtab; for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) { Elf32_Sym *sym; diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c index ed549767a231..24443a332083 100644 --- a/arch/x86/boot/tools/build.c +++ b/arch/x86/boot/tools/build.c @@ -205,8 +205,13 @@ int main(int argc, char ** argv) put_unaligned_le32(file_sz, &buf[pe_header + 0x50]); #ifdef CONFIG_X86_32 - /* Address of entry point */ - put_unaligned_le32(i, &buf[pe_header + 0x28]); + /* + * Address of entry point. + * + * The EFI stub entry point is +16 bytes from the start of + * the .text section. + */ + put_unaligned_le32(i + 16, &buf[pe_header + 0x28]); /* .text size */ put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]); @@ -217,9 +222,11 @@ int main(int argc, char ** argv) /* * Address of entry point. startup_32 is at the beginning and * the 64-bit entry point (startup_64) is always 512 bytes - * after. + * after. The EFI stub entry point is 16 bytes after that, as + * the first instruction allows legacy loaders to jump over + * the EFI stub initialisation */ - put_unaligned_le32(i + 512, &buf[pe_header + 0x28]); + put_unaligned_le32(i + 528, &buf[pe_header + 0x28]); /* .text size */ put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]); diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c index d511d951a052..07b3a68d2d29 100644 --- a/arch/x86/ia32/ia32_aout.c +++ b/arch/x86/ia32/ia32_aout.c @@ -119,9 +119,7 @@ static void set_brk(unsigned long start, unsigned long end) end = PAGE_ALIGN(end); if (end <= start) return; - down_write(¤t->mm->mmap_sem); - do_brk(start, end - start); - up_write(¤t->mm->mmap_sem); + vm_brk(start, end - start); } #ifdef CORE_DUMP @@ -296,8 +294,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) /* OK, This is the point of no return */ set_personality(PER_LINUX); - set_thread_flag(TIF_IA32); - current->mm->context.ia32_compat = 1; + set_personality_ia32(false); setup_new_exec(bprm); @@ -332,9 +329,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) pos = 32; map_size = ex.a_text+ex.a_data; - down_write(¤t->mm->mmap_sem); - error = do_brk(text_addr & PAGE_MASK, map_size); - up_write(¤t->mm->mmap_sem); + error = vm_brk(text_addr & PAGE_MASK, map_size); if (error != (text_addr & PAGE_MASK)) { send_sig(SIGKILL, current, 0); @@ -373,9 +368,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) if (!bprm->file->f_op->mmap || (fd_offset & ~PAGE_MASK) != 0) { loff_t pos = fd_offset; - down_write(¤t->mm->mmap_sem); - do_brk(N_TXTADDR(ex), ex.a_text+ex.a_data); - up_write(¤t->mm->mmap_sem); + vm_brk(N_TXTADDR(ex), ex.a_text+ex.a_data); bprm->file->f_op->read(bprm->file, (char __user *)N_TXTADDR(ex), ex.a_text+ex.a_data, &pos); @@ -385,26 +378,22 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) goto beyond_if; } - down_write(¤t->mm->mmap_sem); - error = do_mmap(bprm->file, N_TXTADDR(ex), ex.a_text, + error = vm_mmap(bprm->file, N_TXTADDR(ex), ex.a_text, PROT_READ | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE | MAP_32BIT, fd_offset); - up_write(¤t->mm->mmap_sem); if (error != N_TXTADDR(ex)) { send_sig(SIGKILL, current, 0); return error; } - down_write(¤t->mm->mmap_sem); - error = do_mmap(bprm->file, N_DATADDR(ex), ex.a_data, + error = vm_mmap(bprm->file, N_DATADDR(ex), ex.a_data, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE | MAP_32BIT, fd_offset + ex.a_text); - up_write(¤t->mm->mmap_sem); if (error != N_DATADDR(ex)) { send_sig(SIGKILL, current, 0); return error; @@ -476,9 +465,7 @@ static int load_aout_library(struct file *file) error_time = jiffies; } #endif - down_write(¤t->mm->mmap_sem); - do_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss); - up_write(¤t->mm->mmap_sem); + vm_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss); file->f_op->read(file, (char __user *)start_addr, ex.a_text + ex.a_data, &pos); @@ -490,12 +477,10 @@ static int load_aout_library(struct file *file) goto out; } /* Now use mmap to map the library into memory. */ - down_write(¤t->mm->mmap_sem); - error = do_mmap(file, start_addr, ex.a_text + ex.a_data, + error = vm_mmap(file, start_addr, ex.a_text + ex.a_data, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_32BIT, N_TXTOFF(ex)); - up_write(¤t->mm->mmap_sem); retval = error; if (error != start_addr) goto out; @@ -503,9 +488,7 @@ static int load_aout_library(struct file *file) len = PAGE_ALIGN(ex.a_text + ex.a_data); bss = ex.a_text + ex.a_data + ex.a_bss; if (bss > len) { - down_write(¤t->mm->mmap_sem); - error = do_brk(start_addr + len, bss - len); - up_write(¤t->mm->mmap_sem); + error = vm_brk(start_addr + len, bss - len); retval = error; if (error != start_addr + len) goto out; diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h index b3b733262909..99480e55973d 100644 --- a/arch/x86/include/asm/cmpxchg.h +++ b/arch/x86/include/asm/cmpxchg.h @@ -43,7 +43,7 @@ extern void __add_wrong_size(void) switch (sizeof(*(ptr))) { \ case __X86_CASE_B: \ asm volatile (lock #op "b %b0, %1\n" \ - : "+r" (__ret), "+m" (*(ptr)) \ + : "+q" (__ret), "+m" (*(ptr)) \ : : "memory", "cc"); \ break; \ case __X86_CASE_W: \ @@ -173,7 +173,7 @@ extern void __add_wrong_size(void) switch (sizeof(*(ptr))) { \ case __X86_CASE_B: \ asm volatile (lock "addb %b1, %0\n" \ - : "+m" (*(ptr)) : "ri" (inc) \ + : "+m" (*(ptr)) : "qi" (inc) \ : "memory", "cc"); \ break; \ case __X86_CASE_W: \ diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h index 3427b7798dbc..7ef7c3020e5c 100644 --- a/arch/x86/include/asm/posix_types.h +++ b/arch/x86/include/asm/posix_types.h @@ -7,9 +7,9 @@ #else # ifdef __i386__ # include "posix_types_32.h" -# elif defined(__LP64__) -# include "posix_types_64.h" -# else +# elif defined(__ILP32__) # include "posix_types_x32.h" +# else +# include "posix_types_64.h" # endif #endif diff --git a/arch/x86/include/asm/sigcontext.h b/arch/x86/include/asm/sigcontext.h index 4a085383af27..5ca71c065eef 100644 --- a/arch/x86/include/asm/sigcontext.h +++ b/arch/x86/include/asm/sigcontext.h @@ -257,7 +257,7 @@ struct sigcontext { __u64 oldmask; __u64 cr2; struct _fpstate __user *fpstate; /* zero when no FPU context */ -#ifndef __LP64__ +#ifdef __ILP32__ __u32 __fpstate_pad; #endif __u64 reserved1[8]; diff --git a/arch/x86/include/asm/siginfo.h b/arch/x86/include/asm/siginfo.h index fc1aa5535646..34c47b3341c0 100644 --- a/arch/x86/include/asm/siginfo.h +++ b/arch/x86/include/asm/siginfo.h @@ -2,7 +2,13 @@ #define _ASM_X86_SIGINFO_H #ifdef __x86_64__ -# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) +# ifdef __ILP32__ /* x32 */ +typedef long long __kernel_si_clock_t __attribute__((aligned(4))); +# define __ARCH_SI_CLOCK_T __kernel_si_clock_t +# define __ARCH_SI_ATTRIBUTES __attribute__((aligned(8))) +# else /* x86-64 */ +# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) +# endif #endif #include <asm-generic/siginfo.h> diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index 8be5f54d9360..e0544597cfe7 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -557,6 +557,8 @@ struct __large_struct { unsigned long buf[100]; }; extern unsigned long copy_from_user_nmi(void *to, const void __user *from, unsigned long n); +extern __must_check long +strncpy_from_user(char *dst, const char __user *src, long count); /* * movsl can be slow when source and dest are not both 8-byte aligned diff --git a/arch/x86/include/asm/uaccess_32.h b/arch/x86/include/asm/uaccess_32.h index 566e803cc602..8084bc73b18c 100644 --- a/arch/x86/include/asm/uaccess_32.h +++ b/arch/x86/include/asm/uaccess_32.h @@ -213,11 +213,6 @@ static inline unsigned long __must_check copy_from_user(void *to, return n; } -long __must_check strncpy_from_user(char *dst, const char __user *src, - long count); -long __must_check __strncpy_from_user(char *dst, - const char __user *src, long count); - /** * strlen_user: - Get the size of a string in user space. * @str: The string to measure. diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h index 1c66d30971ad..fcd4b6f3ef02 100644 --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h @@ -208,10 +208,6 @@ int __copy_in_user(void __user *dst, const void __user *src, unsigned size) } } -__must_check long -strncpy_from_user(char *dst, const char __user *src, long count); -__must_check long -__strncpy_from_user(char *dst, const char __user *src, long count); __must_check long strnlen_user(const char __user *str, long n); __must_check long __strnlen_user(const char __user *str, long n); __must_check long strlen_user(const char __user *str); diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h index 37cdc9d99bb1..4437001d8e3d 100644 --- a/arch/x86/include/asm/unistd.h +++ b/arch/x86/include/asm/unistd.h @@ -63,10 +63,10 @@ #else # ifdef __i386__ # include <asm/unistd_32.h> -# elif defined(__LP64__) -# include <asm/unistd_64.h> -# else +# elif defined(__ILP32__) # include <asm/unistd_x32.h> +# else +# include <asm/unistd_64.h> # endif #endif diff --git a/arch/x86/include/asm/word-at-a-time.h b/arch/x86/include/asm/word-at-a-time.h index 6fe6767b7124..e58f03b206c3 100644 --- a/arch/x86/include/asm/word-at-a-time.h +++ b/arch/x86/include/asm/word-at-a-time.h @@ -43,4 +43,37 @@ static inline unsigned long has_zero(unsigned long a) return ((a - REPEAT_BYTE(0x01)) & ~a) & REPEAT_BYTE(0x80); } +/* + * Load an unaligned word from kernel space. + * + * In the (very unlikely) case of the word being a page-crosser + * and the next page not being mapped, take the exception and + * return zeroes in the non-existing part. + */ +static inline unsigned long load_unaligned_zeropad(const void *addr) +{ + unsigned long ret, dummy; + + asm( + "1:\tmov %2,%0\n" + "2:\n" + ".section .fixup,\"ax\"\n" + "3:\t" + "lea %2,%1\n\t" + "and %3,%1\n\t" + "mov (%1),%0\n\t" + "leal %2,%%ecx\n\t" + "andl %4,%%ecx\n\t" + "shll $3,%%ecx\n\t" + "shr %%cl,%0\n\t" + "jmp 2b\n" + ".previous\n" + _ASM_EXTABLE(1b, 3b) + :"=&r" (ret),"=&c" (dummy) + :"m" (*(unsigned long *)addr), + "i" (-sizeof(unsigned long)), + "i" (sizeof(unsigned long)-1)); + return ret; +} + #endif /* _ASM_WORD_AT_A_TIME_H */ diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index baaca8defec8..764b66a4cf89 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -195,6 +195,5 @@ extern struct x86_msi_ops x86_msi; extern void x86_init_noop(void); extern void x86_init_uint_noop(unsigned int unused); -extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node); #endif diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 103b6ab368d3..146a49c763a4 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags; static char temp_stack[4096]; #endif +asmlinkage void acpi_enter_s3(void) +{ + acpi_enter_sleep_state(3, wake_sleep_flags); +} /** * acpi_suspend_lowlevel - save kernel state * diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h index 416d4be13fef..d68677a2a010 100644 --- a/arch/x86/kernel/acpi/sleep.h +++ b/arch/x86/kernel/acpi/sleep.h @@ -3,12 +3,16 @@ */ #include <asm/trampoline.h> +#include <linux/linkage.h> extern unsigned long saved_video_mode; extern long saved_magic; extern int wakeup_pmode_return; +extern u8 wake_sleep_flags; +extern asmlinkage void acpi_enter_s3(void); + extern unsigned long acpi_copy_wakeup_routine(unsigned long); extern void wakeup_long64(void); diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S index 13ab720573e3..72610839f03b 100644 --- a/arch/x86/kernel/acpi/wakeup_32.S +++ b/arch/x86/kernel/acpi/wakeup_32.S @@ -74,9 +74,7 @@ restore_registers: ENTRY(do_suspend_lowlevel) call save_processor_state call save_registers - pushl $3 - call acpi_enter_sleep_state - addl $4, %esp + call acpi_enter_s3 # In case of S3 failure, we'll emerge here. Jump # to ret_point to recover diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S index 8ea5164cbd04..014d1d28c397 100644 --- a/arch/x86/kernel/acpi/wakeup_64.S +++ b/arch/x86/kernel/acpi/wakeup_64.S @@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel) movq %rsi, saved_rsi addq $8, %rsp - movl $3, %edi - xorl %eax, %eax - call acpi_enter_sleep_state + call acpi_enter_s3 /* in case something went wrong, restore the machine status and go on */ jmp resume_point diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 11544d8f1e97..edc24480469f 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1637,9 +1637,11 @@ static int __init apic_verify(void) mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; /* The BIOS may have set up the APIC at some other address */ - rdmsr(MSR_IA32_APICBASE, l, h); - if (l & MSR_IA32_APICBASE_ENABLE) - mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; + if (boot_cpu_data.x86 >= 6) { + rdmsr(MSR_IA32_APICBASE, l, h); + if (l & MSR_IA32_APICBASE_ENABLE) + mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; + } pr_info("Found and enabled local APIC!\n"); return 0; @@ -1657,13 +1659,15 @@ int __init apic_force_enable(unsigned long addr) * MSR. This can only be done in software for Intel P6 or later * and AMD K7 (Model > 1) or later. */ - rdmsr(MSR_IA32_APICBASE, l, h); - if (!(l & MSR_IA32_APICBASE_ENABLE)) { - pr_info("Local APIC disabled by BIOS -- reenabling.\n"); - l &= ~MSR_IA32_APICBASE_BASE; - l |= MSR_IA32_APICBASE_ENABLE | addr; - wrmsr(MSR_IA32_APICBASE, l, h); - enabled_via_apicbase = 1; + if (boot_cpu_data.x86 >= 6) { + rdmsr(MSR_IA32_APICBASE, l, h); + if (!(l & MSR_IA32_APICBASE_ENABLE)) { + pr_info("Local APIC disabled by BIOS -- reenabling.\n"); + l &= ~MSR_IA32_APICBASE_BASE; + l |= MSR_IA32_APICBASE_ENABLE | addr; + wrmsr(MSR_IA32_APICBASE, l, h); + enabled_via_apicbase = 1; + } } return apic_verify(); } @@ -2209,10 +2213,12 @@ static void lapic_resume(void) * FIXME! This will be wrong if we ever support suspend on * SMP! We'll need to do this as part of the CPU restore! */ - rdmsr(MSR_IA32_APICBASE, l, h); - l &= ~MSR_IA32_APICBASE_BASE; - l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; - wrmsr(MSR_IA32_APICBASE, l, h); + if (boot_cpu_data.x86 >= 6) { + rdmsr(MSR_IA32_APICBASE, l, h); + l &= ~MSR_IA32_APICBASE_BASE; + l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; + wrmsr(MSR_IA32_APICBASE, l, h); + } } maxlvt = lapic_get_maxlvt(); diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c index 899803e03214..23e75422e013 100644 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -207,8 +207,11 @@ static void __init map_csrs(void) static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) { - c->phys_proc_id = node; - per_cpu(cpu_llc_id, smp_processor_id()) = node; + + if (c->phys_proc_id != node) { + c->phys_proc_id = node; + per_cpu(cpu_llc_id, smp_processor_id()) = node; + } } static int __init numachip_system_init(void) diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 8a778db45e3a..991e315f4227 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) { if (x2apic_phys) return x2apic_enabled(); + else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) && + (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) && + x2apic_enabled()) { + printk(KERN_DEBUG "System requires x2apic physical mode\n"); + return 1; + } else return 0; } diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 0a44b90602b0..146bb6218eec 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -26,7 +26,8 @@ * contact AMD for precise details and a CPU swap. * * See http://www.multimania.com/poulot/k6bug.html - * http://www.amd.com/K6/k6docs/revgd.html + * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" + * (Publication # 21266 Issue Date: August 1998) * * The following test is erm.. interesting. AMD neglected to up * the chip setting when fixing the bug but they also tweaked some @@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) "system stability may be impaired when more than 32 MB are used.\n"); else printk(KERN_CONT "probably OK (after B9730xxxx).\n"); - printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); } /* K6 with old style WHCR */ @@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) node = per_cpu(cpu_llc_id, cpu); /* - * If core numbers are inconsistent, it's likely a multi-fabric platform, - * so invoke platform-specific handler + * On multi-fabric platform (e.g. Numascale NumaChip) a + * platform-specific handler needs to be called to fixup some + * IDs of the CPU. */ - if (c->phys_proc_id != node) + if (x86_cpuinit.fixup_cpu_id) x86_cpuinit.fixup_cpu_id(c, node); if (!node_online(node)) { @@ -579,6 +580,24 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) } } + /* re-enable TopologyExtensions if switched off by BIOS */ + if ((c->x86 == 0x15) && + (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) && + !cpu_has(c, X86_FEATURE_TOPOEXT)) { + u64 val; + + if (!rdmsrl_amd_safe(0xc0011005, &val)) { + val |= 1ULL << 54; + wrmsrl_amd_safe(0xc0011005, val); + rdmsrl(0xc0011005, val); + if (val & (1ULL << 54)) { + set_cpu_cap(c, X86_FEATURE_TOPOEXT); + printk(KERN_INFO FW_INFO "CPU: Re-enabling " + "disabled Topology Extensions Support\n"); + } + } + } + cpu_detect_cache_sizes(c); /* Multi core CPU? */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 67e258362a3d..cf79302198a6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1163,15 +1163,6 @@ static void dbg_restore_debug_regs(void) #endif /* ! CONFIG_KGDB */ /* - * Prints an error where the NUMA and configured core-number mismatch and the - * platform didn't override this to fix it up - */ -void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node) -{ - pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id); -} - -/* * cpu_init() initializes state that is per-CPU. Some data is already * initialized (naturally) in the bootstrap process, such as the GDT * and IDT. We reload them nevertheless, this function acts as a diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 73d08ed98a64..b8f3653dddbc 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot, /* check if @slot is already used or the index is already disabled */ ret = amd_get_l3_disable_slot(nb, slot); if (ret >= 0) - return -EINVAL; + return -EEXIST; if (index > nb->l3_cache.indices) return -EINVAL; /* check whether the other slot has disabled the same index already */ if (index == amd_get_l3_disable_slot(nb, !slot)) - return -EINVAL; + return -EEXIST; amd_l3_disable_index(nb, cpu, slot, index); @@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val); if (err) { if (err == -EEXIST) - printk(KERN_WARNING "L3 disable slot %d in use!\n", - slot); + pr_warning("L3 slot %d in use/index already disabled!\n", + slot); return err; } return count; diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c index 7734bcbb5a3a..2d6e6498c176 100644 --- a/arch/x86/kernel/i387.c +++ b/arch/x86/kernel/i387.c @@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk) if (tsk_used_math(tsk)) { if (HAVE_HWFP && tsk == current) unlazy_fpu(tsk); + tsk->thread.fpu.last_cpu = ~0; return 0; } diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c index 73465aab28f8..8a2ce8fd41c0 100644 --- a/arch/x86/kernel/microcode_amd.c +++ b/arch/x86/kernel/microcode_amd.c @@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) { struct cpuinfo_x86 *c = &cpu_data(cpu); - if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { - pr_warning("CPU%d: family %d not supported\n", cpu, c->x86); - return -1; - } - csig->rev = c->microcode; pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); @@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = { struct microcode_ops * __init init_amd_microcode(void) { + struct cpuinfo_x86 *c = &cpu_data(0); + + if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { + pr_warning("AMD CPU family 0x%x not supported\n", c->x86); + return NULL; + } + patch = (void *)get_zeroed_page(GFP_KERNEL); if (!patch) return NULL; diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 87a0f8688301..c9bda6d6035c 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif) if (err) return err; - if (microcode_init_cpu(cpu) == UCODE_ERROR) { - sysfs_remove_group(&dev->kobj, &mc_attr_group); + if (microcode_init_cpu(cpu) == UCODE_ERROR) return -EINVAL; - } return err; } @@ -528,11 +526,11 @@ static int __init microcode_init(void) microcode_ops = init_intel_microcode(); else if (c->x86_vendor == X86_VENDOR_AMD) microcode_ops = init_amd_microcode(); - - if (!microcode_ops) { + else pr_err("no support for this CPU vendor\n"); + + if (!microcode_ops) return -ENODEV; - } microcode_pdev = platform_device_register_simple("microcode", -1, NULL, 0); diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c index f386dc49f988..7515cf0e1805 100644 --- a/arch/x86/kernel/vsyscall_64.c +++ b/arch/x86/kernel/vsyscall_64.c @@ -216,9 +216,9 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) current_thread_info()->sig_on_uaccess_error = 1; /* - * 0 is a valid user pointer (in the access_ok sense) on 32-bit and + * NULL is a valid user pointer (in the access_ok sense) on 32-bit and * 64-bit, so we don't need to special-case it here. For all the - * vsyscalls, 0 means "don't write anything" not "write it at + * vsyscalls, NULL means "don't write anything" not "write it at * address 0". */ ret = -EFAULT; @@ -247,7 +247,7 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) ret = sys_getcpu((unsigned __user *)regs->di, (unsigned __user *)regs->si, - 0); + NULL); break; } diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index e9f265fd79ae..9cf71d0b2d37 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -93,7 +93,6 @@ struct x86_init_ops x86_init __initdata = { struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = { .early_percpu_clock_init = x86_init_noop, .setup_percpu_clockev = setup_secondary_APIC_clock, - .fixup_cpu_id = x86_default_fixup_cpu_id, }; static void default_nmi_init(void) { }; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 173df38dbda5..2e88438ffd83 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -459,17 +459,17 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu) pmu->available_event_types = ~entry->ebx & ((1ull << bitmap_len) - 1); if (pmu->version == 1) { - pmu->global_ctrl = (1 << pmu->nr_arch_gp_counters) - 1; - return; + pmu->nr_arch_fixed_counters = 0; + } else { + pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f), + X86_PMC_MAX_FIXED); + pmu->counter_bitmask[KVM_PMC_FIXED] = + ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1; } - pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f), - X86_PMC_MAX_FIXED); - pmu->counter_bitmask[KVM_PMC_FIXED] = - ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1; - pmu->global_ctrl_mask = ~(((1 << pmu->nr_arch_gp_counters) - 1) - | (((1ull << pmu->nr_arch_fixed_counters) - 1) - << X86_PMC_IDX_FIXED)); + pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) | + (((1ull << pmu->nr_arch_fixed_counters) - 1) << X86_PMC_IDX_FIXED); + pmu->global_ctrl_mask = ~pmu->global_ctrl; } void kvm_pmu_init(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index ad85adfef843..4ff0ab9bc3c8 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2210,9 +2210,12 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) msr = find_msr_entry(vmx, msr_index); if (msr) { msr->data = data; - if (msr - vmx->guest_msrs < vmx->save_nmsrs) + if (msr - vmx->guest_msrs < vmx->save_nmsrs) { + preempt_disable(); kvm_set_shared_msr(msr->index, msr->data, msr->mask); + preempt_enable(); + } break; } ret = kvm_set_msr_common(vcpu, msr_index, data); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 4044ce0bf7c1..91a5e989abcf 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6336,13 +6336,11 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, if (npages && !old.rmap) { unsigned long userspace_addr; - down_write(¤t->mm->mmap_sem); - userspace_addr = do_mmap(NULL, 0, + userspace_addr = vm_mmap(NULL, 0, npages * PAGE_SIZE, PROT_READ | PROT_WRITE, map_flags, 0); - up_write(¤t->mm->mmap_sem); if (IS_ERR((void *)userspace_addr)) return PTR_ERR((void *)userspace_addr); @@ -6366,10 +6364,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, if (!user_alloc && !old.user_alloc && old.rmap && !npages) { int ret; - down_write(¤t->mm->mmap_sem); - ret = do_munmap(current->mm, old.userspace_addr, + ret = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); - up_write(¤t->mm->mmap_sem); if (ret < 0) printk(KERN_WARNING "kvm_vm_ioctl_set_memory_region: " diff --git a/arch/x86/lib/insn.c b/arch/x86/lib/insn.c index 25feb1ae71c5..b1e6c4b2e8eb 100644 --- a/arch/x86/lib/insn.c +++ b/arch/x86/lib/insn.c @@ -379,8 +379,8 @@ err_out: return; } -/* Decode moffset16/32/64 */ -static void __get_moffset(struct insn *insn) +/* Decode moffset16/32/64. Return 0 if failed */ +static int __get_moffset(struct insn *insn) { switch (insn->addr_bytes) { case 2: @@ -397,15 +397,19 @@ static void __get_moffset(struct insn *insn) insn->moffset2.value = get_next(int, insn); insn->moffset2.nbytes = 4; break; + default: /* opnd_bytes must be modified manually */ + goto err_out; } insn->moffset1.got = insn->moffset2.got = 1; + return 1; + err_out: - return; + return 0; } -/* Decode imm v32(Iz) */ -static void __get_immv32(struct insn *insn) +/* Decode imm v32(Iz). Return 0 if failed */ +static int __get_immv32(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -417,14 +421,18 @@ static void __get_immv32(struct insn *insn) insn->immediate.value = get_next(int, insn); insn->immediate.nbytes = 4; break; + default: /* opnd_bytes must be modified manually */ + goto err_out; } + return 1; + err_out: - return; + return 0; } -/* Decode imm v64(Iv/Ov) */ -static void __get_immv(struct insn *insn) +/* Decode imm v64(Iv/Ov), Return 0 if failed */ +static int __get_immv(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -441,15 +449,18 @@ static void __get_immv(struct insn *insn) insn->immediate2.value = get_next(int, insn); insn->immediate2.nbytes = 4; break; + default: /* opnd_bytes must be modified manually */ + goto err_out; } insn->immediate1.got = insn->immediate2.got = 1; + return 1; err_out: - return; + return 0; } /* Decode ptr16:16/32(Ap) */ -static void __get_immptr(struct insn *insn) +static int __get_immptr(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -462,14 +473,17 @@ static void __get_immptr(struct insn *insn) break; case 8: /* ptr16:64 is not exist (no segment) */ - return; + return 0; + default: /* opnd_bytes must be modified manually */ + goto err_out; } insn->immediate2.value = get_next(unsigned short, insn); insn->immediate2.nbytes = 2; insn->immediate1.got = insn->immediate2.got = 1; + return 1; err_out: - return; + return 0; } /** @@ -489,7 +503,8 @@ void insn_get_immediate(struct insn *insn) insn_get_displacement(insn); if (inat_has_moffset(insn->attr)) { - __get_moffset(insn); + if (!__get_moffset(insn)) + goto err_out; goto done; } @@ -517,16 +532,20 @@ void insn_get_immediate(struct insn *insn) insn->immediate2.nbytes = 4; break; case INAT_IMM_PTR: - __get_immptr(insn); + if (!__get_immptr(insn)) + goto err_out; break; case INAT_IMM_VWORD32: - __get_immv32(insn); + if (!__get_immv32(insn)) + goto err_out; break; case INAT_IMM_VWORD: - __get_immv(insn); + if (!__get_immv(insn)) + goto err_out; break; default: - break; + /* Here, insn must have an immediate, but failed */ + goto err_out; } if (inat_has_second_immediate(insn->attr)) { insn->immediate2.value = get_next(char, insn); diff --git a/arch/x86/lib/usercopy.c b/arch/x86/lib/usercopy.c index 97be9cb54483..d6ae30bbd7bb 100644 --- a/arch/x86/lib/usercopy.c +++ b/arch/x86/lib/usercopy.c @@ -7,6 +7,8 @@ #include <linux/highmem.h> #include <linux/module.h> +#include <asm/word-at-a-time.h> + /* * best effort, GUP based copy_from_user() that is NMI-safe */ @@ -41,3 +43,104 @@ copy_from_user_nmi(void *to, const void __user *from, unsigned long n) return len; } EXPORT_SYMBOL_GPL(copy_from_user_nmi); + +static inline unsigned long count_bytes(unsigned long mask) +{ + mask = (mask - 1) & ~mask; + mask >>= 7; + return count_masked_bytes(mask); +} + +/* + * Do a strncpy, return length of string without final '\0'. + * 'count' is the user-supplied count (return 'count' if we + * hit it), 'max' is the address space maximum (and we return + * -EFAULT if we hit it). + */ +static inline long do_strncpy_from_user(char *dst, const char __user *src, long count, unsigned long max) +{ + long res = 0; + + /* + * Truncate 'max' to the user-specified limit, so that + * we only have one limit we need to check in the loop + */ + if (max > count) + max = count; + + while (max >= sizeof(unsigned long)) { + unsigned long c; + + /* Fall back to byte-at-a-time if we get a page fault */ + if (unlikely(__get_user(c,(unsigned long __user *)(src+res)))) + break; + /* This can write a few bytes past the NUL character, but that's ok */ + *(unsigned long *)(dst+res) = c; + c = has_zero(c); + if (c) + return res + count_bytes(c); + res += sizeof(unsigned long); + max -= sizeof(unsigned long); + } + + while (max) { + char c; + + if (unlikely(__get_user(c,src+res))) + return -EFAULT; + dst[res] = c; + if (!c) + return res; + res++; + max--; + } + + /* + * Uhhuh. We hit 'max'. But was that the user-specified maximum + * too? If so, that's ok - we got as much as the user asked for. + */ + if (res >= count) + return res; + + /* + * Nope: we hit the address space limit, and we still had more + * characters the caller would have wanted. That's an EFAULT. + */ + return -EFAULT; +} + +/** + * strncpy_from_user: - Copy a NUL terminated string from userspace. + * @dst: Destination address, in kernel space. This buffer must be at + * least @count bytes long. + * @src: Source address, in user space. + * @count: Maximum number of bytes to copy, including the trailing NUL. + * + * Copies a NUL-terminated string from userspace to kernel space. + * + * On success, returns the length of the string (not including the trailing + * NUL). + * + * If access to userspace fails, returns -EFAULT (some data may have been + * copied). + * + * If @count is smaller than the length of the string, copies @count bytes + * and returns @count. + */ +long +strncpy_from_user(char *dst, const char __user *src, long count) +{ + unsigned long max_addr, src_addr; + + if (unlikely(count <= 0)) + return 0; + + max_addr = current_thread_info()->addr_limit.seg; + src_addr = (unsigned long)src; + if (likely(src_addr < max_addr)) { + unsigned long max = max_addr - src_addr; + return do_strncpy_from_user(dst, src, count, max); + } + return -EFAULT; +} +EXPORT_SYMBOL(strncpy_from_user); diff --git a/arch/x86/lib/usercopy_32.c b/arch/x86/lib/usercopy_32.c index d9b094ca7aaa..ef2a6a5d78e3 100644 --- a/arch/x86/lib/usercopy_32.c +++ b/arch/x86/lib/usercopy_32.c @@ -33,93 +33,6 @@ static inline int __movsl_is_ok(unsigned long a1, unsigned long a2, unsigned lon __movsl_is_ok((unsigned long)(a1), (unsigned long)(a2), (n)) /* - * Copy a null terminated string from userspace. - */ - -#define __do_strncpy_from_user(dst, src, count, res) \ -do { \ - int __d0, __d1, __d2; \ - might_fault(); \ - __asm__ __volatile__( \ - " testl %1,%1\n" \ - " jz 2f\n" \ - "0: lodsb\n" \ - " stosb\n" \ - " testb %%al,%%al\n" \ - " jz 1f\n" \ - " decl %1\n" \ - " jnz 0b\n" \ - "1: subl %1,%0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: movl %5,%0\n" \ - " jmp 2b\n" \ - ".previous\n" \ - _ASM_EXTABLE(0b,3b) \ - : "=&d"(res), "=&c"(count), "=&a" (__d0), "=&S" (__d1), \ - "=&D" (__d2) \ - : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), "4"(dst) \ - : "memory"); \ -} while (0) - -/** - * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking. - * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. - * @src: Source address, in user space. - * @count: Maximum number of bytes to copy, including the trailing NUL. - * - * Copies a NUL-terminated string from userspace to kernel space. - * Caller must check the specified block with access_ok() before calling - * this function. - * - * On success, returns the length of the string (not including the trailing - * NUL). - * - * If access to userspace fails, returns -EFAULT (some data may have been - * copied). - * - * If @count is smaller than the length of the string, copies @count bytes - * and returns @count. - */ -long -__strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res; - __do_strncpy_from_user(dst, src, count, res); - return res; -} -EXPORT_SYMBOL(__strncpy_from_user); - -/** - * strncpy_from_user: - Copy a NUL terminated string from userspace. - * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. - * @src: Source address, in user space. - * @count: Maximum number of bytes to copy, including the trailing NUL. - * - * Copies a NUL-terminated string from userspace to kernel space. - * - * On success, returns the length of the string (not including the trailing - * NUL). - * - * If access to userspace fails, returns -EFAULT (some data may have been - * copied). - * - * If @count is smaller than the length of the string, copies @count bytes - * and returns @count. - */ -long -strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res = -EFAULT; - if (access_ok(VERIFY_READ, src, 1)) - __do_strncpy_from_user(dst, src, count, res); - return res; -} -EXPORT_SYMBOL(strncpy_from_user); - -/* * Zero Userspace */ diff --git a/arch/x86/lib/usercopy_64.c b/arch/x86/lib/usercopy_64.c index b7c2849ffb66..0d0326f388c0 100644 --- a/arch/x86/lib/usercopy_64.c +++ b/arch/x86/lib/usercopy_64.c @@ -9,55 +9,6 @@ #include <asm/uaccess.h> /* - * Copy a null terminated string from userspace. - */ - -#define __do_strncpy_from_user(dst,src,count,res) \ -do { \ - long __d0, __d1, __d2; \ - might_fault(); \ - __asm__ __volatile__( \ - " testq %1,%1\n" \ - " jz 2f\n" \ - "0: lodsb\n" \ - " stosb\n" \ - " testb %%al,%%al\n" \ - " jz 1f\n" \ - " decq %1\n" \ - " jnz 0b\n" \ - "1: subq %1,%0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: movq %5,%0\n" \ - " jmp 2b\n" \ - ".previous\n" \ - _ASM_EXTABLE(0b,3b) \ - : "=&r"(res), "=&c"(count), "=&a" (__d0), "=&S" (__d1), \ - "=&D" (__d2) \ - : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), "4"(dst) \ - : "memory"); \ -} while (0) - -long -__strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res; - __do_strncpy_from_user(dst, src, count, res); - return res; -} -EXPORT_SYMBOL(__strncpy_from_user); - -long -strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res = -EFAULT; - if (access_ok(VERIFY_READ, src, 1)) - return __strncpy_from_user(dst, src, count); - return res; -} -EXPORT_SYMBOL(strncpy_from_user); - -/* * Zero Userspace */ diff --git a/arch/x86/platform/geode/net5501.c b/arch/x86/platform/geode/net5501.c index 66d377e334f7..646e3b5b4bb6 100644 --- a/arch/x86/platform/geode/net5501.c +++ b/arch/x86/platform/geode/net5501.c @@ -63,7 +63,7 @@ static struct gpio_led net5501_leds[] = { .name = "net5501:1", .gpio = 6, .default_trigger = "default-on", - .active_low = 1, + .active_low = 0, }, }; diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index e0a37233c0af..e31bcd8f2eee 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c @@ -805,7 +805,7 @@ void intel_scu_devices_create(void) } else i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1); } - intel_scu_notifier_post(SCU_AVAILABLE, 0L); + intel_scu_notifier_post(SCU_AVAILABLE, NULL); } EXPORT_SYMBOL_GPL(intel_scu_devices_create); @@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void) { int i; - intel_scu_notifier_post(SCU_DOWN, 0L); + intel_scu_notifier_post(SCU_DOWN, NULL); for (i = 0; i < ipc_next_dev; i++) platform_device_del(ipc_devs[i]); diff --git a/arch/x86/um/asm/barrier.h b/arch/x86/um/asm/barrier.h new file mode 100644 index 000000000000..7d01b8c56c00 --- /dev/null +++ b/arch/x86/um/asm/barrier.h @@ -0,0 +1,75 @@ +#ifndef _ASM_UM_BARRIER_H_ +#define _ASM_UM_BARRIER_H_ + +#include <asm/asm.h> +#include <asm/segment.h> +#include <asm/cpufeature.h> +#include <asm/cmpxchg.h> +#include <asm/nops.h> + +#include <linux/kernel.h> +#include <linux/irqflags.h> + +/* + * Force strict CPU ordering. + * And yes, this is required on UP too when we're talking + * to devices. + */ +#ifdef CONFIG_X86_32 + +#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2) +#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2) +#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM) + +#else /* CONFIG_X86_32 */ + +#define mb() asm volatile("mfence" : : : "memory") +#define rmb() asm volatile("lfence" : : : "memory") +#define wmb() asm volatile("sfence" : : : "memory") + +#endif /* CONFIG_X86_32 */ + +#define read_barrier_depends() do { } while (0) + +#ifdef CONFIG_SMP + +#define smp_mb() mb() +#ifdef CONFIG_X86_PPRO_FENCE +#define smp_rmb() rmb() +#else /* CONFIG_X86_PPRO_FENCE */ +#define smp_rmb() barrier() +#endif /* CONFIG_X86_PPRO_FENCE */ + +#ifdef CONFIG_X86_OOSTORE +#define smp_wmb() wmb() +#else /* CONFIG_X86_OOSTORE */ +#define smp_wmb() barrier() +#endif /* CONFIG_X86_OOSTORE */ + +#define smp_read_barrier_depends() read_barrier_depends() +#define set_mb(var, value) do { (void)xchg(&var, value); } while (0) + +#else /* CONFIG_SMP */ + +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do { } while (0) +#define set_mb(var, value) do { var = value; barrier(); } while (0) + +#endif /* CONFIG_SMP */ + +/* + * Stop RDTSC speculation. This is needed when you need to use RDTSC + * (or get_cycles or vread that possibly accesses the TSC) in a defined + * code region. + * + * (Could use an alternative three way for this if there was one.) + */ +static inline void rdtsc_barrier(void) +{ + alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC); + alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC); +} + +#endif diff --git a/arch/x86/um/asm/system.h b/arch/x86/um/asm/system.h deleted file mode 100644 index a459fd9b7598..000000000000 --- a/arch/x86/um/asm/system.h +++ /dev/null @@ -1,135 +0,0 @@ -#ifndef _ASM_X86_SYSTEM_H_ -#define _ASM_X86_SYSTEM_H_ - -#include <asm/asm.h> -#include <asm/segment.h> -#include <asm/cpufeature.h> -#include <asm/cmpxchg.h> -#include <asm/nops.h> - -#include <linux/kernel.h> -#include <linux/irqflags.h> - -/* entries in ARCH_DLINFO: */ -#ifdef CONFIG_IA32_EMULATION -# define AT_VECTOR_SIZE_ARCH 2 -#else -# define AT_VECTOR_SIZE_ARCH 1 -#endif - -extern unsigned long arch_align_stack(unsigned long sp); - -void default_idle(void); - -/* - * Force strict CPU ordering. - * And yes, this is required on UP too when we're talking - * to devices. - */ -#ifdef CONFIG_X86_32 -/* - * Some non-Intel clones support out of order store. wmb() ceases to be a - * nop for these. - */ -#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2) -#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2) -#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM) -#else -#define mb() asm volatile("mfence":::"memory") -#define rmb() asm volatile("lfence":::"memory") -#define wmb() asm volatile("sfence" ::: "memory") -#endif - -/** - * read_barrier_depends - Flush all pending reads that subsequents reads - * depend on. - * - * No data-dependent reads from memory-like regions are ever reordered - * over this barrier. All reads preceding this primitive are guaranteed - * to access memory (but not necessarily other CPUs' caches) before any - * reads following this primitive that depend on the data return by - * any of the preceding reads. This primitive is much lighter weight than - * rmb() on most CPUs, and is never heavier weight than is - * rmb(). - * - * These ordering constraints are respected by both the local CPU - * and the compiler. - * - * Ordering is not guaranteed by anything other than these primitives, - * not even by data dependencies. See the documentation for - * memory_barrier() for examples and URLs to more information. - * - * For example, the following code would force ordering (the initial - * value of "a" is zero, "b" is one, and "p" is "&a"): - * - * <programlisting> - * CPU 0 CPU 1 - * - * b = 2; - * memory_barrier(); - * p = &b; q = p; - * read_barrier_depends(); - * d = *q; - * </programlisting> - * - * because the read of "*q" depends on the read of "p" and these - * two reads are separated by a read_barrier_depends(). However, - * the following code, with the same initial values for "a" and "b": - * - * <programlisting> - * CPU 0 CPU 1 - * - * a = 2; - * memory_barrier(); - * b = 3; y = b; - * read_barrier_depends(); - * x = a; - * </programlisting> - * - * does not enforce ordering, since there is no data dependency between - * the read of "a" and the read of "b". Therefore, on some CPUs, such - * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() - * in cases like this where there are no data dependencies. - **/ - -#define read_barrier_depends() do { } while (0) - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#ifdef CONFIG_X86_PPRO_FENCE -# define smp_rmb() rmb() -#else -# define smp_rmb() barrier() -#endif -#ifdef CONFIG_X86_OOSTORE -# define smp_wmb() wmb() -#else -# define smp_wmb() barrier() -#endif -#define smp_read_barrier_depends() read_barrier_depends() -#define set_mb(var, value) do { (void)xchg(&var, value); } while (0) -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while (0) -#define set_mb(var, value) do { var = value; barrier(); } while (0) -#endif - -/* - * Stop RDTSC speculation. This is needed when you need to use RDTSC - * (or get_cycles or vread that possibly accesses the TSC) in a defined - * code region. - * - * (Could use an alternative three way for this if there was one.) - */ -static inline void rdtsc_barrier(void) -{ - alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC); - alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC); -} - -extern void *_switch_to(void *prev, void *next, void *last); -#define switch_to(prev, next, last) prev = _switch_to(prev, next, last) - -#endif diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 4f51bebac02c..a8f8844b8d32 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -261,7 +261,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx, static bool __init xen_check_mwait(void) { -#ifdef CONFIG_ACPI +#if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \ + !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE) struct xen_platform_op op = { .cmd = XENPF_set_processor_pminfo, .u.set_pminfo.id = -1, @@ -349,7 +350,6 @@ static void __init xen_init_cpuid_mask(void) /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ if ((cx & xsave_mask) != xsave_mask) cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */ - if (xen_check_mwait()) cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32)); } diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c index 5fac6919b957..0503c0c493a9 100644 --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c @@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void) static void __init xen_filter_cpu_maps(void) { int i, rc; + unsigned int subtract = 0; if (!xen_initial_domain()) return; @@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void) } else { set_cpu_possible(i, false); set_cpu_present(i, false); + subtract++; } } +#ifdef CONFIG_HOTPLUG_CPU + /* This is akin to using 'nr_cpus' on the Linux command line. + * Which is OK as when we use 'dom0_max_vcpus=X' we can only + * have up to X, while nr_cpu_ids is greater than X. This + * normally is not a problem, except when CPU hotplugging + * is involved and then there might be more than X CPUs + * in the guest - which will not work as there is no + * hypercall to expand the max number of VCPUs an already + * running guest has. So cap it up to X. */ + if (subtract) + nr_cpu_ids = nr_cpu_ids - subtract; +#endif + } static void __init xen_smp_prepare_boot_cpu(void) diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S index 79d7362ad6d1..3e45aa000718 100644 --- a/arch/x86/xen/xen-asm.S +++ b/arch/x86/xen/xen-asm.S @@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct) /* check for unmasked and pending */ cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending - jz 1f + jnz 1f 2: call check_events 1: ENDPATCH(xen_restore_fl_direct) diff --git a/arch/xtensa/include/asm/hardirq.h b/arch/xtensa/include/asm/hardirq.h index 26664cef8f11..91695a135498 100644 --- a/arch/xtensa/include/asm/hardirq.h +++ b/arch/xtensa/include/asm/hardirq.h @@ -11,9 +11,6 @@ #ifndef _XTENSA_HARDIRQ_H #define _XTENSA_HARDIRQ_H -void ack_bad_irq(unsigned int irq); -#define ack_bad_irq ack_bad_irq - #include <asm-generic/hardirq.h> #endif /* _XTENSA_HARDIRQ_H */ diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h index d04cd3a625fa..4beb43c087d3 100644 --- a/arch/xtensa/include/asm/io.h +++ b/arch/xtensa/include/asm/io.h @@ -14,6 +14,7 @@ #ifdef __KERNEL__ #include <asm/byteorder.h> #include <asm/page.h> +#include <linux/bug.h> #include <linux/kernel.h> #include <linux/types.h> diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c index b69b000349fc..d78869a00b11 100644 --- a/arch/xtensa/kernel/signal.c +++ b/arch/xtensa/kernel/signal.c @@ -496,6 +496,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset) signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { + int ret; /* Are we from a system call? */ |