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path: root/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h66
1 files changed, 64 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 49854eb73d1d..ed7d9588b309 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -52,24 +52,47 @@ enum dp_component_depth {
DP_COMPONENT_PIXEL_DEPTH_16BPC = 0x00000004
};
+struct audio_clock_info {
+ /* pixel clock frequency*/
+ uint32_t pixel_clock_in_10khz;
+ /* N - 32KHz audio */
+ uint32_t n_32khz;
+ /* CTS - 32KHz audio*/
+ uint32_t cts_32khz;
+ uint32_t n_44khz;
+ uint32_t cts_44khz;
+ uint32_t n_48khz;
+ uint32_t cts_48khz;
+};
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+enum dynamic_metadata_mode {
+ dmdata_dp,
+ dmdata_hdmi,
+ dmdata_dolby_vision
+};
+#endif
+
struct encoder_info_frame {
/* auxiliary video information */
struct dc_info_packet avi;
struct dc_info_packet gamut;
struct dc_info_packet vendor;
+ struct dc_info_packet hfvsif;
/* source product description */
struct dc_info_packet spd;
/* video stream configuration */
struct dc_info_packet vsc;
/* HDR Static MetaData */
struct dc_info_packet hdrsmd;
- /* custom sdp message */
- struct dc_info_packet dpsdp;
};
struct encoder_unblank_param {
struct dc_link_settings link_settings;
struct dc_crtc_timing timing;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool odm;
+#endif
};
struct encoder_set_dp_phy_pattern_param {
@@ -86,7 +109,22 @@ struct stream_encoder {
enum engine_id id;
};
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+struct enc_state {
+ uint32_t dsc_mode; // DISABLED 0; 1 or 2 indicate enabled state.
+ uint32_t dsc_slice_width;
+ uint32_t sec_gsp_pps_line_num;
+ uint32_t vbid6_line_reference;
+ uint32_t vbid6_line_num;
+ uint32_t sec_gsp_pps_enable;
+ uint32_t sec_stream_enable;
+};
+#endif
+
struct stream_encoder_funcs {
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s);
+ #endif
void (*dp_set_stream_attribute)(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
@@ -123,6 +161,11 @@ struct stream_encoder_funcs {
struct stream_encoder *enc,
const struct encoder_info_frame *info_frame);
+ void (*send_immediate_sdp_message)(
+ struct stream_encoder *enc,
+ const uint8_t *custom_sdp_message,
+ unsigned int sdp_message_size);
+
void (*stop_dp_info_packets)(
struct stream_encoder *enc);
@@ -168,6 +211,25 @@ struct stream_encoder_funcs {
struct stream_encoder *enc,
int tg_inst);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void (*dp_set_dsc_config)(
+ struct stream_encoder *enc,
+ enum optc_dsc_mode dsc_mode,
+ uint32_t dsc_bytes_per_pixel,
+ uint32_t dsc_slice_width,
+ uint8_t *dsc_packed_pps);
+#endif
+
+ void (*set_dynamic_metadata)(struct stream_encoder *enc,
+ bool enable,
+ uint32_t hubp_requestor_id,
+ enum dynamic_metadata_mode dmdata_mode);
+
+ void (*dp_set_odm_combine)(
+ struct stream_encoder *enc,
+ bool odm_combine);
+#endif
};
#endif /* STREAM_ENCODER_H_ */