diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h new file mode 100644 index 000000000000..e3d954434fcc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _clk_11_0_0_SH_MASK_HEADER +#define _clk_11_0_0_SH_MASK_HEADER + + +// addressBlock: clk_clk3_0_SmuClkDec +//CLK3_0_CLK3_CLK_PLL_REQ +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 +#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL +#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L +#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L +//CLK3_0_CLK3_CLK2_DFS_CNTL +#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER__SHIFT 0x0 +#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER_MASK 0x0000007FL + + +#endif |