diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/dce')
| -rw-r--r--[-rwxr-xr-x] | drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h | 0 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 4457 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h | 9836 |
4 files changed, 14293 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h index 09a7df17570d..09a7df17570d 100755..100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h index 1ddc4183a1c9..1ddc4183a1c9 100755..100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h new file mode 100644 index 000000000000..ae798f768853 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h @@ -0,0 +1,4457 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_6_0_D_H +#define DCE_6_0_D_H + +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000A +#define ixATTR0B 0x000B +#define ixATTR0C 0x000C +#define ixATTR0D 0x000D +#define ixATTR0E 0x000E +#define ixATTR0F 0x000F +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR10 0x000B +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR11 0x000C +#define ixAUDIO_DESCRIPTOR12 0x000D +#define ixAUDIO_DESCRIPTOR13 0x000E +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000A +#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002A +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002B +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002C +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002D +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002E +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002F +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003A +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003B +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003C +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003D +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003E +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003F +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005A +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005B +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005C +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005D +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005E +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005F +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270D +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270E +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273E +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2F09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2F0B +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2F0A +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17FF +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1F05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1F0F +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1F0B +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1F04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1F0A +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377B +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377A +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371C +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371D +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371E +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371F +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3F09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3F0C +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3F0E +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0F02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0F04 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0F00 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378A +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378B +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378C +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378D +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378E +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378F +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZALIA_STREAM_DEBUG 0x0005 +#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000A +#define ixCRT0B 0x000B +#define ixCRT0C 0x000C +#define ixCRT0D 0x000D +#define ixCRT0E 0x000E +#define ixCRT0F 0x000F +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001E +#define ixCRT1F 0x001F +#define ixCRT22 0x0022 +#define ixDCIO_DEBUG10 0x0010 +#define ixDCIO_DEBUG1 0x0001 +#define ixDCIO_DEBUG11 0x0011 +#define ixDCIO_DEBUG12 0x0012 +#define ixDCIO_DEBUG13 0x0013 +#define ixDCIO_DEBUG2 0x0002 +#define ixDCIO_DEBUG3 0x0003 +#define ixDCIO_DEBUG4 0x0004 +#define ixDCIO_DEBUG5 0x0005 +#define ixDCIO_DEBUG6 0x0006 +#define ixDCIO_DEBUG7 0x0007 +#define ixDCIO_DEBUG8 0x0008 +#define ixDCIO_DEBUG9 0x0009 +#define ixDCIO_DEBUGA 0x000A +#define ixDCIO_DEBUGB 0x000B +#define ixDCIO_DEBUGC 0x000C +#define ixDCIO_DEBUGD 0x000D +#define ixDCIO_DEBUGE 0x000E +#define ixDCIO_DEBUGF 0x000F +#define ixDCIO_DEBUG_ID 0x0000 +#define ixDMIF_DEBUG02_CORE0 0x0002 +#define ixDMIF_DEBUG02_CORE1 0x000A +#define ixDP_AUX1_DEBUG_A 0x0010 +#define ixDP_AUX1_DEBUG_B 0x0011 +#define ixDP_AUX1_DEBUG_C 0x0012 +#define ixDP_AUX1_DEBUG_D 0x0013 +#define ixDP_AUX1_DEBUG_E 0x0014 +#define ixDP_AUX1_DEBUG_F 0x0015 +#define ixDP_AUX1_DEBUG_G 0x0016 +#define ixDP_AUX1_DEBUG_H 0x0017 +#define ixDP_AUX1_DEBUG_I 0x0018 +#define ixDP_AUX2_DEBUG_A 0x0020 +#define ixDP_AUX2_DEBUG_B 0x0021 +#define ixDP_AUX2_DEBUG_C 0x0022 +#define ixDP_AUX2_DEBUG_D 0x0023 +#define ixDP_AUX2_DEBUG_E 0x0024 +#define ixDP_AUX2_DEBUG_F 0x0025 +#define ixDP_AUX2_DEBUG_G 0x0026 +#define ixDP_AUX2_DEBUG_H 0x0027 +#define ixDP_AUX2_DEBUG_I 0x0028 +#define ixDP_AUX3_DEBUG_A 0x0030 +#define ixDP_AUX3_DEBUG_B 0x0031 +#define ixDP_AUX3_DEBUG_C 0x0032 +#define ixDP_AUX3_DEBUG_D 0x0033 +#define ixDP_AUX3_DEBUG_E 0x0034 +#define ixDP_AUX3_DEBUG_F 0x0035 +#define ixDP_AUX3_DEBUG_G 0x0036 +#define ixDP_AUX3_DEBUG_H 0x0037 +#define ixDP_AUX3_DEBUG_I 0x0038 +#define ixDP_AUX4_DEBUG_A 0x0040 +#define ixDP_AUX4_DEBUG_B 0x0041 +#define ixDP_AUX4_DEBUG_C 0x0042 +#define ixDP_AUX4_DEBUG_D 0x0043 +#define ixDP_AUX4_DEBUG_E 0x0044 +#define ixDP_AUX4_DEBUG_F 0x0045 +#define ixDP_AUX4_DEBUG_G 0x0046 +#define ixDP_AUX4_DEBUG_H 0x0047 +#define ixDP_AUX4_DEBUG_I 0x0048 +#define ixDP_AUX5_DEBUG_A 0x0070 +#define ixDP_AUX5_DEBUG_B 0x0071 +#define ixDP_AUX5_DEBUG_C 0x0072 +#define ixDP_AUX5_DEBUG_D 0x0073 +#define ixDP_AUX5_DEBUG_E 0x0074 +#define ixDP_AUX5_DEBUG_F 0x0075 +#define ixDP_AUX5_DEBUG_G 0x0076 +#define ixDP_AUX5_DEBUG_H 0x0077 +#define ixDP_AUX5_DEBUG_I 0x0078 +#define ixDP_AUX6_DEBUG_A 0x0080 +#define ixDP_AUX6_DEBUG_B 0x0081 +#define ixDP_AUX6_DEBUG_C 0x0082 +#define ixDP_AUX6_DEBUG_D 0x0083 +#define ixDP_AUX6_DEBUG_E 0x0084 +#define ixDP_AUX6_DEBUG_F 0x0085 +#define ixDP_AUX6_DEBUG_G 0x0086 +#define ixDP_AUX6_DEBUG_H 0x0087 +#define ixDP_AUX6_DEBUG_I 0x0088 +#define ixFMT_DEBUG0 0x0001 +#define ixFMT_DEBUG1 0x0002 +#define ixFMT_DEBUG2 0x0003 +#define ixFMT_DEBUG_ID 0x0000 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 +#define ixIDDCCIF02_DBG_DCCIF_C 0x0009 +#define ixIDDCCIF04_DBG_DCCIF_E 0x000B +#define ixIDDCCIF05_DBG_DCCIF_F 0x000C +#define ixMVP_DEBUG_12 0x000C +#define ixMVP_DEBUG_13 0x000D +#define ixMVP_DEBUG_14 0x000E +#define ixMVP_DEBUG_15 0x000F +#define ixMVP_DEBUG_16 0x0010 +#define ixMVP_DEBUG_17 0x0011 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION10 0x000F +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000A +#define ixSINK_DESCRIPTION6 0x000B +#define ixSINK_DESCRIPTION7 0x000C +#define ixSINK_DESCRIPTION8 0x000D +#define ixSINK_DESCRIPTION9 0x000E +#define ixVGADCC_DBG_DCCIF_C 0x007E +#define mmABM_TEST_DEBUG_DATA 0x169F +#define mmABM_TEST_DEBUG_INDEX 0x169E +#define mmAFMT_60958_0 0x1C41 +#define mmAFMT_60958_1 0x1C42 +#define mmAFMT_60958_2 0x1C48 +#define mmAFMT_AUDIO_CRC_CONTROL 0x1C43 +#define mmAFMT_AUDIO_CRC_RESULT 0x1C49 +#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1C52 +#define mmAFMT_AUDIO_INFO0 0x1C3F +#define mmAFMT_AUDIO_INFO1 0x1C40 +#define mmAFMT_AUDIO_PACKET_CONTROL 0x1C4B +#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1C17 +#define mmAFMT_AUDIO_SRC_CONTROL 0x1C4F +#define mmAFMT_AVI_INFO0 0x1C21 +#define mmAFMT_AVI_INFO1 0x1C22 +#define mmAFMT_AVI_INFO2 0x1C23 +#define mmAFMT_AVI_INFO3 0x1C24 +#define mmAFMT_GENERIC_0 0x1C28 +#define mmAFMT_GENERIC_1 0x1C29 +#define mmAFMT_GENERIC_2 0x1C2A +#define mmAFMT_GENERIC_3 0x1C2B +#define mmAFMT_GENERIC_4 0x1C2C +#define mmAFMT_GENERIC_5 0x1C2D +#define mmAFMT_GENERIC_6 0x1C2E +#define mmAFMT_GENERIC_7 0x1C2F +#define mmAFMT_GENERIC_HDR 0x1C27 +#define mmAFMT_INFOFRAME_CONTROL0 0x1C4D +#define mmAFMT_INTERRUPT_STATUS 0x1C14 +#define mmAFMT_ISRC1_0 0x1C18 +#define mmAFMT_ISRC1_1 0x1C19 +#define mmAFMT_ISRC1_2 0x1C1A +#define mmAFMT_ISRC1_3 0x1C1B +#define mmAFMT_ISRC1_4 0x1C1C +#define mmAFMT_ISRC2_0 0x1C1D +#define mmAFMT_ISRC2_1 0x1C1E +#define mmAFMT_ISRC2_2 0x1C1F +#define mmAFMT_ISRC2_3 0x1C20 +#define mmAFMT_MPEG_INFO0 0x1C25 +#define mmAFMT_MPEG_INFO1 0x1C26 +#define mmAFMT_RAMP_CONTROL0 0x1C44 +#define mmAFMT_RAMP_CONTROL1 0x1C45 +#define mmAFMT_RAMP_CONTROL2 0x1C46 +#define mmAFMT_RAMP_CONTROL3 0x1C47 +#define mmAFMT_STATUS 0x1C4A +#define mmAFMT_VBI_PACKET_CONTROL 0x1C4C +#define mmATTRDR 0x00F0 +#define mmATTRDW 0x00F0 +#define mmATTRX 0x00F0 +#define mmAUX_ARB_CONTROL 0x1882 +#define mmAUX_CONTROL 0x1880 +#define mmAUX_DPHY_RX_CONTROL0 0x188A +#define mmAUX_DPHY_RX_CONTROL1 0x188B +#define mmAUX_DPHY_RX_STATUS 0x188D +#define mmAUX_DPHY_TX_CONTROL 0x1889 +#define mmAUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmAUX_DPHY_TX_STATUS 0x188C +#define mmAUX_GTC_SYNC_CONTROL 0x188E +#define mmAUX_GTC_SYNC_DATA 0x1890 +#define mmAUX_INTERRUPT_CONTROL 0x1883 +#define mmAUX_LS_DATA 0x1887 +#define mmAUX_LS_STATUS 0x1885 +#define mmAUXN_IMPCAL 0x190C +#define mmAUXP_IMPCAL 0x190B +#define mmAUX_SW_CONTROL 0x1881 +#define mmAUX_SW_DATA 0x1886 +#define mmAUX_SW_STATUS 0x1884 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17C9 +#define mmAZALIA_AUDIO_DTO 0x17BA +#define mmAZALIA_AUDIO_DTO_CONTROL 0x17BB +#define mmAZALIA_BDL_DMA_CONTROL 0x17BF +#define mmAZALIA_CONTROLLER_DEBUG 0x17CF +#define mmAZALIA_CORB_DMA_CONTROL 0x17C1 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17CA +#define mmAZALIA_DATA_DMA_CONTROL 0x17BE +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17D5 +#define mmAZALIA_F0_CODEC_DEBUG 0x17DF +#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17DE +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17DB +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17DC +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17DD +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17D7 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17DA +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17D9 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17D8 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17D6 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17D3 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17D2 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x17CB +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17CC +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17CD +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0 +#define mmAZALIA_SCLK_CONTROL 0x17BC +#define mmAZALIA_STREAM_DATA 0x17E9 +#define mmAZALIA_STREAM_INDEX 0x17E8 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17BD +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178D +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178C +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179F +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179E +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17E9 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17E8 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ED +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17EC +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17F1 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17F0 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17F5 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17F4 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17F9 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17F8 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17FD +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17FC +#define mmAZ_TEST_DEBUG_DATA 0x17D1 +#define mmAZ_TEST_DEBUG_INDEX 0x17D0 +#define mmBL1_PWM_ABM_CNTL 0x162E +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162F +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162B +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162C +#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162D +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162A +#define mmBL1_PWM_USER_LEVEL 0x1629 +#define mmBL_PWM_CNTL 0x191E +#define mmBL_PWM_CNTL2 0x191F +#define mmBL_PWM_GRP1_REG_LOCK 0x1921 +#define mmBL_PWM_PERIOD_CNTL 0x1920 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19FE +#define mmBPHYC_DAC_MACRO_CNTL 0x19FD +#define mmCC_DC_PIPE_DIS 0x177F +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17D4 +#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1A43 +#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1A44 +#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1A45 +#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1A46 +#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1A47 +#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1A48 +#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1A49 +#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1A4A +#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1A4B +#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1A4C +#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1A4D +#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1A4E +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1B78 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 +#define mmCRTC0_CRTC_BLACK_COLOR 0x1BA2 +#define mmCRTC0_CRTC_BLANK_CONTROL 0x1B9D +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1BA1 +#define mmCRTC0_CRTC_CONTROL 0x1B9C +#define mmCRTC0_CRTC_COUNT_CONTROL 0x1BA9 +#define mmCRTC0_CRTC_COUNT_RESET 0x1BAA +#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1B7C +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1B92 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1B93 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x1B99 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1B98 +#define mmCRTC0_CRTC_GSL_CONTROL 0x1B7B +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1B79 +#define mmCRTC0_CRTC_GSL_WINDOW 0x1B7A +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1B7D +#define mmCRTC0_CRTC_H_BLANK_START_END 0x1B81 +#define mmCRTC0_CRTC_H_SYNC_A 0x1B82 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1B83 +#define mmCRTC0_CRTC_H_SYNC_B 0x1B84 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1B85 +#define mmCRTC0_CRTC_H_TOTAL 0x1B80 +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1B9E +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1B9F +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1BB4 +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB +#define mmCRTC0_CRTC_MASTER_EN 0x1BC2 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1BBF +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 +#define mmCRTC0_CRTC_MVP_STATUS 0x1BC1 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1BA5 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1BA0 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1BB0 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1BB2 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1BB1 +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1BAF +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1BB3 +#define mmCRTC0_CRTC_STATUS 0x1BA3 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1BA6 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1BA8 +#define mmCRTC0_CRTC_STATUS_POSITION 0x1BA4 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1BA7 +#define mmCRTC0_CRTC_STEREO_CONTROL 0x1BAE +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1B9B +#define mmCRTC0_CRTC_STEREO_STATUS 0x1BAD +#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1BC7 +#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1BC6 +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1BBC +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1BBA +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1BBB +#define mmCRTC0_CRTC_TRIGA_CNTL 0x1B94 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1B95 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x1B96 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1B97 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x1BB5 +#define mmCRTC0_CRTC_VBI_END 0x1B86 +#define mmCRTC0_CRTC_V_BLANK_START_END 0x1B8D +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1BAC +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 +#define mmCRTC0_CRTC_V_SYNC_A 0x1B8E +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1B8F +#define mmCRTC0_CRTC_V_SYNC_B 0x1B90 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1B91 +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1B8C +#define mmCRTC0_CRTC_V_TOTAL 0x1B87 +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1B8A +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1B8B +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1B89 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1B88 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1BC4 +#define mmCRTC0_DCFE_DBG_SEL 0x1B7E +#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F +#define mmCRTC0_MASTER_UPDATE_LOCK 0x1BBD +#define mmCRTC0_MASTER_UPDATE_MODE 0x1BBE +#define mmCRTC0_PIXEL_RATE_CNTL 0x0140 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1E78 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1EC3 +#define mmCRTC1_CRTC_BLACK_COLOR 0x1EA2 +#define mmCRTC1_CRTC_BLANK_CONTROL 0x1E9D +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1EA1 +#define mmCRTC1_CRTC_CONTROL 0x1E9C +#define mmCRTC1_CRTC_COUNT_CONTROL 0x1EA9 +#define mmCRTC1_CRTC_COUNT_RESET 0x1EAA +#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1E7C +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1EB6 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1E92 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1E93 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x1E99 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1E98 +#define mmCRTC1_CRTC_GSL_CONTROL 0x1E7B +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1E79 +#define mmCRTC1_CRTC_GSL_WINDOW 0x1E7A +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1E7D +#define mmCRTC1_CRTC_H_BLANK_START_END 0x1E81 +#define mmCRTC1_CRTC_H_SYNC_A 0x1E82 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1E83 +#define mmCRTC1_CRTC_H_SYNC_B 0x1E84 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1E85 +#define mmCRTC1_CRTC_H_TOTAL 0x1E80 +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1E9E +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1E9F +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1EB4 +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1EAB +#define mmCRTC1_CRTC_MASTER_EN 0x1EC2 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1EBF +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1EC0 +#define mmCRTC1_CRTC_MVP_STATUS 0x1EC1 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1EA5 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1EA0 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1EB0 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1EB2 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1EB1 +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1EAF +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1EB3 +#define mmCRTC1_CRTC_STATUS 0x1EA3 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1EA6 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1EA8 +#define mmCRTC1_CRTC_STATUS_POSITION 0x1EA4 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1EA7 +#define mmCRTC1_CRTC_STEREO_CONTROL 0x1EAE +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1E9B +#define mmCRTC1_CRTC_STEREO_STATUS 0x1EAD +#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1EC7 +#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1EC6 +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1EBC +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1EBA +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1EBB +#define mmCRTC1_CRTC_TRIGA_CNTL 0x1E94 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1E95 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x1E96 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1E97 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x1EB5 +#define mmCRTC1_CRTC_VBI_END 0x1E86 +#define mmCRTC1_CRTC_V_BLANK_START_END 0x1E8D +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1EAC +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1EB7 +#define mmCRTC1_CRTC_V_SYNC_A 0x1E8E +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1E8F +#define mmCRTC1_CRTC_V_SYNC_B 0x1E90 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1E91 +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1E8C +#define mmCRTC1_CRTC_V_TOTAL 0x1E87 +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1E8A +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1E8B +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1E89 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1E88 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1EC4 +#define mmCRTC1_DCFE_DBG_SEL 0x1E7E +#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1E7F +#define mmCRTC1_MASTER_UPDATE_LOCK 0x1EBD +#define mmCRTC1_MASTER_UPDATE_MODE 0x1EBE +#define mmCRTC1_PIXEL_RATE_CNTL 0x0144 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41C3 +#define mmCRTC2_CRTC_BLACK_COLOR 0x41A2 +#define mmCRTC2_CRTC_BLANK_CONTROL 0x419D +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41A1 +#define mmCRTC2_CRTC_CONTROL 0x419C +#define mmCRTC2_CRTC_COUNT_CONTROL 0x41A9 +#define mmCRTC2_CRTC_COUNT_RESET 0x41AA +#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417C +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41B6 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define mmCRTC2_CRTC_GSL_CONTROL 0x417B +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 +#define mmCRTC2_CRTC_GSL_WINDOW 0x417A +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417D +#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 +#define mmCRTC2_CRTC_H_SYNC_A 0x4182 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 +#define mmCRTC2_CRTC_H_SYNC_B 0x4184 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 +#define mmCRTC2_CRTC_H_TOTAL 0x4180 +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419E +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419F +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41B4 +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41AB +#define mmCRTC2_CRTC_MASTER_EN 0x41C2 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41BF +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41C0 +#define mmCRTC2_CRTC_MVP_STATUS 0x41C1 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41A5 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41A0 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41B0 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41B2 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41B1 +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41AF +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41B3 +#define mmCRTC2_CRTC_STATUS 0x41A3 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41A6 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41A8 +#define mmCRTC2_CRTC_STATUS_POSITION 0x41A4 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41A7 +#define mmCRTC2_CRTC_STEREO_CONTROL 0x41AE +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419B +#define mmCRTC2_CRTC_STEREO_STATUS 0x41AD +#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41C7 +#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41C6 +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41BC +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41BA +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41BB +#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x41B5 +#define mmCRTC2_CRTC_VBI_END 0x4186 +#define mmCRTC2_CRTC_V_BLANK_START_END 0x418D +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41AC +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41B7 +#define mmCRTC2_CRTC_V_SYNC_A 0x418E +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418F +#define mmCRTC2_CRTC_V_SYNC_B 0x4190 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418C +#define mmCRTC2_CRTC_V_TOTAL 0x4187 +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418A +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418B +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41C4 +#define mmCRTC2_DCFE_DBG_SEL 0x417E +#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417F +#define mmCRTC2_MASTER_UPDATE_LOCK 0x41BD +#define mmCRTC2_MASTER_UPDATE_MODE 0x41BE +#define mmCRTC2_PIXEL_RATE_CNTL 0x0148 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44C3 +#define mmCRTC3_CRTC_BLACK_COLOR 0x44A2 +#define mmCRTC3_CRTC_BLANK_CONTROL 0x449D +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44A1 +#define mmCRTC3_CRTC_CONTROL 0x449C +#define mmCRTC3_CRTC_COUNT_CONTROL 0x44A9 +#define mmCRTC3_CRTC_COUNT_RESET 0x44AA +#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447C +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44B6 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 +#define mmCRTC3_CRTC_GSL_CONTROL 0x447B +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 +#define mmCRTC3_CRTC_GSL_WINDOW 0x447A +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447D +#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 +#define mmCRTC3_CRTC_H_SYNC_A 0x4482 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 +#define mmCRTC3_CRTC_H_SYNC_B 0x4484 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 +#define mmCRTC3_CRTC_H_TOTAL 0x4480 +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449E +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449F +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44B4 +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44AB +#define mmCRTC3_CRTC_MASTER_EN 0x44C2 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44BF +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44C0 +#define mmCRTC3_CRTC_MVP_STATUS 0x44C1 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44A5 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44A0 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44B0 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44B2 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44B1 +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44AF +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44B3 +#define mmCRTC3_CRTC_STATUS 0x44A3 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44A6 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44A8 +#define mmCRTC3_CRTC_STATUS_POSITION 0x44A4 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44A7 +#define mmCRTC3_CRTC_STEREO_CONTROL 0x44AE +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449B +#define mmCRTC3_CRTC_STEREO_STATUS 0x44AD +#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44C7 +#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44C6 +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44BC +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44BA +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44BB +#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x44B5 +#define mmCRTC3_CRTC_VBI_END 0x4486 +#define mmCRTC3_CRTC_V_BLANK_START_END 0x448D +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44AC +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44B7 +#define mmCRTC3_CRTC_V_SYNC_A 0x448E +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448F +#define mmCRTC3_CRTC_V_SYNC_B 0x4490 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448C +#define mmCRTC3_CRTC_V_TOTAL 0x4487 +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448A +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448B +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44C4 +#define mmCRTC3_DCFE_DBG_SEL 0x447E +#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447F +#define mmCRTC_3D_STRUCTURE_CONTROL 0x1B78 +#define mmCRTC3_MASTER_UPDATE_LOCK 0x44BD +#define mmCRTC3_MASTER_UPDATE_MODE 0x44BE +#define mmCRTC3_PIXEL_RATE_CNTL 0x014C +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47C3 +#define mmCRTC4_CRTC_BLACK_COLOR 0x47A2 +#define mmCRTC4_CRTC_BLANK_CONTROL 0x479D +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47A1 +#define mmCRTC4_CRTC_CONTROL 0x479C +#define mmCRTC4_CRTC_COUNT_CONTROL 0x47A9 +#define mmCRTC4_CRTC_COUNT_RESET 0x47AA +#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477C +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47B6 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 +#define mmCRTC4_CRTC_GSL_CONTROL 0x477B +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 +#define mmCRTC4_CRTC_GSL_WINDOW 0x477A +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477D +#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 +#define mmCRTC4_CRTC_H_SYNC_A 0x4782 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 +#define mmCRTC4_CRTC_H_SYNC_B 0x4784 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 +#define mmCRTC4_CRTC_H_TOTAL 0x4780 +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479E +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479F +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47B4 +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47AB +#define mmCRTC4_CRTC_MASTER_EN 0x47C2 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47BF +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47C0 +#define mmCRTC4_CRTC_MVP_STATUS 0x47C1 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47A5 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47A0 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47B0 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47B2 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47B1 +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47AF +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47B3 +#define mmCRTC4_CRTC_STATUS 0x47A3 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47A6 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47A8 +#define mmCRTC4_CRTC_STATUS_POSITION 0x47A4 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47A7 +#define mmCRTC4_CRTC_STEREO_CONTROL 0x47AE +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479B +#define mmCRTC4_CRTC_STEREO_STATUS 0x47AD +#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47C7 +#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47C6 +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47BC +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47BA +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47BB +#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x47B5 +#define mmCRTC4_CRTC_VBI_END 0x4786 +#define mmCRTC4_CRTC_V_BLANK_START_END 0x478D +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47AC +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47B7 +#define mmCRTC4_CRTC_V_SYNC_A 0x478E +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478F +#define mmCRTC4_CRTC_V_SYNC_B 0x4790 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478C +#define mmCRTC4_CRTC_V_TOTAL 0x4787 +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478A +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478B +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47C4 +#define mmCRTC4_DCFE_DBG_SEL 0x477E +#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477F +#define mmCRTC4_MASTER_UPDATE_LOCK 0x47BD +#define mmCRTC4_MASTER_UPDATE_MODE 0x47BE +#define mmCRTC4_PIXEL_RATE_CNTL 0x0150 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4A78 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4AC3 +#define mmCRTC5_CRTC_BLACK_COLOR 0x4AA2 +#define mmCRTC5_CRTC_BLANK_CONTROL 0x4A9D +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4AA1 +#define mmCRTC5_CRTC_CONTROL 0x4A9C +#define mmCRTC5_CRTC_COUNT_CONTROL 0x4AA9 +#define mmCRTC5_CRTC_COUNT_RESET 0x4AAA +#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4A7C +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4AB6 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4A92 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4A93 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x4A99 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4A98 +#define mmCRTC5_CRTC_GSL_CONTROL 0x4A7B +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4A79 +#define mmCRTC5_CRTC_GSL_WINDOW 0x4A7A +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4A7D +#define mmCRTC5_CRTC_H_BLANK_START_END 0x4A81 +#define mmCRTC5_CRTC_H_SYNC_A 0x4A82 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4A83 +#define mmCRTC5_CRTC_H_SYNC_B 0x4A84 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4A85 +#define mmCRTC5_CRTC_H_TOTAL 0x4A80 +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4A9E +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4A9F +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4AB4 +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4AAB +#define mmCRTC5_CRTC_MASTER_EN 0x4AC2 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4ABF +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4AC0 +#define mmCRTC5_CRTC_MVP_STATUS 0x4AC1 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4AA5 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4AA0 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4AB0 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4AB2 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4AB1 +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4AAF +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4AB3 +#define mmCRTC5_CRTC_STATUS 0x4AA3 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4AA6 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4AA8 +#define mmCRTC5_CRTC_STATUS_POSITION 0x4AA4 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4AA7 +#define mmCRTC5_CRTC_STEREO_CONTROL 0x4AAE +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4A9B +#define mmCRTC5_CRTC_STEREO_STATUS 0x4AAD +#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4AC7 +#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4AC6 +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4ABC +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4ABA +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4ABB +#define mmCRTC5_CRTC_TRIGA_CNTL 0x4A94 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4A95 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x4A96 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4A97 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x4AB5 +#define mmCRTC5_CRTC_VBI_END 0x4A86 +#define mmCRTC5_CRTC_V_BLANK_START_END 0x4A8D +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4AAC +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4AB7 +#define mmCRTC5_CRTC_V_SYNC_A 0x4A8E +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4A8F +#define mmCRTC5_CRTC_V_SYNC_B 0x4A90 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4A91 +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4A8C +#define mmCRTC5_CRTC_V_TOTAL 0x4A87 +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4A8A +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4A8B +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4A89 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4A88 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4AC4 +#define mmCRTC5_DCFE_DBG_SEL 0x4A7E +#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4A7F +#define mmCRTC5_MASTER_UPDATE_LOCK 0x4ABD +#define mmCRTC5_MASTER_UPDATE_MODE 0x4ABE +#define mmCRTC5_PIXEL_RATE_CNTL 0x0154 +#define mmCRTC8_DATA 0x00ED +#define mmCRTC8_IDX 0x00ED +#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 +#define mmCRTC_BLACK_COLOR 0x1BA2 +#define mmCRTC_BLANK_CONTROL 0x1B9D +#define mmCRTC_BLANK_DATA_COLOR 0x1BA1 +#define mmCRTC_CONTROL 0x1B9C +#define mmCRTC_COUNT_CONTROL 0x1BA9 +#define mmCRTC_COUNT_RESET 0x1BAA +#define mmCRTC_DCFE_CLOCK_CONTROL 0x1B7C +#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 +#define mmCRTC_DTMTEST_CNTL 0x1B92 +#define mmCRTC_DTMTEST_STATUS_POSITION 0x1B93 +#define mmCRTC_FLOW_CONTROL 0x1B99 +#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1B98 +#define mmCRTC_GSL_CONTROL 0x1B7B +#define mmCRTC_GSL_VSYNC_GAP 0x1B79 +#define mmCRTC_GSL_WINDOW 0x1B7A +#define mmCRTC_H_BLANK_EARLY_NUM 0x1B7D +#define mmCRTC_H_BLANK_START_END 0x1B81 +#define mmCRTC_H_SYNC_A 0x1B82 +#define mmCRTC_H_SYNC_A_CNTL 0x1B83 +#define mmCRTC_H_SYNC_B 0x1B84 +#define mmCRTC_H_SYNC_B_CNTL 0x1B85 +#define mmCRTC_H_TOTAL 0x1B80 +#define mmCRTC_INTERLACE_CONTROL 0x1B9E +#define mmCRTC_INTERLACE_STATUS 0x1B9F +#define mmCRTC_INTERRUPT_CONTROL 0x1BB4 +#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB +#define mmCRTC_MASTER_EN 0x1BC2 +#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1BBF +#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 +#define mmCRTC_MVP_STATUS 0x1BC1 +#define mmCRTC_NOM_VERT_POSITION 0x1BA5 +#define mmCRTC_OVERSCAN_COLOR 0x1BA0 +#define mmCRTC_SNAPSHOT_CONTROL 0x1BB0 +#define mmCRTC_SNAPSHOT_FRAME 0x1BB2 +#define mmCRTC_SNAPSHOT_POSITION 0x1BB1 +#define mmCRTC_SNAPSHOT_STATUS 0x1BAF +#define mmCRTC_START_LINE_CONTROL 0x1BB3 +#define mmCRTC_STATUS 0x1BA3 +#define mmCRTC_STATUS_FRAME_COUNT 0x1BA6 +#define mmCRTC_STATUS_HV_COUNT 0x1BA8 +#define mmCRTC_STATUS_POSITION 0x1BA4 +#define mmCRTC_STATUS_VF_COUNT 0x1BA7 +#define mmCRTC_STEREO_CONTROL 0x1BAE +#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1B9B +#define mmCRTC_STEREO_STATUS 0x1BAD +#define mmCRTC_TEST_DEBUG_DATA 0x1BC7 +#define mmCRTC_TEST_DEBUG_INDEX 0x1BC6 +#define mmCRTC_TEST_PATTERN_COLOR 0x1BBC +#define mmCRTC_TEST_PATTERN_CONTROL 0x1BBA +#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1BBB +#define mmCRTC_TRIGA_CNTL 0x1B94 +#define mmCRTC_TRIGA_MANUAL_TRIG 0x1B95 +#define mmCRTC_TRIGB_CNTL 0x1B96 +#define mmCRTC_TRIGB_MANUAL_TRIG 0x1B97 +#define mmCRTC_UPDATE_LOCK 0x1BB5 +#define mmCRTC_VBI_END 0x1B86 +#define mmCRTC_V_BLANK_START_END 0x1B8D +#define mmCRTC_VERT_SYNC_CONTROL 0x1BAC +#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 +#define mmCRTC_V_SYNC_A 0x1B8E +#define mmCRTC_V_SYNC_A_CNTL 0x1B8F +#define mmCRTC_V_SYNC_B 0x1B90 +#define mmCRTC_V_SYNC_B_CNTL 0x1B91 +#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1B8C +#define mmCRTC_V_TOTAL 0x1B87 +#define mmCRTC_V_TOTAL_CONTROL 0x1B8A +#define mmCRTC_V_TOTAL_INT_STATUS 0x1B8B +#define mmCRTC_V_TOTAL_MAX 0x1B89 +#define mmCRTC_V_TOTAL_MIN 0x1B88 +#define mmCRTC_V_UPDATE_INT_STATUS 0x1BC4 +#define mmCUR_COLOR1 0x1A6C +#define mmCUR_COLOR2 0x1A6D +#define mmCUR_CONTROL 0x1A66 +#define mmCUR_HOT_SPOT 0x1A6B +#define mmCUR_POSITION 0x1A6A +#define mmCUR_REQUEST_FILTER_CNTL 0x1A99 +#define mmCUR_SIZE 0x1A68 +#define mmCUR_SURFACE_ADDRESS 0x1A67 +#define mmCUR_SURFACE_ADDRESS_HIGH 0x1A69 +#define mmCUR_UPDATE 0x1A6E +#define mmD1VGA_CONTROL 0x00CC +#define mmD2VGA_CONTROL 0x00CE +#define mmD3VGA_CONTROL 0x00F8 +#define mmD4VGA_CONTROL 0x00F9 +#define mmD5VGA_CONTROL 0x00FA +#define mmD6VGA_CONTROL 0x00FB +#define mmDAC_AUTODETECT_CONTROL 0x19EE +#define mmDAC_AUTODETECT_CONTROL2 0x19EF +#define mmDAC_AUTODETECT_CONTROL3 0x19F0 +#define mmDAC_AUTODETECT_INT_CONTROL 0x19F2 +#define mmDAC_AUTODETECT_STATUS 0x19F1 +#define mmDAC_CLK_ENABLE 0x0128 +#define mmDAC_COMPARATOR_ENABLE 0x19F7 +#define mmDAC_COMPARATOR_OUTPUT 0x19F8 +#define mmDAC_CONTROL 0x19F6 +#define mmDAC_CRC_CONTROL 0x19E7 +#define mmDAC_CRC_EN 0x19E6 +#define mmDAC_CRC_SIG_CONTROL 0x19EB +#define mmDAC_CRC_SIG_CONTROL_MASK 0x19E9 +#define mmDAC_CRC_SIG_RGB 0x19EA +#define mmDAC_CRC_SIG_RGB_MASK 0x19E8 +#define mmDAC_DATA 0x00F2 +#define mmDAC_DFT_CONFIG 0x19FA +#define mmDAC_ENABLE 0x19E4 +#define mmDAC_FIFO_STATUS 0x19FB +#define mmDAC_FORCE_DATA 0x19F4 +#define mmDAC_FORCE_OUTPUT_CNTL 0x19F3 +#define mmDAC_MACRO_CNTL_RESERVED0 0x19FC +#define mmDAC_MACRO_CNTL_RESERVED1 0x19FD +#define mmDAC_MACRO_CNTL_RESERVED2 0x19FE +#define mmDAC_MACRO_CNTL_RESERVED3 0x19FF +#define mmDAC_MASK 0x00F1 +#define mmDAC_POWERDOWN 0x19F5 +#define mmDAC_PWR_CNTL 0x19F9 +#define mmDAC_R_INDEX 0x00F1 +#define mmDAC_SOURCE_SELECT 0x19E5 +#define mmDAC_STEREOSYNC_SELECT 0x19ED +#define mmDAC_SYNC_TRISTATE_CONTROL 0x19EC +#define mmDAC_W_INDEX 0x00F2 +#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163A +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163B +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163C +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163D +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163E +#define mmDC_ABM1_ACE_THRES_12 0x163F +#define mmDC_ABM1_ACE_THRES_34 0x1640 +#define mmDC_ABM1_BL_MASTER_LOCK 0x169C +#define mmDC_ABM1_CNTL 0x1638 +#define mmDC_ABM1_DEBUG_MISC 0x1649 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165A +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164A +#define mmDC_ABM1_HG_MISC_CTRL 0x164B +#define mmDC_ABM1_HG_RESULT_10 0x1664 +#define mmDC_ABM1_HG_RESULT_1 0x165B +#define mmDC_ABM1_HG_RESULT_11 0x1665 +#define mmDC_ABM1_HG_RESULT_12 0x1666 +#define mmDC_ABM1_HG_RESULT_13 0x1667 +#define mmDC_ABM1_HG_RESULT_14 0x1668 +#define mmDC_ABM1_HG_RESULT_15 0x1669 +#define mmDC_ABM1_HG_RESULT_16 0x166A +#define mmDC_ABM1_HG_RESULT_17 0x166B +#define mmDC_ABM1_HG_RESULT_18 0x166C +#define mmDC_ABM1_HG_RESULT_19 0x166D +#define mmDC_ABM1_HG_RESULT_20 0x166E +#define mmDC_ABM1_HG_RESULT_2 0x165C +#define mmDC_ABM1_HG_RESULT_21 0x166F +#define mmDC_ABM1_HG_RESULT_22 0x1670 +#define mmDC_ABM1_HG_RESULT_23 0x1671 +#define mmDC_ABM1_HG_RESULT_24 0x1672 +#define mmDC_ABM1_HG_RESULT_3 0x165D +#define mmDC_ABM1_HG_RESULT_4 0x165E +#define mmDC_ABM1_HG_RESULT_5 0x165F +#define mmDC_ABM1_HG_RESULT_6 0x1660 +#define mmDC_ABM1_HG_RESULT_7 0x1661 +#define mmDC_ABM1_HG_RESULT_8 0x1662 +#define mmDC_ABM1_HG_RESULT_9 0x1663 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164E +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164D +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define mmDC_ABM1_LS_PIXEL_COUNT 0x164F +#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164C +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169B +#define mmDCCG_AUDIO_DTO0_MODULE 0x016D +#define mmDCCG_AUDIO_DTO0_PHASE 0x016C +#define mmDCCG_AUDIO_DTO1_MODULE 0x0171 +#define mmDCCG_AUDIO_DTO1_PHASE 0x0170 +#define mmDCCG_AUDIO_DTO_SOURCE 0x016B +#define mmDCCG_CAC_STATUS 0x0137 +#define mmDCCG_GATE_DISABLE_CNTL 0x0134 +#define mmDCCG_GTC_CNTL 0x0120 +#define mmDCCG_GTC_CURRENT 0x0123 +#define mmDCCG_GTC_DTO_MODULO 0x0122 +#define mmDCCG_PERFMON_CNTL 0x0133 +#define mmDCCG_PLL0_PLL_ANALOG 0x1708 +#define mmDCCG_PLL0_PLL_CNTL 0x1707 +#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170B +#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170F +#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170E +#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 +#define mmDCCG_PLL0_PLL_FB_DIV 0x1701 +#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 +#define mmDCCG_PLL0_PLL_POST_DIV 0x1702 +#define mmDCCG_PLL0_PLL_REF_DIV 0x1700 +#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 +#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170A +#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170D +#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170C +#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 +#define mmDCCG_PLL1_PLL_ANALOG 0x1718 +#define mmDCCG_PLL1_PLL_CNTL 0x1717 +#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171B +#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x171F +#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x171E +#define mmDCCG_PLL1_PLL_DS_CNTL 0x1715 +#define mmDCCG_PLL1_PLL_FB_DIV 0x1711 +#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x1716 +#define mmDCCG_PLL1_PLL_POST_DIV 0x1712 +#define mmDCCG_PLL1_PLL_REF_DIV 0x1710 +#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1713 +#define mmDCCG_PLL1_PLL_SS_CNTL 0x1714 +#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171A +#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x171D +#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x171C +#define mmDCCG_PLL1_PLL_VREG_CNTL 0x1719 +#define mmDCCG_PLL2_PLL_ANALOG 0x1728 +#define mmDCCG_PLL2_PLL_CNTL 0x1727 +#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x172B +#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x172F +#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x172E +#define mmDCCG_PLL2_PLL_DS_CNTL 0x1725 +#define mmDCCG_PLL2_PLL_FB_DIV 0x1721 +#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x1726 +#define mmDCCG_PLL2_PLL_POST_DIV 0x1722 +#define mmDCCG_PLL2_PLL_REF_DIV 0x1720 +#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1723 +#define mmDCCG_PLL2_PLL_SS_CNTL 0x1724 +#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x172A +#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x172D +#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x172C +#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1729 +#define mmDCCG_SOFT_RESET 0x015F +#define mmDCCG_TEST_CLK_SEL 0x017E +#define mmDCCG_TEST_DEBUG_DATA 0x017D +#define mmDCCG_TEST_DEBUG_INDEX 0x017C +#define mmDCCG_VPCLK_CNTL 0x031F +#define mmDCDEBUG_BUS_CLK1_SEL 0x1860 +#define mmDCDEBUG_BUS_CLK2_SEL 0x1861 +#define mmDCDEBUG_BUS_CLK3_SEL 0x1862 +#define mmDCDEBUG_BUS_CLK4_SEL 0x1863 +#define mmDCDEBUG_OUT_CNTL 0x186B +#define mmDCDEBUG_OUT_DATA 0x186E +#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186A +#define mmDC_DMCU_SCRATCH 0x1618 +#define mmDC_DVODATA_CONFIG 0x1905 +#define mmDCFE0_SOFT_RESET 0x0158 +#define mmDCFE1_SOFT_RESET 0x0159 +#define mmDCFE2_SOFT_RESET 0x015A +#define mmDCFE3_SOFT_RESET 0x015B +#define mmDCFE4_SOFT_RESET 0x015C +#define mmDCFE5_SOFT_RESET 0x015D +#define mmDCFE_DBG_SEL 0x1B7E +#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F +#define mmDC_GENERICA 0x1900 +#define mmDC_GENERICB 0x1901 +#define mmDC_GPIO_DDC1_A 0x194D +#define mmDC_GPIO_DDC1_EN 0x194E +#define mmDC_GPIO_DDC1_MASK 0x194C +#define mmDC_GPIO_DDC1_Y 0x194F +#define mmDC_GPIO_DDC2_A 0x1951 +#define mmDC_GPIO_DDC2_EN 0x1952 +#define mmDC_GPIO_DDC2_MASK 0x1950 +#define mmDC_GPIO_DDC2_Y 0x1953 +#define mmDC_GPIO_DDC3_A 0x1955 +#define mmDC_GPIO_DDC3_EN 0x1956 +#define mmDC_GPIO_DDC3_MASK 0x1954 +#define mmDC_GPIO_DDC3_Y 0x1957 +#define mmDC_GPIO_DDC4_A 0x1959 +#define mmDC_GPIO_DDC4_EN 0x195A +#define mmDC_GPIO_DDC4_MASK 0x1958 +#define mmDC_GPIO_DDC4_Y 0x195B +#define mmDC_GPIO_DDC5_A 0x195D +#define mmDC_GPIO_DDC5_EN 0x195E +#define mmDC_GPIO_DDC5_MASK 0x195C +#define mmDC_GPIO_DDC5_Y 0x195F +#define mmDC_GPIO_DDC6_A 0x1961 +#define mmDC_GPIO_DDC6_EN 0x1962 +#define mmDC_GPIO_DDC6_MASK 0x1960 +#define mmDC_GPIO_DDC6_Y 0x1963 +#define mmDC_GPIO_DDCVGA_A 0x1971 +#define mmDC_GPIO_DDCVGA_EN 0x1972 +#define mmDC_GPIO_DDCVGA_MASK 0x1970 +#define mmDC_GPIO_DDCVGA_Y 0x1973 +#define mmDC_GPIO_DEBUG 0x1904 +#define mmDC_GPIO_DVODATA_A 0x1949 +#define mmDC_GPIO_DVODATA_EN 0x194A +#define mmDC_GPIO_DVODATA_MASK 0x1948 +#define mmDC_GPIO_DVODATA_Y 0x194B +#define mmDC_GPIO_GENERIC_A 0x1945 +#define mmDC_GPIO_GENERIC_EN 0x1946 +#define mmDC_GPIO_GENERIC_MASK 0x1944 +#define mmDC_GPIO_GENERIC_Y 0x1947 +#define mmDC_GPIO_GENLK_A 0x1969 +#define mmDC_GPIO_GENLK_EN 0x196A +#define mmDC_GPIO_GENLK_MASK 0x1968 +#define mmDC_GPIO_GENLK_Y 0x196B +#define mmDC_GPIO_HPD_A 0x196D +#define mmDC_GPIO_HPD_EN 0x196E +#define mmDC_GPIO_HPD_MASK 0x196C +#define mmDC_GPIO_HPD_Y 0x196F +#define mmDC_GPIO_I2CPAD_A 0x1975 +#define mmDC_GPIO_I2CPAD_EN 0x1976 +#define mmDC_GPIO_I2CPAD_MASK 0x1974 +#define mmDC_GPIO_I2CPAD_STRENGTH 0x197A +#define mmDC_GPIO_I2CPAD_Y 0x1977 +#define mmDC_GPIO_PAD_STRENGTH_1 0x1978 +#define mmDC_GPIO_PAD_STRENGTH_2 0x1979 +#define mmDC_GPIO_PWRSEQ_A 0x1941 +#define mmDC_GPIO_PWRSEQ_EN 0x1942 +#define mmDC_GPIO_PWRSEQ_MASK 0x1940 +#define mmDC_GPIO_PWRSEQ_Y 0x1943 +#define mmDC_GPIO_SYNCA_A 0x1965 +#define mmDC_GPIO_SYNCA_EN 0x1966 +#define mmDC_GPIO_SYNCA_MASK 0x1964 +#define mmDC_GPIO_SYNCA_Y 0x1967 +#define mmDC_GPU_TIMER_READ 0x1929 +#define mmDC_GPU_TIMER_READ_CNTL 0x192A +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 +#define mmDC_HPD1_CONTROL 0x1809 +#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 +#define mmDC_HPD1_INT_CONTROL 0x1808 +#define mmDC_HPD1_INT_STATUS 0x1807 +#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18BC +#define mmDC_HPD2_CONTROL 0x180C +#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 +#define mmDC_HPD2_INT_CONTROL 0x180B +#define mmDC_HPD2_INT_STATUS 0x180A +#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18BD +#define mmDC_HPD3_CONTROL 0x180F +#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 +#define mmDC_HPD3_INT_CONTROL 0x180E +#define mmDC_HPD3_INT_STATUS 0x180D +#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18BE +#define mmDC_HPD4_CONTROL 0x1812 +#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 +#define mmDC_HPD4_INT_CONTROL 0x1811 +#define mmDC_HPD4_INT_STATUS 0x1810 +#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18FC +#define mmDC_HPD5_CONTROL 0x1815 +#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 +#define mmDC_HPD5_INT_CONTROL 0x1814 +#define mmDC_HPD5_INT_STATUS 0x1813 +#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18FD +#define mmDC_HPD6_CONTROL 0x1818 +#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 +#define mmDC_HPD6_INT_CONTROL 0x1817 +#define mmDC_HPD6_INT_STATUS 0x1816 +#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18FE +#define mmDC_I2C_ARBITRATION 0x181A +#define mmDC_I2C_CONTROL 0x1819 +#define mmDC_I2C_DATA 0x1833 +#define mmDC_I2C_DDC1_HW_STATUS 0x181D +#define mmDC_I2C_DDC1_SETUP 0x1824 +#define mmDC_I2C_DDC1_SPEED 0x1823 +#define mmDC_I2C_DDC2_HW_STATUS 0x181E +#define mmDC_I2C_DDC2_SETUP 0x1826 +#define mmDC_I2C_DDC2_SPEED 0x1825 +#define mmDC_I2C_DDC3_HW_STATUS 0x181F +#define mmDC_I2C_DDC3_SETUP 0x1828 +#define mmDC_I2C_DDC3_SPEED 0x1827 +#define mmDC_I2C_DDC4_HW_STATUS 0x1820 +#define mmDC_I2C_DDC4_SETUP 0x182A +#define mmDC_I2C_DDC4_SPEED 0x1829 +#define mmDC_I2C_DDC5_HW_STATUS 0x1821 +#define mmDC_I2C_DDC5_SETUP 0x182C +#define mmDC_I2C_DDC5_SPEED 0x182B +#define mmDC_I2C_DDC6_HW_STATUS 0x1822 +#define mmDC_I2C_DDC6_SETUP 0x182E +#define mmDC_I2C_DDC6_SPEED 0x182D +#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 +#define mmDC_I2C_DDCVGA_SETUP 0x1857 +#define mmDC_I2C_DDCVGA_SPEED 0x1856 +#define mmDC_I2C_EDID_DETECT_CTRL 0x186F +#define mmDC_I2C_INTERRUPT_CONTROL 0x181B +#define mmDC_I2C_SW_STATUS 0x181C +#define mmDC_I2C_TRANSACTION0 0x182F +#define mmDC_I2C_TRANSACTION1 0x1830 +#define mmDC_I2C_TRANSACTION2 0x1831 +#define mmDC_I2C_TRANSACTION3 0x1832 +#define mmDCI_CLK_CNTL 0x031E +#define mmDCI_CLK_RAMP_CNTL 0x0324 +#define mmDCI_DEBUG_CONFIG 0x0323 +#define mmDCI_MEM_PWR_CNTL 0x0326 +#define mmDCI_MEM_PWR_STATE 0x031B +#define mmDCI_MEM_PWR_STATE2 0x0322 +#define mmDCIO_DEBUG 0x192E +#define mmDCIO_GSL0_CNTL 0x1924 +#define mmDCIO_GSL1_CNTL 0x1925 +#define mmDCIO_GSL2_CNTL 0x1926 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 +#define mmDCIO_IMPCAL_CNTL_AB 0x190D +#define mmDCIO_IMPCAL_CNTL_CD 0x1911 +#define mmDCIO_IMPCAL_CNTL_EF 0x1915 +#define mmDCIO_TEST_DEBUG_DATA 0x1930 +#define mmDCIO_TEST_DEBUG_INDEX 0x192F +#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198C +#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198E +#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198A +#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198D +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 +#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198B +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 +#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199C +#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199E +#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199A +#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199D +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 +#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 +#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199B +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 +#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19AC +#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19AE +#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19AA +#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19AD +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19A6 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19A7 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19A5 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19A9 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19A8 +#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19A4 +#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19AB +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19A0 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19A1 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19A2 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19A3 +#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19BC +#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19BE +#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19BA +#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19BD +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19B6 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19B7 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19B5 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19B9 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19B8 +#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19B4 +#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19BB +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19B0 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19B1 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19B2 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19B3 +#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19CC +#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19CE +#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19CA +#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19CD +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19C6 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19C7 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19C5 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19C9 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19C8 +#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19C4 +#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19CB +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19C0 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19C1 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19C2 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19C3 +#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19DC +#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19DE +#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19DA +#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19DD +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19D6 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19D7 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19D5 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19D9 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19D8 +#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19D4 +#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19DB +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19D0 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19D1 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19D2 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19D3 +#define mmDCI_SOFT_RESET 0x015E +#define mmDCI_TEST_DEBUG_DATA 0x0321 +#define mmDCI_TEST_DEBUG_INDEX 0x0320 +#define mmDC_LUT_30_COLOR 0x1A7C +#define mmDC_LUT_AUTOFILL 0x1A7F +#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1A81 +#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1A82 +#define mmDC_LUT_BLACK_OFFSET_RED 0x1A83 +#define mmDC_LUT_CONTROL 0x1A80 +#define mmDC_LUT_PWL_DATA 0x1A7B +#define mmDC_LUT_RW_INDEX 0x1A79 +#define mmDC_LUT_RW_MODE 0x1A78 +#define mmDC_LUT_SEQ_COLOR 0x1A7A +#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1A7D +#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1A84 +#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1A85 +#define mmDC_LUT_WHITE_OFFSET_RED 0x1A86 +#define mmDC_LUT_WRITE_EN_MASK 0x1A7E +#define mmDC_MVP_LB_CONTROL 0x1ADB +#define mmDCO_CLK_CNTL 0x192B +#define mmDCO_CLK_RAMP_CNTL 0x192C +#define mmDCO_LIGHT_SLEEP_DIS 0x1907 +#define mmDCO_MEM_POWER_STATE 0x1906 +#define mmDCO_SOFT_RESET 0x0167 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1A43 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1A44 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1A45 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1A46 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1A47 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1A48 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1A49 +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1A4A +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1A4B +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1A4C +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1A4D +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1A4E +#define mmDCP0_CUR_COLOR1 0x1A6C +#define mmDCP0_CUR_COLOR2 0x1A6D +#define mmDCP0_CUR_CONTROL 0x1A66 +#define mmDCP0_CUR_HOT_SPOT 0x1A6B +#define mmDCP0_CUR_POSITION 0x1A6A +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1A99 +#define mmDCP0_CUR_SIZE 0x1A68 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x1A67 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1A69 +#define mmDCP0_CUR_UPDATE 0x1A6E +#define mmDCP0_DC_LUT_30_COLOR 0x1A7C +#define mmDCP0_DC_LUT_AUTOFILL 0x1A7F +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1A81 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1A82 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1A83 +#define mmDCP0_DC_LUT_CONTROL 0x1A80 +#define mmDCP0_DC_LUT_PWL_DATA 0x1A7B +#define mmDCP0_DC_LUT_RW_INDEX 0x1A79 +#define mmDCP0_DC_LUT_RW_MODE 0x1A78 +#define mmDCP0_DC_LUT_SEQ_COLOR 0x1A7A +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1A7D +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1A84 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1A85 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1A86 +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1A7E +#define mmDCP0_DCP_CRC_CONTROL 0x1A87 +#define mmDCP0_DCP_CRC_CURRENT 0x1A89 +#define mmDCP0_DCP_CRC_LAST 0x1A8B +#define mmDCP0_DCP_CRC_MASK 0x1A88 +#define mmDCP0_DCP_DEBUG 0x1A8D +#define mmDCP0_DCP_DEBUG2 0x1A98 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1A65 +#define mmDCP0_DCP_GSL_CONTROL 0x1A90 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 +#define mmDCP0_DCP_RANDOM_SEEDS 0x1A61 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1A60 +#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1A96 +#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1A95 +#define mmDCP0_DEGAMMA_CONTROL 0x1A58 +#define mmDCP0_DENORM_CONTROL 0x1A50 +#define mmDCP0_GAMUT_REMAP_C11_C12 0x1A5A +#define mmDCP0_GAMUT_REMAP_C13_C14 0x1A5B +#define mmDCP0_GAMUT_REMAP_C21_C22 0x1A5C +#define mmDCP0_GAMUT_REMAP_C23_C24 0x1A5D +#define mmDCP0_GAMUT_REMAP_C31_C32 0x1A5E +#define mmDCP0_GAMUT_REMAP_C33_C34 0x1A5F +#define mmDCP0_GAMUT_REMAP_CONTROL 0x1A59 +#define mmDCP0_GRPH_COMPRESS_PITCH 0x1A1A +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B +#define mmDCP0_GRPH_CONTROL 0x1A01 +#define mmDCP0_GRPH_DFQ_CONTROL 0x1A14 +#define mmDCP0_GRPH_DFQ_STATUS 0x1A15 +#define mmDCP0_GRPH_ENABLE 0x1A00 +#define mmDCP0_GRPH_FLIP_CONTROL 0x1A12 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1A17 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1A16 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1A02 +#define mmDCP0_GRPH_PITCH 0x1A06 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1A97 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1A13 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1A09 +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1A0A +#define mmDCP0_GRPH_SWAP_CNTL 0x1A03 +#define mmDCP0_GRPH_UPDATE 0x1A11 +#define mmDCP0_GRPH_X_END 0x1A0D +#define mmDCP0_GRPH_X_START 0x1A0B +#define mmDCP0_GRPH_Y_END 0x1A0E +#define mmDCP0_GRPH_Y_START 0x1A0C +#define mmDCP0_INPUT_CSC_C11_C12 0x1A36 +#define mmDCP0_INPUT_CSC_C13_C14 0x1A37 +#define mmDCP0_INPUT_CSC_C21_C22 0x1A38 +#define mmDCP0_INPUT_CSC_C23_C24 0x1A39 +#define mmDCP0_INPUT_CSC_C31_C32 0x1A3A +#define mmDCP0_INPUT_CSC_C33_C34 0x1A3B +#define mmDCP0_INPUT_CSC_CONTROL 0x1A35 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x1A10 +#define mmDCP0_KEY_CONTROL 0x1A53 +#define mmDCP0_KEY_RANGE_ALPHA 0x1A54 +#define mmDCP0_KEY_RANGE_BLUE 0x1A57 +#define mmDCP0_KEY_RANGE_GREEN 0x1A56 +#define mmDCP0_KEY_RANGE_RED 0x1A55 +#define mmDCP0_OUTPUT_CSC_C11_C12 0x1A3D +#define mmDCP0_OUTPUT_CSC_C13_C14 0x1A3E +#define mmDCP0_OUTPUT_CSC_C21_C22 0x1A3F +#define mmDCP0_OUTPUT_CSC_C23_C24 0x1A40 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x1A41 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x1A42 +#define mmDCP0_OUTPUT_CSC_CONTROL 0x1A3C +#define mmDCP0_OUT_ROUND_CONTROL 0x1A51 +#define mmDCP0_OVL_CONTROL1 0x1A1D +#define mmDCP0_OVL_CONTROL2 0x1A1E +#define mmDCP0_OVL_DFQ_CONTROL 0x1A29 +#define mmDCP0_OVL_DFQ_STATUS 0x1A2A +#define mmDCP0_OVL_ENABLE 0x1A1C +#define mmDCP0_OVL_END 0x1A26 +#define mmDCP0_OVL_PITCH 0x1A21 +#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1A2C +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1A92 +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 +#define mmDCP0_OVL_START 0x1A25 +#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1A93 +#define mmDCP0_OVL_SURFACE_ADDRESS 0x1A20 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1A22 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B +#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1A28 +#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1A23 +#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1A24 +#define mmDCP0_OVL_SWAP_CNTL 0x1A1F +#define mmDCP0_OVL_UPDATE 0x1A27 +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1A2D +#define mmDCP0_PRESCALE_OVL_CONTROL 0x1A31 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1A30 +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1A2F +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1A2E +#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1A32 +#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1A34 +#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1A33 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1AA6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1AA7 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1AA8 +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1AAD +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1AAE +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1AAF +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1AA9 +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1AAA +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1AAB +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1AAC +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1AA4 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1AB2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1AB3 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1AB4 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1AB9 +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1ABA +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1ABB +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1AB5 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1AB6 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1AB7 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1AB8 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1AB0 +#define mmDCP0_REGAMMA_CONTROL 0x1AA0 +#define mmDCP0_REGAMMA_LUT_DATA 0x1AA2 +#define mmDCP0_REGAMMA_LUT_INDEX 0x1AA1 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1AA3 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1D43 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1D44 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1D45 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1D46 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1D47 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1D48 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1D49 +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1D4A +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1D4B +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1D4C +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1D4D +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1D4E +#define mmDCP1_CUR_COLOR1 0x1D6C +#define mmDCP1_CUR_COLOR2 0x1D6D +#define mmDCP1_CUR_CONTROL 0x1D66 +#define mmDCP1_CUR_HOT_SPOT 0x1D6B +#define mmDCP1_CUR_POSITION 0x1D6A +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1D99 +#define mmDCP1_CUR_SIZE 0x1D68 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x1D67 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1D69 +#define mmDCP1_CUR_UPDATE 0x1D6E +#define mmDCP1_DC_LUT_30_COLOR 0x1D7C +#define mmDCP1_DC_LUT_AUTOFILL 0x1D7F +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1D81 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1D82 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1D83 +#define mmDCP1_DC_LUT_CONTROL 0x1D80 +#define mmDCP1_DC_LUT_PWL_DATA 0x1D7B +#define mmDCP1_DC_LUT_RW_INDEX 0x1D79 +#define mmDCP1_DC_LUT_RW_MODE 0x1D78 +#define mmDCP1_DC_LUT_SEQ_COLOR 0x1D7A +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1D7D +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1D84 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1D85 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1D86 +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1D7E +#define mmDCP1_DCP_CRC_CONTROL 0x1D87 +#define mmDCP1_DCP_CRC_CURRENT 0x1D89 +#define mmDCP1_DCP_CRC_LAST 0x1D8B +#define mmDCP1_DCP_CRC_MASK 0x1D88 +#define mmDCP1_DCP_DEBUG 0x1D8D +#define mmDCP1_DCP_DEBUG2 0x1D98 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1D65 +#define mmDCP1_DCP_GSL_CONTROL 0x1D90 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1D91 +#define mmDCP1_DCP_RANDOM_SEEDS 0x1D61 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1D60 +#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1D96 +#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1D95 +#define mmDCP1_DEGAMMA_CONTROL 0x1D58 +#define mmDCP1_DENORM_CONTROL 0x1D50 +#define mmDCP1_GAMUT_REMAP_C11_C12 0x1D5A +#define mmDCP1_GAMUT_REMAP_C13_C14 0x1D5B +#define mmDCP1_GAMUT_REMAP_C21_C22 0x1D5C +#define mmDCP1_GAMUT_REMAP_C23_C24 0x1D5D +#define mmDCP1_GAMUT_REMAP_C31_C32 0x1D5E +#define mmDCP1_GAMUT_REMAP_C33_C34 0x1D5F +#define mmDCP1_GAMUT_REMAP_CONTROL 0x1D59 +#define mmDCP1_GRPH_COMPRESS_PITCH 0x1D1A +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1D19 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1D1B +#define mmDCP1_GRPH_CONTROL 0x1D01 +#define mmDCP1_GRPH_DFQ_CONTROL 0x1D14 +#define mmDCP1_GRPH_DFQ_STATUS 0x1D15 +#define mmDCP1_GRPH_ENABLE 0x1D00 +#define mmDCP1_GRPH_FLIP_CONTROL 0x1D12 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1D17 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1D16 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1D02 +#define mmDCP1_GRPH_PITCH 0x1D06 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1D04 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1D07 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1D05 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D08 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1D97 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1D18 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1D13 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1D09 +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1D0A +#define mmDCP1_GRPH_SWAP_CNTL 0x1D03 +#define mmDCP1_GRPH_UPDATE 0x1D11 +#define mmDCP1_GRPH_X_END 0x1D0D +#define mmDCP1_GRPH_X_START 0x1D0B +#define mmDCP1_GRPH_Y_END 0x1D0E +#define mmDCP1_GRPH_Y_START 0x1D0C +#define mmDCP1_INPUT_CSC_C11_C12 0x1D36 +#define mmDCP1_INPUT_CSC_C13_C14 0x1D37 +#define mmDCP1_INPUT_CSC_C21_C22 0x1D38 +#define mmDCP1_INPUT_CSC_C23_C24 0x1D39 +#define mmDCP1_INPUT_CSC_C31_C32 0x1D3A +#define mmDCP1_INPUT_CSC_C33_C34 0x1D3B +#define mmDCP1_INPUT_CSC_CONTROL 0x1D35 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x1D10 +#define mmDCP1_KEY_CONTROL 0x1D53 +#define mmDCP1_KEY_RANGE_ALPHA 0x1D54 +#define mmDCP1_KEY_RANGE_BLUE 0x1D57 +#define mmDCP1_KEY_RANGE_GREEN 0x1D56 +#define mmDCP1_KEY_RANGE_RED 0x1D55 +#define mmDCP1_OUTPUT_CSC_C11_C12 0x1D3D +#define mmDCP1_OUTPUT_CSC_C13_C14 0x1D3E +#define mmDCP1_OUTPUT_CSC_C21_C22 0x1D3F +#define mmDCP1_OUTPUT_CSC_C23_C24 0x1D40 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x1D41 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x1D42 +#define mmDCP1_OUTPUT_CSC_CONTROL 0x1D3C +#define mmDCP1_OUT_ROUND_CONTROL 0x1D51 +#define mmDCP1_OVL_CONTROL1 0x1D1D +#define mmDCP1_OVL_CONTROL2 0x1D1E +#define mmDCP1_OVL_DFQ_CONTROL 0x1D29 +#define mmDCP1_OVL_DFQ_STATUS 0x1D2A +#define mmDCP1_OVL_ENABLE 0x1D1C +#define mmDCP1_OVL_END 0x1D26 +#define mmDCP1_OVL_PITCH 0x1D21 +#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1D2C +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1D92 +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D94 +#define mmDCP1_OVL_START 0x1D25 +#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1D93 +#define mmDCP1_OVL_SURFACE_ADDRESS 0x1D20 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1D22 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1D2B +#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1D28 +#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1D23 +#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1D24 +#define mmDCP1_OVL_SWAP_CNTL 0x1D1F +#define mmDCP1_OVL_UPDATE 0x1D27 +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1D2D +#define mmDCP1_PRESCALE_OVL_CONTROL 0x1D31 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1D30 +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1D2F +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1D2E +#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1D32 +#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1D34 +#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1D33 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1DA6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1DA7 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1DA8 +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1DAD +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1DAE +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1DAF +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1DA9 +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1DAA +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1DAB +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1DAC +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1DA5 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1DA4 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1DB2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1DB3 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1DB4 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1DB9 +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1DBA +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1DBB +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1DB5 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1DB6 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1DB7 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1DB8 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1DB1 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1DB0 +#define mmDCP1_REGAMMA_CONTROL 0x1DA0 +#define mmDCP1_REGAMMA_LUT_DATA 0x1DA2 +#define mmDCP1_REGAMMA_LUT_INDEX 0x1DA1 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1DA3 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404A +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404B +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404C +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404D +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404E +#define mmDCP2_CUR_COLOR1 0x406C +#define mmDCP2_CUR_COLOR2 0x406D +#define mmDCP2_CUR_CONTROL 0x4066 +#define mmDCP2_CUR_HOT_SPOT 0x406B +#define mmDCP2_CUR_POSITION 0x406A +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 +#define mmDCP2_CUR_SIZE 0x4068 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define mmDCP2_CUR_UPDATE 0x406E +#define mmDCP2_DC_LUT_30_COLOR 0x407C +#define mmDCP2_DC_LUT_AUTOFILL 0x407F +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define mmDCP2_DC_LUT_CONTROL 0x4080 +#define mmDCP2_DC_LUT_PWL_DATA 0x407B +#define mmDCP2_DC_LUT_RW_INDEX 0x4079 +#define mmDCP2_DC_LUT_RW_MODE 0x4078 +#define mmDCP2_DC_LUT_SEQ_COLOR 0x407A +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407D +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407E +#define mmDCP2_DCP_CRC_CONTROL 0x4087 +#define mmDCP2_DCP_CRC_CURRENT 0x4089 +#define mmDCP2_DCP_CRC_LAST 0x408B +#define mmDCP2_DCP_CRC_MASK 0x4088 +#define mmDCP2_DCP_DEBUG 0x408D +#define mmDCP2_DCP_DEBUG2 0x4098 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 +#define mmDCP2_DCP_GSL_CONTROL 0x4090 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define mmDCP2_DCP_RANDOM_SEEDS 0x4061 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 +#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 +#define mmDCP2_DEGAMMA_CONTROL 0x4058 +#define mmDCP2_DENORM_CONTROL 0x4050 +#define mmDCP2_GAMUT_REMAP_C11_C12 0x405A +#define mmDCP2_GAMUT_REMAP_C13_C14 0x405B +#define mmDCP2_GAMUT_REMAP_C21_C22 0x405C +#define mmDCP2_GAMUT_REMAP_C23_C24 0x405D +#define mmDCP2_GAMUT_REMAP_C31_C32 0x405E +#define mmDCP2_GAMUT_REMAP_C33_C34 0x405F +#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 +#define mmDCP2_GRPH_COMPRESS_PITCH 0x401A +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401B +#define mmDCP2_GRPH_CONTROL 0x4001 +#define mmDCP2_GRPH_DFQ_CONTROL 0x4014 +#define mmDCP2_GRPH_DFQ_STATUS 0x4015 +#define mmDCP2_GRPH_ENABLE 0x4000 +#define mmDCP2_GRPH_FLIP_CONTROL 0x4012 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 +#define mmDCP2_GRPH_PITCH 0x4006 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400A +#define mmDCP2_GRPH_SWAP_CNTL 0x4003 +#define mmDCP2_GRPH_UPDATE 0x4011 +#define mmDCP2_GRPH_X_END 0x400D +#define mmDCP2_GRPH_X_START 0x400B +#define mmDCP2_GRPH_Y_END 0x400E +#define mmDCP2_GRPH_Y_START 0x400C +#define mmDCP2_INPUT_CSC_C11_C12 0x4036 +#define mmDCP2_INPUT_CSC_C13_C14 0x4037 +#define mmDCP2_INPUT_CSC_C21_C22 0x4038 +#define mmDCP2_INPUT_CSC_C23_C24 0x4039 +#define mmDCP2_INPUT_CSC_C31_C32 0x403A +#define mmDCP2_INPUT_CSC_C33_C34 0x403B +#define mmDCP2_INPUT_CSC_CONTROL 0x4035 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 +#define mmDCP2_KEY_CONTROL 0x4053 +#define mmDCP2_KEY_RANGE_ALPHA 0x4054 +#define mmDCP2_KEY_RANGE_BLUE 0x4057 +#define mmDCP2_KEY_RANGE_GREEN 0x4056 +#define mmDCP2_KEY_RANGE_RED 0x4055 +#define mmDCP2_OUTPUT_CSC_C11_C12 0x403D +#define mmDCP2_OUTPUT_CSC_C13_C14 0x403E +#define mmDCP2_OUTPUT_CSC_C21_C22 0x403F +#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 +#define mmDCP2_OUTPUT_CSC_CONTROL 0x403C +#define mmDCP2_OUT_ROUND_CONTROL 0x4051 +#define mmDCP2_OVL_CONTROL1 0x401D +#define mmDCP2_OVL_CONTROL2 0x401E +#define mmDCP2_OVL_DFQ_CONTROL 0x4029 +#define mmDCP2_OVL_DFQ_STATUS 0x402A +#define mmDCP2_OVL_ENABLE 0x401C +#define mmDCP2_OVL_END 0x4026 +#define mmDCP2_OVL_PITCH 0x4021 +#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402C +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 +#define mmDCP2_OVL_START 0x4025 +#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 +#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402B +#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 +#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 +#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 +#define mmDCP2_OVL_SWAP_CNTL 0x401F +#define mmDCP2_OVL_UPDATE 0x4027 +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402D +#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402F +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402E +#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 +#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 +#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40A6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40A7 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40A8 +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40AD +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40AE +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40AF +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40A9 +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40AA +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40AB +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40AC +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40A5 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40A4 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40B2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40B3 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40B4 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40B9 +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40BA +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40BB +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40B5 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40B6 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40B7 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40B8 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40B1 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40B0 +#define mmDCP2_REGAMMA_CONTROL 0x40A0 +#define mmDCP2_REGAMMA_LUT_DATA 0x40A2 +#define mmDCP2_REGAMMA_LUT_INDEX 0x40A1 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40A3 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434A +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434B +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434C +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434D +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434E +#define mmDCP3_CUR_COLOR1 0x436C +#define mmDCP3_CUR_COLOR2 0x436D +#define mmDCP3_CUR_CONTROL 0x4366 +#define mmDCP3_CUR_HOT_SPOT 0x436B +#define mmDCP3_CUR_POSITION 0x436A +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 +#define mmDCP3_CUR_SIZE 0x4368 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 +#define mmDCP3_CUR_UPDATE 0x436E +#define mmDCP3_DC_LUT_30_COLOR 0x437C +#define mmDCP3_DC_LUT_AUTOFILL 0x437F +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 +#define mmDCP3_DC_LUT_CONTROL 0x4380 +#define mmDCP3_DC_LUT_PWL_DATA 0x437B +#define mmDCP3_DC_LUT_RW_INDEX 0x4379 +#define mmDCP3_DC_LUT_RW_MODE 0x4378 +#define mmDCP3_DC_LUT_SEQ_COLOR 0x437A +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437D +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437E +#define mmDCP3_DCP_CRC_CONTROL 0x4387 +#define mmDCP3_DCP_CRC_CURRENT 0x4389 +#define mmDCP3_DCP_CRC_LAST 0x438B +#define mmDCP3_DCP_CRC_MASK 0x4388 +#define mmDCP3_DCP_DEBUG 0x438D +#define mmDCP3_DCP_DEBUG2 0x4398 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 +#define mmDCP3_DCP_GSL_CONTROL 0x4390 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 +#define mmDCP3_DCP_RANDOM_SEEDS 0x4361 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 +#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 +#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 +#define mmDCP3_DEGAMMA_CONTROL 0x4358 +#define mmDCP3_DENORM_CONTROL 0x4350 +#define mmDCP3_GAMUT_REMAP_C11_C12 0x435A +#define mmDCP3_GAMUT_REMAP_C13_C14 0x435B +#define mmDCP3_GAMUT_REMAP_C21_C22 0x435C +#define mmDCP3_GAMUT_REMAP_C23_C24 0x435D +#define mmDCP3_GAMUT_REMAP_C31_C32 0x435E +#define mmDCP3_GAMUT_REMAP_C33_C34 0x435F +#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 +#define mmDCP3_GRPH_COMPRESS_PITCH 0x431A +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431B +#define mmDCP3_GRPH_CONTROL 0x4301 +#define mmDCP3_GRPH_DFQ_CONTROL 0x4314 +#define mmDCP3_GRPH_DFQ_STATUS 0x4315 +#define mmDCP3_GRPH_ENABLE 0x4300 +#define mmDCP3_GRPH_FLIP_CONTROL 0x4312 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 +#define mmDCP3_GRPH_PITCH 0x4306 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430A +#define mmDCP3_GRPH_SWAP_CNTL 0x4303 +#define mmDCP3_GRPH_UPDATE 0x4311 +#define mmDCP3_GRPH_X_END 0x430D +#define mmDCP3_GRPH_X_START 0x430B +#define mmDCP3_GRPH_Y_END 0x430E +#define mmDCP3_GRPH_Y_START 0x430C +#define mmDCP3_INPUT_CSC_C11_C12 0x4336 +#define mmDCP3_INPUT_CSC_C13_C14 0x4337 +#define mmDCP3_INPUT_CSC_C21_C22 0x4338 +#define mmDCP3_INPUT_CSC_C23_C24 0x4339 +#define mmDCP3_INPUT_CSC_C31_C32 0x433A +#define mmDCP3_INPUT_CSC_C33_C34 0x433B +#define mmDCP3_INPUT_CSC_CONTROL 0x4335 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 +#define mmDCP3_KEY_CONTROL 0x4353 +#define mmDCP3_KEY_RANGE_ALPHA 0x4354 +#define mmDCP3_KEY_RANGE_BLUE 0x4357 +#define mmDCP3_KEY_RANGE_GREEN 0x4356 +#define mmDCP3_KEY_RANGE_RED 0x4355 +#define mmDCP3_OUTPUT_CSC_C11_C12 0x433D +#define mmDCP3_OUTPUT_CSC_C13_C14 0x433E +#define mmDCP3_OUTPUT_CSC_C21_C22 0x433F +#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 +#define mmDCP3_OUTPUT_CSC_CONTROL 0x433C +#define mmDCP3_OUT_ROUND_CONTROL 0x4351 +#define mmDCP3_OVL_CONTROL1 0x431D +#define mmDCP3_OVL_CONTROL2 0x431E +#define mmDCP3_OVL_DFQ_CONTROL 0x4329 +#define mmDCP3_OVL_DFQ_STATUS 0x432A +#define mmDCP3_OVL_ENABLE 0x431C +#define mmDCP3_OVL_END 0x4326 +#define mmDCP3_OVL_PITCH 0x4321 +#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432C +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 +#define mmDCP3_OVL_START 0x4325 +#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 +#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432B +#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 +#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 +#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 +#define mmDCP3_OVL_SWAP_CNTL 0x431F +#define mmDCP3_OVL_UPDATE 0x4327 +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432D +#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432F +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432E +#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 +#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 +#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43A6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43A7 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43A8 +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43AD +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43AE +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43AF +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43A9 +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43AA +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43AB +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43AC +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43A5 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43A4 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43B2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43B3 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43B4 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43B9 +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43BA +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43BB +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43B5 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43B6 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43B7 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43B8 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43B1 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43B0 +#define mmDCP3_REGAMMA_CONTROL 0x43A0 +#define mmDCP3_REGAMMA_LUT_DATA 0x43A2 +#define mmDCP3_REGAMMA_LUT_INDEX 0x43A1 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43A3 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464A +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464B +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464C +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464D +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464E +#define mmDCP4_CUR_COLOR1 0x466C +#define mmDCP4_CUR_COLOR2 0x466D +#define mmDCP4_CUR_CONTROL 0x4666 +#define mmDCP4_CUR_HOT_SPOT 0x466B +#define mmDCP4_CUR_POSITION 0x466A +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 +#define mmDCP4_CUR_SIZE 0x4668 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 +#define mmDCP4_CUR_UPDATE 0x466E +#define mmDCP4_DC_LUT_30_COLOR 0x467C +#define mmDCP4_DC_LUT_AUTOFILL 0x467F +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 +#define mmDCP4_DC_LUT_CONTROL 0x4680 +#define mmDCP4_DC_LUT_PWL_DATA 0x467B +#define mmDCP4_DC_LUT_RW_INDEX 0x4679 +#define mmDCP4_DC_LUT_RW_MODE 0x4678 +#define mmDCP4_DC_LUT_SEQ_COLOR 0x467A +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467D +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467E +#define mmDCP4_DCP_CRC_CONTROL 0x4687 +#define mmDCP4_DCP_CRC_CURRENT 0x4689 +#define mmDCP4_DCP_CRC_LAST 0x468B +#define mmDCP4_DCP_CRC_MASK 0x4688 +#define mmDCP4_DCP_DEBUG 0x468D +#define mmDCP4_DCP_DEBUG2 0x4698 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 +#define mmDCP4_DCP_GSL_CONTROL 0x4690 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 +#define mmDCP4_DCP_RANDOM_SEEDS 0x4661 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 +#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 +#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 +#define mmDCP4_DEGAMMA_CONTROL 0x4658 +#define mmDCP4_DENORM_CONTROL 0x4650 +#define mmDCP4_GAMUT_REMAP_C11_C12 0x465A +#define mmDCP4_GAMUT_REMAP_C13_C14 0x465B +#define mmDCP4_GAMUT_REMAP_C21_C22 0x465C +#define mmDCP4_GAMUT_REMAP_C23_C24 0x465D +#define mmDCP4_GAMUT_REMAP_C31_C32 0x465E +#define mmDCP4_GAMUT_REMAP_C33_C34 0x465F +#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 +#define mmDCP4_GRPH_COMPRESS_PITCH 0x461A +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461B +#define mmDCP4_GRPH_CONTROL 0x4601 +#define mmDCP4_GRPH_DFQ_CONTROL 0x4614 +#define mmDCP4_GRPH_DFQ_STATUS 0x4615 +#define mmDCP4_GRPH_ENABLE 0x4600 +#define mmDCP4_GRPH_FLIP_CONTROL 0x4612 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 +#define mmDCP4_GRPH_PITCH 0x4606 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460A +#define mmDCP4_GRPH_SWAP_CNTL 0x4603 +#define mmDCP4_GRPH_UPDATE 0x4611 +#define mmDCP4_GRPH_X_END 0x460D +#define mmDCP4_GRPH_X_START 0x460B +#define mmDCP4_GRPH_Y_END 0x460E +#define mmDCP4_GRPH_Y_START 0x460C +#define mmDCP4_INPUT_CSC_C11_C12 0x4636 +#define mmDCP4_INPUT_CSC_C13_C14 0x4637 +#define mmDCP4_INPUT_CSC_C21_C22 0x4638 +#define mmDCP4_INPUT_CSC_C23_C24 0x4639 +#define mmDCP4_INPUT_CSC_C31_C32 0x463A +#define mmDCP4_INPUT_CSC_C33_C34 0x463B +#define mmDCP4_INPUT_CSC_CONTROL 0x4635 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 +#define mmDCP4_KEY_CONTROL 0x4653 +#define mmDCP4_KEY_RANGE_ALPHA 0x4654 +#define mmDCP4_KEY_RANGE_BLUE 0x4657 +#define mmDCP4_KEY_RANGE_GREEN 0x4656 +#define mmDCP4_KEY_RANGE_RED 0x4655 +#define mmDCP4_OUTPUT_CSC_C11_C12 0x463D +#define mmDCP4_OUTPUT_CSC_C13_C14 0x463E +#define mmDCP4_OUTPUT_CSC_C21_C22 0x463F +#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 +#define mmDCP4_OUTPUT_CSC_CONTROL 0x463C +#define mmDCP4_OUT_ROUND_CONTROL 0x4651 +#define mmDCP4_OVL_CONTROL1 0x461D +#define mmDCP4_OVL_CONTROL2 0x461E +#define mmDCP4_OVL_DFQ_CONTROL 0x4629 +#define mmDCP4_OVL_DFQ_STATUS 0x462A +#define mmDCP4_OVL_ENABLE 0x461C +#define mmDCP4_OVL_END 0x4626 +#define mmDCP4_OVL_PITCH 0x4621 +#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462C +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 +#define mmDCP4_OVL_START 0x4625 +#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 +#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462B +#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 +#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 +#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 +#define mmDCP4_OVL_SWAP_CNTL 0x461F +#define mmDCP4_OVL_UPDATE 0x4627 +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462D +#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462F +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462E +#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 +#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 +#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46A6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46A7 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46A8 +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46AD +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46AE +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46AF +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46A9 +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46AA +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46AB +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46AC +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46A5 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46A4 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46B2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46B3 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46B4 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46B9 +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46BA +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46BB +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46B5 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46B6 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46B7 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46B8 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46B1 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46B0 +#define mmDCP4_REGAMMA_CONTROL 0x46A0 +#define mmDCP4_REGAMMA_LUT_DATA 0x46A2 +#define mmDCP4_REGAMMA_LUT_INDEX 0x46A1 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46A3 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494A +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494B +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494C +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494D +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494E +#define mmDCP5_CUR_COLOR1 0x496C +#define mmDCP5_CUR_COLOR2 0x496D +#define mmDCP5_CUR_CONTROL 0x4966 +#define mmDCP5_CUR_HOT_SPOT 0x496B +#define mmDCP5_CUR_POSITION 0x496A +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 +#define mmDCP5_CUR_SIZE 0x4968 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 +#define mmDCP5_CUR_UPDATE 0x496E +#define mmDCP5_DC_LUT_30_COLOR 0x497C +#define mmDCP5_DC_LUT_AUTOFILL 0x497F +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 +#define mmDCP5_DC_LUT_CONTROL 0x4980 +#define mmDCP5_DC_LUT_PWL_DATA 0x497B +#define mmDCP5_DC_LUT_RW_INDEX 0x4979 +#define mmDCP5_DC_LUT_RW_MODE 0x4978 +#define mmDCP5_DC_LUT_SEQ_COLOR 0x497A +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497D +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497E +#define mmDCP5_DCP_CRC_CONTROL 0x4987 +#define mmDCP5_DCP_CRC_CURRENT 0x4989 +#define mmDCP5_DCP_CRC_LAST 0x498B +#define mmDCP5_DCP_CRC_MASK 0x4988 +#define mmDCP5_DCP_DEBUG 0x498D +#define mmDCP5_DCP_DEBUG2 0x4998 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 +#define mmDCP5_DCP_GSL_CONTROL 0x4990 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 +#define mmDCP5_DCP_RANDOM_SEEDS 0x4961 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 +#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 +#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 +#define mmDCP5_DEGAMMA_CONTROL 0x4958 +#define mmDCP5_DENORM_CONTROL 0x4950 +#define mmDCP5_GAMUT_REMAP_C11_C12 0x495A +#define mmDCP5_GAMUT_REMAP_C13_C14 0x495B +#define mmDCP5_GAMUT_REMAP_C21_C22 0x495C +#define mmDCP5_GAMUT_REMAP_C23_C24 0x495D +#define mmDCP5_GAMUT_REMAP_C31_C32 0x495E +#define mmDCP5_GAMUT_REMAP_C33_C34 0x495F +#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 +#define mmDCP5_GRPH_COMPRESS_PITCH 0x491A +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491B +#define mmDCP5_GRPH_CONTROL 0x4901 +#define mmDCP5_GRPH_DFQ_CONTROL 0x4914 +#define mmDCP5_GRPH_DFQ_STATUS 0x4915 +#define mmDCP5_GRPH_ENABLE 0x4900 +#define mmDCP5_GRPH_FLIP_CONTROL 0x4912 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 +#define mmDCP5_GRPH_PITCH 0x4906 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490A +#define mmDCP5_GRPH_SWAP_CNTL 0x4903 +#define mmDCP5_GRPH_UPDATE 0x4911 +#define mmDCP5_GRPH_X_END 0x490D +#define mmDCP5_GRPH_X_START 0x490B +#define mmDCP5_GRPH_Y_END 0x490E +#define mmDCP5_GRPH_Y_START 0x490C +#define mmDCP5_INPUT_CSC_C11_C12 0x4936 +#define mmDCP5_INPUT_CSC_C13_C14 0x4937 +#define mmDCP5_INPUT_CSC_C21_C22 0x4938 +#define mmDCP5_INPUT_CSC_C23_C24 0x4939 +#define mmDCP5_INPUT_CSC_C31_C32 0x493A +#define mmDCP5_INPUT_CSC_C33_C34 0x493B +#define mmDCP5_INPUT_CSC_CONTROL 0x4935 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 +#define mmDCP5_KEY_CONTROL 0x4953 +#define mmDCP5_KEY_RANGE_ALPHA 0x4954 +#define mmDCP5_KEY_RANGE_BLUE 0x4957 +#define mmDCP5_KEY_RANGE_GREEN 0x4956 +#define mmDCP5_KEY_RANGE_RED 0x4955 +#define mmDCP5_OUTPUT_CSC_C11_C12 0x493D +#define mmDCP5_OUTPUT_CSC_C13_C14 0x493E +#define mmDCP5_OUTPUT_CSC_C21_C22 0x493F +#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 +#define mmDCP5_OUTPUT_CSC_CONTROL 0x493C +#define mmDCP5_OUT_ROUND_CONTROL 0x4951 +#define mmDCP5_OVL_CONTROL1 0x491D +#define mmDCP5_OVL_CONTROL2 0x491E +#define mmDCP5_OVL_DFQ_CONTROL 0x4929 +#define mmDCP5_OVL_DFQ_STATUS 0x492A +#define mmDCP5_OVL_ENABLE 0x491C +#define mmDCP5_OVL_END 0x4926 +#define mmDCP5_OVL_PITCH 0x4921 +#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492C +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 +#define mmDCP5_OVL_START 0x4925 +#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 +#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492B +#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 +#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 +#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 +#define mmDCP5_OVL_SWAP_CNTL 0x491F +#define mmDCP5_OVL_UPDATE 0x4927 +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492D +#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492F +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492E +#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 +#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 +#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49A6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49A7 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49A8 +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49AD +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49AE +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49AF +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49A9 +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49AA +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49AB +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49AC +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49A5 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49A4 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49B2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49B3 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49B4 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49B9 +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49BA +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49BB +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49B5 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49B6 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49B7 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49B8 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49B1 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49B0 +#define mmDCP5_REGAMMA_CONTROL 0x49A0 +#define mmDCP5_REGAMMA_LUT_DATA 0x49A2 +#define mmDCP5_REGAMMA_LUT_INDEX 0x49A1 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49A3 +#define mmDC_PAD_EXTERN_SIG 0x1902 +#define mmDCP_CRC_CONTROL 0x1A87 +#define mmDCP_CRC_CURRENT 0x1A89 +#define mmDCP_CRC_LAST 0x1A8B +#define mmDCP_CRC_MASK 0x1A88 +#define mmDCP_DEBUG 0x1A8D +#define mmDCP_DEBUG2 0x1A98 +#define mmDCP_FP_CONVERTED_FIELD 0x1A65 +#define mmDC_PGCNTL_STATUS_REG 0x177E +#define mmDC_PGFSM_CONFIG_REG 0x177C +#define mmDC_PGFSM_WRITE_REG 0x177D +#define mmDCP_GSL_CONTROL 0x1A90 +#define mmDCPG_TEST_DEBUG_DATA 0x177B +#define mmDCPG_TEST_DEBUG_INDEX 0x1779 +#define mmDC_PINSTRAPS 0x1917 +#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 +#define mmDCP_RANDOM_SEEDS 0x1A61 +#define mmDCP_SPATIAL_DITHER_CNTL 0x1A60 +#define mmDCP_TEST_DEBUG_DATA 0x1A96 +#define mmDCP_TEST_DEBUG_INDEX 0x1A95 +#define mmDC_RBBMIF_RDWR_CNTL1 0x031A +#define mmDC_RBBMIF_RDWR_CNTL2 0x031D +#define mmDC_REF_CLK_CNTL 0x1903 +#define mmDC_XDMA_INTERFACE_CNTL 0x0327 +#define mmDEGAMMA_CONTROL 0x1A58 +#define mmDENORM_CONTROL 0x1A50 +#define mmDENTIST_DISPCLK_CNTL 0x0124 +#define mmDIG0_AFMT_60958_0 0x1C41 +#define mmDIG0_AFMT_60958_1 0x1C42 +#define mmDIG0_AFMT_60958_2 0x1C48 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1C43 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1C49 +#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1C52 +#define mmDIG0_AFMT_AUDIO_INFO0 0x1C3F +#define mmDIG0_AFMT_AUDIO_INFO1 0x1C40 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1C4B +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1C17 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1C4F +#define mmDIG0_AFMT_AVI_INFO0 0x1C21 +#define mmDIG0_AFMT_AVI_INFO1 0x1C22 +#define mmDIG0_AFMT_AVI_INFO2 0x1C23 +#define mmDIG0_AFMT_AVI_INFO3 0x1C24 +#define mmDIG0_AFMT_GENERIC_0 0x1C28 +#define mmDIG0_AFMT_GENERIC_1 0x1C29 +#define mmDIG0_AFMT_GENERIC_2 0x1C2A +#define mmDIG0_AFMT_GENERIC_3 0x1C2B +#define mmDIG0_AFMT_GENERIC_4 0x1C2C +#define mmDIG0_AFMT_GENERIC_5 0x1C2D +#define mmDIG0_AFMT_GENERIC_6 0x1C2E +#define mmDIG0_AFMT_GENERIC_7 0x1C2F +#define mmDIG0_AFMT_GENERIC_HDR 0x1C27 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1C4D +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1C14 +#define mmDIG0_AFMT_ISRC1_0 0x1C18 +#define mmDIG0_AFMT_ISRC1_1 0x1C19 +#define mmDIG0_AFMT_ISRC1_2 0x1C1A +#define mmDIG0_AFMT_ISRC1_3 0x1C1B +#define mmDIG0_AFMT_ISRC1_4 0x1C1C +#define mmDIG0_AFMT_ISRC2_0 0x1C1D +#define mmDIG0_AFMT_ISRC2_1 0x1C1E +#define mmDIG0_AFMT_ISRC2_2 0x1C1F +#define mmDIG0_AFMT_ISRC2_3 0x1C20 +#define mmDIG0_AFMT_MPEG_INFO0 0x1C25 +#define mmDIG0_AFMT_MPEG_INFO1 0x1C26 +#define mmDIG0_AFMT_RAMP_CONTROL0 0x1C44 +#define mmDIG0_AFMT_RAMP_CONTROL1 0x1C45 +#define mmDIG0_AFMT_RAMP_CONTROL2 0x1C46 +#define mmDIG0_AFMT_RAMP_CONTROL3 0x1C47 +#define mmDIG0_AFMT_STATUS 0x1C4A +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1C4C +#define mmDIG0_DIG_BE_CNTL 0x1C50 +#define mmDIG0_DIG_BE_EN_CNTL 0x1C51 +#define mmDIG0_DIG_CLOCK_PATTERN 0x1C03 +#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1C08 +#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1C09 +#define mmDIG0_DIG_FE_CNTL 0x1C00 +#define mmDIG0_DIG_FIFO_STATUS 0x1C0A +#define mmDIG0_DIG_LANE_ENABLE 0x1C8D +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1C01 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1C02 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1C05 +#define mmDIG0_DIG_TEST_PATTERN 0x1C04 +#define mmDIG0_HDMI_ACR_32_0 0x1C37 +#define mmDIG0_HDMI_ACR_32_1 0x1C38 +#define mmDIG0_HDMI_ACR_44_0 0x1C39 +#define mmDIG0_HDMI_ACR_44_1 0x1C3A +#define mmDIG0_HDMI_ACR_48_0 0x1C3B +#define mmDIG0_HDMI_ACR_48_1 0x1C3C +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1C0F +#define mmDIG0_HDMI_ACR_STATUS_0 0x1C3D +#define mmDIG0_HDMI_ACR_STATUS_1 0x1C3E +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1C0E +#define mmDIG0_HDMI_CONTROL 0x1C0C +#define mmDIG0_HDMI_GC 0x1C16 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1C13 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1C30 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1C11 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1C12 +#define mmDIG0_HDMI_STATUS 0x1C0D +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1C10 +#define mmDIG0_LVDS_DATA_CNTL 0x1C8C +#define mmDIG0_TMDS_CNTL 0x1C7C +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1C7E +#define mmDIG0_TMDS_CONTROL_CHAR 0x1C7D +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1C86 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1C87 +#define mmDIG0_TMDS_CTL_BITS 0x1C83 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1C84 +#define mmDIG0_TMDS_DEBUG 0x1C82 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1C7F +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 +#define mmDIG1_AFMT_60958_0 0x1F41 +#define mmDIG1_AFMT_60958_1 0x1F42 +#define mmDIG1_AFMT_60958_2 0x1F48 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1F43 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1F49 +#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1F52 +#define mmDIG1_AFMT_AUDIO_INFO0 0x1F3F +#define mmDIG1_AFMT_AUDIO_INFO1 0x1F40 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1F4B +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1F17 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1F4F +#define mmDIG1_AFMT_AVI_INFO0 0x1F21 +#define mmDIG1_AFMT_AVI_INFO1 0x1F22 +#define mmDIG1_AFMT_AVI_INFO2 0x1F23 +#define mmDIG1_AFMT_AVI_INFO3 0x1F24 +#define mmDIG1_AFMT_GENERIC_0 0x1F28 +#define mmDIG1_AFMT_GENERIC_1 0x1F29 +#define mmDIG1_AFMT_GENERIC_2 0x1F2A +#define mmDIG1_AFMT_GENERIC_3 0x1F2B +#define mmDIG1_AFMT_GENERIC_4 0x1F2C +#define mmDIG1_AFMT_GENERIC_5 0x1F2D +#define mmDIG1_AFMT_GENERIC_6 0x1F2E +#define mmDIG1_AFMT_GENERIC_7 0x1F2F +#define mmDIG1_AFMT_GENERIC_HDR 0x1F27 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1F4D +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1F14 +#define mmDIG1_AFMT_ISRC1_0 0x1F18 +#define mmDIG1_AFMT_ISRC1_1 0x1F19 +#define mmDIG1_AFMT_ISRC1_2 0x1F1A +#define mmDIG1_AFMT_ISRC1_3 0x1F1B +#define mmDIG1_AFMT_ISRC1_4 0x1F1C +#define mmDIG1_AFMT_ISRC2_0 0x1F1D +#define mmDIG1_AFMT_ISRC2_1 0x1F1E +#define mmDIG1_AFMT_ISRC2_2 0x1F1F +#define mmDIG1_AFMT_ISRC2_3 0x1F20 +#define mmDIG1_AFMT_MPEG_INFO0 0x1F25 +#define mmDIG1_AFMT_MPEG_INFO1 0x1F26 +#define mmDIG1_AFMT_RAMP_CONTROL0 0x1F44 +#define mmDIG1_AFMT_RAMP_CONTROL1 0x1F45 +#define mmDIG1_AFMT_RAMP_CONTROL2 0x1F46 +#define mmDIG1_AFMT_RAMP_CONTROL3 0x1F47 +#define mmDIG1_AFMT_STATUS 0x1F4A +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1F4C +#define mmDIG1_DIG_BE_CNTL 0x1F50 +#define mmDIG1_DIG_BE_EN_CNTL 0x1F51 +#define mmDIG1_DIG_CLOCK_PATTERN 0x1F03 +#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1F08 +#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1F09 +#define mmDIG1_DIG_FE_CNTL 0x1F00 +#define mmDIG1_DIG_FIFO_STATUS 0x1F0A +#define mmDIG1_DIG_LANE_ENABLE 0x1F8D +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1F01 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1F02 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1F05 +#define mmDIG1_DIG_TEST_PATTERN 0x1F04 +#define mmDIG1_HDMI_ACR_32_0 0x1F37 +#define mmDIG1_HDMI_ACR_32_1 0x1F38 +#define mmDIG1_HDMI_ACR_44_0 0x1F39 +#define mmDIG1_HDMI_ACR_44_1 0x1F3A +#define mmDIG1_HDMI_ACR_48_0 0x1F3B +#define mmDIG1_HDMI_ACR_48_1 0x1F3C +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1F0F +#define mmDIG1_HDMI_ACR_STATUS_0 0x1F3D +#define mmDIG1_HDMI_ACR_STATUS_1 0x1F3E +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1F0E +#define mmDIG1_HDMI_CONTROL 0x1F0C +#define mmDIG1_HDMI_GC 0x1F16 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1F13 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1F30 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1F11 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1F12 +#define mmDIG1_HDMI_STATUS 0x1F0D +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1F10 +#define mmDIG1_LVDS_DATA_CNTL 0x1F8C +#define mmDIG1_TMDS_CNTL 0x1F7C +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1F7E +#define mmDIG1_TMDS_CONTROL_CHAR 0x1F7D +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1F86 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1F87 +#define mmDIG1_TMDS_CTL_BITS 0x1F83 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1F84 +#define mmDIG1_TMDS_DEBUG 0x1F82 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1F7F +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1F80 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1F81 +#define mmDIG2_AFMT_60958_0 0x4241 +#define mmDIG2_AFMT_60958_1 0x4242 +#define mmDIG2_AFMT_60958_2 0x4248 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 +#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 +#define mmDIG2_AFMT_AUDIO_INFO0 0x423F +#define mmDIG2_AFMT_AUDIO_INFO1 0x4240 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424B +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424F +#define mmDIG2_AFMT_AVI_INFO0 0x4221 +#define mmDIG2_AFMT_AVI_INFO1 0x4222 +#define mmDIG2_AFMT_AVI_INFO2 0x4223 +#define mmDIG2_AFMT_AVI_INFO3 0x4224 +#define mmDIG2_AFMT_GENERIC_0 0x4228 +#define mmDIG2_AFMT_GENERIC_1 0x4229 +#define mmDIG2_AFMT_GENERIC_2 0x422A +#define mmDIG2_AFMT_GENERIC_3 0x422B +#define mmDIG2_AFMT_GENERIC_4 0x422C +#define mmDIG2_AFMT_GENERIC_5 0x422D +#define mmDIG2_AFMT_GENERIC_6 0x422E +#define mmDIG2_AFMT_GENERIC_7 0x422F +#define mmDIG2_AFMT_GENERIC_HDR 0x4227 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424D +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 +#define mmDIG2_AFMT_ISRC1_0 0x4218 +#define mmDIG2_AFMT_ISRC1_1 0x4219 +#define mmDIG2_AFMT_ISRC1_2 0x421A +#define mmDIG2_AFMT_ISRC1_3 0x421B +#define mmDIG2_AFMT_ISRC1_4 0x421C +#define mmDIG2_AFMT_ISRC2_0 0x421D +#define mmDIG2_AFMT_ISRC2_1 0x421E +#define mmDIG2_AFMT_ISRC2_2 0x421F +#define mmDIG2_AFMT_ISRC2_3 0x4220 +#define mmDIG2_AFMT_MPEG_INFO0 0x4225 +#define mmDIG2_AFMT_MPEG_INFO1 0x4226 +#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 +#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 +#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 +#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 +#define mmDIG2_AFMT_STATUS 0x424A +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424C +#define mmDIG2_DIG_BE_CNTL 0x4250 +#define mmDIG2_DIG_BE_EN_CNTL 0x4251 +#define mmDIG2_DIG_CLOCK_PATTERN 0x4203 +#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 +#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 +#define mmDIG2_DIG_FE_CNTL 0x4200 +#define mmDIG2_DIG_FIFO_STATUS 0x420A +#define mmDIG2_DIG_LANE_ENABLE 0x428D +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 +#define mmDIG2_DIG_TEST_PATTERN 0x4204 +#define mmDIG2_HDMI_ACR_32_0 0x4237 +#define mmDIG2_HDMI_ACR_32_1 0x4238 +#define mmDIG2_HDMI_ACR_44_0 0x4239 +#define mmDIG2_HDMI_ACR_44_1 0x423A +#define mmDIG2_HDMI_ACR_48_0 0x423B +#define mmDIG2_HDMI_ACR_48_1 0x423C +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420F +#define mmDIG2_HDMI_ACR_STATUS_0 0x423D +#define mmDIG2_HDMI_ACR_STATUS_1 0x423E +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420E +#define mmDIG2_HDMI_CONTROL 0x420C +#define mmDIG2_HDMI_GC 0x4216 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 +#define mmDIG2_HDMI_STATUS 0x420D +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 +#define mmDIG2_LVDS_DATA_CNTL 0x428C +#define mmDIG2_TMDS_CNTL 0x427C +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427E +#define mmDIG2_TMDS_CONTROL_CHAR 0x427D +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 +#define mmDIG2_TMDS_CTL_BITS 0x4283 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 +#define mmDIG2_TMDS_DEBUG 0x4282 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427F +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 +#define mmDIG3_AFMT_60958_0 0x4541 +#define mmDIG3_AFMT_60958_1 0x4542 +#define mmDIG3_AFMT_60958_2 0x4548 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 +#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 +#define mmDIG3_AFMT_AUDIO_INFO0 0x453F +#define mmDIG3_AFMT_AUDIO_INFO1 0x4540 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454B +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454F +#define mmDIG3_AFMT_AVI_INFO0 0x4521 +#define mmDIG3_AFMT_AVI_INFO1 0x4522 +#define mmDIG3_AFMT_AVI_INFO2 0x4523 +#define mmDIG3_AFMT_AVI_INFO3 0x4524 +#define mmDIG3_AFMT_GENERIC_0 0x4528 +#define mmDIG3_AFMT_GENERIC_1 0x4529 +#define mmDIG3_AFMT_GENERIC_2 0x452A +#define mmDIG3_AFMT_GENERIC_3 0x452B +#define mmDIG3_AFMT_GENERIC_4 0x452C +#define mmDIG3_AFMT_GENERIC_5 0x452D +#define mmDIG3_AFMT_GENERIC_6 0x452E +#define mmDIG3_AFMT_GENERIC_7 0x452F +#define mmDIG3_AFMT_GENERIC_HDR 0x4527 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454D +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 +#define mmDIG3_AFMT_ISRC1_0 0x4518 +#define mmDIG3_AFMT_ISRC1_1 0x4519 +#define mmDIG3_AFMT_ISRC1_2 0x451A +#define mmDIG3_AFMT_ISRC1_3 0x451B +#define mmDIG3_AFMT_ISRC1_4 0x451C +#define mmDIG3_AFMT_ISRC2_0 0x451D +#define mmDIG3_AFMT_ISRC2_1 0x451E +#define mmDIG3_AFMT_ISRC2_2 0x451F +#define mmDIG3_AFMT_ISRC2_3 0x4520 +#define mmDIG3_AFMT_MPEG_INFO0 0x4525 +#define mmDIG3_AFMT_MPEG_INFO1 0x4526 +#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 +#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 +#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 +#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 +#define mmDIG3_AFMT_STATUS 0x454A +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454C +#define mmDIG3_DIG_BE_CNTL 0x4550 +#define mmDIG3_DIG_BE_EN_CNTL 0x4551 +#define mmDIG3_DIG_CLOCK_PATTERN 0x4503 +#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 +#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 +#define mmDIG3_DIG_FE_CNTL 0x4500 +#define mmDIG3_DIG_FIFO_STATUS 0x450A +#define mmDIG3_DIG_LANE_ENABLE 0x458D +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 +#define mmDIG3_DIG_TEST_PATTERN 0x4504 +#define mmDIG3_HDMI_ACR_32_0 0x4537 +#define mmDIG3_HDMI_ACR_32_1 0x4538 +#define mmDIG3_HDMI_ACR_44_0 0x4539 +#define mmDIG3_HDMI_ACR_44_1 0x453A +#define mmDIG3_HDMI_ACR_48_0 0x453B +#define mmDIG3_HDMI_ACR_48_1 0x453C +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450F +#define mmDIG3_HDMI_ACR_STATUS_0 0x453D +#define mmDIG3_HDMI_ACR_STATUS_1 0x453E +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450E +#define mmDIG3_HDMI_CONTROL 0x450C +#define mmDIG3_HDMI_GC 0x4516 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 +#define mmDIG3_HDMI_STATUS 0x450D +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 +#define mmDIG3_LVDS_DATA_CNTL 0x458C +#define mmDIG3_TMDS_CNTL 0x457C +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457E +#define mmDIG3_TMDS_CONTROL_CHAR 0x457D +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 +#define mmDIG3_TMDS_CTL_BITS 0x4583 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 +#define mmDIG3_TMDS_DEBUG 0x4582 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457F +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 +#define mmDIG4_AFMT_60958_0 0x4841 +#define mmDIG4_AFMT_60958_1 0x4842 +#define mmDIG4_AFMT_60958_2 0x4848 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 +#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 +#define mmDIG4_AFMT_AUDIO_INFO0 0x483F +#define mmDIG4_AFMT_AUDIO_INFO1 0x4840 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484B +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484F +#define mmDIG4_AFMT_AVI_INFO0 0x4821 +#define mmDIG4_AFMT_AVI_INFO1 0x4822 +#define mmDIG4_AFMT_AVI_INFO2 0x4823 +#define mmDIG4_AFMT_AVI_INFO3 0x4824 +#define mmDIG4_AFMT_GENERIC_0 0x4828 +#define mmDIG4_AFMT_GENERIC_1 0x4829 +#define mmDIG4_AFMT_GENERIC_2 0x482A +#define mmDIG4_AFMT_GENERIC_3 0x482B +#define mmDIG4_AFMT_GENERIC_4 0x482C +#define mmDIG4_AFMT_GENERIC_5 0x482D +#define mmDIG4_AFMT_GENERIC_6 0x482E +#define mmDIG4_AFMT_GENERIC_7 0x482F +#define mmDIG4_AFMT_GENERIC_HDR 0x4827 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484D +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 +#define mmDIG4_AFMT_ISRC1_0 0x4818 +#define mmDIG4_AFMT_ISRC1_1 0x4819 +#define mmDIG4_AFMT_ISRC1_2 0x481A +#define mmDIG4_AFMT_ISRC1_3 0x481B +#define mmDIG4_AFMT_ISRC1_4 0x481C +#define mmDIG4_AFMT_ISRC2_0 0x481D +#define mmDIG4_AFMT_ISRC2_1 0x481E +#define mmDIG4_AFMT_ISRC2_2 0x481F +#define mmDIG4_AFMT_ISRC2_3 0x4820 +#define mmDIG4_AFMT_MPEG_INFO0 0x4825 +#define mmDIG4_AFMT_MPEG_INFO1 0x4826 +#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 +#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 +#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 +#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 +#define mmDIG4_AFMT_STATUS 0x484A +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484C +#define mmDIG4_DIG_BE_CNTL 0x4850 +#define mmDIG4_DIG_BE_EN_CNTL 0x4851 +#define mmDIG4_DIG_CLOCK_PATTERN 0x4803 +#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 +#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 +#define mmDIG4_DIG_FE_CNTL 0x4800 +#define mmDIG4_DIG_FIFO_STATUS 0x480A +#define mmDIG4_DIG_LANE_ENABLE 0x488D +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 +#define mmDIG4_DIG_TEST_PATTERN 0x4804 +#define mmDIG4_HDMI_ACR_32_0 0x4837 +#define mmDIG4_HDMI_ACR_32_1 0x4838 +#define mmDIG4_HDMI_ACR_44_0 0x4839 +#define mmDIG4_HDMI_ACR_44_1 0x483A +#define mmDIG4_HDMI_ACR_48_0 0x483B +#define mmDIG4_HDMI_ACR_48_1 0x483C +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480F +#define mmDIG4_HDMI_ACR_STATUS_0 0x483D +#define mmDIG4_HDMI_ACR_STATUS_1 0x483E +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480E +#define mmDIG4_HDMI_CONTROL 0x480C +#define mmDIG4_HDMI_GC 0x4816 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 +#define mmDIG4_HDMI_STATUS 0x480D +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 +#define mmDIG4_LVDS_DATA_CNTL 0x488C +#define mmDIG4_TMDS_CNTL 0x487C +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487E +#define mmDIG4_TMDS_CONTROL_CHAR 0x487D +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 +#define mmDIG4_TMDS_CTL_BITS 0x4883 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 +#define mmDIG4_TMDS_DEBUG 0x4882 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487F +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 +#define mmDIG5_AFMT_60958_0 0x4B41 +#define mmDIG5_AFMT_60958_1 0x4B42 +#define mmDIG5_AFMT_60958_2 0x4B48 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4B43 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4B49 +#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4B52 +#define mmDIG5_AFMT_AUDIO_INFO0 0x4B3F +#define mmDIG5_AFMT_AUDIO_INFO1 0x4B40 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4B4B +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4B17 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4B4F +#define mmDIG5_AFMT_AVI_INFO0 0x4B21 +#define mmDIG5_AFMT_AVI_INFO1 0x4B22 +#define mmDIG5_AFMT_AVI_INFO2 0x4B23 +#define mmDIG5_AFMT_AVI_INFO3 0x4B24 +#define mmDIG5_AFMT_GENERIC_0 0x4B28 +#define mmDIG5_AFMT_GENERIC_1 0x4B29 +#define mmDIG5_AFMT_GENERIC_2 0x4B2A +#define mmDIG5_AFMT_GENERIC_3 0x4B2B +#define mmDIG5_AFMT_GENERIC_4 0x4B2C +#define mmDIG5_AFMT_GENERIC_5 0x4B2D +#define mmDIG5_AFMT_GENERIC_6 0x4B2E +#define mmDIG5_AFMT_GENERIC_7 0x4B2F +#define mmDIG5_AFMT_GENERIC_HDR 0x4B27 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4B4D +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4B14 +#define mmDIG5_AFMT_ISRC1_0 0x4B18 +#define mmDIG5_AFMT_ISRC1_1 0x4B19 +#define mmDIG5_AFMT_ISRC1_2 0x4B1A +#define mmDIG5_AFMT_ISRC1_3 0x4B1B +#define mmDIG5_AFMT_ISRC1_4 0x4B1C +#define mmDIG5_AFMT_ISRC2_0 0x4B1D +#define mmDIG5_AFMT_ISRC2_1 0x4B1E +#define mmDIG5_AFMT_ISRC2_2 0x4B1F +#define mmDIG5_AFMT_ISRC2_3 0x4B20 +#define mmDIG5_AFMT_MPEG_INFO0 0x4B25 +#define mmDIG5_AFMT_MPEG_INFO1 0x4B26 +#define mmDIG5_AFMT_RAMP_CONTROL0 0x4B44 +#define mmDIG5_AFMT_RAMP_CONTROL1 0x4B45 +#define mmDIG5_AFMT_RAMP_CONTROL2 0x4B46 +#define mmDIG5_AFMT_RAMP_CONTROL3 0x4B47 +#define mmDIG5_AFMT_STATUS 0x4B4A +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4B4C +#define mmDIG5_DIG_BE_CNTL 0x4B50 +#define mmDIG5_DIG_BE_EN_CNTL 0x4B51 +#define mmDIG5_DIG_CLOCK_PATTERN 0x4B03 +#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4B08 +#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4B09 +#define mmDIG5_DIG_FE_CNTL 0x4B00 +#define mmDIG5_DIG_FIFO_STATUS 0x4B0A +#define mmDIG5_DIG_LANE_ENABLE 0x4B8D +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4B01 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4B02 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4B05 +#define mmDIG5_DIG_TEST_PATTERN 0x4B04 +#define mmDIG5_HDMI_ACR_32_0 0x4B37 +#define mmDIG5_HDMI_ACR_32_1 0x4B38 +#define mmDIG5_HDMI_ACR_44_0 0x4B39 +#define mmDIG5_HDMI_ACR_44_1 0x4B3A +#define mmDIG5_HDMI_ACR_48_0 0x4B3B +#define mmDIG5_HDMI_ACR_48_1 0x4B3C +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4B0F +#define mmDIG5_HDMI_ACR_STATUS_0 0x4B3D +#define mmDIG5_HDMI_ACR_STATUS_1 0x4B3E +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4B0E +#define mmDIG5_HDMI_CONTROL 0x4B0C +#define mmDIG5_HDMI_GC 0x4B16 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4B13 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4B30 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4B11 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4B12 +#define mmDIG5_HDMI_STATUS 0x4B0D +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4B10 +#define mmDIG5_LVDS_DATA_CNTL 0x4B8C +#define mmDIG5_TMDS_CNTL 0x4B7C +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4B7E +#define mmDIG5_TMDS_CONTROL_CHAR 0x4B7D +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4B86 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4B87 +#define mmDIG5_TMDS_CTL_BITS 0x4B83 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4B84 +#define mmDIG5_TMDS_DEBUG 0x4B82 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4B7F +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4B80 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4B81 +#define mmDIG_BE_CNTL 0x1C50 +#define mmDIG_BE_EN_CNTL 0x1C51 +#define mmDIG_CLOCK_PATTERN 0x1C03 +#define mmDIG_DISPCLK_SWITCH_CNTL 0x1C08 +#define mmDIG_DISPCLK_SWITCH_STATUS 0x1C09 +#define mmDIG_FE_CNTL 0x1C00 +#define mmDIG_FIFO_STATUS 0x1C0A +#define mmDIG_LANE_ENABLE 0x1C8D +#define mmDIG_OUTPUT_CRC_CNTL 0x1C01 +#define mmDIG_OUTPUT_CRC_RESULT 0x1C02 +#define mmDIG_RANDOM_PATTERN_SEED 0x1C05 +#define mmDIG_SOFT_RESET 0x013D +#define mmDIG_TEST_PATTERN 0x1C04 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0135 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0131 +#define mmDISP_INTERRUPT_STATUS 0x183D +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183E +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183F +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 +#define mmDISPOUT_STEREOSYNC_SEL 0x18BF +#define mmDISPPLL_BG_CNTL 0x013C +#define mmDISP_TIMER_CONTROL 0x1842 +#define mmDMCU_CTRL 0x1600 +#define mmDMCU_ERAM_RD_CTRL 0x160B +#define mmDMCU_ERAM_RD_DATA 0x160C +#define mmDMCU_ERAM_WR_CTRL 0x1609 +#define mmDMCU_ERAM_WR_DATA 0x160A +#define mmDMCU_EVENT_TRIGGER 0x1611 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161A +#define mmDMCU_FW_CS_HI 0x1606 +#define mmDMCU_FW_CS_LO 0x1607 +#define mmDMCU_FW_END_ADDR 0x1604 +#define mmDMCU_FW_ISR_START_ADDR 0x1605 +#define mmDMCU_FW_START_ADDR 0x1603 +#define mmDMCU_INT_CNT 0x1619 +#define mmDMCU_INTERRUPT_STATUS 0x1614 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define mmDMCU_IRAM_RD_CTRL 0x160F +#define mmDMCU_IRAM_RD_DATA 0x1610 +#define mmDMCU_IRAM_WR_CTRL 0x160D +#define mmDMCU_IRAM_WR_DATA 0x160E +#define mmDMCU_PC_START_ADDR 0x1602 +#define mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define mmDMCU_STATUS 0x1601 +#define mmDMCU_TEST_DEBUG_DATA 0x1627 +#define mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define mmDMCU_UC_CLK_GATING_CNTL 0x161B +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define mmDMIF_ADDR_CALC 0x0300 +#define mmDMIF_ADDR_CONFIG 0x02F5 +#define mmDMIF_ARBITRATION_CONTROL 0x02F9 +#define mmDMIF_CONTROL 0x02F6 +#define mmDMIF_HW_DEBUG 0x02F8 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1B30 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1B31 +#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1B34 +#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1B35 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1B33 +#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1B39 +#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1B38 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1E30 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1E31 +#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1E34 +#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1E36 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1E35 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1E37 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1E33 +#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1E39 +#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1E38 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 +#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 +#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 +#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 +#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 +#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 +#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 +#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 +#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 +#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4A30 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4A31 +#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4A34 +#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4A36 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4A35 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4A37 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4A33 +#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4A39 +#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4A38 +#define mmDMIF_STATUS 0x02F7 +#define mmDMIF_STATUS2 0x0301 +#define mmDMIF_TEST_DEBUG_DATA 0x0313 +#define mmDMIF_TEST_DEBUG_INDEX 0x0312 +#define mmDOUT_DCE_VCE_CONTROL 0x18FF +#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 +#define mmDOUT_SCRATCH0 0x1844 +#define mmDOUT_SCRATCH1 0x1845 +#define mmDOUT_SCRATCH2 0x1846 +#define mmDOUT_SCRATCH3 0x1847 +#define mmDOUT_SCRATCH4 0x1848 +#define mmDOUT_SCRATCH5 0x1849 +#define mmDOUT_SCRATCH6 0x184A +#define mmDOUT_SCRATCH7 0x184B +#define mmDOUT_TEST_DEBUG_DATA 0x184E +#define mmDOUT_TEST_DEBUG_INDEX 0x184D +#define mmDP0_DP_CONFIG 0x1CC2 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x1CD3 +#define mmDP0_DP_DPHY_CNTL 0x1CD0 +#define mmDP0_DP_DPHY_CRC_CNTL 0x1CD7 +#define mmDP0_DP_DPHY_CRC_EN 0x1CD6 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1CC6 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1CC7 +#define mmDP0_DP_DPHY_CRC_RESULT 0x1CD8 +#define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1CE9 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x1CD4 +#define mmDP0_DP_DPHY_SYM0 0x1CD2 +#define mmDP0_DP_DPHY_SYM1 0x1CE0 +#define mmDP0_DP_DPHY_SYM2 0x1CDF +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x1CC8 +#define mmDP0_DP_LINK_CNTL 0x1CC0 +#define mmDP0_DP_LINK_FRAMING_CNTL 0x1CCC +#define mmDP0_DP_MSA_COLORIMETRY 0x1CDA +#define mmDP0_DP_MSA_MISC 0x1CC5 +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1CEA +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1CEB +#define mmDP0_DP_MSE_LINK_TIMING 0x1CE8 +#define mmDP0_DP_MSE_MISC_CNTL 0x1CDB +#define mmDP0_DP_MSE_RATE_CNTL 0x1CE1 +#define mmDP0_DP_MSE_RATE_UPDATE 0x1CE3 +#define mmDP0_DP_MSE_SAT0 0x1CE4 +#define mmDP0_DP_MSE_SAT1 0x1CE5 +#define mmDP0_DP_MSE_SAT2 0x1CE6 +#define mmDP0_DP_MSE_SAT_UPDATE 0x1CE7 +#define mmDP0_DP_PIXEL_FORMAT 0x1CC1 +#define mmDP0_DP_SEC_AUD_M 0x1CA7 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x1CA8 +#define mmDP0_DP_SEC_AUD_N 0x1CA5 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x1CA6 +#define mmDP0_DP_SEC_CNTL 0x1CA0 +#define mmDP0_DP_SEC_CNTL1 0x1CAB +#define mmDP0_DP_SEC_FRAMING1 0x1CA1 +#define mmDP0_DP_SEC_FRAMING2 0x1CA2 +#define mmDP0_DP_SEC_FRAMING3 0x1CA3 +#define mmDP0_DP_SEC_FRAMING4 0x1CA4 +#define mmDP0_DP_SEC_PACKET_CNTL 0x1CAA +#define mmDP0_DP_SEC_TIMESTAMP 0x1CA9 +#define mmDP0_DP_STEER_FIFO 0x1CC4 +#define mmDP0_DP_TEST_DEBUG_DATA 0x1CFD +#define mmDP0_DP_TEST_DEBUG_INDEX 0x1CFC +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1CCF +#define mmDP0_DP_VID_M 0x1CCB +#define mmDP0_DP_VID_MSA_VBID 0x1CCD +#define mmDP0_DP_VID_N 0x1CCA +#define mmDP0_DP_VID_STREAM_CNTL 0x1CC3 +#define mmDP0_DP_VID_TIMING 0x1CC9 +#define mmDP1_DP_CONFIG 0x1FC2 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x1FD3 +#define mmDP1_DP_DPHY_CNTL 0x1FD0 +#define mmDP1_DP_DPHY_CRC_CNTL 0x1FD7 +#define mmDP1_DP_DPHY_CRC_EN 0x1FD6 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1FC6 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1FC7 +#define mmDP1_DP_DPHY_CRC_RESULT 0x1FD8 +#define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1FE9 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4 +#define mmDP1_DP_DPHY_SYM0 0x1FD2 +#define mmDP1_DP_DPHY_SYM1 0x1FE0 +#define mmDP1_DP_DPHY_SYM2 0x1FDF +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1FD1 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x1FC8 +#define mmDP1_DP_LINK_CNTL 0x1FC0 +#define mmDP1_DP_LINK_FRAMING_CNTL 0x1FCC +#define mmDP1_DP_MSA_COLORIMETRY 0x1FDA +#define mmDP1_DP_MSA_MISC 0x1FC5 +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1FEA +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1FEB +#define mmDP1_DP_MSE_LINK_TIMING 0x1FE8 +#define mmDP1_DP_MSE_MISC_CNTL 0x1FDB +#define mmDP1_DP_MSE_RATE_CNTL 0x1FE1 +#define mmDP1_DP_MSE_RATE_UPDATE 0x1FE3 +#define mmDP1_DP_MSE_SAT0 0x1FE4 +#define mmDP1_DP_MSE_SAT1 0x1FE5 +#define mmDP1_DP_MSE_SAT2 0x1FE6 +#define mmDP1_DP_MSE_SAT_UPDATE 0x1FE7 +#define mmDP1_DP_PIXEL_FORMAT 0x1FC1 +#define mmDP1_DP_SEC_AUD_M 0x1FA7 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x1FA8 +#define mmDP1_DP_SEC_AUD_N 0x1FA5 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x1FA6 +#define mmDP1_DP_SEC_CNTL 0x1FA0 +#define mmDP1_DP_SEC_CNTL1 0x1FAB +#define mmDP1_DP_SEC_FRAMING1 0x1FA1 +#define mmDP1_DP_SEC_FRAMING2 0x1FA2 +#define mmDP1_DP_SEC_FRAMING3 0x1FA3 +#define mmDP1_DP_SEC_FRAMING4 0x1FA4 +#define mmDP1_DP_SEC_PACKET_CNTL 0x1FAA +#define mmDP1_DP_SEC_TIMESTAMP 0x1FA9 +#define mmDP1_DP_STEER_FIFO 0x1FC4 +#define mmDP1_DP_TEST_DEBUG_DATA 0x1FFD +#define mmDP1_DP_TEST_DEBUG_INDEX 0x1FFC +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1FCF +#define mmDP1_DP_VID_M 0x1FCB +#define mmDP1_DP_VID_MSA_VBID 0x1FCD +#define mmDP1_DP_VID_N 0x1FCA +#define mmDP1_DP_VID_STREAM_CNTL 0x1FC3 +#define mmDP1_DP_VID_TIMING 0x1FC9 +#define mmDP2_DP_CONFIG 0x42C2 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x42D3 +#define mmDP2_DP_DPHY_CNTL 0x42D0 +#define mmDP2_DP_DPHY_CRC_CNTL 0x42D7 +#define mmDP2_DP_DPHY_CRC_EN 0x42D6 +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42C6 +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42C7 +#define mmDP2_DP_DPHY_CRC_RESULT 0x42D8 +#define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42E9 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x42D4 +#define mmDP2_DP_DPHY_SYM0 0x42D2 +#define mmDP2_DP_DPHY_SYM1 0x42E0 +#define mmDP2_DP_DPHY_SYM2 0x42DF +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42D1 +#define mmDP2_DP_HBR2_EYE_PATTERN 0x42C8 +#define mmDP2_DP_LINK_CNTL 0x42C0 +#define mmDP2_DP_LINK_FRAMING_CNTL 0x42CC +#define mmDP2_DP_MSA_COLORIMETRY 0x42DA +#define mmDP2_DP_MSA_MISC 0x42C5 +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42EA +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42EB +#define mmDP2_DP_MSE_LINK_TIMING 0x42E8 +#define mmDP2_DP_MSE_MISC_CNTL 0x42DB +#define mmDP2_DP_MSE_RATE_CNTL 0x42E1 +#define mmDP2_DP_MSE_RATE_UPDATE 0x42E3 +#define mmDP2_DP_MSE_SAT0 0x42E4 +#define mmDP2_DP_MSE_SAT1 0x42E5 +#define mmDP2_DP_MSE_SAT2 0x42E6 +#define mmDP2_DP_MSE_SAT_UPDATE 0x42E7 +#define mmDP2_DP_PIXEL_FORMAT 0x42C1 +#define mmDP2_DP_SEC_AUD_M 0x42A7 +#define mmDP2_DP_SEC_AUD_M_READBACK 0x42A8 +#define mmDP2_DP_SEC_AUD_N 0x42A5 +#define mmDP2_DP_SEC_AUD_N_READBACK 0x42A6 +#define mmDP2_DP_SEC_CNTL 0x42A0 +#define mmDP2_DP_SEC_CNTL1 0x42AB +#define mmDP2_DP_SEC_FRAMING1 0x42A1 +#define mmDP2_DP_SEC_FRAMING2 0x42A2 +#define mmDP2_DP_SEC_FRAMING3 0x42A3 +#define mmDP2_DP_SEC_FRAMING4 0x42A4 +#define mmDP2_DP_SEC_PACKET_CNTL 0x42AA +#define mmDP2_DP_SEC_TIMESTAMP 0x42A9 +#define mmDP2_DP_STEER_FIFO 0x42C4 +#define mmDP2_DP_TEST_DEBUG_DATA 0x42FD +#define mmDP2_DP_TEST_DEBUG_INDEX 0x42FC +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42CF +#define mmDP2_DP_VID_M 0x42CB +#define mmDP2_DP_VID_MSA_VBID 0x42CD +#define mmDP2_DP_VID_N 0x42CA +#define mmDP2_DP_VID_STREAM_CNTL 0x42C3 +#define mmDP2_DP_VID_TIMING 0x42C9 +#define mmDP3_DP_CONFIG 0x45C2 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x45D3 +#define mmDP3_DP_DPHY_CNTL 0x45D0 +#define mmDP3_DP_DPHY_CRC_CNTL 0x45D7 +#define mmDP3_DP_DPHY_CRC_EN 0x45D6 +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45C6 +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45C7 +#define mmDP3_DP_DPHY_CRC_RESULT 0x45D8 +#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45E9 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x45D4 +#define mmDP3_DP_DPHY_SYM0 0x45D2 +#define mmDP3_DP_DPHY_SYM1 0x45E0 +#define mmDP3_DP_DPHY_SYM2 0x45DF +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45D1 +#define mmDP3_DP_HBR2_EYE_PATTERN 0x45C8 +#define mmDP3_DP_LINK_CNTL 0x45C0 +#define mmDP3_DP_LINK_FRAMING_CNTL 0x45CC +#define mmDP3_DP_MSA_COLORIMETRY 0x45DA +#define mmDP3_DP_MSA_MISC 0x45C5 +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45EA +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45EB +#define mmDP3_DP_MSE_LINK_TIMING 0x45E8 +#define mmDP3_DP_MSE_MISC_CNTL 0x45DB +#define mmDP3_DP_MSE_RATE_CNTL 0x45E1 +#define mmDP3_DP_MSE_RATE_UPDATE 0x45E3 +#define mmDP3_DP_MSE_SAT0 0x45E4 +#define mmDP3_DP_MSE_SAT1 0x45E5 +#define mmDP3_DP_MSE_SAT2 0x45E6 +#define mmDP3_DP_MSE_SAT_UPDATE 0x45E7 +#define mmDP3_DP_PIXEL_FORMAT 0x45C1 +#define mmDP3_DP_SEC_AUD_M 0x45A7 +#define mmDP3_DP_SEC_AUD_M_READBACK 0x45A8 +#define mmDP3_DP_SEC_AUD_N 0x45A5 +#define mmDP3_DP_SEC_AUD_N_READBACK 0x45A6 +#define mmDP3_DP_SEC_CNTL 0x45A0 +#define mmDP3_DP_SEC_CNTL1 0x45AB +#define mmDP3_DP_SEC_FRAMING1 0x45A1 +#define mmDP3_DP_SEC_FRAMING2 0x45A2 +#define mmDP3_DP_SEC_FRAMING3 0x45A3 +#define mmDP3_DP_SEC_FRAMING4 0x45A4 +#define mmDP3_DP_SEC_PACKET_CNTL 0x45AA +#define mmDP3_DP_SEC_TIMESTAMP 0x45A9 +#define mmDP3_DP_STEER_FIFO 0x45C4 +#define mmDP3_DP_TEST_DEBUG_DATA 0x45FD +#define mmDP3_DP_TEST_DEBUG_INDEX 0x45FC +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45CF +#define mmDP3_DP_VID_M 0x45CB +#define mmDP3_DP_VID_MSA_VBID 0x45CD +#define mmDP3_DP_VID_N 0x45CA +#define mmDP3_DP_VID_STREAM_CNTL 0x45C3 +#define mmDP3_DP_VID_TIMING 0x45C9 +#define mmDP4_DP_CONFIG 0x48C2 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x48D3 +#define mmDP4_DP_DPHY_CNTL 0x48D0 +#define mmDP4_DP_DPHY_CRC_CNTL 0x48D7 +#define mmDP4_DP_DPHY_CRC_EN 0x48D6 +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48C6 +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48C7 +#define mmDP4_DP_DPHY_CRC_RESULT 0x48D8 +#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48E9 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x48D4 +#define mmDP4_DP_DPHY_SYM0 0x48D2 +#define mmDP4_DP_DPHY_SYM1 0x48E0 +#define mmDP4_DP_DPHY_SYM2 0x48DF +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48D1 +#define mmDP4_DP_HBR2_EYE_PATTERN 0x48C8 +#define mmDP4_DP_LINK_CNTL 0x48C0 +#define mmDP4_DP_LINK_FRAMING_CNTL 0x48CC +#define mmDP4_DP_MSA_COLORIMETRY 0x48DA +#define mmDP4_DP_MSA_MISC 0x48C5 +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48EA +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48EB +#define mmDP4_DP_MSE_LINK_TIMING 0x48E8 +#define mmDP4_DP_MSE_MISC_CNTL 0x48DB +#define mmDP4_DP_MSE_RATE_CNTL 0x48E1 +#define mmDP4_DP_MSE_RATE_UPDATE 0x48E3 +#define mmDP4_DP_MSE_SAT0 0x48E4 +#define mmDP4_DP_MSE_SAT1 0x48E5 +#define mmDP4_DP_MSE_SAT2 0x48E6 +#define mmDP4_DP_MSE_SAT_UPDATE 0x48E7 +#define mmDP4_DP_PIXEL_FORMAT 0x48C1 +#define mmDP4_DP_SEC_AUD_M 0x48A7 +#define mmDP4_DP_SEC_AUD_M_READBACK 0x48A8 +#define mmDP4_DP_SEC_AUD_N 0x48A5 +#define mmDP4_DP_SEC_AUD_N_READBACK 0x48A6 +#define mmDP4_DP_SEC_CNTL 0x48A0 +#define mmDP4_DP_SEC_CNTL1 0x48AB +#define mmDP4_DP_SEC_FRAMING1 0x48A1 +#define mmDP4_DP_SEC_FRAMING2 0x48A2 +#define mmDP4_DP_SEC_FRAMING3 0x48A3 +#define mmDP4_DP_SEC_FRAMING4 0x48A4 +#define mmDP4_DP_SEC_PACKET_CNTL 0x48AA +#define mmDP4_DP_SEC_TIMESTAMP 0x48A9 +#define mmDP4_DP_STEER_FIFO 0x48C4 +#define mmDP4_DP_TEST_DEBUG_DATA 0x48FD +#define mmDP4_DP_TEST_DEBUG_INDEX 0x48FC +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48CF +#define mmDP4_DP_VID_M 0x48CB +#define mmDP4_DP_VID_MSA_VBID 0x48CD +#define mmDP4_DP_VID_N 0x48CA +#define mmDP4_DP_VID_STREAM_CNTL 0x48C3 +#define mmDP4_DP_VID_TIMING 0x48C9 +#define mmDP5_DP_CONFIG 0x4BC2 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x4BD3 +#define mmDP5_DP_DPHY_CNTL 0x4BD0 +#define mmDP5_DP_DPHY_CRC_CNTL 0x4BD7 +#define mmDP5_DP_DPHY_CRC_EN 0x4BD6 +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4BC6 +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4BC7 +#define mmDP5_DP_DPHY_CRC_RESULT 0x4BD8 +#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4BE9 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x4BD4 +#define mmDP5_DP_DPHY_SYM0 0x4BD2 +#define mmDP5_DP_DPHY_SYM1 0x4BE0 +#define mmDP5_DP_DPHY_SYM2 0x4BDF +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4BD1 +#define mmDP5_DP_HBR2_EYE_PATTERN 0x4BC8 +#define mmDP5_DP_LINK_CNTL 0x4BC0 +#define mmDP5_DP_LINK_FRAMING_CNTL 0x4BCC +#define mmDP5_DP_MSA_COLORIMETRY 0x4BDA +#define mmDP5_DP_MSA_MISC 0x4BC5 +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4BEA +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4BEB +#define mmDP5_DP_MSE_LINK_TIMING 0x4BE8 +#define mmDP5_DP_MSE_MISC_CNTL 0x4BDB +#define mmDP5_DP_MSE_RATE_CNTL 0x4BE1 +#define mmDP5_DP_MSE_RATE_UPDATE 0x4BE3 +#define mmDP5_DP_MSE_SAT0 0x4BE4 +#define mmDP5_DP_MSE_SAT1 0x4BE5 +#define mmDP5_DP_MSE_SAT2 0x4BE6 +#define mmDP5_DP_MSE_SAT_UPDATE 0x4BE7 +#define mmDP5_DP_PIXEL_FORMAT 0x4BC1 +#define mmDP5_DP_SEC_AUD_M 0x4BA7 +#define mmDP5_DP_SEC_AUD_M_READBACK 0x4BA8 +#define mmDP5_DP_SEC_AUD_N 0x4BA5 +#define mmDP5_DP_SEC_AUD_N_READBACK 0x4BA6 +#define mmDP5_DP_SEC_CNTL 0x4BA0 +#define mmDP5_DP_SEC_CNTL1 0x4BAB +#define mmDP5_DP_SEC_FRAMING1 0x4BA1 +#define mmDP5_DP_SEC_FRAMING2 0x4BA2 +#define mmDP5_DP_SEC_FRAMING3 0x4BA3 +#define mmDP5_DP_SEC_FRAMING4 0x4BA4 +#define mmDP5_DP_SEC_PACKET_CNTL 0x4BAA +#define mmDP5_DP_SEC_TIMESTAMP 0x4BA9 +#define mmDP5_DP_STEER_FIFO 0x4BC4 +#define mmDP5_DP_TEST_DEBUG_DATA 0x4BFD +#define mmDP5_DP_TEST_DEBUG_INDEX 0x4BFC +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4BCF +#define mmDP5_DP_VID_M 0x4BCB +#define mmDP5_DP_VID_MSA_VBID 0x4BCD +#define mmDP5_DP_VID_N 0x4BCA +#define mmDP5_DP_VID_STREAM_CNTL 0x4BC3 +#define mmDP5_DP_VID_TIMING 0x4BC9 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 +#define mmDP_AUX0_AUX_CONTROL 0x1880 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188A +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188B +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188D +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188C +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188E +#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1890 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 +#define mmDP_AUX0_AUX_LS_DATA 0x1887 +#define mmDP_AUX0_AUX_LS_STATUS 0x1885 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1881 +#define mmDP_AUX0_AUX_SW_DATA 0x1886 +#define mmDP_AUX0_AUX_SW_STATUS 0x1884 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 +#define mmDP_AUX1_AUX_CONTROL 0x1894 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189E +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189F +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18A1 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189D +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189C +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18A0 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18A2 +#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18A4 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 +#define mmDP_AUX1_AUX_LS_DATA 0x189B +#define mmDP_AUX1_AUX_LS_STATUS 0x1899 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1895 +#define mmDP_AUX1_AUX_SW_DATA 0x189A +#define mmDP_AUX1_AUX_SW_STATUS 0x1898 +#define mmDP_AUX2_AUX_ARB_CONTROL 0x18AA +#define mmDP_AUX2_AUX_CONTROL 0x18A8 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18B2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18B3 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18B5 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18B1 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18B0 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18B4 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18B6 +#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18B8 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18AB +#define mmDP_AUX2_AUX_LS_DATA 0x18AF +#define mmDP_AUX2_AUX_LS_STATUS 0x18AD +#define mmDP_AUX2_AUX_SW_CONTROL 0x18A9 +#define mmDP_AUX2_AUX_SW_DATA 0x18AE +#define mmDP_AUX2_AUX_SW_STATUS 0x18AC +#define mmDP_AUX3_AUX_ARB_CONTROL 0x18C2 +#define mmDP_AUX3_AUX_CONTROL 0x18C0 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18CA +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18CB +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18CD +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18C9 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18C8 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18CC +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18CE +#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18D0 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18C3 +#define mmDP_AUX3_AUX_LS_DATA 0x18C7 +#define mmDP_AUX3_AUX_LS_STATUS 0x18C5 +#define mmDP_AUX3_AUX_SW_CONTROL 0x18C1 +#define mmDP_AUX3_AUX_SW_DATA 0x18C6 +#define mmDP_AUX3_AUX_SW_STATUS 0x18C4 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x18D6 +#define mmDP_AUX4_AUX_CONTROL 0x18D4 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18DE +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18DF +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18E1 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18DD +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18DC +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18E0 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18E2 +#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18E4 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18D7 +#define mmDP_AUX4_AUX_LS_DATA 0x18DB +#define mmDP_AUX4_AUX_LS_STATUS 0x18D9 +#define mmDP_AUX4_AUX_SW_CONTROL 0x18D5 +#define mmDP_AUX4_AUX_SW_DATA 0x18DA +#define mmDP_AUX4_AUX_SW_STATUS 0x18D8 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x18EA +#define mmDP_AUX5_AUX_CONTROL 0x18E8 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18F2 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18F3 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18F5 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18F1 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18F0 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18F4 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18F6 +#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18F8 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18EB +#define mmDP_AUX5_AUX_LS_DATA 0x18EF +#define mmDP_AUX5_AUX_LS_STATUS 0x18ED +#define mmDP_AUX5_AUX_SW_CONTROL 0x18E9 +#define mmDP_AUX5_AUX_SW_DATA 0x18EE +#define mmDP_AUX5_AUX_SW_STATUS 0x18EC +#define mmDP_CONFIG 0x1CC2 +#define mmDP_DPHY_8B10B_CNTL 0x1CD3 +#define mmDP_DPHY_CNTL 0x1CD0 +#define mmDP_DPHY_CRC_CNTL 0x1CD7 +#define mmDP_DPHY_CRC_EN 0x1CD6 +#define mmDP_DPHY_CRC_MST_CNTL 0x1CC6 +#define mmDP_DPHY_CRC_MST_STATUS 0x1CC7 +#define mmDP_DPHY_CRC_RESULT 0x1CD8 +#define mmDP_DPHY_FAST_TRAINING 0x1CCE +#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1CE9 +#define mmDP_DPHY_PRBS_CNTL 0x1CD4 +#define mmDP_DPHY_SYM0 0x1CD2 +#define mmDP_DPHY_SYM1 0x1CE0 +#define mmDP_DPHY_SYM2 0x1CDF +#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 +#define mmDP_DTO0_MODULO 0x0142 +#define mmDP_DTO0_PHASE 0x0141 +#define mmDP_DTO1_MODULO 0x0146 +#define mmDP_DTO1_PHASE 0x0145 +#define mmDP_DTO2_MODULO 0x014A +#define mmDP_DTO2_PHASE 0x0149 +#define mmDP_DTO3_MODULO 0x014E +#define mmDP_DTO3_PHASE 0x014D +#define mmDP_DTO4_MODULO 0x0152 +#define mmDP_DTO4_PHASE 0x0151 +#define mmDP_DTO5_MODULO 0x0156 +#define mmDP_DTO5_PHASE 0x0155 +#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1B30 +#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1B31 +#define mmDPG_PIPE_DPM_CONTROL 0x1B34 +#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 +#define mmDPG_PIPE_STUTTER_CONTROL 0x1B35 +#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 +#define mmDPG_PIPE_URGENCY_CONTROL 0x1B33 +#define mmDPG_TEST_DEBUG_DATA 0x1B39 +#define mmDPG_TEST_DEBUG_INDEX 0x1B38 +#define mmDP_HBR2_EYE_PATTERN 0x1CC8 +#define mmDP_LINK_CNTL 0x1CC0 +#define mmDP_LINK_FRAMING_CNTL 0x1CCC +#define mmDP_MSA_COLORIMETRY 0x1CDA +#define mmDP_MSA_MISC 0x1CC5 +#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1CEA +#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1CEB +#define mmDP_MSE_LINK_TIMING 0x1CE8 +#define mmDP_MSE_MISC_CNTL 0x1CDB +#define mmDP_MSE_RATE_CNTL 0x1CE1 +#define mmDP_MSE_RATE_UPDATE 0x1CE3 +#define mmDP_MSE_SAT0 0x1CE4 +#define mmDP_MSE_SAT1 0x1CE5 +#define mmDP_MSE_SAT2 0x1CE6 +#define mmDP_MSE_SAT_UPDATE 0x1CE7 +#define mmDP_PIXEL_FORMAT 0x1CC1 +#define mmDP_SEC_AUD_M 0x1CA7 +#define mmDP_SEC_AUD_M_READBACK 0x1CA8 +#define mmDP_SEC_AUD_N 0x1CA5 +#define mmDP_SEC_AUD_N_READBACK 0x1CA6 +#define mmDP_SEC_CNTL 0x1CA0 +#define mmDP_SEC_CNTL1 0x1CAB +#define mmDP_SEC_FRAMING1 0x1CA1 +#define mmDP_SEC_FRAMING2 0x1CA2 +#define mmDP_SEC_FRAMING3 0x1CA3 +#define mmDP_SEC_FRAMING4 0x1CA4 +#define mmDP_SEC_PACKET_CNTL 0x1CAA +#define mmDP_SEC_TIMESTAMP 0x1CA9 +#define mmDP_STEER_FIFO 0x1CC4 +#define mmDP_TEST_DEBUG_DATA 0x1CFD +#define mmDP_TEST_DEBUG_INDEX 0x1CFC +#define mmDP_VID_INTERRUPT_CNTL 0x1CCF +#define mmDP_VID_M 0x1CCB +#define mmDP_VID_MSA_VBID 0x1CCD +#define mmDP_VID_N 0x1CCA +#define mmDP_VID_STREAM_CNTL 0x1CC3 +#define mmDP_VID_TIMING 0x1CC9 +#define mmDVOACLKC_CNTL 0x016A +#define mmDVOACLKC_MVP_CNTL 0x0169 +#define mmDVOACLKD_CNTL 0x0168 +#define mmDVO_CLK_ENABLE 0x0129 +#define mmDVO_CONTROL 0x185B +#define mmDVO_CRC2_SIG_MASK 0x185D +#define mmDVO_CRC2_SIG_RESULT 0x185E +#define mmDVO_CRC_EN 0x185C +#define mmDVO_ENABLE 0x1858 +#define mmDVO_FIFO_ERROR_STATUS 0x185F +#define mmDVO_OUTPUT 0x185A +#define mmDVO_SKEW_ADJUST 0x197D +#define mmDVO_SOURCE_SELECT 0x1859 +#define mmDVO_STRENGTH_CONTROL 0x197B +#define mmDVO_VREF_CONTROL 0x197C +#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1B5E +#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1B5F +#define mmFBC_CLIENT_REGION_MASK 0x16EB +#define mmFBC_CNTL 0x16D0 +#define mmFBC_COMP_CNTL 0x16D4 +#define mmFBC_COMP_MODE 0x16D5 +#define mmFBC_CSM_REGION_OFFSET_01 0x16E9 +#define mmFBC_CSM_REGION_OFFSET_23 0x16EA +#define mmFBC_DEBUG0 0x16D6 +#define mmFBC_DEBUG1 0x16D7 +#define mmFBC_DEBUG2 0x16D8 +#define mmFBC_DEBUG_COMP 0x16EC +#define mmFBC_DEBUG_CSR 0x16ED +#define mmFBC_DEBUG_CSR_RDATA 0x16EE +#define mmFBC_DEBUG_CSR_RDATA_HI 0x16F6 +#define mmFBC_DEBUG_CSR_WDATA 0x16EF +#define mmFBC_DEBUG_CSR_WDATA_HI 0x16F7 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16D2 +#define mmFBC_IDLE_MASK 0x16D1 +#define mmFBC_IND_LUT0 0x16D9 +#define mmFBC_IND_LUT10 0x16E3 +#define mmFBC_IND_LUT1 0x16DA +#define mmFBC_IND_LUT11 0x16E4 +#define mmFBC_IND_LUT12 0x16E5 +#define mmFBC_IND_LUT13 0x16E6 +#define mmFBC_IND_LUT14 0x16E7 +#define mmFBC_IND_LUT15 0x16E8 +#define mmFBC_IND_LUT2 0x16DB +#define mmFBC_IND_LUT3 0x16DC +#define mmFBC_IND_LUT4 0x16DD +#define mmFBC_IND_LUT5 0x16DE +#define mmFBC_IND_LUT6 0x16DF +#define mmFBC_IND_LUT7 0x16E0 +#define mmFBC_IND_LUT8 0x16E1 +#define mmFBC_IND_LUT9 0x16E2 +#define mmFBC_MISC 0x16F0 +#define mmFBC_START_STOP_DELAY 0x16D3 +#define mmFBC_STATUS 0x16F1 +#define mmFBC_TEST_DEBUG_DATA 0x16F5 +#define mmFBC_TEST_DEBUG_INDEX 0x16F4 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1BF2 +#define mmFMT0_FMT_CLAMP_CNTL 0x1BF9 +#define mmFMT0_FMT_CONTROL 0x1BEE +#define mmFMT0_FMT_CRC_CNTL 0x1BFA +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1BFE +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1BFD +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1BFB +#define mmFMT0_FMT_DEBUG_CNTL 0x1BFF +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1BF5 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1BF4 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1BF3 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1BED +#define mmFMT0_FMT_FORCE_DATA_0_1 0x1BF0 +#define mmFMT0_FMT_FORCE_DATA_2_3 0x1BF1 +#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1BEF +#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 +#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1BEC +#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1BEB +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1EF2 +#define mmFMT1_FMT_CLAMP_CNTL 0x1EF9 +#define mmFMT1_FMT_CONTROL 0x1EEE +#define mmFMT1_FMT_CRC_CNTL 0x1EFA +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1EFE +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1EFC +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1EFD +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1EFB +#define mmFMT1_FMT_DEBUG_CNTL 0x1EFF +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1EF5 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1EF4 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1EF3 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1EED +#define mmFMT1_FMT_FORCE_DATA_0_1 0x1EF0 +#define mmFMT1_FMT_FORCE_DATA_2_3 0x1EF1 +#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1EEF +#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1EF6 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1EF7 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1EF8 +#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1EEC +#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1EEB +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41F2 +#define mmFMT2_FMT_CLAMP_CNTL 0x41F9 +#define mmFMT2_FMT_CONTROL 0x41EE +#define mmFMT2_FMT_CRC_CNTL 0x41FA +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41FE +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41FC +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41FD +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41FB +#define mmFMT2_FMT_DEBUG_CNTL 0x41FF +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41F5 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41F4 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41F3 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ED +#define mmFMT2_FMT_FORCE_DATA_0_1 0x41F0 +#define mmFMT2_FMT_FORCE_DATA_2_3 0x41F1 +#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41EF +#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41F6 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41F7 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41F8 +#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41EC +#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41EB +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44F2 +#define mmFMT3_FMT_CLAMP_CNTL 0x44F9 +#define mmFMT3_FMT_CONTROL 0x44EE +#define mmFMT3_FMT_CRC_CNTL 0x44FA +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44FE +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44FC +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44FD +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44FB +#define mmFMT3_FMT_DEBUG_CNTL 0x44FF +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44F5 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44F4 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44F3 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ED +#define mmFMT3_FMT_FORCE_DATA_0_1 0x44F0 +#define mmFMT3_FMT_FORCE_DATA_2_3 0x44F1 +#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44EF +#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44F6 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44F7 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44F8 +#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44EC +#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44EB +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47F2 +#define mmFMT4_FMT_CLAMP_CNTL 0x47F9 +#define mmFMT4_FMT_CONTROL 0x47EE +#define mmFMT4_FMT_CRC_CNTL 0x47FA +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47FE +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47FC +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47FD +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47FB +#define mmFMT4_FMT_DEBUG_CNTL 0x47FF +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47F5 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47F4 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47F3 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ED +#define mmFMT4_FMT_FORCE_DATA_0_1 0x47F0 +#define mmFMT4_FMT_FORCE_DATA_2_3 0x47F1 +#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47EF +#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47F6 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47F7 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47F8 +#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47EC +#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47EB +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4AF2 +#define mmFMT5_FMT_CLAMP_CNTL 0x4AF9 +#define mmFMT5_FMT_CONTROL 0x4AEE +#define mmFMT5_FMT_CRC_CNTL 0x4AFA +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4AFE +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4AFC +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4AFD +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4AFB +#define mmFMT5_FMT_DEBUG_CNTL 0x4AFF +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4AF5 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4AF4 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4AF3 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4AED +#define mmFMT5_FMT_FORCE_DATA_0_1 0x4AF0 +#define mmFMT5_FMT_FORCE_DATA_2_3 0x4AF1 +#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4AEF +#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4AF6 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4AF7 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4AF8 +#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4AEC +#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4AEB +#define mmFMT_BIT_DEPTH_CONTROL 0x1BF2 +#define mmFMT_CLAMP_CNTL 0x1BF9 +#define mmFMT_CONTROL 0x1BEE +#define mmFMT_CRC_CNTL 0x1BFA +#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1BFE +#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC +#define mmFMT_CRC_SIG_RED_GREEN 0x1BFD +#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1BFB +#define mmFMT_DEBUG_CNTL 0x1BFF +#define mmFMT_DITHER_RAND_B_SEED 0x1BF5 +#define mmFMT_DITHER_RAND_G_SEED 0x1BF4 +#define mmFMT_DITHER_RAND_R_SEED 0x1BF3 +#define mmFMT_DYNAMIC_EXP_CNTL 0x1BED +#define mmFMT_FORCE_DATA_0_1 0x1BF0 +#define mmFMT_FORCE_DATA_2_3 0x1BF1 +#define mmFMT_FORCE_OUTPUT_CNTL 0x1BEF +#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 +#define mmFMT_TEST_DEBUG_DATA 0x1BEC +#define mmFMT_TEST_DEBUG_INDEX 0x1BEB +#define mmGAMUT_REMAP_C11_C12 0x1A5A +#define mmGAMUT_REMAP_C13_C14 0x1A5B +#define mmGAMUT_REMAP_C21_C22 0x1A5C +#define mmGAMUT_REMAP_C23_C24 0x1A5D +#define mmGAMUT_REMAP_C31_C32 0x1A5E +#define mmGAMUT_REMAP_C33_C34 0x1A5F +#define mmGAMUT_REMAP_CONTROL 0x1A59 +#define mmGENENB 0x00F0 +#define mmGENERIC_I2C_CONTROL 0x1834 +#define mmGENERIC_I2C_DATA 0x183A +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 +#define mmGENERIC_I2C_PIN_DEBUG 0x183C +#define mmGENERIC_I2C_PIN_SELECTION 0x183B +#define mmGENERIC_I2C_SETUP 0x1838 +#define mmGENERIC_I2C_SPEED 0x1837 +#define mmGENERIC_I2C_STATUS 0x1836 +#define mmGENERIC_I2C_TRANSACTION 0x1839 +#define mmGENFC_RD 0x00F2 +#define mmGENFC_WT 0x00EE +#define mmGENMO_RD 0x00F3 +#define mmGENMO_WT 0x00F0 +#define mmGENS0 0x00F0 +#define mmGENS1 0x00EE +#define mmGRPH8_DATA 0x00F3 +#define mmGRPH8_IDX 0x00F3 +#define mmGRPH_COMPRESS_PITCH 0x1A1A +#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 +#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B +#define mmGRPH_CONTROL 0x1A01 +#define mmGRPH_DFQ_CONTROL 0x1A14 +#define mmGRPH_DFQ_STATUS 0x1A15 +#define mmGRPH_ENABLE 0x1A00 +#define mmGRPH_FLIP_CONTROL 0x1A12 +#define mmGRPH_INTERRUPT_CONTROL 0x1A17 +#define mmGRPH_INTERRUPT_STATUS 0x1A16 +#define mmGRPH_LUT_10BIT_BYPASS 0x1A02 +#define mmGRPH_PITCH 0x1A06 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 +#define mmGRPH_STEREOSYNC_FLIP 0x1A97 +#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 +#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1A13 +#define mmGRPH_SURFACE_OFFSET_X 0x1A09 +#define mmGRPH_SURFACE_OFFSET_Y 0x1A0A +#define mmGRPH_SWAP_CNTL 0x1A03 +#define mmGRPH_UPDATE 0x1A11 +#define mmGRPH_X_END 0x1A0D +#define mmGRPH_X_START 0x1A0B +#define mmGRPH_Y_END 0x1A0E +#define mmGRPH_Y_START 0x1A0C +#define mmHDMI_ACR_32_0 0x1C37 +#define mmHDMI_ACR_32_1 0x1C38 +#define mmHDMI_ACR_44_0 0x1C39 +#define mmHDMI_ACR_44_1 0x1C3A +#define mmHDMI_ACR_48_0 0x1C3B +#define mmHDMI_ACR_48_1 0x1C3C +#define mmHDMI_ACR_PACKET_CONTROL 0x1C0F +#define mmHDMI_ACR_STATUS_0 0x1C3D +#define mmHDMI_ACR_STATUS_1 0x1C3E +#define mmHDMI_AUDIO_PACKET_CONTROL 0x1C0E +#define mmHDMI_CONTROL 0x1C0C +#define mmHDMI_GC 0x1C16 +#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1C13 +#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1C30 +#define mmHDMI_INFOFRAME_CONTROL0 0x1C11 +#define mmHDMI_INFOFRAME_CONTROL1 0x1C12 +#define mmHDMI_STATUS 0x1C0D +#define mmHDMI_VBI_PACKET_CONTROL 0x1C10 +#define mmINPUT_CSC_C11_C12 0x1A36 +#define mmINPUT_CSC_C13_C14 0x1A37 +#define mmINPUT_CSC_C21_C22 0x1A38 +#define mmINPUT_CSC_C23_C24 0x1A39 +#define mmINPUT_CSC_C31_C32 0x1A3A +#define mmINPUT_CSC_C33_C34 0x1A3B +#define mmINPUT_CSC_CONTROL 0x1A35 +#define mmINPUT_GAMMA_CONTROL 0x1A10 +#define mmKEY_CONTROL 0x1A53 +#define mmKEY_RANGE_ALPHA 0x1A54 +#define mmKEY_RANGE_BLUE 0x1A57 +#define mmKEY_RANGE_GREEN 0x1A56 +#define mmKEY_RANGE_RED 0x1A55 +#define mmLB0_DC_MVP_LB_CONTROL 0x1ADB +#define mmLB0_LB_DEBUG 0x1AFC +#define mmLB0_LB_DEBUG2 0x1AC9 +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 +#define mmLB0_LB_SYNC_RESET_SEL 0x1ACA +#define mmLB0_LB_TEST_DEBUG_DATA 0x1AFF +#define mmLB0_LB_TEST_DEBUG_INDEX 0x1AFE +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9 +#define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA +#define mmLB1_DC_MVP_LB_CONTROL 0x1DDB +#define mmLB1_LB_DEBUG 0x1DFC +#define mmLB1_LB_DEBUG2 0x1DC9 +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8 +#define mmLB1_LB_SYNC_RESET_SEL 0x1DCA +#define mmLB1_LB_TEST_DEBUG_DATA 0x1DFF +#define mmLB1_LB_TEST_DEBUG_INDEX 0x1DFE +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9 +#define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA +#define mmLB2_DC_MVP_LB_CONTROL 0x40DB +#define mmLB2_LB_DEBUG 0x40FC +#define mmLB2_LB_DEBUG2 0x40C9 +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8 +#define mmLB2_LB_SYNC_RESET_SEL 0x40CA +#define mmLB2_LB_TEST_DEBUG_DATA 0x40FF +#define mmLB2_LB_TEST_DEBUG_INDEX 0x40FE +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9 +#define mmLB2_MVP_AFR_FLIP_MODE 0x40D8 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA +#define mmLB3_DC_MVP_LB_CONTROL 0x43DB +#define mmLB3_LB_DEBUG 0x43FC +#define mmLB3_LB_DEBUG2 0x43C9 +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8 +#define mmLB3_LB_SYNC_RESET_SEL 0x43CA +#define mmLB3_LB_TEST_DEBUG_DATA 0x43FF +#define mmLB3_LB_TEST_DEBUG_INDEX 0x43FE +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9 +#define mmLB3_MVP_AFR_FLIP_MODE 0x43D8 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA +#define mmLB4_DC_MVP_LB_CONTROL 0x46DB +#define mmLB4_LB_DEBUG 0x46FC +#define mmLB4_LB_DEBUG2 0x46C9 +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8 +#define mmLB4_LB_SYNC_RESET_SEL 0x46CA +#define mmLB4_LB_TEST_DEBUG_DATA 0x46FF +#define mmLB4_LB_TEST_DEBUG_INDEX 0x46FE +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9 +#define mmLB4_MVP_AFR_FLIP_MODE 0x46D8 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA +#define mmLB5_DC_MVP_LB_CONTROL 0x49DB +#define mmLB5_LB_DEBUG 0x49FC +#define mmLB5_LB_DEBUG2 0x49C9 +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8 +#define mmLB5_LB_SYNC_RESET_SEL 0x49CA +#define mmLB5_LB_TEST_DEBUG_DATA 0x49FF +#define mmLB5_LB_TEST_DEBUG_INDEX 0x49FE +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9 +#define mmLB5_MVP_AFR_FLIP_MODE 0x49D8 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA +#define mmLB_DEBUG 0x1AFC +#define mmLB_DEBUG2 0x1AC9 +#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 +#define mmLB_SYNC_RESET_SEL 0x1ACA +#define mmLB_TEST_DEBUG_DATA 0x1AFF +#define mmLB_TEST_DEBUG_INDEX 0x1AFE +#define mmLIGHT_SLEEP_CNTL 0x0132 +#define mmLOW_POWER_TILING_CONTROL 0x0325 +#define mmLVDS_DATA_CNTL 0x1C8C +#define mmLVTMA_PWRSEQ_CNTL 0x1919 +#define mmLVTMA_PWRSEQ_DELAY1 0x191C +#define mmLVTMA_PWRSEQ_DELAY2 0x191D +#define mmLVTMA_PWRSEQ_REF_DIV 0x191B +#define mmLVTMA_PWRSEQ_STATE 0x191A +#define mmMASTER_COMM_CMD_REG 0x161F +#define mmMASTER_COMM_CNTL_REG 0x1620 +#define mmMASTER_COMM_DATA_REG1 0x161C +#define mmMASTER_COMM_DATA_REG2 0x161D +#define mmMASTER_COMM_DATA_REG3 0x161E +#define mmMASTER_UPDATE_LOCK 0x1BBD +#define mmMASTER_UPDATE_MODE 0x1BBE +#define mmMC_DC_INTERFACE_NACK_STATUS 0x031C +#define mmMCIF_CONTROL 0x0314 +#define mmMCIF_MEM_CONTROL 0x0319 +#define mmMCIF_TEST_DEBUG_DATA 0x0317 +#define mmMCIF_TEST_DEBUG_INDEX 0x0316 +#define mmMCIF_VMID 0x0318 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x0315 +#define mmMICROSECOND_TIME_BASE_DIV 0x013B +#define mmMILLISECOND_TIME_BASE_DIV 0x0130 +#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1AD9 +#define mmMVP_AFR_FLIP_MODE 0x1AD8 +#define mmMVP_BLACK_KEYER 0x1686 +#define mmMVP_CONTROL1 0x1680 +#define mmMVP_CONTROL2 0x1681 +#define mmMVP_CONTROL3 0x168A +#define mmMVP_CRC_CNTL 0x1687 +#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 +#define mmMVP_CRC_RESULT_RED 0x1689 +#define mmMVP_DEBUG 0x168F +#define mmMVP_FIFO_CONTROL 0x1682 +#define mmMVP_FIFO_STATUS 0x1683 +#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ADA +#define mmMVP_INBAND_CNTL_CAP 0x1685 +#define mmMVP_RECEIVE_CNT_CNTL1 0x168B +#define mmMVP_RECEIVE_CNT_CNTL2 0x168C +#define mmMVP_SLAVE_STATUS 0x1684 +#define mmMVP_TEST_DEBUG_DATA 0x168E +#define mmMVP_TEST_DEBUG_INDEX 0x168D +#define mmOUTPUT_CSC_C11_C12 0x1A3D +#define mmOUTPUT_CSC_C13_C14 0x1A3E +#define mmOUTPUT_CSC_C21_C22 0x1A3F +#define mmOUTPUT_CSC_C23_C24 0x1A40 +#define mmOUTPUT_CSC_C31_C32 0x1A41 +#define mmOUTPUT_CSC_C33_C34 0x1A42 +#define mmOUTPUT_CSC_CONTROL 0x1A3C +#define mmOUT_ROUND_CONTROL 0x1A51 +#define mmOVL_CONTROL1 0x1A1D +#define mmOVL_CONTROL2 0x1A1E +#define mmOVL_DFQ_CONTROL 0x1A29 +#define mmOVL_DFQ_STATUS 0x1A2A +#define mmOVL_ENABLE 0x1A1C +#define mmOVL_END 0x1A26 +#define mmOVL_PITCH 0x1A21 +#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1A2C +#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1A92 +#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 +#define mmOVL_START 0x1A25 +#define mmOVL_STEREOSYNC_FLIP 0x1A93 +#define mmOVL_SURFACE_ADDRESS 0x1A20 +#define mmOVL_SURFACE_ADDRESS_HIGH 0x1A22 +#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B +#define mmOVL_SURFACE_ADDRESS_INUSE 0x1A28 +#define mmOVL_SURFACE_OFFSET_X 0x1A23 +#define mmOVL_SURFACE_OFFSET_Y 0x1A24 +#define mmOVL_SWAP_CNTL 0x1A1F +#define mmOVL_UPDATE 0x1A27 +#define mmPHY_AUX_CNTL 0x197F +#define mmPIPE0_ARBITRATION_CONTROL3 0x02FA +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x0328 +#define mmPIPE0_MAX_REQUESTS 0x0302 +#define mmPIPE0_PG_CONFIG 0x1760 +#define mmPIPE0_PG_ENABLE 0x1761 +#define mmPIPE0_PG_STATUS 0x1762 +#define mmPIPE1_ARBITRATION_CONTROL3 0x02FB +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x0330 +#define mmPIPE1_MAX_REQUESTS 0x0303 +#define mmPIPE1_PG_CONFIG 0x1764 +#define mmPIPE1_PG_ENABLE 0x1765 +#define mmPIPE1_PG_STATUS 0x1766 +#define mmPIPE2_ARBITRATION_CONTROL3 0x02FC +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x0338 +#define mmPIPE2_MAX_REQUESTS 0x0304 +#define mmPIPE2_PG_CONFIG 0x1768 +#define mmPIPE2_PG_ENABLE 0x1769 +#define mmPIPE2_PG_STATUS 0x176A +#define mmPIPE3_ARBITRATION_CONTROL3 0x02FD +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x0340 +#define mmPIPE3_MAX_REQUESTS 0x0305 +#define mmPIPE3_PG_CONFIG 0x176C +#define mmPIPE3_PG_ENABLE 0x176D +#define mmPIPE3_PG_STATUS 0x176E +#define mmPIPE4_ARBITRATION_CONTROL3 0x02FE +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x0348 +#define mmPIPE4_MAX_REQUESTS 0x0306 +#define mmPIPE4_PG_CONFIG 0x1770 +#define mmPIPE4_PG_ENABLE 0x1771 +#define mmPIPE4_PG_STATUS 0x1772 +#define mmPIPE5_ARBITRATION_CONTROL3 0x02FF +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x0350 +#define mmPIPE5_MAX_REQUESTS 0x0307 +#define mmPIPE5_PG_CONFIG 0x1774 +#define mmPIPE5_PG_ENABLE 0x1775 +#define mmPIPE5_PG_STATUS 0x1776 +#define mmPIXCLK0_RESYNC_CNTL 0x013A +#define mmPIXCLK1_RESYNC_CNTL 0x0138 +#define mmPIXCLK2_RESYNC_CNTL 0x0139 +#define mmPLL_ANALOG 0x1708 +#define mmPLL_CNTL 0x1707 +#define mmPLL_DEBUG_CNTL 0x170B +#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170F +#define mmPLL_DISPCLK_DTO_CNTL 0x170E +#define mmPLL_DS_CNTL 0x1705 +#define mmPLL_FB_DIV 0x1701 +#define mmPLL_IDCLK_CNTL 0x1706 +#define mmPLL_POST_DIV 0x1702 +#define mmPLL_REF_DIV 0x1700 +#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmPLL_SS_CNTL 0x1704 +#define mmPLL_UNLOCK_DETECT_CNTL 0x170A +#define mmPLL_UPDATE_CNTL 0x170D +#define mmPLL_UPDATE_LOCK 0x170C +#define mmPLL_VREG_CNTL 0x1709 +#define mmPRESCALE_GRPH_CONTROL 0x1A2D +#define mmPRESCALE_OVL_CONTROL 0x1A31 +#define mmPRESCALE_VALUES_GRPH_B 0x1A30 +#define mmPRESCALE_VALUES_GRPH_G 0x1A2F +#define mmPRESCALE_VALUES_GRPH_R 0x1A2E +#define mmPRESCALE_VALUES_OVL_CB 0x1A32 +#define mmPRESCALE_VALUES_OVL_CR 0x1A34 +#define mmPRESCALE_VALUES_OVL_Y 0x1A33 +#define mmREGAMMA_CNTLA_END_CNTL1 0x1AA6 +#define mmREGAMMA_CNTLA_END_CNTL2 0x1AA7 +#define mmREGAMMA_CNTLA_REGION_0_1 0x1AA8 +#define mmREGAMMA_CNTLA_REGION_10_11 0x1AAD +#define mmREGAMMA_CNTLA_REGION_12_13 0x1AAE +#define mmREGAMMA_CNTLA_REGION_14_15 0x1AAF +#define mmREGAMMA_CNTLA_REGION_2_3 0x1AA9 +#define mmREGAMMA_CNTLA_REGION_4_5 0x1AAA +#define mmREGAMMA_CNTLA_REGION_6_7 0x1AAB +#define mmREGAMMA_CNTLA_REGION_8_9 0x1AAC +#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 +#define mmREGAMMA_CNTLA_START_CNTL 0x1AA4 +#define mmREGAMMA_CNTLB_END_CNTL1 0x1AB2 +#define mmREGAMMA_CNTLB_END_CNTL2 0x1AB3 +#define mmREGAMMA_CNTLB_REGION_0_1 0x1AB4 +#define mmREGAMMA_CNTLB_REGION_10_11 0x1AB9 +#define mmREGAMMA_CNTLB_REGION_12_13 0x1ABA +#define mmREGAMMA_CNTLB_REGION_14_15 0x1ABB +#define mmREGAMMA_CNTLB_REGION_2_3 0x1AB5 +#define mmREGAMMA_CNTLB_REGION_4_5 0x1AB6 +#define mmREGAMMA_CNTLB_REGION_6_7 0x1AB7 +#define mmREGAMMA_CNTLB_REGION_8_9 0x1AB8 +#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 +#define mmREGAMMA_CNTLB_START_CNTL 0x1AB0 +#define mmREGAMMA_CONTROL 0x1AA0 +#define mmREGAMMA_LUT_DATA 0x1AA2 +#define mmREGAMMA_LUT_INDEX 0x1AA1 +#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1AA3 +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1B5E +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1B5F +#define mmSCL0_SCL_ALU_CONTROL 0x1B54 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1B47 +#define mmSCL0_SCL_BYPASS_CONTROL 0x1B45 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL0_SCL_CONTROL 0x1B44 +#define mmSCL0_SCL_DEBUG 0x1B6A +#define mmSCL0_SCL_DEBUG2 0x1B69 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x1B53 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1B4A +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1B4B +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1B46 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1B60 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1B61 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1B62 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1B63 +#define mmSCL0_SCL_TAP_CONTROL 0x1B43 +#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1B6C +#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1B6B +#define mmSCL0_SCL_UPDATE 0x1B51 +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1B4E +#define mmSCL0_SCL_VERT_FILTER_INIT 0x1B50 +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1B57 +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1B4F +#define mmSCL0_VIEWPORT_SIZE 0x1B5D +#define mmSCL0_VIEWPORT_START 0x1B5C +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1E5E +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1E5F +#define mmSCL1_SCL_ALU_CONTROL 0x1E54 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1E47 +#define mmSCL1_SCL_BYPASS_CONTROL 0x1E45 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41 +#define mmSCL1_SCL_CONTROL 0x1E44 +#define mmSCL1_SCL_DEBUG 0x1E6A +#define mmSCL1_SCL_DEBUG2 0x1E69 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x1E53 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1E4A +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1E4B +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1E46 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1E60 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1E61 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1E62 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1E63 +#define mmSCL1_SCL_TAP_CONTROL 0x1E43 +#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1E6C +#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1E6B +#define mmSCL1_SCL_UPDATE 0x1E51 +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1E4E +#define mmSCL1_SCL_VERT_FILTER_INIT 0x1E50 +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1E57 +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1E4F +#define mmSCL1_VIEWPORT_SIZE 0x1E5D +#define mmSCL1_VIEWPORT_START 0x1E5C +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415E +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415F +#define mmSCL2_SCL_ALU_CONTROL 0x4154 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define mmSCL2_SCL_BYPASS_CONTROL 0x4145 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL2_SCL_CONTROL 0x4144 +#define mmSCL2_SCL_DEBUG 0x416A +#define mmSCL2_SCL_DEBUG2 0x4169 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x414A +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x414B +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 +#define mmSCL2_SCL_TAP_CONTROL 0x4143 +#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416C +#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416B +#define mmSCL2_SCL_UPDATE 0x4151 +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414E +#define mmSCL2_SCL_VERT_FILTER_INIT 0x4150 +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x4157 +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414F +#define mmSCL2_VIEWPORT_SIZE 0x415D +#define mmSCL2_VIEWPORT_START 0x415C +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445E +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445F +#define mmSCL3_SCL_ALU_CONTROL 0x4454 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 +#define mmSCL3_SCL_BYPASS_CONTROL 0x4445 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 +#define mmSCL3_SCL_CONTROL 0x4444 +#define mmSCL3_SCL_DEBUG 0x446A +#define mmSCL3_SCL_DEBUG2 0x4469 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x444A +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x444B +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 +#define mmSCL3_SCL_TAP_CONTROL 0x4443 +#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446C +#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446B +#define mmSCL3_SCL_UPDATE 0x4451 +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444E +#define mmSCL3_SCL_VERT_FILTER_INIT 0x4450 +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x4457 +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444F +#define mmSCL3_VIEWPORT_SIZE 0x445D +#define mmSCL3_VIEWPORT_START 0x445C +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475E +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475F +#define mmSCL4_SCL_ALU_CONTROL 0x4754 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 +#define mmSCL4_SCL_BYPASS_CONTROL 0x4745 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 +#define mmSCL4_SCL_CONTROL 0x4744 +#define mmSCL4_SCL_DEBUG 0x476A +#define mmSCL4_SCL_DEBUG2 0x4769 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x474A +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x474B +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 +#define mmSCL4_SCL_TAP_CONTROL 0x4743 +#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476C +#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476B +#define mmSCL4_SCL_UPDATE 0x4751 +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474E +#define mmSCL4_SCL_VERT_FILTER_INIT 0x4750 +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x4757 +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474F +#define mmSCL4_VIEWPORT_SIZE 0x475D +#define mmSCL4_VIEWPORT_START 0x475C +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4A5E +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4A5F +#define mmSCL5_SCL_ALU_CONTROL 0x4A54 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4A47 +#define mmSCL5_SCL_BYPASS_CONTROL 0x4A45 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 +#define mmSCL5_SCL_CONTROL 0x4A44 +#define mmSCL5_SCL_DEBUG 0x4A6A +#define mmSCL5_SCL_DEBUG2 0x4A69 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x4A53 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4A4A +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4A4B +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4A46 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4A60 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4A61 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4A62 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4A63 +#define mmSCL5_SCL_TAP_CONTROL 0x4A43 +#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4A6C +#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4A6B +#define mmSCL5_SCL_UPDATE 0x4A51 +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4A4E +#define mmSCL5_SCL_VERT_FILTER_INIT 0x4A50 +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4A57 +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4A4F +#define mmSCL5_VIEWPORT_SIZE 0x4A5D +#define mmSCL5_VIEWPORT_START 0x4A5C +#define mmSCL_ALU_CONTROL 0x1B54 +#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1B47 +#define mmSCL_BYPASS_CONTROL 0x1B45 +#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55 +#define mmSCL_COEF_RAM_SELECT 0x1B40 +#define mmSCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL_CONTROL 0x1B44 +#define mmSCL_DEBUG 0x1B6A +#define mmSCL_DEBUG2 0x1B69 +#define mmSCL_F_SHARP_CONTROL 0x1B53 +#define mmSCL_HORZ_FILTER_CONTROL 0x1B4A +#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1B4B +#define mmSCLK_CGTT_BLK_CTRL_REG 0x0136 +#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1B46 +#define mmSCL_MODE_CHANGE_DET1 0x1B60 +#define mmSCL_MODE_CHANGE_DET2 0x1B61 +#define mmSCL_MODE_CHANGE_DET3 0x1B62 +#define mmSCL_MODE_CHANGE_MASK 0x1B63 +#define mmSCL_TAP_CONTROL 0x1B43 +#define mmSCL_TEST_DEBUG_DATA 0x1B6C +#define mmSCL_TEST_DEBUG_INDEX 0x1B6B +#define mmSCL_UPDATE 0x1B51 +#define mmSCL_VERT_FILTER_CONTROL 0x1B4E +#define mmSCL_VERT_FILTER_INIT 0x1B50 +#define mmSCL_VERT_FILTER_INIT_BOT 0x1B57 +#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1B4F +#define mmSEQ8_DATA 0x00F1 +#define mmSEQ8_IDX 0x00F1 +#define mmSLAVE_COMM_CMD_REG 0x1624 +#define mmSLAVE_COMM_CNTL_REG 0x1625 +#define mmSLAVE_COMM_DATA_REG1 0x1621 +#define mmSLAVE_COMM_DATA_REG2 0x1622 +#define mmSLAVE_COMM_DATA_REG3 0x1623 +#define mmSYMCLKA_CLOCK_ENABLE 0x0160 +#define mmSYMCLKB_CLOCK_ENABLE 0x0161 +#define mmSYMCLKC_CLOCK_ENABLE 0x0162 +#define mmSYMCLKD_CLOCK_ENABLE 0x0163 +#define mmSYMCLKE_CLOCK_ENABLE 0x0164 +#define mmSYMCLKF_CLOCK_ENABLE 0x0165 +#define mmTMDS_CNTL 0x1C7C +#define mmTMDS_CONTROL0_FEEDBACK 0x1C7E +#define mmTMDS_CONTROL_CHAR 0x1C7D +#define mmTMDS_CTL0_1_GEN_CNTL 0x1C86 +#define mmTMDS_CTL2_3_GEN_CNTL 0x1C87 +#define mmTMDS_CTL_BITS 0x1C83 +#define mmTMDS_DCBALANCER_CONTROL 0x1C84 +#define mmTMDS_DEBUG 0x1C82 +#define mmTMDS_STEREOSYNC_CTL_SEL 0x1C7F +#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 +#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 +#define mmUNIPHYAB_TPG_CONTROL 0x1931 +#define mmUNIPHYAB_TPG_SEED 0x1932 +#define mmUNIPHY_ANG_BIST_CNTL 0x198C +#define mmUNIPHYCD_TPG_CONTROL 0x1933 +#define mmUNIPHYCD_TPG_SEED 0x1934 +#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198E +#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198A +#define mmUNIPHYEF_TPG_CONTROL 0x1935 +#define mmUNIPHYEF_TPG_SEED 0x1936 +#define mmUNIPHY_IMPCAL_LINKA 0x1908 +#define mmUNIPHY_IMPCAL_LINKB 0x1909 +#define mmUNIPHY_IMPCAL_LINKC 0x190F +#define mmUNIPHY_IMPCAL_LINKD 0x1910 +#define mmUNIPHY_IMPCAL_LINKE 0x1913 +#define mmUNIPHY_IMPCAL_LINKF 0x1914 +#define mmUNIPHY_IMPCAL_PERIOD 0x190A +#define mmUNIPHY_IMPCAL_PSW_AB 0x190E +#define mmUNIPHY_IMPCAL_PSW_CD 0x1912 +#define mmUNIPHY_IMPCAL_PSW_EF 0x1916 +#define mmUNIPHY_LINK_CNTL 0x198D +#define mmUNIPHY_PLL_CONTROL1 0x1986 +#define mmUNIPHY_PLL_CONTROL2 0x1987 +#define mmUNIPHY_PLL_FBDIV 0x1985 +#define mmUNIPHY_PLL_SS_CNTL 0x1989 +#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmUNIPHY_POWER_CONTROL 0x1984 +#define mmUNIPHY_REG_TEST_OUTPUT 0x198B +#define mmUNIPHY_SOFT_RESET 0x0166 +#define mmUNIPHY_TX_CONTROL1 0x1980 +#define mmUNIPHY_TX_CONTROL2 0x1981 +#define mmUNIPHY_TX_CONTROL3 0x1982 +#define mmUNIPHY_TX_CONTROL4 0x1983 +#define mmVGA25_PPLL_ANALOG 0x00E4 +#define mmVGA25_PPLL_FB_DIV 0x00DC +#define mmVGA25_PPLL_POST_DIV 0x00E0 +#define mmVGA25_PPLL_REF_DIV 0x00D8 +#define mmVGA28_PPLL_ANALOG 0x00E5 +#define mmVGA28_PPLL_FB_DIV 0x00DD +#define mmVGA28_PPLL_POST_DIV 0x00E1 +#define mmVGA28_PPLL_REF_DIV 0x00D9 +#define mmVGA41_PPLL_ANALOG 0x00E6 +#define mmVGA41_PPLL_FB_DIV 0x00DE +#define mmVGA41_PPLL_POST_DIV 0x00E2 +#define mmVGA41_PPLL_REF_DIV 0x00DA +#define mmVGA_CACHE_CONTROL 0x00CB +#define mmVGA_DEBUG_READBACK_DATA 0x00D7 +#define mmVGA_DEBUG_READBACK_INDEX 0x00D6 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0x00C6 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0x00C8 +#define mmVGA_HDP_CONTROL 0x00CA +#define mmVGA_HW_DEBUG 0x00CF +#define mmVGA_INTERRUPT_CONTROL 0x00D1 +#define mmVGA_INTERRUPT_STATUS 0x00D3 +#define mmVGA_MAIN_CONTROL 0x00D4 +#define mmVGA_MEMORY_BASE_ADDRESS 0x00C4 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x00C9 +#define mmVGA_MEM_READ_PAGE_ADDR 0x0013 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0012 +#define mmVGA_MODE_CONTROL 0x00C2 +#define mmVGA_RENDER_CONTROL 0x00C0 +#define mmVGA_SEQUENCER_RESET_CONTROL 0x00C1 +#define mmVGA_SOURCE_SELECT 0x00FC +#define mmVGA_STATUS 0x00D0 +#define mmVGA_STATUS_CLEAR 0x00D2 +#define mmVGA_SURFACE_PITCH_SELECT 0x00C3 +#define mmVGA_TEST_CONTROL 0x00D5 +#define mmVGA_TEST_DEBUG_DATA 0x00C7 +#define mmVGA_TEST_DEBUG_INDEX 0x00C5 +#define mmVIEWPORT_SIZE 0x1B5D +#define mmVIEWPORT_START 0x1B5C +#define mmXDMA_CLOCK_GATING_CNTL 0x0409 +#define mmXDMA_IF_BIF_STATUS 0x0418 +#define mmXDMA_INTERRUPT 0x0406 +#define mmXDMA_LOCAL_SURFACE_TILING1 0x03F4 +#define mmXDMA_LOCAL_SURFACE_TILING2 0x03F5 +#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x03E9 +#define mmXDMA_MEM_POWER_CNTL 0x040B +#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x03F6 +#define mmXDMA_MSTR_CNTL 0x03E0 +#define mmXDMA_MSTR_HEIGHT 0x03E3 +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x03F1 +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x03F2 +#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x03F3 +#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x03EA +#define mmXDMA_MSTR_MEM_NACK_STATUS 0x040D +#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x03F7 +#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x040C +#define mmXDMA_MSTR_READ_COMMAND 0x03E1 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x03E6 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x03E7 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x03E4 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x03E5 +#define mmXDMA_MSTR_STATUS 0x03E8 +#define mmXDMA_RBBMIF_RDWR_CNTL 0x040A +#define mmXDMA_SLV_CNTL 0x03FB +#define mmXDMA_SLV_FLIP_PENDING 0x0407 +#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x03FD +#define mmXDMA_SLV_MEM_NACK_STATUS 0x040F +#define mmXDMA_SLV_PCIE_NACK_STATUS 0x040E +#define mmXDMA_SLV_READ_LATENCY_AVE 0x0405 +#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x0404 +#define mmXDMA_SLV_READ_LATENCY_TIMER 0x0412 +#define mmXDMA_SLV_READ_URGENT_CNTL 0x03FF +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x0402 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x0403 +#define mmXDMA_SLV_SLS_PITCH 0x03FE +#define mmXDMA_SLV_WB_RATE_CNTL 0x0401 +#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x0400 +#define mmXDMA_TEST_DEBUG_DATA 0x041D +#define mmXDMA_TEST_DEBUG_INDEX 0x041C + +/* Registers that spilled out of sid.h */ +#define mmDATA_FORMAT 0x1AC0 +#define mmDESKTOP_HEIGHT 0x1AC1 +#define mmDC_LB_MEMORY_SPLIT 0x1AC3 +#define mmPRIORITY_A_CNT 0x1AC6 +#define mmPRIORITY_B_CNT 0x1AC7 +#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32 +#define mmINT_MASK 0x1AD0 +#define mmVLINE_STATUS 0x1AEE +#define mmVBLANK_STATUS 0x1AEF + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h new file mode 100644 index 000000000000..9a4d4c299d5b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h @@ -0,0 +1,9836 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_6_0_SH_MASK_H +#define DCE_6_0_SH_MASK_H + +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000 +#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000ff00L +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x00000008 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00f00000L +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000014 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x0000001c +#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x00000002 +#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x00000003 +#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000c0L +#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x00000006 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0f000000L +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000018 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000f0000L +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x00000010 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00f00000L +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000014 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000f0L +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000004 +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000fL +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x00000000 +#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x00000010 +#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x00000012 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000f00L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000008 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000f000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x0000000c +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000f0000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000010 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00f00000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000014 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000f000L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0x0000000c +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x00000004 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x00000010 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x00000000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x00000008 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x00000000 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00L +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x00000008 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x00000008 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x00000010 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0x0000000c +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x00000008 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00ff0000L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x00000010 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0x0000000b +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x00000018 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000ffL +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0x0000000f +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x00000010 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0x0000000b +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x0000001c +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000ff00L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x00000008 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x00000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x00000001 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00ff0000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x00000010 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x00000018 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x0000001a +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x00000018 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x00000017 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x00000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0x0000000c +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0x0000000e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x0000001e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x0000001f +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0x0000000b +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x00000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0x0000000c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000c00L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0x0000000a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00c00000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x00000016 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x0000001c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x0000001f +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x00000014 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x00008000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0x0000000f +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0c000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x0000001a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000f0000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x00000010 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x00000018 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x00000008 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x00006000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0x0000000d +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0x0000000c +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x00000080L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x00000007 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000f00L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x00000008 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x00000010 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x0000007fL +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x00000000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000c000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0x0000000e +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000ffffL +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x00000000 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000L +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x00000010 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000ffffL +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x00000000 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000L +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x00000018 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000ffL +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x00000000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000ff00L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x00000008 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00ff0000L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x00000010 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x00000018 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000ffL +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x00000000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000ff00L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x00000008 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00ff0000L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x00000010 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x00000018 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00ff0000L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x00000010 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x00000018 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000ffL +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x00000000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000ff00L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x00000008 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000ffL +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x00000000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000ff00L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x00000008 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00ff0000L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x00000010 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x00000018 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000ffL +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x00000000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000ff00L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x00000008 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00ff0000L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x00000010 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x00000018 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000ffL +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x00000000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000ff00L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x00000008 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00ff0000L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x00000010 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x00000018 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000ffL +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x00000000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000ff00L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x00000008 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00ff0000L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x00000010 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x00000018 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000ffL +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x00000000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000ff00L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x00000008 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00ff0000L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x00000010 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x00000018 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000ffL +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x00000000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000ff00L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x00000008 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00ff0000L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x00000010 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x00000018 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x00000006 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x00000007 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0x0000000a +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x00000006 +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x00000000 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x00000007 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000ffL +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x00000000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000ff00L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x00000008 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00ff0000L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x00000010 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x00000018 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000ffL +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x00000000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000ff00L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x00000008 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00ff0000L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x00000010 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x00000018 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00ff0000L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x00000010 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x00000018 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000ffL +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x00000000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000ff00L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x00000008 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000ffL +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x00000000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000ff00L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x00000008 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00ff0000L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x00000010 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x00000018 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000ffL +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x00000000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000ff00L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x00000008 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00ff0000L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x00000010 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x00000018 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000ffL +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x00000000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000ff00L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x00000008 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00ff0000L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x00000010 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x00000018 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000ffL +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x00000000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000ff00L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x00000008 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00ff0000L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x00000010 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x00000018 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000ffL +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x00000000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000ff00L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x00000008 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00ff0000L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x00000010 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x00000018 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000ff00L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x00000008 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00ff0000L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x00000010 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x00000018 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0x0000000c +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000ffL +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x00000000 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x00000008 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x0000001f +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000L +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x00000018 +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x00000000 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x00000004 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x00000018 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x0000001e +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x00000008 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x00000002 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x00000003 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x0000001e +#define ATTR00__ATTR_PAL_MASK 0x0000003fL +#define ATTR00__ATTR_PAL__SHIFT 0x00000000 +#define ATTR01__ATTR_PAL_MASK 0x0000003fL +#define ATTR01__ATTR_PAL__SHIFT 0x00000000 +#define ATTR02__ATTR_PAL_MASK 0x0000003fL +#define ATTR02__ATTR_PAL__SHIFT 0x00000000 +#define ATTR03__ATTR_PAL_MASK 0x0000003fL +#define ATTR03__ATTR_PAL__SHIFT 0x00000000 +#define ATTR04__ATTR_PAL_MASK 0x0000003fL +#define ATTR04__ATTR_PAL__SHIFT 0x00000000 +#define ATTR05__ATTR_PAL_MASK 0x0000003fL +#define ATTR05__ATTR_PAL__SHIFT 0x00000000 +#define ATTR06__ATTR_PAL_MASK 0x0000003fL +#define ATTR06__ATTR_PAL__SHIFT 0x00000000 +#define ATTR07__ATTR_PAL_MASK 0x0000003fL +#define ATTR07__ATTR_PAL__SHIFT 0x00000000 +#define ATTR08__ATTR_PAL_MASK 0x0000003fL +#define ATTR08__ATTR_PAL__SHIFT 0x00000000 +#define ATTR09__ATTR_PAL_MASK 0x0000003fL +#define ATTR09__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0A__ATTR_PAL_MASK 0x0000003fL +#define ATTR0A__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0B__ATTR_PAL_MASK 0x0000003fL +#define ATTR0B__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0C__ATTR_PAL_MASK 0x0000003fL +#define ATTR0C__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0D__ATTR_PAL_MASK 0x0000003fL +#define ATTR0D__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0E__ATTR_PAL_MASK 0x0000003fL +#define ATTR0E__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0F__ATTR_PAL_MASK 0x0000003fL +#define ATTR0F__ATTR_PAL__SHIFT 0x00000000 +#define ATTR10__ATTR_BLINK_EN_MASK 0x00000008L +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x00000003 +#define ATTR10__ATTR_CSEL_EN_MASK 0x00000080L +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x00000007 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x00000001L +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x00000000 +#define ATTR10__ATTR_LGRPH_EN_MASK 0x00000004L +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x00000002 +#define ATTR10__ATTR_MONO_EN_MASK 0x00000002L +#define ATTR10__ATTR_MONO_EN__SHIFT 0x00000001 +#define ATTR10__ATTR_PANTOPONLY_MASK 0x00000020L +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x00000005 +#define ATTR10__ATTR_PCLKBY2_MASK 0x00000040L +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x00000006 +#define ATTR11__ATTR_OVSC_MASK 0x000000ffL +#define ATTR11__ATTR_OVSC__SHIFT 0x00000000 +#define ATTR12__ATTR_MAP_EN_MASK 0x0000000fL +#define ATTR12__ATTR_MAP_EN__SHIFT 0x00000000 +#define ATTR12__ATTR_VSMUX_MASK 0x00000030L +#define ATTR12__ATTR_VSMUX__SHIFT 0x00000004 +#define ATTR13__ATTR_PPAN_MASK 0x0000000fL +#define ATTR13__ATTR_PPAN__SHIFT 0x00000000 +#define ATTR14__ATTR_CSEL1_MASK 0x00000003L +#define ATTR14__ATTR_CSEL1__SHIFT 0x00000000 +#define ATTR14__ATTR_CSEL2_MASK 0x0000000cL +#define ATTR14__ATTR_CSEL2__SHIFT 0x00000002 +#define ATTRDR__ATTR_DATA_MASK 0x000000ffL +#define ATTRDR__ATTR_DATA__SHIFT 0x00000000 +#define ATTRDW__ATTR_DATA_MASK 0x000000ffL +#define ATTRDW__ATTR_DATA__SHIFT 0x00000000 +#define ATTRX__ATTR_IDX_MASK 0x0000001fL +#define ATTRX__ATTR_IDX__SHIFT 0x00000000 +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x00000020L +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x00000005 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x00000000 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x00000019 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0x0000000a +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x00000008 +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000cL +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x00000002 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x00000011 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000010 +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x00000010 +#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x0000001d +#define AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define AUX_CONTROL__AUX_EN__SHIFT 0x00000000 +#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x00000014 +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x00000010 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x00000018 +#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x00000008 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0x0000000c +#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x00000012 +#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x0000001c +#define AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define AUX_CONTROL__SPARE_0__SHIFT 0x0000001e +#define AUX_CONTROL__SPARE_1_MASK 0x80000000L +#define AUX_CONTROL__SPARE_1__SHIFT 0x0000001f +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x00000011 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x00000012 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x00000013 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x0000001c +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0x0000000c +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x00000014 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x00000008 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x00000004 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x00000018 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x00000010 +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000ffL +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x00000000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001f0000L +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x00000010 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000L +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x00000015 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x00000000 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001f00L +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x00000008 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x00000000 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003f00L +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x00000008 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x00000004 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01ff0000L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x00000010 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x00000000 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x00000000 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01ff0000L +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x00000010 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x00000004 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x00000000 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x00000005 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x00000004 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x00000006 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x00000001 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x00000000 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x00000002 +#define AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000ff00L +#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x00000008 +#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001f0000L +#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x00000010 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x0000001d +#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x00000000 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x00000009 +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0x0000000b +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000L +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x00000018 +#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x00000001 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x00000013 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0x0000000e +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x00000008 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0x0000000a +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x00000016 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x00000017 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x00000014 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x00000012 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x00000011 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x00000007 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x00000004 +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x0000001f +#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x0000001e +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0x0000000a +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x00000009 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x00000008 +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x00000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0f000000L +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x00000018 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00f00000L +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x00000014 +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000f0000L +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x00000010 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0x0000000a +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x00000009 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x00000008 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x00000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0f000000L +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x00000018 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00f00000L +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x00000014 +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000f0000L +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x00000010 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x00000002 +#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x00000000 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000f0L +#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x00000004 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001f0000L +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x00000010 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x0000001f +#define AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000ff00L +#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x00000000 +#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x00000008 +#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001f0000L +#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x00000010 +#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000L +#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x0000001e +#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x00000000 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x00000009 +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0x0000000b +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000L +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x00000018 +#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x00000001 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x00000013 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0x0000000e +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x00000008 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0x0000000a +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x00000016 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x00000017 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x00000014 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x00000012 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x00000011 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x00000007 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x00000004 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffffL +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x00000000 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000L +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x00000010 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000ffffL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x00000000 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x00000008 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffffL +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x00000000 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffffL +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x00000000 +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffffL +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x00000000 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x00000000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x00000010 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x00000011 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffffL +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00fc0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x00000012 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x0000001b +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007fL +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x00000019 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000019 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000ffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03ffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003fL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0x0000000f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000ffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000ffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000c0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x0000001f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000fc00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007f00L +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x00000008 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00ff0000L +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x00000010 +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007fL +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x00000000 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x00000001 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x00000000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000ffffL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x00000000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000L +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x00000010 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000ffL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x00000000 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x00000008 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x00000004 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x00000030L +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x00000004 +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffffL +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x00000000 +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffffL +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x00000000 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000ffL +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x00000000 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x00000008 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffffL +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x00000000 +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffffL +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffffL +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x00000003 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x00000002 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x00000010 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x00000000 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x00000001 +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001ffffL +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x00000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000e0000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x00000011 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x00000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x00000008 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x00000010 +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001ffffL +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x00000000 +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x00000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x0000001e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x0000001f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000ffffL +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x00000000 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x0000001c +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000ffffL +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x00000000 +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x0000001f +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x0000001e +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000e0000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x00000011 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x00000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x00000008 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x00000010 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000f0000L +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x00000010 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000ffffL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x00000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x0000001c +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x00000002 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x00000001 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x00000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x00000014 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003ff0L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x00000004 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0f000000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x00000018 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003f0000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x00000010 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x0000001c +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003f00L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x00000008 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x00000000 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007eL +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x00000001 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x00000004 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x00000010 +#define CRT00__H_TOTAL_MASK 0x000000ffL +#define CRT00__H_TOTAL__SHIFT 0x00000000 +#define CRT01__H_DISP_END_MASK 0x000000ffL +#define CRT01__H_DISP_END__SHIFT 0x00000000 +#define CRT02__H_BLANK_START_MASK 0x000000ffL +#define CRT02__H_BLANK_START__SHIFT 0x00000000 +#define CRT03__CR10CR11_R_DIS_B_MASK 0x00000080L +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x00000007 +#define CRT03__H_BLANK_END_MASK 0x0000001fL +#define CRT03__H_BLANK_END__SHIFT 0x00000000 +#define CRT03__H_DE_SKEW_MASK 0x00000060L +#define CRT03__H_DE_SKEW__SHIFT 0x00000005 +#define CRT04__H_SYNC_START_MASK 0x000000ffL +#define CRT04__H_SYNC_START__SHIFT 0x00000000 +#define CRT05__H_BLANK_END_B5_MASK 0x00000080L +#define CRT05__H_BLANK_END_B5__SHIFT 0x00000007 +#define CRT05__H_SYNC_END_MASK 0x0000001fL +#define CRT05__H_SYNC_END__SHIFT 0x00000000 +#define CRT05__H_SYNC_SKEW_MASK 0x00000060L +#define CRT05__H_SYNC_SKEW__SHIFT 0x00000005 +#define CRT06__V_TOTAL_MASK 0x000000ffL +#define CRT06__V_TOTAL__SHIFT 0x00000000 +#define CRT07__LINE_CMP_B8_MASK 0x00000010L +#define CRT07__LINE_CMP_B8__SHIFT 0x00000004 +#define CRT07__V_BLANK_START_B8_MASK 0x00000008L +#define CRT07__V_BLANK_START_B8__SHIFT 0x00000003 +#define CRT07__V_DISP_END_B8_MASK 0x00000002L +#define CRT07__V_DISP_END_B8__SHIFT 0x00000001 +#define CRT07__V_DISP_END_B9_MASK 0x00000040L +#define CRT07__V_DISP_END_B9__SHIFT 0x00000006 +#define CRT07__V_SYNC_START_B8_MASK 0x00000004L +#define CRT07__V_SYNC_START_B8__SHIFT 0x00000002 +#define CRT07__V_SYNC_START_B9_MASK 0x00000080L +#define CRT07__V_SYNC_START_B9__SHIFT 0x00000007 +#define CRT07__V_TOTAL_B8_MASK 0x00000001L +#define CRT07__V_TOTAL_B8__SHIFT 0x00000000 +#define CRT07__V_TOTAL_B9_MASK 0x00000020L +#define CRT07__V_TOTAL_B9__SHIFT 0x00000005 +#define CRT08__BYTE_PAN_MASK 0x00000060L +#define CRT08__BYTE_PAN__SHIFT 0x00000005 +#define CRT08__ROW_SCAN_START_MASK 0x0000001fL +#define CRT08__ROW_SCAN_START__SHIFT 0x00000000 +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x00000080L +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x00000007 +#define CRT09__LINE_CMP_B9_MASK 0x00000040L +#define CRT09__LINE_CMP_B9__SHIFT 0x00000006 +#define CRT09__MAX_ROW_SCAN_MASK 0x0000001fL +#define CRT09__MAX_ROW_SCAN__SHIFT 0x00000000 +#define CRT09__V_BLANK_START_B9_MASK 0x00000020L +#define CRT09__V_BLANK_START_B9__SHIFT 0x00000005 +#define CRT0A__CURSOR_DISABLE_MASK 0x00000020L +#define CRT0A__CURSOR_DISABLE__SHIFT 0x00000005 +#define CRT0A__CURSOR_START_MASK 0x0000001fL +#define CRT0A__CURSOR_START__SHIFT 0x00000000 +#define CRT0B__CURSOR_END_MASK 0x0000001fL +#define CRT0B__CURSOR_END__SHIFT 0x00000000 +#define CRT0B__CURSOR_SKEW_MASK 0x00000060L +#define CRT0B__CURSOR_SKEW__SHIFT 0x00000005 +#define CRT0C__DISP_START_MASK 0x000000ffL +#define CRT0C__DISP_START__SHIFT 0x00000000 +#define CRT0D__DISP_START_MASK 0x000000ffL +#define CRT0D__DISP_START__SHIFT 0x00000000 +#define CRT0E__CURSOR_LOC_HI_MASK 0x000000ffL +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x00000000 +#define CRT0F__CURSOR_LOC_LO_MASK 0x000000ffL +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x00000000 +#define CRT10__V_SYNC_START_MASK 0x000000ffL +#define CRT10__V_SYNC_START__SHIFT 0x00000000 +#define CRT11__C0T7_WR_ONLY_MASK 0x00000080L +#define CRT11__C0T7_WR_ONLY__SHIFT 0x00000007 +#define CRT11__SEL5_REFRESH_CYC_MASK 0x00000040L +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x00000006 +#define CRT11__V_INTR_CLR_MASK 0x00000010L +#define CRT11__V_INTR_CLR__SHIFT 0x00000004 +#define CRT11__V_INTR_EN_MASK 0x00000020L +#define CRT11__V_INTR_EN__SHIFT 0x00000005 +#define CRT11__V_SYNC_END_MASK 0x0000000fL +#define CRT11__V_SYNC_END__SHIFT 0x00000000 +#define CRT12__V_DISP_END_MASK 0x000000ffL +#define CRT12__V_DISP_END__SHIFT 0x00000000 +#define CRT13__DISP_PITCH_MASK 0x000000ffL +#define CRT13__DISP_PITCH__SHIFT 0x00000000 +#define CRT14__ADDR_CNT_BY4_MASK 0x00000020L +#define CRT14__ADDR_CNT_BY4__SHIFT 0x00000005 +#define CRT14__DOUBLE_WORD_MASK 0x00000040L +#define CRT14__DOUBLE_WORD__SHIFT 0x00000006 +#define CRT14__UNDRLN_LOC_MASK 0x0000001fL +#define CRT14__UNDRLN_LOC__SHIFT 0x00000000 +#define CRT15__V_BLANK_START_MASK 0x000000ffL +#define CRT15__V_BLANK_START__SHIFT 0x00000000 +#define CRT16__V_BLANK_END_MASK 0x000000ffL +#define CRT16__V_BLANK_END__SHIFT 0x00000000 +#define CRT17__ADDR_CNT_BY2_MASK 0x00000008L +#define CRT17__ADDR_CNT_BY2__SHIFT 0x00000003 +#define CRT17__BYTE_MODE_MASK 0x00000040L +#define CRT17__BYTE_MODE__SHIFT 0x00000006 +#define CRT17__CRTC_SYNC_EN_MASK 0x00000080L +#define CRT17__CRTC_SYNC_EN__SHIFT 0x00000007 +#define CRT17__RA0_AS_A13B_MASK 0x00000001L +#define CRT17__RA0_AS_A13B__SHIFT 0x00000000 +#define CRT17__RA1_AS_A14B_MASK 0x00000002L +#define CRT17__RA1_AS_A14B__SHIFT 0x00000001 +#define CRT17__VCOUNT_BY2_MASK 0x00000004L +#define CRT17__VCOUNT_BY2__SHIFT 0x00000002 +#define CRT17__WRAP_A15TOA0_MASK 0x00000020L +#define CRT17__WRAP_A15TOA0__SHIFT 0x00000005 +#define CRT18__LINE_CMP_MASK 0x000000ffL +#define CRT18__LINE_CMP__SHIFT 0x00000000 +#define CRT1E__GRPH_DEC_RD1_MASK 0x00000002L +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x00000001 +#define CRT1F__GRPH_DEC_RD0_MASK 0x000000ffL +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x00000000 +#define CRT22__GRPH_LATCH_DATA_MASK 0x000000ffL +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x00000000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x00000004 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x00000004 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x00000004 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x00000004 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x00000000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000c0000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x00000011 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x00000010 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x00000012 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0x0000000c +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x00000008 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x00000004 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x00000004 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x00000004 +#define CRTC8_DATA__VCRTC_DATA_MASK 0x000000ffL +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x00000000 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x0000003fL +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x00000000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000ffL +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000010 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003ffL +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x00000000 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000ffc00L +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0x0000000a +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000L +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x00000014 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x00000008 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x00000010 +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x00000000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003ffL +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x00000000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000ffc00L +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0x0000000a +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000L +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x00000014 +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x00000010 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x00000008 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x00000018 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0x0000000d +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x00000014 +#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L +#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x00000000 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L +#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x0000001d +#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L +#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x00000001 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x0000001f +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x00000018 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x00000008 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0x0000000c +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x00000004 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x00000010 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x00000008 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x00000000 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001eL +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x00000001 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x00000000 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00001fffL +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x00000010 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x00000018 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x00000008 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x00000004 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x00000018 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x00000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x00000010 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x00000008 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x0000001c +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00001fffL +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x00000000 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001f0000L +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x00000010 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x00000013 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000ff00L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x00000008 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000ffL +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x00000000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x00000017 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x00000011 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x00000014 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x00000018 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x00000010 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000L +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x00000010 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00001fffL +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x00000000 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x00000010 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003ffL +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x00000000 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000L +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x00000010 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00001fffL +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x00000000 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x00000010 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x00000011 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x00000000 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000L +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x00000010 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00001fffL +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x00000000 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x00000010 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x00000011 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x00000000 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000L +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x00000010 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00001fffL +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x00000000 +#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00001fffL +#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x00000000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x00000000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x00000010 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x00000000 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x00000001 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x00000008 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x00000009 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x00000010 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x00000011 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x0000001e +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x0000001f +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x00000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x00000001 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x00000018 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x0000001a +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x00000019 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x0000001b +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x0000001c +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x0000001d +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x00000004 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x00000005 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x00000000 +#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L +#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x00000000 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00L +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x00000008 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x00000000 +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000ffL +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x00000000 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x00000014 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x00000004 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x00000010 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x00000000 +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00001fffL +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x00000000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003ffL +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x00000000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000ffc00L +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0x0000000a +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000L +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x00000014 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00ffffffL +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00001fffL +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x00000001 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x00000002 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x00000000 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000f0000L +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x00000011 +#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L +#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x00000010 +#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L +#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x00000012 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x00000001 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x00000005 +#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L +#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x00000000 +#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L +#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x00000004 +#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L +#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x00000002 +#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L +#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x00000003 +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00ffffffL +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffffL +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00001fffL +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffffL +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x00000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x00000018 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00001fffL +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x00000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0x0000000f +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x00000010 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x00000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x00000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x00000018 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x00000008 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x00000010 +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffffL +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000ffffL +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003f0000L +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x00000018 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x00000008 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000f000L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0x0000000c +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000fL +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000f0L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x00000004 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000f00L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x00000008 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x0000001f +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x00000018 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x00000014 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x00000009 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0x0000000b +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000e0L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x00000005 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0x0000000a +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x00000008 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x00000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x0000001f +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x00000018 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x00000014 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x00000009 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0x0000000b +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000e0L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x00000005 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0x0000000a +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x00000008 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x00000000 +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x00000000 +#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000L +#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x00000010 +#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00001fffL +#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x00000000 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000L +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x00000010 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00001fffL +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x00000000 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x00000010 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x00000008 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x00000000 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x00000000 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x00000000 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000L +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x00000010 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00001fffL +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x00000000 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x00000000 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000L +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x00000010 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00001fffL +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x00000000 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x00000004 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x00000000 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x00000008 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0x0000000c +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000L +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x00000010 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x00000004 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x00000000 +#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00001fffL +#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x00000000 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x00000008 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x00000004 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0x0000000c +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x00000000 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x00000010 +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00001fffL +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x00000000 +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00001fffL +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x00000000 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x00000008 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x00000000 +#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000ffL +#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x00000000 +#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000ff00L +#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x00000008 +#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00ff0000L +#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x00000010 +#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000ffL +#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x00000000 +#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000ff00L +#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x00000008 +#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00ff0000L +#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x00000010 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x00000004 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L +#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x00000010 +#define CUR_CONTROL__CURSOR_EN_MASK 0x00000001L +#define CUR_CONTROL__CURSOR_EN__SHIFT 0x00000000 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L +#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x00000014 +#define CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L +#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x00000008 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L +#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x00000018 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x003f0000L +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x00000010 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000003fL +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x00000000 +#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000L +#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x00000010 +#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003fffL +#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x00000000 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x00000000 +#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000003fL +#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x00000000 +#define CUR_SIZE__CURSOR_WIDTH_MASK 0x003f0000L +#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x00000010 +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffffL +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x00000000 +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L +#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x00000010 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L +#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x00000000 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x00000001 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x00000018 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x00000018 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x00000018 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x00000018 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x00000018 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x00000018 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000ffL +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x00000000 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000ffL +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x00000000 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000ff00L +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x00000010 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000ff00L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x00000000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x00000000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x00000010 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x00000018 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x00000004 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x00000010 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x00000008 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x00000000 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x00000000 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x00000004 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x00000012 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x00000000 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x00000008 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x00000011 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x00000010 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x00000001 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x00000002 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x00000003 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x00000000 +#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L +#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x00000000 +#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L +#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x00000008 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L +#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x00000010 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L +#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x00000000 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x00000100L +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x00000008 +#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L +#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x00000010 +#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L +#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x00000000 +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003fL +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x00000000 +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003fL +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003ffL +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000ffc00L +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0x0000000a +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000L +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x00000014 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003ffL +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000ffc00L +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0x0000000a +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000L +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x00000014 +#define DAC_DATA__DAC_DATA_MASK 0x0000003fL +#define DAC_DATA__DAC_DATA__SHIFT 0x00000000 +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffffL +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x00000000 +#define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L +#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x00000000 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x00000001 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x00000005 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x00000004 +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000cL +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x00000002 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x00000008 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003ffL +#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x00000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x00000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x01000000L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000018 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x00000008 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MASK__DAC_MASK_MASK 0x000000ffL +#define DAC_MASK__DAC_MASK__SHIFT 0x00000000 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x00000008 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x00000010 +#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L +#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L +#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x00000018 +#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x00000000 +#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L +#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x00000000 +#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L +#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x00000010 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0x000000ffL +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x00000000 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x00000000 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L +#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x00000003 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x00000000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x00000000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x00000010 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x00000008 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0x000000ffL +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x00000000 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x00000008 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003ffL +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03ff0000L +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x00000010 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x0000001e +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001c +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x0000001d +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003ffL +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03ff0000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x00000010 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x0000001f +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x0000001f +#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x00000000 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x00000008 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x00010000L +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x00000010 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x00000001L +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x00000000 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x00000100L +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x00000008 +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x00000002 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x0000001f +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0x0000000a +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x00000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000010 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x00000008 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x00000001 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000018 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x00000009 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000017 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x00000018 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x0000001c +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x0000001e +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x00000010 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0x0000000c +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001d +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x00000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x00000008 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x00000014 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x00000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000fL +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x00000000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000f00L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x00000008 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000f0000L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x00000010 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03ff0000L +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x00000010 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003ffL +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x00000000 +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03ff0000L +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x00000010 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003ffL +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03ff0000L +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x00000010 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003ffL +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00ffffffL +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x00000000 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffffL +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x00000000 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000L +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x00000014 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000ffc00L +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0x0000000a +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003ffL +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000010L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x00000004 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffffL +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x00000000 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x00000004 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x00000005 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x00000000 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x07000000L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x00000018 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x00000001 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x00000014 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x00000006 +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x00000010 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x00000002 +#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000L +#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x0000001c +#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x00000008 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x00000009 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0x0000000a +#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0x0000000b +#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0x0000000c +#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0x0000000d +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x00000000 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffffL +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x00000000 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffffL +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x00000000 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x00000008 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x00000000 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x00000001 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x00000007 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x00000006 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x00000004 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x00000002 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x00000003 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x00000005 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x00000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00010000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0x00000010 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000000ffL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x00000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x01000000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x00000018 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x0000ff00L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x00000008 +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x00001000L +#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0x0000000c +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x04000000L +#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x0000001a +#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x00000001L +#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x00000000 +#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x00010000L +#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 +#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x00000008 +#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x00100000L +#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 +#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x00000009 +#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x00200000L +#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 +#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x00000400L +#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0x0000000a +#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x00400000L +#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 +#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x00000800L +#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0x0000000b +#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x00800000L +#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x00000017 +#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x00001000L +#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0x0000000c +#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x01000000L +#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x00000018 +#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x00002000L +#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0x0000000d +#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x02000000L +#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x00000019 +#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000020L +#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000005 +#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00040000L +#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000012 +#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x00004000L +#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0x0000000e +#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x00080000L +#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 +#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000010L +#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000004 +#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00020000L +#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000011 +#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000002L +#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000001 +#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x00008000L +#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0x0000000f +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x0000001fL +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x00000020L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x00000005 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x00000040L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x00000006 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x00300000L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x00000014 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x00000080L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x00000007 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0x000fff00L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x00000008 +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffffL +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x00000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x00001000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0x0000000c +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x0000000fL +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x000001f0L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x00000004 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x0000001c +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0x000f0000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x00000010 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x01f00000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x00000014 +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffffL +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x00000000 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x00000015 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x00000014 +#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L +#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x00000013 +#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x00000010L +#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x00000004 +#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x00000008L +#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x00000003 +#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x00000010L +#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x00000004 +#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x00000008L +#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x00000003 +#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x00000010L +#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x00000004 +#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x00000008L +#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x00000003 +#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x00000010L +#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x00000004 +#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x00000008L +#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x00000003 +#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x00000010L +#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x00000004 +#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x00000008L +#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x00000003 +#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x00000010L +#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x00000004 +#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x00000008L +#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x00000003 +#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0x0000000fL +#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x00000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x00000300L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x00003000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x0000001d +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x0000001e +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x00030000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x00000010 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0x00c00000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x00000016 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x03000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x00000018 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0x0000c000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x0000001c +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000006 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x00300000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0x000c0000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x00000012 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_EN__SHIFT 0x00000000 +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000f00L +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x00000008 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_EN__SHIFT 0x00000000 +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000f00L +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x00000008 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L +#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x00000014 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x00000010 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x00000008 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x10000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x07000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x10000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x07000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x10000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x07000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x10000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x07000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x0000001e +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x00000017 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x00000017 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x00000004L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x00000002 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x00000004 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x00000005 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x00000040L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x00000006 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000400L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0x0000000a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0x0000000c +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0x0000000d +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x00004000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0x0000000e +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x00040000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x00000012 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00400000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x00000018 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x04000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x0000001a +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x00000017 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x00000000 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x00000008 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x00000010 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x00000018 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x00000008 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x00000010 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x00000018 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x00000003 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000004L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x00000002 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x00000008 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0x0000000b +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00000400L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0x0000000a +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x00000010 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x00000013 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00040000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x00000012 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x00000018 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x0000001b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x04000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x0000001a +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x00000008 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x00000010 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x00000018 +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x00000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x00000008 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x00000010 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x00000018 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x0000001a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x0000001c +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x00000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x00000008 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x00000010 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x00000018 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x0000001a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x0000001c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x00000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x00000040L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x00000006 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x00000008 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000400L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0x0000000a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x00000010 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x00040000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x00000012 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x00000014 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x00000015 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00400000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x00000016 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x00000018 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x04000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x0000001a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x0000001c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x0000001d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x0000001e +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x00000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x00000008 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x00000010 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x00000018 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x0000001a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x0000001c +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x00000002 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x00000004 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x00000005 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x00000006 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x00000001 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0f000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x00000018 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x0000001c +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000f0000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x00000010 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00f00000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x00000014 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x00000001 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00000040L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x00000006 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0x0000000c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x00004000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0x0000000e +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x00000014 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00400000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x00000016 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x00000010 +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x00000018 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x00000040L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x00000006 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x0000001c +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0x0000000c +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x00004000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0x0000000e +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x00000008 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003fL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x00000000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x00000008 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0x0000000b +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001c000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0x0000000e +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000e0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x00000011 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x00000014 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x00000017 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffffL +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x00000004 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x00000008 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0x0000000c +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x00000010 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x00000014 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x00000004 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x00000008 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0x0000000c +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x00000010 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x00000014 +#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000L +#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x0000001c +#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x00000001L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x00000000 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x00010000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x00000010 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x00000100L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x01000000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x00000001L +#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x00000002L +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x00000001 +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000L +#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x0000001c +#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x00000001L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x00000000 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x00010000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x00000010 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x00000100L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x01000000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x00000001L +#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x00000002L +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x00000001 +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000L +#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x0000001c +#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x00000001L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x00000000 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x00010000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x00000010 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x00000100L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x01000000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x00000001L +#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x00000002L +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x00000001 +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000L +#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x0000001c +#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x00000001L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x00000000 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x00010000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x00000010 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x00000100L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x01000000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x00000001L +#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x00000002L +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x00000001 +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000L +#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x0000001c +#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x00000001L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x00000000 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x00010000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x00000010 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x00000100L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x01000000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x00000001L +#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x00000002L +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x00000001 +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000L +#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x0000001c +#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x00000001L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x00000000 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x00010000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x00000010 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x00000100L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x01000000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x00000001L +#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x00000002L +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x00000001 +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x00000008 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0x0000000c +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x00000019 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x00000018 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x00000004 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000cL +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x00000002 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x00000015 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x00000000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x00000014 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x0000001f +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x00000008 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x00000000 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x00000002 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x00000001 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x00000003 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x00000014 +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000ff00L +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x00000000 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x00000008 +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x00ff0000L +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x00000010 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x0000001f +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00f00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x00000014 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x0000001c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000ffffL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x00000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x00000005 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x00000004 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x00000006 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x00000009 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x00000008 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0x0000000a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0x0000000d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0x0000000c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0x0000000e +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x00000011 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x00000010 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x00000012 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x00000015 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x00000014 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x00000016 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x00000019 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x00000018 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x0000001a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x0000001c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x0000001b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x0000001d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x00000001 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x00000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x00000002 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x00000004 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x00000007 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x00000002 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x00000006 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0x0000000c +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0x0000000d +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0x0000000e +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0x0000000f +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x00000012 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x00000000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x00000008 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x00000005 +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x00000008 +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000L +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x0000001b +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001fL +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x00000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x0000000f +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x00000010 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x00000011 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x00000012 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x00000013 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x00000014 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x00000015 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x00000009 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x0000000b +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0x0000000d +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x00000006 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x00000005 +#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x00004000L +#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0x0000000e +#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x00000400L +#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0x0000000a +#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x00001000L +#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0x0000000c +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x00400000L +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x00000016 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x00000017 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x00000008 +#define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0x0000000fL +#define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x00000000 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x00003000L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000040L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000006 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000001 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x0000c000L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000080L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000007 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00030000L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x000c0000L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000200L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000009 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00300000L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000400L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000a +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00c00000L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000800L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000b +#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x00000003L +#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x00000000 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0x0000000cL +#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x00000002 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x00000030L +#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x00000004 +#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0x00c00000L +#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000L +#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x0000001c +#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x00000003L +#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x00000000 +#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0x0000000cL +#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x00000002 +#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x00000030L +#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x00000004 +#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0x000000c0L +#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x00000006 +#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x00000300L +#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0x00000c00L +#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0x0000000a +#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x00003000L +#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0x0c000000L +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x0000001a +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x03000000L +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x00000018 +#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x00030000L +#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0x000c0000L +#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0x0000c000L +#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x00300000L +#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x00040000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x00000012 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x00008000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x00004000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0x0000000e +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x00002000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0x0000000d +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0x0000000f +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x00100000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x00080000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x00000013 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x00010000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x00000010 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x00000014 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x00400000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x00000016 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x00200000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x00000015 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x08000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x04000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x0000001a +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x0000001b +#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x00800000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x00000017 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x00020000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x00000011 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x02000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x00000019 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x01000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x00000018 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x00001000L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0x0000000c +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0x000000c0L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x00000003L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x00000000 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x00000006 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0x00000c00L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x00000030L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x00000004 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0x0000000a +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0x0000000cL +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x00000002 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x00000300L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x00000008 +#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffffL +#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x00000000 +#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffffL +#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x00000000 +#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffffL +#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x00000000 +#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffffL +#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x00000000 +#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffffL +#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x00000000 +#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffffL +#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x00000000 +#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffffL +#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x00000000 +#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffffL +#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x00000000 +#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffffL +#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x00000000 +#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffffL +#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x00000000 +#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffffL +#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x00000000 +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffffL +#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x00000000 +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffffL +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x00000000 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x00000008 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x00000018 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x00000008 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x00000018 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 +#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x00000004 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x00000005 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x00000006 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x00000007 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x00000008 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x00000009 +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00001000L +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0x0000000c +#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L +#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x00000003 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L +#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x00000002 +#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x00000000 +#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L +#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x00000001 +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003ffL +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x00000000 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000ffc00L +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0x0000000a +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000L +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x00000014 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x00000001 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x00000000 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x00000005 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000c0L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x00000006 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x00000004 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0x0000000d +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000c000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0x0000000e +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0x0000000c +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x00000015 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00c00000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x00000016 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x00000014 +#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000fL +#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x00000000 +#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000f00L +#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x00000008 +#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000f0000L +#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x00000010 +#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000ffffL +#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x00000000 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000L +#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x00000010 +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000ffL +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x00000000 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x00000000 +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000ffffL +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x00000000 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x00000000 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x0000001f +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x0000001c +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0x0000000c +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x00000010 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x00000008 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x00000014 +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x00000000 +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x0000001fL +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x00000000 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x00000006 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x00000008 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x00000009 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x00000018 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x00000019 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x0000001a +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x0000001b +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x0000001c +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x0000001d +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x00000007 +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x00000010 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x00000011 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x00000012 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x00000013 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x00000014 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x00000015 +#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x00001000L +#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0x0000000c +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x00000005 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x00000040L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x00000006 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x00000100L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x00000008 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x00000200L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x00000009 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x01000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x00000018 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x02000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x00000019 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x04000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x0000001a +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x08000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x0000001b +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x0000001c +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x0000001d +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x00000080L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x00000007 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x00010000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x00000010 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x00020000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x00000011 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x00040000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x00000012 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x00080000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x00000013 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x00100000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x00000014 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x00200000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x00000015 +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x00001000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0x0000000c +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x00000020L +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x00000005 +#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x00020000L +#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x00000011 +#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x00040000L +#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x00000012 +#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x00080000L +#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 +#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x00000006 +#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x00100000L +#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 +#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x00000007 +#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x00200000L +#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 +#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x00000008 +#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x00400000L +#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 +#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x00000009 +#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x00000400L +#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0x0000000a +#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x00000800L +#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0x0000000b +#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x00001000L +#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0x0000000c +#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x00002000L +#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0x0000000d +#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x00004000L +#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0x0000000e +#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000002L +#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x00000001 +#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x00010000L +#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 +#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0x000000c0L +#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x00000006 +#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x00000300L +#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0x00000c00L +#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0x0000000a +#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x00003000L +#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0x0000c000L +#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x00030000L +#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0x000c0000L +#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x00300000L +#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0x00c00000L +#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x03000000L +#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x00000018 +#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0x0c000000L +#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x0000001a +#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000L +#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x0000001c +#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0x0000000cL +#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x00000002 +#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x00000030L +#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x00000004 +#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x00000003L +#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x00000000 +#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L +#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x00000019 +#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000L +#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x0000001d +#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L +#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x00000000 +#define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x00000002L +#define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x00000001 +#define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x00000003 +#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L +#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x0000001b +#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L +#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x00000010 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L +#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x00000011 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L +#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x00000012 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L +#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x00000013 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L +#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x00000014 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L +#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x00000015 +#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L +#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x00000018 +#define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x00000002 +#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000L +#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x0000001c +#define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x04000000L +#define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x0000001a +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000fL +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x00000000 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x00000004 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x00000000 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x00000008 +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001cL +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x00000002 +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffffL +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x00000000 +#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffffL +#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x00000000 +#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffffL +#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x00000000 +#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffffL +#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x00000000 +#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffffL +#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x00000000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003ffffL +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x00000000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07f00000L +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x00000014 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000L +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x00000010 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x00000004L +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x00000002 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x00000001L +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x00000000 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x00000002L +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x00000001 +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffffL +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x00000000 +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffffL +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x00000000 +#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L +#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x00000000 +#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L +#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x00000001 +#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L +#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x00000002 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x0000001b +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000L +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x0000001c +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x0000f000L +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x0000000c +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00010000L +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x00000010 +#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x00000300L +#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x00000008 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x00000018 +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000c000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0x0000000e +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x00000400L +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0x0000000a +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x00000010 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0x0000000d +#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x00000800L +#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0x0000000b +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000fL +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x00000000 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000000f0L +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x00000004 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00ff0000L +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x00000010 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000ff00L +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x00000008 +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000ffL +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x00000000 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x00000008 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000a +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x00000009 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x00000040L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x00000006 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x00000000 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x00000004 +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0x00000007L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x00000000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x00000070L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x00000004 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x00000080L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0x00000700L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0x00000008 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x00000800L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x0000000b +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x00007000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x0000000c +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x00008000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x0000000f +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0x00070000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x00000010 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x00080000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x00000013 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x00000007L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x00000000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0x00000070L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x00000004 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x00000080L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x00000008 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000 +#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x00400000L +#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x00000016 +#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x00010000L +#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x00000010 +#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x00100000L +#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x00000014 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x0000003fL +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x00000000 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x00000700L +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x00000008 +#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x00200000L +#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x00000015 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000 +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004 +#define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L +#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x00000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x00000013 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0x0000000f +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x00000011 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x00000012 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007f00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x00000008 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007fL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x00000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x00000014 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x00000015 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x00000016 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x00000018 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00003f00L +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x00000008 +#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x0000001c +#define DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x00000010 +#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x00000000 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x00000008 +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003ffL +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x00000000 +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x00000001L +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x00000000 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x00000100L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x00000008 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x00000010L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x00001000L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0x0000000c +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x00000004 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x00000001L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x00000000 +#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00010000L +#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x00000010 +#define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00100000L +#define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x00000014 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x00000000 +#define DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG_FE_CNTL__DIG_START__SHIFT 0x0000000a +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x00000008 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x00000004 +#define DIG_FE_CNTL__DIG_SWAP_MASK 0x00040000L +#define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x00000012 +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x00000018 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x00000008 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x00000000 +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001f0000L +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x00000008 +#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x00000000 +#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x00000001 +#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x00000002 +#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x00000003 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x00000008 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x00000000 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x00000004 +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffffL +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x00000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00ffffffL +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x00000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x00000018 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x00000001 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x00000000 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x00000005 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x00000004 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x00000009 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x00000008 +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0x0000000d +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0x0000000c +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x00000011 +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x00000010 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x00000015 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x00000014 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x00000001 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x00000004 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x00000005 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03ff0000L +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x00000010 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x00000006 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x00000000 +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x00000100L +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x00000008 +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x00000004L +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x00000002 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x0000001e +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x0000001c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x0000001d +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x0000001f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x00000014 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0e000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x00000019 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003fffL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x00000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000f0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x0000001e +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x0000001c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x0000001d +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x00000018 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x00000016 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x00000017 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x00000019 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x00000018 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x00000015 +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x0000001b +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x0000001a +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L +#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x00000000 +#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L +#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x00000010 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0x000000f0L +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x00000004 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x00000001L +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x00000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01ffffffL +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x00000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x00000019 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x08000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x0000001b +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x04000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x0000001a +#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x0000001e +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x0000001d +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x0000001c +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x00000002 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x00000003 +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x00000004 +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x00000001 +#define DMCU_CTRL__RESET_UC_MASK 0x00000001L +#define DMCU_CTRL__RESET_UC__SHIFT 0x00000000 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000L +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x00000016 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000ffffL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x00000000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000f0000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x00000010 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x00000014 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffffL +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x00000000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000ffffL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x00000000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000f0000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x00000010 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x00000014 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffffL +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x00000000 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x00000000 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x00000017 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007f0000L +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x00000010 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000cL +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x00000002 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x00000000 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffffL +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x00000000 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffffL +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x00000000 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00ff0000L +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x00000010 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000ffL +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x00000000 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000ff00L +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x00000002 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x00000002 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x00000000 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x00000000 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x00000001 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x00000001 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x00000012 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000012 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x0000000c +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0000000c +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x00000013 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000013 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x0000000d +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x0000000d +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x00000014 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000014 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x0000000e +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x0000000e +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x00000015 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000015 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0x0000000f +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x0000000f +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x00000016 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000016 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x00000010 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x00000010 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x00000017 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000017 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x00000011 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x00000011 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x00000003 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x00000009 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0x0000000a +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0x0000000a +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0x0000000b +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0x0000000b +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x00000018 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x00000018 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x00000019 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x00000019 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x0000001a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x0000001a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x0000001b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x0000001b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x0000001c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x0000001c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x0000001d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x0000001d +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x00000009 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0x0000000a +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0x0000000b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x00000008 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x00000003 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x00000018 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x00000019 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x0000001a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x0000001b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x0000001c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x0000001d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x00000008 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000003 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x00000018 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x00000019 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001d +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003ffL +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x00000000 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000ffL +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x00000000 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003ffL +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x00000000 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000ffL +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x00000000 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x00000004 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x00000001 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x00000000 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x00000005 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x00000003 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x00000002 +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0x0000ff00L +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x00000008 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x00000000 +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x00000002 +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x00000001 +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x00000008 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x00000000 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x00000010 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x00000003 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x00000000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0x0000000e +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0x0000000f +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x00000009 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x00000002 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0x0000000d +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0x0000000c +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0x0000000b +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0x0000000a +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x00000007 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x00000006 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x00000005 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x00000004 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x00000008 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x00000001 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x0000001c +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000ffffL +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x00000000 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000L +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x00000010 +#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L +#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x00000000 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x0000001d +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000L +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x00000018 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x00000004 +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0000f000L +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0x0000000c +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x00000002 +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x003f0000L +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x00000010 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x00000008 +#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0x0000ffffL +#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x00000000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x00010000L +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x00000010 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0x0ffe0000L +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x00000011 +#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0x0000ffffL +#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x00000000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x00010000L +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x00000010 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0x0ffe0000L +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x00000011 +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffffL +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x00000000 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x00000008 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x00000009 +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x00000000 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x00000001 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x00000002 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x00000003 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x00000004 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x00000005 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003f00L +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x00000008 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00010000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x00000010 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00700000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x00000014 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00020000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x00000011 +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003fL +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x00000000 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x07000000L +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x00000018 +#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L +#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x0000001c +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L +#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x00000004 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L +#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x00000000 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x00000008 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x00000000 +#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffffL +#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x00000000 +#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffffL +#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x00000000 +#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffffL +#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x00000000 +#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffffL +#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x00000000 +#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffffL +#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x00000000 +#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffffL +#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x00000000 +#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffffL +#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x00000000 +#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffffL +#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffffL +#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffffL +#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffffL +#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffffL +#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffffL +#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffffL +#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffffL +#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffffL +#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffffL +#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffffL +#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffffL +#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffffL +#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffffL +#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffffL +#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffffL +#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffffL +#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffffL +#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffffL +#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffffL +#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffffL +#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffffL +#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffffL +#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffffL +#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffffL +#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffffL +#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffffL +#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffffL +#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffffL +#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffffL +#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffffL +#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffffL +#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffffL +#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffffL +#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffffL +#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffffL +#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffffL +#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffffL +#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffffL +#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffffL +#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffffL +#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffffL +#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffffL +#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffffL +#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffffL +#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffffL +#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffffL +#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffffL +#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffffL +#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffffL +#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffffL +#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffffL +#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffffL +#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffffL +#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffffL +#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x00000000 +#define DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x00000000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x00000018 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x00000010 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x00000008 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x00000000 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x00000001 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x00000002 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x00000003 +#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x00000010 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x00000018 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x00000000 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00ff0000L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x00000010 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x00000004 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x00000004 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x00000000 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003fL +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x00000000 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003f00L +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x00000010 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x00000000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000ff00L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x00000008 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00ff0000L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x00000010 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x00000018 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000ffL +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x00000000 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000fff00L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x00000008 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x00000014 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x00000002 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x00000000 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x00000001 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0x0000000c +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x00000008 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x00000004 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x00000000 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x00000000 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x00000008 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x00000004 +#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003ffL +#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x00000000 +#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000ffc00L +#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0x0000000a +#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000L +#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x00000014 +#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003ffL +#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x00000000 +#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000ffc00L +#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0x0000000a +#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000L +#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x00000014 +#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003ffL +#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x00000000 +#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000ffc00L +#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0x0000000a +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x00000000 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffffL +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x00000000 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffffL +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x00000000 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffffL +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x00000000 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffffL +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x00000000 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffffL +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x00000000 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffffL +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x00000000 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffffL +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x00000000 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffffL +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x00000000 +#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffffL +#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x00000000 +#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffffL +#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x00000000 +#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffffL +#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x00000000 +#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffffL +#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000L +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x00000010 +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000ffffL +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000ffffL +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x00000004 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x00000100L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x00000008 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x00003000L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x0000000a +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x00000009 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x00000000 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x00000004 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x00000007 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x00000005 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x00000006 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x0000000b +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x0000000a +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x00000009 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x00000004 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x00000007 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x00000005 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x00000006 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0x0000000b +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0x0000000a +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x00000009 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x00000008 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000ffffL +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x00000000 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x00000011 +#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x00000008 +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x00000004 +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003ffffL +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x00000000 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x00000018 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x0000001c +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x00000008 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000ffL +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x00000000 +#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000f8L +#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x00000003 +#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000ff00L +#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x00000008 +#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00ff0000L +#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x00000010 +#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000L +#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x00000018 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x00000000 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0001fff0L +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x00000004 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000L +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x00000010 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00001fffL +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x00000000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003ffL +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x00000000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x00000010 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x00000000 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x00000004 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x00000008 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000L +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x0000001a +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03ffffffL +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x00000000 +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x00000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003f00L +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x00000008 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000L +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x00000018 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x00000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x00000010 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003f00L +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x00000008 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000L +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x00000018 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x00000000 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x00000010 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003f00L +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x00000008 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000L +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x00000018 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x00000000 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x00000010 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x00000008 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x00000000 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x00000018 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L +#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x00000008 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000003L +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x00000000 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x00000010 +#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00ffffffL +#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x00000000 +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00ffffffL +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x00000000 +#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00ffffffL +#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x00000000 +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00ffffffL +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x00000000 +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x00000000 +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x00000010 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0x0000000c +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x00000004 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x00000008 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x00000018 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x00000014 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x00000015 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x00000016 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x00000017 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x0000001c +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x00000000 +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000fffL +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x00000000 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000ffffL +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x00000000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003fffL +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x00000000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x0000001c +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x0000001d +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x00000018 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x00000014 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x00000010 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000eL +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x00000001 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x00000004 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003f00L +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x00000008 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x00000000 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x00000000 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x00000006 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x00000004 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x00000005 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x00000007 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0x0000000c +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x00000008 +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x00000001 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x00000000 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x00000002 +#define DP_VID_M__DP_VID_M_MASK 0x00ffffffL +#define DP_VID_M__DP_VID_M__SHIFT 0x00000000 +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000fffL +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x00000000 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x00000010 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x00000018 +#define DP_VID_N__DP_VID_N_MASK 0x00ffffffL +#define DP_VID_N__DP_VID_N__SHIFT 0x00000000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x00000014 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x00000008 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x00000000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x00000010 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x00000008 +#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000L +#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x00000018 +#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L +#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x00000000 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x00000012 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x00000012 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x00000014 +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x00000018 +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x0000001c +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x00000012 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x00000000 +#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x03000000L +#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x00000018 +#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000L +#define DVO_CONTROL__DVO_CTL3__SHIFT 0x0000001f +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x00000100L +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x00000008 +#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x00040000L +#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x00000012 +#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x00000001L +#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x00000000 +#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x00010000L +#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x00000010 +#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x00000002L +#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x00000001 +#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x00020000L +#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x00000011 +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x07ffffffL +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x00000000 +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x07ffffffL +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x00000000 +#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x00010000L +#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x00000010 +#define DVO_ENABLE__DVO_ENABLE_MASK 0x00000001L +#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x00000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x00000100L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x00000008 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x00000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x00000100L +#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x00000008 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x00000003L +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x00000000 +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffffL +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x00000000 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x00000007L +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x00000000 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x00070000L +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x00000010 +#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000f000L +#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0x0000000c +#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000f00L +#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x00000008 +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x0000001c +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x0000001d +#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000f0L +#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x00000004 +#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000fL +#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x00000000 +#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000f0L +#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x00000004 +#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L +#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x00000000 +#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L +#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x00000001 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x0fff0000L +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00000fffL +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00000fffL +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x0fff0000L +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000f0000L +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x00000010 +#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L +#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x00000010 +#define FBC_CNTL__FBC_EN_MASK 0x80000000L +#define FBC_CNTL__FBC_EN__SHIFT 0x0000001f +#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L +#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x00000000 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x00000019 +#define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000eL +#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x00000001 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x00000010 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x00000011 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x00000012 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x00000013 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x00000014 +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000fL +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x00000000 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x00000008 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0x0000000a +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x00000009 +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0x0000000b +#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L +#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x00000010 +#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L +#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x000003ffL +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x03ff0000L +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x00000010 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x000003ffL +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x03ff0000L +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x00000010 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x00010000L +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x00000010 +#define FBC_DEBUG0__FBC_DEBUG0_MASK 0x00fe0000L +#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x00000011 +#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000L +#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x00000018 +#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0x000000ffL +#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x00000000 +#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0x0000ff00L +#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x00000008 +#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffffL +#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x00000000 +#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffffL +#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x00000000 +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x0000000b +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000f0L +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x00000004 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x00000008 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x0000000a +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x00000003 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L +#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x00000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x000003ffL +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x00000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x0000001f +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x00020000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x00000011 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x00010000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x00000010 +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffffL +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0x000000ffL +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffffL +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0x000000ffL +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x00000000 +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffffL +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x00000000 +#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffffL +#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x00000000 +#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0x00ffffffL +#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x00000000 +#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0x00ffffffL +#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x00000000 +#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0x00ffffffL +#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x00000000 +#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0x00ffffffL +#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x00000000 +#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0x00ffffffL +#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x00000000 +#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0x00ffffffL +#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x00000000 +#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0x00ffffffL +#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x00000000 +#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0x00ffffffL +#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x00000000 +#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0x00ffffffL +#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x00000000 +#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0x00ffffffL +#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x00000000 +#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0x00ffffffL +#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x00000000 +#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0x00ffffffL +#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x00000000 +#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0x00ffffffL +#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x00000000 +#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0x00ffffffL +#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x00000000 +#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0x00ffffffL +#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x00000000 +#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0x00ffffffL +#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x00000000 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x00000010 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L +#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x00000000 +#define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L +#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x00000008 +#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L +#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0x0000000a +#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000f0L +#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x00000004 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x00000003 +#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L +#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x00000015 +#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L +#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x00000014 +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0x0000000c +#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L +#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0x0000000b +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000L +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x0000001c +#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L +#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x00000002 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001f00L +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x00000008 +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001fL +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x00000000 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x00000007 +#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L +#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffffL +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0c000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x0000001a +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x0000001c +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x0000001e +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001000L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000c +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x00000008 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00100000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x00000014 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x00000010 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x00000015 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x00000019 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x00000018 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000010L +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x00000004 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x00000000 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x00000000 +#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00010000L +#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x00000010 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x00000000 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x00000004 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x00000004 +#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L +#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x00000000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x00000014 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x00000018 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0x0000000c +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x00000100L +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x00000008 +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x00000010 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000ffffL +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x00000000 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000L +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x00000010 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000ffffL +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000L +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000L +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000ffffL +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x00000000 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000L +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000ffffL +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x00000000 +#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffffL +#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x00000000 +#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffffL +#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x00000000 +#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffffL +#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x00000000 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x00000003L +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x00000000 +#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffffL +#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x00000000 +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x00000000 +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x00000000 +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x00000000 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x00000000 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0x0000ffffL +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x00000000 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000L +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x00000010 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0x0000ffffL +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x00000000 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000L +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x00000010 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x00000001L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x00000000 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x00010000L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000010 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x00000700L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x00000008 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0x0000f000L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0x0000000c +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x00000010L +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x00000004 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x00000001L +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x00000000 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffffL +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x00000000 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffffL +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffffL +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000ffffL +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x00000000 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000L +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x00000010 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000ffffL +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x00000000 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000L +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x00000010 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000ffffL +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x00000000 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000L +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x00000010 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000ffffL +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x00000000 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000L +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x00000010 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000ffffL +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x00000000 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000L +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x00000010 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000ffffL +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x00000000 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000L +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x00000010 +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x00000030L +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x00000004 +#define GENENB__BLK_IO_BASE_MASK 0x000000ffL +#define GENENB__BLK_IO_BASE__SHIFT 0x00000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x0000001f +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x00000003 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x00000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x00000002 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x00000001 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000ff00L +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x00000000 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x00000008 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000f0000L +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x00000010 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x0000001f +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x00000001 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x00000000 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x00000002 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x00000004L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x00000002 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x00000002L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x00000001 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x00000001L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x00000000 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x00000040L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x00000006 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x00000020L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x00000005 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x00000010L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x00000004 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007fL +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x00000000 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007f00L +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x00000008 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x00000007 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x00000000 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000L +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x00000018 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000L +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x00000010 +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x00000000 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x00000005 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x00000004 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0x0000000a +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000fL +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x00000000 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x00000009 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x00000006 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x00000009 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000f0000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x00000010 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x00000000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0x0000000c +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x00000008 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0x0000000d +#define GENFC_RD__VSYNC_SEL_R_MASK 0x00000008L +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x00000003 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x00000008L +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x00000001L +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x00000020L +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 +#define GENMO_RD__VGA_CKSEL_MASK 0x0000000cL +#define GENMO_RD__VGA_CKSEL__SHIFT 0x00000002 +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x00000040L +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006 +#define GENMO_RD__VGA_RAM_EN_MASK 0x00000002L +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x00000001 +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x00000007 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x00000001L +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x00000020L +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 +#define GENMO_WT__VGA_CKSEL_MASK 0x0000000cL +#define GENMO_WT__VGA_CKSEL__SHIFT 0x00000002 +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006 +#define GENMO_WT__VGA_RAM_EN_MASK 0x00000002L +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x00000001 +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x00000080L +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x00000007 +#define GENS0__CRT_INTR_MASK 0x00000080L +#define GENS0__CRT_INTR__SHIFT 0x00000007 +#define GENS0__SENSE_SWITCH_MASK 0x00000010L +#define GENS0__SENSE_SWITCH__SHIFT 0x00000004 +#define GENS1__NO_DISPLAY_MASK 0x00000001L +#define GENS1__NO_DISPLAY__SHIFT 0x00000000 +#define GENS1__PIXEL_READ_BACK_MASK 0x00000030L +#define GENS1__PIXEL_READ_BACK__SHIFT 0x00000004 +#define GENS1__VGA_VSTATUS_MASK 0x00000008L +#define GENS1__VGA_VSTATUS__SHIFT 0x00000003 +#define GRA00__GRPH_SET_RESET0_MASK 0x00000001L +#define GRA00__GRPH_SET_RESET0__SHIFT 0x00000000 +#define GRA00__GRPH_SET_RESET1_MASK 0x00000002L +#define GRA00__GRPH_SET_RESET1__SHIFT 0x00000001 +#define GRA00__GRPH_SET_RESET2_MASK 0x00000004L +#define GRA00__GRPH_SET_RESET2__SHIFT 0x00000002 +#define GRA00__GRPH_SET_RESET3_MASK 0x00000008L +#define GRA00__GRPH_SET_RESET3__SHIFT 0x00000003 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x00000001L +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x00000000 +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x00000002L +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x00000001 +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x00000004L +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x00000002 +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x00000008L +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x00000003 +#define GRA02__GRPH_CCOMP_MASK 0x0000000fL +#define GRA02__GRPH_CCOMP__SHIFT 0x00000000 +#define GRA03__GRPH_FN_SEL_MASK 0x00000018L +#define GRA03__GRPH_FN_SEL__SHIFT 0x00000003 +#define GRA03__GRPH_ROTATE_MASK 0x00000007L +#define GRA03__GRPH_ROTATE__SHIFT 0x00000000 +#define GRA04__GRPH_RMAP_MASK 0x00000003L +#define GRA04__GRPH_RMAP__SHIFT 0x00000000 +#define GRA05__CGA_ODDEVEN_MASK 0x00000010L +#define GRA05__CGA_ODDEVEN__SHIFT 0x00000004 +#define GRA05__GRPH_OES_MASK 0x00000020L +#define GRA05__GRPH_OES__SHIFT 0x00000005 +#define GRA05__GRPH_PACK_MASK 0x00000040L +#define GRA05__GRPH_PACK__SHIFT 0x00000006 +#define GRA05__GRPH_READ1_MASK 0x00000008L +#define GRA05__GRPH_READ1__SHIFT 0x00000003 +#define GRA05__GRPH_WRITE_MODE_MASK 0x00000003L +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x00000000 +#define GRA06__GRPH_ADRSEL_MASK 0x0000000cL +#define GRA06__GRPH_ADRSEL__SHIFT 0x00000002 +#define GRA06__GRPH_GRAPHICS_MASK 0x00000001L +#define GRA06__GRPH_GRAPHICS__SHIFT 0x00000000 +#define GRA06__GRPH_ODDEVEN_MASK 0x00000002L +#define GRA06__GRPH_ODDEVEN__SHIFT 0x00000001 +#define GRA07__GRPH_XCARE0_MASK 0x00000001L +#define GRA07__GRPH_XCARE0__SHIFT 0x00000000 +#define GRA07__GRPH_XCARE1_MASK 0x00000002L +#define GRA07__GRPH_XCARE1__SHIFT 0x00000001 +#define GRA07__GRPH_XCARE2_MASK 0x00000004L +#define GRA07__GRPH_XCARE2__SHIFT 0x00000002 +#define GRA07__GRPH_XCARE3_MASK 0x00000008L +#define GRA07__GRPH_XCARE3__SHIFT 0x00000003 +#define GRA08__GRPH_BMSK_MASK 0x000000ffL +#define GRA08__GRPH_BMSK__SHIFT 0x00000000 +#define GRPH8_DATA__GRPH_DATA_MASK 0x000000ffL +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x00000000 +#define GRPH8_IDX__GRPH_IDX_MASK 0x0000000fL +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x00000000 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001ffc0L +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x00000006 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 +#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L +#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x00001800L +#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0x0000000b +#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0x000000c0L +#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x00000006 +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x0000001f +#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L +#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x00000000 +#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L +#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012 +#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL +#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L +#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x00000018 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 +#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0x0000e000L +#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0x0000000d +#define GRPH_CONTROL__GRPH_Z_MASK 0x00000030L +#define GRPH_CONTROL__GRPH_Z__SHIFT 0x00000004 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x00000000 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x00000004 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x00000009 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x00000008 +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000fL +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x00000000 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 +#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L +#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x00000000 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x00000000 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x00000000 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x00000008 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x00000008 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x00000000 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x00000010 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x00000008 +#define GRPH_PITCH__GRPH_PITCH_MASK 0x00007fffL +#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x00000000 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x00000000 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003fffL +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x00000000 +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003fffL +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x00000000 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000c00L +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0x0000000a +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x00000008 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x00000000 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000c0L +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x00000006 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x00000004 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x00000000 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x00000001 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x0000001c +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x00000002 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x00000003 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x00000100L +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x00000008 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L +#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x00000010 +#define GRPH_X_END__GRPH_X_END_MASK 0x00007fffL +#define GRPH_X_END__GRPH_X_END__SHIFT 0x00000000 +#define GRPH_X_START__GRPH_X_START_MASK 0x00003fffL +#define GRPH_X_START__GRPH_X_START__SHIFT 0x00000000 +#define GRPH_Y_END__GRPH_Y_END_MASK 0x00007fffL +#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x00000000 +#define GRPH_Y_START__GRPH_Y_START_MASK 0x00003fffL +#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x00000000 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000L +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0x0000000c +#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000fffffL +#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x00000000 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000L +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0x0000000c +#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000fffffL +#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x00000000 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000L +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0x0000000c +#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000fffffL +#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x00000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x0000001f +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0x0000000c +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x00000001 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x00000010 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x00000004 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x00000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x00000008 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000L +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0x0000000c +#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000fffffL +#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x00000000 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x00000004 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001f0000L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x00000010 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x00000008 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x0000001c +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x00000018 +#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x00000008 +#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x00000009 +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x00000000 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x00000004 +#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x00000004 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x00000002 +#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x00000000 +#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000f00L +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0x0000000c +#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x00000008 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x00000001 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003f0000L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x00000010 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x00000000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x00000005 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x00000018 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x00000004 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x00000001 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003f0000L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x00000010 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x00000000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x00000005 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x00000018 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x00000004 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x00000005 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x00000004 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x00000001 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x00000000 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x00000009 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x00000008 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003f00L +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x00000008 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003fL +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x00000000 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003f0000L +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x00000010 +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x00000000 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x00000010 +#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x0000001b +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x00000014 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x00000005 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x00000004 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x00000009 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003f0000L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x00000010 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x00000008 +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x00000000 +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffffL +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x00000000 +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffffL +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x00000000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000ffffL +#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x00000000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000L +#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x00000010 +#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000ffffL +#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x00000000 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000L +#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x00000010 +#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000ffffL +#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x00000000 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000L +#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x00000010 +#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000ffffL +#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x00000000 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000L +#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x00000010 +#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000ffffL +#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x00000000 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000L +#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x00000010 +#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000ffffL +#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x00000000 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000L +#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x00000010 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x00000000 +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x00000030L +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x00000004 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000003L +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000 +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004 +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c +#define KEY_CONTROL__KEY_MODE_MASK 0x00000006L +#define KEY_CONTROL__KEY_MODE__SHIFT 0x00000001 +#define KEY_CONTROL__KEY_SELECT_MASK 0x00000001L +#define KEY_CONTROL__KEY_SELECT__SHIFT 0x00000000 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000L +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000ffffL +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x00000000 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000L +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000ffffL +#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x00000000 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000L +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000ffffL +#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x00000000 +#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000L +#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000ffffL +#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x00000000 +#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffffL +#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x00000000 +#define LB_DEBUG__LB_DEBUG_MASK 0xffffffffL +#define LB_DEBUG__LB_DEBUG__SHIFT 0x00000000 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x00000000 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x00000004 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x00000000 +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffffL +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x00000001L +#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x00000000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x00000003 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x00000008 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000e0L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x00000005 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0x0000000b +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0x0000000c +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0fff0000L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x00000010 +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x00000001L +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x00000000 +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x00000010L +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x00000004 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x00000100L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x00000008 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x00000400L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0x0000000a +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x00000200L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x00000009 +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x00007000L +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0x0000000c +#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x00040000L +#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x00000012 +#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x00010000L +#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x00000010 +#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x00020000L +#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x00000011 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x00000019 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x0000001a +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x00000012 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x00000001 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x00000004 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x00000009 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0x0000000a +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00ff0000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000ffL +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000ff00L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00ff0000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000ffL +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000ff00L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000fffL +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x00000003 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x00000001 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x00000004 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000f00L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x00000002 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x00000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x00000008 +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x00000000 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x00000010 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x00000000 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x00000010L +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x00000004 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x00000001L +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x00000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x00100000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x00000014 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x00010000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x00000010 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x0000001c +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x01000000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x00000018 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x00001000L +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0x0000000c +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x00000100L +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x00000008 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000004 +#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00ff0000L +#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x00000010 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000L +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x00000018 +#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x00000003L +#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x00000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x0000001e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x0000001f +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0x0000f000L +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0x0000000c +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000008 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x00000001L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x00000000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x00000030L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x00000004 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x00070000L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x00000010 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0x00007f00L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x00000008 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x00180000L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x00000013 +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffffL +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define MCIF_VMID__MCIF_WR_VMID_MASK 0x0000000fL +#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x00000000 +#define MCIF_VMID__VIP_WR_VMID_MASK 0x000000f0L +#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x00000004 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000000ffL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000000 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0x0000ff00L +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000008 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007fL +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x00000000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x00000011 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007f00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x00000008 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x00000010 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001ffffL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x00000000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000fL +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x00000000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0x0000000c +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x00000008 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x00000004 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x00000000 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000L +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x00000014 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0x000ffc00L +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0x0000000a +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x000003ffL +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x00000000 +#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000L +#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x0000001c +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x00000400L +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0x0000000a +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x00010000L +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x00000010 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x01000000L +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x00000018 +#define MVP_CONTROL1__MVP_EN_MASK 0x00000001L +#define MVP_CONTROL1__MVP_EN__SHIFT 0x00000000 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x00300000L +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000014 +#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x00000070L +#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x00000004 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x00000200L +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x00000009 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x00000100L +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x00000008 +#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x00001000L +#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0x0000000c +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000L +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x0000001e +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000L +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x0000001f +#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x00010000L +#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x00000010 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x00100000L +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x00000014 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x00000100L +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x00000008 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x00001000L +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0x0000000c +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x00000001L +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x00000000 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x00000010L +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x00000004 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000L +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x0000001c +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x01000000L +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x00000018 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x00000010L +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x00000004 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x00000100L +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x00000008 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x00100000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x00000014 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x0000001c +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x00001000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0x0000000c +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x00010000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x00000010 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x00000001L +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x00000000 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x01000000L +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x00000018 +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0x000000ffL +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x00000000 +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000L +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x0000001d +#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000L +#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x0000001c +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0x0000ff00L +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x00000008 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0x00ff0000L +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x00000010 +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000L +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x0000001e +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0x0000ffffL +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x00000000 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000L +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x00000010 +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0x0000ffffL +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x00000000 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x00000001L +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x00000000 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x01fffffeL +#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x00000001 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x00000001L +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x00000000 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x01fffffeL +#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x00000001 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x04000000L +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000001a +#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x02000000L +#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x00000019 +#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000L +#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x0000001b +#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x00100000L +#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x00000014 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x00080000L +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x00000013 +#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x00000007L +#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x00000000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x00020000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x00000011 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x00010000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x00000010 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x00040000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x00000012 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x00008000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000000f +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x00004000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0x0000000e +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x00000800L +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0x0000000b +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x00001000L +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0x0000000c +#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x00000400L +#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0x0000000a +#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x00000200L +#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x00000009 +#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x00002000L +#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0x0000000d +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x00000038L +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x00000003 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x000001c0L +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x00000006 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0L +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x00000004 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x00000001L +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x00000000 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x00000008L +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x00000003 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x00000004L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x00000002 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x00000002L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x00000001 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0x00000ff0L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x00000004 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x00001000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0x0000000c +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x00000001L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x00002000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0x0000000d +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0x00ff0000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x00000010 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x00000018 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x00000002L +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x00000001 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffcL +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x00000002 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x00000001L +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 +#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00L +#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x00000008 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x00000020L +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x00000005 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x00000010L +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x00000004 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x00000080L +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x00000007 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x00000040L +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x00000006 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x00000002L +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x00000001 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x00000008L +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x00000003 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x00000001L +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x00000000 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x00000004L +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x00000002 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0x00ff0000L +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x00000010 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0x0000ff00L +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x00000008 +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0x000000ffL +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x00000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000L +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x0000001f +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000L +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x0000001e +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0x000000ffL +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x00000000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x00010000L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x00000010 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x00000100L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x00001000L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0x0000000c +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x00000008 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x0000001c +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x00100000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x01000000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x00000018 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x00000014 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x0000001e +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007fff00L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x00000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x00000008 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x00000018 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x00000001L +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x00000000 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00L +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x00000008 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x00000010L +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x00000004 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000L +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x0000001f +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000L +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x00000010 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x00001fffL +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x00000000 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x00001fffL +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000L +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x0000001f +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x00000000 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000L +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x00000010 +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x00001fffL +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000ffffL +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x00000000 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000L +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x00000010 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000ffffL +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x00000000 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000L +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x00000010 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000ffffL +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x00000000 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000L +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x00000010 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000ffffL +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x00000000 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000L +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x00000010 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000ffffL +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x00000000 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000L +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x00000010 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000ffffL +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x00000000 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000L +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x00000010 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x00000000 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x00000070L +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x00000004 +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000fL +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x00000000 +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 +#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0x00f00000L +#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x00000014 +#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x00001800L +#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0x0000000b +#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0x000000c0L +#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x00000006 +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x01000000L +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x00000018 +#define OVL_CONTROL1__OVL_DEPTH_MASK 0x00000003L +#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x00000000 +#define OVL_CONTROL1__OVL_FORMAT_MASK 0x00000700L +#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x00000008 +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0x000c0000L +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x00000012 +#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0x0000000cL +#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x00000002 +#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000L +#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x00000019 +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 +#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0x0000e000L +#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0x0000000d +#define OVL_CONTROL1__OVL_Z_MASK 0x00000030L +#define OVL_CONTROL1__OVL_Z__SHIFT 0x00000004 +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x00000001L +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x00000000 +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x00000001L +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x00000000 +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x00000070L +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x00000004 +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0x0000000fL +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x00000000 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x00000200L +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x00000009 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x00000100L +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x00000008 +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 +#define OVL_ENABLE__OVL_ENABLE_MASK 0x00000001L +#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x00000000 +#define OVL_ENABLE__OVLSCL_EN_MASK 0x00000100L +#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x00000008 +#define OVL_END__OVL_X_END_MASK 0x7fff0000L +#define OVL_END__OVL_X_END__SHIFT 0x00000010 +#define OVL_END__OVL_Y_END_MASK 0x00007fffL +#define OVL_END__OVL_Y_END__SHIFT 0x00000000 +#define OVL_PITCH__OVL_PITCH_MASK 0x00007fffL +#define OVL_PITCH__OVL_PITCH__SHIFT 0x00000000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x000003ffL +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x00000000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0x000ffc00L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0x0000000a +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x00000014 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x0000001f +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x00000001L +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define OVL_START__OVL_X_START_MASK 0x3fff0000L +#define OVL_START__OVL_X_START__SHIFT 0x00000010 +#define OVL_START__OVL_Y_START_MASK 0x00003fffL +#define OVL_START__OVL_Y_START__SHIFT 0x00000000 +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x00010000L +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x00020000L +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x00000001L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x00000300L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x00000001L +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00L +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x00000008 +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x00003fffL +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x00000000 +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x00003fffL +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x00000000 +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0x00000c00L +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0x0000000a +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x00000300L +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x00000008 +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x00000003L +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x00000000 +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0x000000c0L +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x00000006 +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x00000030L +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x00000004 +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x00010000L +#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x00000010 +#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x00000001L +#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x00000000 +#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x00000002L +#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x00000001 +#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00010000L +#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x00000010 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L +#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0x0000000c +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x0000000e +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x00000000 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x00000000 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x00000000 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x00000000 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x00000000 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x00000000 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x00000004 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x00000000 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x00000004 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x00000000 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x00000004 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x00000000 +#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x0000001fL +#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x00000000 +#define PLL_ANALOG__PLL_CP_MASK 0x00000f00L +#define PLL_ANALOG__PLL_CP__SHIFT 0x00000008 +#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000L +#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x00000018 +#define PLL_ANALOG__PLL_LF_MODE_MASK 0x001ff000L +#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0x0000000c +#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x00000060L +#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x00000080L +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x00000007 +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x00002000L +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0x0000000d +#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x00000004L +#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x00000002 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x00000400L +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0x0000000a +#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x00100000L +#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x00000014 +#define PLL_CNTL__PLL_CALREF_MASK 0x00000300L +#define PLL_CNTL__PLL_CALREF__SHIFT 0x00000008 +#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000L +#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x0000001a +#define PLL_CNTL__PLL_LOCKED_MASK 0x00200000L +#define PLL_CNTL__PLL_LOCKED__SHIFT 0x00000015 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x00080000L +#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x00000013 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x00000040L +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x00000006 +#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x00000008L +#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x00000003 +#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x00000002L +#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x00000001 +#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x00001800L +#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0x0000000b +#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x00070000L +#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x00000010 +#define PLL_CNTL__PLL_RESET_MASK 0x00000001L +#define PLL_CNTL__PLL_RESET__SHIFT 0x00000000 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x03000000L +#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x00000018 +#define PLL_CNTL__PLL_VCOREF_MASK 0x00000030L +#define PLL_CNTL__PLL_VCOREF__SHIFT 0x00000004 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x00000f00L +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x00000008 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0x000000f0L +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x00000004 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x00000001L +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x00000000 +#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x000001ffL +#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x00000000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x00000018 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x00010000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x00000010 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x000001ffL +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x00000000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x00400000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x00000016 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x00060000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x00000011 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x00100000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x00000014 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x00200000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x00000015 +#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0x0000ffffL +#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x00000000 +#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x00040000L +#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x00000012 +#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x00030000L +#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x00000010 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x00080000L +#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x00000013 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define PLL_FB_DIV__PLL_FB_DIV_MASK 0x0fff0000L +#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x00000010 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0x000f0000L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x00000100L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x00000008 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x00001000L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0x0000000c +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x00000010 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x00000002L +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x00000001 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x00000001L +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x00000000 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x00000008L +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x00000003 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x00000004L +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x00000002 +#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x00000010L +#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x00000004 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x00000080L +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x00000007 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x00008000L +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0x0000000f +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0x0000f000L +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0x0000000c +#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x000003ffL +#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x00000000 +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0x0000ffffL +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x00000000 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0x000000ffL +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x00000000 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0x00000f00L +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x00000008 +#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x00001000L +#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0x0000000c +#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x00002000L +#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0x0000000d +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000L +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x00000010 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x00000070L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x00000004 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x00000001L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x00000000 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x00000002L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x00000001 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x00000008L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x00000003 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x00000004L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x00000002 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x00010000L +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x00000010 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x00000001L +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x00000000 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x00000100L +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x00000008 +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x00000001L +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x00000000 +#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x04000000L +#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x0000001a +#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000L +#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x0000001c +#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0x000fffffL +#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x00000000 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x00000003 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x00000004 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x00000002 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x00000001 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x00000000 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x00000010L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x00000004 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x00000002L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x00000001 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x00000008L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x00000003 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x00000001L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x00000000 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x00000004L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x00000002 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x00000010 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x00000010 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x00000010 +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000ffffL +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x00000000 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000L +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x00000010 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000ffffL +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003ffffL +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07f00000L +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x00000000 +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000ffffL +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x00000000 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000L +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x00000010 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000ffffL +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003ffffL +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07f00000L +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x00000000 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x00000000 +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x00000070L +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x00000004 +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007ffffL +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x00000000 +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001ffL +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x00000000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x00000008 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x00000000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x00000010 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0x0000000c +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x00000010 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000f00L +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x00000008 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000fL +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x00000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003fffL +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x00000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x00000010 +#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xffffffffL +#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x00000000 +#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffffL +#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x00000000 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x00000004 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x00000000 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0x0000000c +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x00000008 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x00000000 +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03ffffffL +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00L +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fL +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0fffff80L +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x00000007 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x00000004 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001fffffL +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003fffL +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000L +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x00000010 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffffL +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L +#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x00000010 +#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000 +#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L +#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x00000008 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x0000ffffL +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x00070000L +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000010 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x0000ffffL +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x00070000L +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000010 +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03ffffffL +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000 +#define SEQ00__SEQ_RST0B_MASK 0x00000001L +#define SEQ00__SEQ_RST0B__SHIFT 0x00000000 +#define SEQ00__SEQ_RST1B_MASK 0x00000002L +#define SEQ00__SEQ_RST1B__SHIFT 0x00000001 +#define SEQ01__SEQ_DOT8_MASK 0x00000001L +#define SEQ01__SEQ_DOT8__SHIFT 0x00000000 +#define SEQ01__SEQ_MAXBW_MASK 0x00000020L +#define SEQ01__SEQ_MAXBW__SHIFT 0x00000005 +#define SEQ01__SEQ_PCLKBY2_MASK 0x00000008L +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x00000003 +#define SEQ01__SEQ_SHIFT2_MASK 0x00000004L +#define SEQ01__SEQ_SHIFT2__SHIFT 0x00000002 +#define SEQ01__SEQ_SHIFT4_MASK 0x00000010L +#define SEQ01__SEQ_SHIFT4__SHIFT 0x00000004 +#define SEQ02__SEQ_MAP0_EN_MASK 0x00000001L +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x00000000 +#define SEQ02__SEQ_MAP1_EN_MASK 0x00000002L +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x00000001 +#define SEQ02__SEQ_MAP2_EN_MASK 0x00000004L +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x00000002 +#define SEQ02__SEQ_MAP3_EN_MASK 0x00000008L +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x00000003 +#define SEQ03__SEQ_FONT_A0_MASK 0x00000020L +#define SEQ03__SEQ_FONT_A0__SHIFT 0x00000005 +#define SEQ03__SEQ_FONT_A1_MASK 0x00000004L +#define SEQ03__SEQ_FONT_A1__SHIFT 0x00000002 +#define SEQ03__SEQ_FONT_A2_MASK 0x00000008L +#define SEQ03__SEQ_FONT_A2__SHIFT 0x00000003 +#define SEQ03__SEQ_FONT_B0_MASK 0x00000010L +#define SEQ03__SEQ_FONT_B0__SHIFT 0x00000004 +#define SEQ03__SEQ_FONT_B1_MASK 0x00000001L +#define SEQ03__SEQ_FONT_B1__SHIFT 0x00000000 +#define SEQ03__SEQ_FONT_B2_MASK 0x00000002L +#define SEQ03__SEQ_FONT_B2__SHIFT 0x00000001 +#define SEQ04__SEQ_256K_MASK 0x00000002L +#define SEQ04__SEQ_256K__SHIFT 0x00000001 +#define SEQ04__SEQ_CHAIN_MASK 0x00000008L +#define SEQ04__SEQ_CHAIN__SHIFT 0x00000003 +#define SEQ04__SEQ_ODDEVEN_MASK 0x00000004L +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x00000002 +#define SEQ8_DATA__SEQ_DATA_MASK 0x000000ffL +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x00000000 +#define SEQ8_IDX__SEQ_IDX_MASK 0x00000007L +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x00000000 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x00000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x00000008 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x00000008 +#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L +#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 +#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L +#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 +#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x00000000 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x00000008 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x00000000 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x00000000 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x00000001 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x00000002 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x00000003 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x0000001f +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x00000004 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x00000007 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x00000008 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000fL +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x00000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0x0000000b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0x0000000c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0x0000000a +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x00000014 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x00000017 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x00000018 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000f0000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x00000010 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x0000001b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x0000001c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x0000001a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x00000004 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x00000007 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x00000008 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000fL +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x00000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0x0000000b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0x0000000c +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0x0000000a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x00000014 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x00000017 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x00000018 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000f0000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x00000010 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x0000001b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x0000001c +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x0000001a +#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x00000000 +#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x00000008 +#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x00000010 +#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x00000018 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x00000000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x00000018 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x00000008 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000f0000L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x00000010 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x00000004 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x02000000L +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x00000019 +#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x01000000L +#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x00000018 +#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x00000001L +#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x00000000 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x00000200L +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x00000009 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x00000100L +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x00000008 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x00020000L +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x00000011 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x00010000L +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x00000010 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003ffL +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03ff0000L +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x00000010 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003ffL +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03ff0000L +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x00000010 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x00010000L +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x00000010 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0x000e0000L +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x007fffffL +#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x001f0000L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x00000010 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x00000002L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x00000001 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x01000000L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x00000018 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0x00000f00L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x00000008 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x00000001L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x00000000 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x00010000L +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x00000010 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0x000e0000L +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x007fffffL +#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x00000000 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x00000008 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x00000010 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x00000018 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x00000040L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x00000006 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x00000030L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x00000004 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x00000001L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x00000000 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x00010000L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x00000010 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x00001000L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0x0000000c +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x00000100L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x00000008 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x00010000L +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x00000010 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0x000e0000L +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x007fffffL +#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffffL +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x00000010 +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0x0000000c +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0x0000000d +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0x0000000e +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0x0000000f +#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x00000014 +#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x00030000L +#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x00000010 +#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x00000008 +#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x00000000 +#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0x00ff0000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x00000010 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x00000008L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x00000003 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0x000000f0L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x00000001L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x00000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x00000004L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x00000002 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x00007f00L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x00000008 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x00000002L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x00000001 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x02000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x00000019 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x01000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x00000018 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x04000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x0000001a +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x0000001c +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x00002000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0x0000000d +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0x0000000cL +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x00000002 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x00001000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0x0000000c +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x00000010L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x00000020L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x00000005 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x00000040L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x00000006 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x00000800L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0x0000000b +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x00100000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x00000014 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x0000001d +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x00000003L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x00000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x00000700L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x00000008 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x00000018 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x00080000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000013 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x00010000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x00000010 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0x0000fffcL +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x00000002 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0x0fff0000L +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x00000010 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x00001000L +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0x0000000c +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x00002000L +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0x0000000d +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0x00000fffL +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x00000000 +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x03ffffffL +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x00000000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0x000f0000L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x00000010 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0x00000f00L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x00000008 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0x0000f000L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0x0000000c +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x00000001L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x00000000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x00000004L +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x00000002 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x00000002L +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x00000001 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x01f00000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x00000014 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x00008000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0x0000000f +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x00010000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x00000010 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x0000001d +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x0000001c +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0x0e000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x00000019 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x0000001fL +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x00000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x00020000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x00000011 +#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000001L +#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x00000000 +#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000002L +#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x00000001 +#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000004L +#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x00000002 +#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000008L +#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x00000003 +#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000010L +#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x00000004 +#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000020L +#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x00000005 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x00000007L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x00000070L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x00000700L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x00007000L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x00070000L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x00300000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0x00c00000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x00000016 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x03000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0x0c000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x0000001a +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x0000001c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x00000003L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x00000030L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x00000300L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x00003000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x00030000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x00100000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x00600000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x00000015 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x01800000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x00000017 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x06000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x00000019 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x0000001b +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x0000001d +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000L +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x0000001f +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x00100000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x00200000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x00000015 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x00400000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x00000016 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x00800000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x00000017 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0x000000f0L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0x00000f00L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x00000003L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0x0000000cL +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x00000002 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x00007000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x00070000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000L +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x0000001fL +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x000003e0L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x00000005 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x07000000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x0000001c +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x0001f000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011 +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x00000008 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x0000001fL +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x00000000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0x00000f00L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x00000008 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x0000001fL +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x00000000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0x00000f00L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x00000008 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x00000014 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x00000018 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x00000010 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x00000008 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x00000000 +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffffL +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x00000000 +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0x000000ffL +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x00000000 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01ffffffL +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x00000000 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01ffffffL +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x00000000 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x00000004 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x00000000 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x00000008 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x00000010 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x00000018 +#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffffL +#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x00000000 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x00000010 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x00000000 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x00000018 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x00000008 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x00000002 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x00000000 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x00000003 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x00000001 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x00000000 +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x0000001d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x0000001f +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x00000018 +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x00000010 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x0000001a +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x00000008 +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x08000000L +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x0000001b +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x00000003 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000e0L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x00000005 +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000L +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x0000001c +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000ffL +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x00000000 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffffL +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x00000000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003ffL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x00000000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03ff0000L +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x00000010 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003ffL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x00000000 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03ff0000L +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x00000010 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x00000008 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x00000000 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x00000004 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x00000010 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x00000005 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001fL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x00000000 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x00000007 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x00000008 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x00000018 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x00000019 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x00000010 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000000 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000008 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000001 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000009 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000002 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000a +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000003 +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000b +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000004 +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000c +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000005 +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000d +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x00000010 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00fc0000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x00000012 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x00000011 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x00000000 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x00000008 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x00000010 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x00000000 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x00000018 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x00000008 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x00000002 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x00000000 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x00000003 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x00000001 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x00000008 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x00000000 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x00000000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x00000018 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x00000010 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x00000008 +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffffL +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003fffL +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x00000000 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000L +#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x00000010 +#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000L +#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x00000010 +#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003fffL +#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x00000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x00008000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0x0000000f +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x00080000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x00000013 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x00040000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x00000012 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x00100000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x00000014 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x00010000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x00000010 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x00000100L +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x00000008 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0x0000000fL +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x00000000 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x00000400L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0x0000000a +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x00000200L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x00000009 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x00000100L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x00000008 +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x00004000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0x0000000e +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x00002000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0x0000000d +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x00001000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0x0000000c +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x00040000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x00000012 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x00020000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x00000011 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x00010000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x00000010 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0x0000000fL +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x00000000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0x00000c00L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0x0000000a +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x00000300L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x00000008 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x00003000L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0x0000000c +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x00300000L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x00000014 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x00000070L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x00000004 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x00c00000L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x00000016 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x0000001b +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x00000007L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x00010000L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x00000010 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x00000300L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x00000008 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0x0000f000L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0x0000000c +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x00010000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000010 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x0000001e +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x01000000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000018 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x00040000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x00000012 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x00010000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x00000010 +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x00000200L +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0x00000009 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x00100000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x00000014 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x00003fffL +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x00000000 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000L +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x00000010 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffffL +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x00000000 +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x00003fffL +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x00010000L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x00000010 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x00000300L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x00000008 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0x0000f000L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x00010000L +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x00000010 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x00003000L +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x000003ffL +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x00000001L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0x0000f000L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0x000000f0L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x00000004 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x00000010 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x00010000L +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x00000010 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x00003000L +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0x0000000c +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x000003ffL +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x00000000 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000L +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x00000010 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x00003fffL +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffffL +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffffL +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x00000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x00003fffL +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x00000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0x3fff0000L +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x00000010 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x00000007L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x00000000 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0x0000000f +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x00000100L +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0x00000008 +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x00010000L +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x00000010 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x00000200L +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x00000009 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x00080000L +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x00000013 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x00100000L +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x00000014 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x00000001L +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x00000000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x00010000L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x00000010 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x00000300L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x00000008 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0x0000f000L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0x0000000c +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000L +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x0000001f +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x00030000L +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x00000010 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0x0000ffffL +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x00000000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x00010000L +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x00000010 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x00003000L +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0x0000000c +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x000003ffL +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0x000fffffL +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000L +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x00000014 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000L +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x00000010 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0x0000ffffL +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0x0000ffffL +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x00000000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x00000001L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x00000000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0x0000f000L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0x000000f0L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x00000004 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x00000010 +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffffL +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x00003fffL +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x00000000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000L +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x00000010 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000L +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x00000010 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x000001ffL +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x00000000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0x0000f000L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x00000001L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x00000000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffffL +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +#endif |