diff options
Diffstat (limited to 'drivers/gpu/drm/amd')
176 files changed, 60896 insertions, 6494 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 248a05d02917..41bd2bf28f4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -24,7 +24,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ - amdgpu_gtt_mgr.o + amdgpu_gtt_mgr.o amdgpu_vram_mgr.o # add asic specific block amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/ObjectID.h b/drivers/gpu/drm/amd/amdgpu/ObjectID.h index b8d66670bb17..06192698bd96 100644 --- a/drivers/gpu/drm/amd/amdgpu/ObjectID.h +++ b/drivers/gpu/drm/amd/amdgpu/ObjectID.h @@ -90,7 +90,6 @@ #define ENCODER_OBJECT_ID_INTERNAL_VCE 0x24 #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 0x25 #define ENCODER_OBJECT_ID_INTERNAL_AMCLK 0x27 -#define ENCODER_OBJECT_ID_VIRTUAL 0x28 #define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO 0xFF @@ -120,7 +119,6 @@ #define CONNECTOR_OBJECT_ID_eDP 0x14 #define CONNECTOR_OBJECT_ID_MXM 0x15 #define CONNECTOR_OBJECT_ID_LVDS_eDP 0x16 -#define CONNECTOR_OBJECT_ID_VIRTUAL 0x17 /* deleted */ @@ -149,7 +147,6 @@ #define GRAPH_OBJECT_ENUM_ID5 0x05 #define GRAPH_OBJECT_ENUM_ID6 0x06 #define GRAPH_OBJECT_ENUM_ID7 0x07 -#define GRAPH_OBJECT_ENUM_VIRTUAL 0x08 /****************************************************/ /* Graphics Object ID Bit definition */ @@ -411,10 +408,6 @@ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ENCODER_OBJECT_ID_HDMI_ANX9805 << OBJECT_ID_SHIFT) -#define ENCODER_VIRTUAL_ENUM_VIRTUAL ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ - GRAPH_OBJECT_ENUM_VIRTUAL << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_VIRTUAL << OBJECT_ID_SHIFT) - /****************************************************/ /* Connector Object ID definition - Shared with BIOS */ /****************************************************/ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 039b57e4644c..63208e5c1588 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -34,7 +34,7 @@ #include <linux/kref.h> #include <linux/interval_tree.h> #include <linux/hashtable.h> -#include <linux/fence.h> +#include <linux/dma-fence.h> #include <ttm/ttm_bo_api.h> #include <ttm/ttm_bo_driver.h> @@ -53,7 +53,11 @@ #include "amdgpu_ucode.h" #include "amdgpu_ttm.h" #include "amdgpu_gds.h" +#include "amdgpu_sync.h" +#include "amdgpu_ring.h" +#include "amdgpu_vm.h" #include "amd_powerplay.h" +#include "amdgpu_dpm.h" #include "amdgpu_acp.h" #include "gpu_scheduler.h" @@ -88,15 +92,16 @@ extern int amdgpu_vm_debug; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; extern int amdgpu_powerplay; -extern int amdgpu_powercontainment; +extern int amdgpu_no_evict; +extern int amdgpu_direct_gma_size; extern unsigned amdgpu_pcie_gen_cap; extern unsigned amdgpu_pcie_lane_cap; extern unsigned amdgpu_cg_mask; extern unsigned amdgpu_pg_mask; extern char *amdgpu_disable_cu; -extern int amdgpu_sclk_deep_sleep_en; extern char *amdgpu_virtual_display; extern unsigned amdgpu_pp_feature_mask; +extern int amdgpu_vram_page_split; #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ @@ -107,12 +112,6 @@ extern unsigned amdgpu_pp_feature_mask; #define AMDGPUFB_CONN_LIMIT 4 #define AMDGPU_BIOS_NUM_SCRATCH 8 -/* max number of rings */ -#define AMDGPU_MAX_RINGS 16 -#define AMDGPU_MAX_GFX_RINGS 1 -#define AMDGPU_MAX_COMPUTE_RINGS 8 -#define AMDGPU_MAX_VCE_RINGS 3 - /* max number of IP instances */ #define AMDGPU_MAX_SDMA_INSTANCES 2 @@ -152,8 +151,6 @@ extern unsigned amdgpu_pp_feature_mask; struct amdgpu_device; struct amdgpu_ib; -struct amdgpu_vm; -struct amdgpu_ring; struct amdgpu_cs_parser; struct amdgpu_job; struct amdgpu_irq_src; @@ -198,21 +195,38 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev, bool amdgpu_is_idle(struct amdgpu_device *adev, enum amd_ip_block_type block_type); +#define AMDGPU_MAX_IP_NUM 16 + +struct amdgpu_ip_block_status { + bool valid; + bool sw; + bool hw; + bool late_initialized; + bool hang; +}; + struct amdgpu_ip_block_version { - enum amd_ip_block_type type; - u32 major; - u32 minor; - u32 rev; + const enum amd_ip_block_type type; + const u32 major; + const u32 minor; + const u32 rev; const struct amd_ip_funcs *funcs; }; +struct amdgpu_ip_block { + struct amdgpu_ip_block_status status; + const struct amdgpu_ip_block_version *version; +}; + int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, enum amd_ip_block_type type, u32 major, u32 minor); -const struct amdgpu_ip_block_version * amdgpu_get_ip_block( - struct amdgpu_device *adev, - enum amd_ip_block_type type); +struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, + enum amd_ip_block_type type); + +int amdgpu_ip_block_add(struct amdgpu_device *adev, + const struct amdgpu_ip_block_version *ip_block_version); /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ struct amdgpu_buffer_funcs { @@ -286,47 +300,6 @@ struct amdgpu_ih_funcs { void (*set_rptr)(struct amdgpu_device *adev); }; -/* provided by hw blocks that expose a ring buffer for commands */ -struct amdgpu_ring_funcs { - /* ring read/write ptr handling */ - u32 (*get_rptr)(struct amdgpu_ring *ring); - u32 (*get_wptr)(struct amdgpu_ring *ring); - void (*set_wptr)(struct amdgpu_ring *ring); - /* validating and patching of IBs */ - int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); - /* command emit functions */ - void (*emit_ib)(struct amdgpu_ring *ring, - struct amdgpu_ib *ib, - unsigned vm_id, bool ctx_switch); - void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, - uint64_t seq, unsigned flags); - void (*emit_pipeline_sync)(struct amdgpu_ring *ring); - void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, - uint64_t pd_addr); - void (*emit_hdp_flush)(struct amdgpu_ring *ring); - void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); - void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, - uint32_t gds_base, uint32_t gds_size, - uint32_t gws_base, uint32_t gws_size, - uint32_t oa_base, uint32_t oa_size); - /* testing functions */ - int (*test_ring)(struct amdgpu_ring *ring); - int (*test_ib)(struct amdgpu_ring *ring, long timeout); - /* insert NOP packets */ - void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); - /* pad the indirect buffer to the necessary number of dw */ - void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); - unsigned (*init_cond_exec)(struct amdgpu_ring *ring); - void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); - /* note usage for clock and power gating */ - void (*begin_use)(struct amdgpu_ring *ring); - void (*end_use)(struct amdgpu_ring *ring); - void (*emit_switch_buffer) (struct amdgpu_ring *ring); - void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); - unsigned (*get_emit_ib_size) (struct amdgpu_ring *ring); - unsigned (*get_dma_frame_size) (struct amdgpu_ring *ring); -}; - /* * BIOS. */ @@ -364,47 +337,6 @@ struct amdgpu_clock { }; /* - * Fences. - */ -struct amdgpu_fence_driver { - uint64_t gpu_addr; - volatile uint32_t *cpu_addr; - /* sync_seq is protected by ring emission lock */ - uint32_t sync_seq; - atomic_t last_seq; - bool initialized; - struct amdgpu_irq_src *irq_src; - unsigned irq_type; - struct timer_list fallback_timer; - unsigned num_fences_mask; - spinlock_t lock; - struct fence **fences; -}; - -/* some special values for the owner field */ -#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) -#define AMDGPU_FENCE_OWNER_VM ((void*)1ul) - -#define AMDGPU_FENCE_FLAG_64BIT (1 << 0) -#define AMDGPU_FENCE_FLAG_INT (1 << 1) - -int amdgpu_fence_driver_init(struct amdgpu_device *adev); -void amdgpu_fence_driver_fini(struct amdgpu_device *adev); -void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); - -int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, - unsigned num_hw_submission); -int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, - struct amdgpu_irq_src *irq_src, - unsigned irq_type); -void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); -void amdgpu_fence_driver_resume(struct amdgpu_device *adev); -int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); -void amdgpu_fence_process(struct amdgpu_ring *ring); -int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); -unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); - -/* * BO. */ struct amdgpu_bo_list_entry { @@ -427,7 +359,7 @@ struct amdgpu_bo_va_mapping { struct amdgpu_bo_va { /* protected by bo being reserved */ struct list_head bo_list; - struct fence *last_pt_update; + struct dma_fence *last_pt_update; unsigned ref_count; /* protected by vm mutex and spinlock */ @@ -459,12 +391,12 @@ struct amdgpu_bo { u64 metadata_flags; void *metadata; u32 metadata_size; + unsigned prime_shared_count; /* list of all virtual address to which this bo * is associated to */ struct list_head va; /* Constant after initialization */ - struct amdgpu_device *adev; struct drm_gem_object gem_base; struct amdgpu_bo *parent; struct amdgpu_bo *shadow; @@ -543,7 +475,7 @@ struct amdgpu_sa_bo { struct amdgpu_sa_manager *manager; unsigned soffset; unsigned eoffset; - struct fence *fence; + struct dma_fence *fence; }; /* @@ -561,27 +493,6 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, int amdgpu_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p); -/* - * Synchronization - */ -struct amdgpu_sync { - DECLARE_HASHTABLE(fences, 4); - struct fence *last_vm_update; -}; - -void amdgpu_sync_create(struct amdgpu_sync *sync); -int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, - struct fence *f); -int amdgpu_sync_resv(struct amdgpu_device *adev, - struct amdgpu_sync *sync, - struct reservation_object *resv, - void *owner); -struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, - struct amdgpu_ring *ring); -struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); -void amdgpu_sync_free(struct amdgpu_sync *sync); -int amdgpu_sync_init(void); -void amdgpu_sync_fini(void); int amdgpu_fence_slab_init(void); void amdgpu_fence_slab_fini(void); @@ -703,10 +614,10 @@ struct amdgpu_flip_work { uint64_t base; struct drm_pending_vblank_event *event; struct amdgpu_bo *old_abo; - struct fence *excl; + struct dma_fence *excl; unsigned shared_count; - struct fence **shared; - struct fence_cb cb; + struct dma_fence **shared; + struct dma_fence_cb cb; bool async; }; @@ -723,14 +634,6 @@ struct amdgpu_ib { uint32_t flags; }; -enum amdgpu_ring_type { - AMDGPU_RING_TYPE_GFX, - AMDGPU_RING_TYPE_COMPUTE, - AMDGPU_RING_TYPE_SDMA, - AMDGPU_RING_TYPE_UVD, - AMDGPU_RING_TYPE_VCE -}; - extern const struct amd_sched_backend_ops amdgpu_sched_ops; int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, @@ -742,214 +645,7 @@ void amdgpu_job_free_resources(struct amdgpu_job *job); void amdgpu_job_free(struct amdgpu_job *job); int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, struct amd_sched_entity *entity, void *owner, - struct fence **f); - -struct amdgpu_ring { - struct amdgpu_device *adev; - const struct amdgpu_ring_funcs *funcs; - struct amdgpu_fence_driver fence_drv; - struct amd_gpu_scheduler sched; - - struct amdgpu_bo *ring_obj; - volatile uint32_t *ring; - unsigned rptr_offs; - unsigned wptr; - unsigned wptr_old; - unsigned ring_size; - unsigned max_dw; - int count_dw; - uint64_t gpu_addr; - uint32_t align_mask; - uint32_t ptr_mask; - bool ready; - u32 nop; - u32 idx; - u32 me; - u32 pipe; - u32 queue; - struct amdgpu_bo *mqd_obj; - u32 doorbell_index; - bool use_doorbell; - unsigned wptr_offs; - unsigned fence_offs; - uint64_t current_ctx; - enum amdgpu_ring_type type; - char name[16]; - unsigned cond_exe_offs; - u64 cond_exe_gpu_addr; - volatile u32 *cond_exe_cpu_addr; -#if defined(CONFIG_DEBUG_FS) - struct dentry *ent; -#endif -}; - -/* - * VM - */ - -/* maximum number of VMIDs */ -#define AMDGPU_NUM_VM 16 - -/* Maximum number of PTEs the hardware can write with one command */ -#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF - -/* number of entries in page table */ -#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) - -/* PTBs (Page Table Blocks) need to be aligned to 32K */ -#define AMDGPU_VM_PTB_ALIGN_SIZE 32768 - -/* LOG2 number of continuous pages for the fragment field */ -#define AMDGPU_LOG2_PAGES_PER_FRAG 4 - -#define AMDGPU_PTE_VALID (1 << 0) -#define AMDGPU_PTE_SYSTEM (1 << 1) -#define AMDGPU_PTE_SNOOPED (1 << 2) - -/* VI only */ -#define AMDGPU_PTE_EXECUTABLE (1 << 4) - -#define AMDGPU_PTE_READABLE (1 << 5) -#define AMDGPU_PTE_WRITEABLE (1 << 6) - -#define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7) - -/* How to programm VM fault handling */ -#define AMDGPU_VM_FAULT_STOP_NEVER 0 -#define AMDGPU_VM_FAULT_STOP_FIRST 1 -#define AMDGPU_VM_FAULT_STOP_ALWAYS 2 - -struct amdgpu_vm_pt { - struct amdgpu_bo_list_entry entry; - uint64_t addr; - uint64_t shadow_addr; -}; - -struct amdgpu_vm { - /* tree of virtual addresses mapped */ - struct rb_root va; - - /* protecting invalidated */ - spinlock_t status_lock; - - /* BOs moved, but not yet updated in the PT */ - struct list_head invalidated; - - /* BOs cleared in the PT because of a move */ - struct list_head cleared; - - /* BO mappings freed, but not yet updated in the PT */ - struct list_head freed; - - /* contains the page directory */ - struct amdgpu_bo *page_directory; - unsigned max_pde_used; - struct fence *page_directory_fence; - uint64_t last_eviction_counter; - - /* array of page tables, one for each page directory entry */ - struct amdgpu_vm_pt *page_tables; - - /* for id and flush management per ring */ - struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; - - /* protecting freed */ - spinlock_t freed_lock; - - /* Scheduler entity for page table updates */ - struct amd_sched_entity entity; - - /* client id */ - u64 client_id; -}; - -struct amdgpu_vm_id { - struct list_head list; - struct fence *first; - struct amdgpu_sync active; - struct fence *last_flush; - atomic64_t owner; - - uint64_t pd_gpu_addr; - /* last flushed PD/PT update */ - struct fence *flushed_updates; - - uint32_t current_gpu_reset_count; - - uint32_t gds_base; - uint32_t gds_size; - uint32_t gws_base; - uint32_t gws_size; - uint32_t oa_base; - uint32_t oa_size; -}; - -struct amdgpu_vm_manager { - /* Handling of VMIDs */ - struct mutex lock; - unsigned num_ids; - struct list_head ids_lru; - struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; - - /* Handling of VM fences */ - u64 fence_context; - unsigned seqno[AMDGPU_MAX_RINGS]; - - uint32_t max_pfn; - /* vram base address for page table entry */ - u64 vram_base_offset; - /* is vm enabled? */ - bool enabled; - /* vm pte handling */ - const struct amdgpu_vm_pte_funcs *vm_pte_funcs; - struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; - unsigned vm_pte_num_rings; - atomic_t vm_pte_next_ring; - /* client id counter */ - atomic64_t client_counter; -}; - -void amdgpu_vm_manager_init(struct amdgpu_device *adev); -void amdgpu_vm_manager_fini(struct amdgpu_device *adev); -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); -void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); -void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, - struct list_head *validated, - struct amdgpu_bo_list_entry *entry); -void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, - struct list_head *duplicates); -void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, - struct amdgpu_vm *vm); -int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, - struct amdgpu_sync *sync, struct fence *fence, - struct amdgpu_job *job); -int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job); -void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); -int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, - struct amdgpu_vm *vm); -int amdgpu_vm_clear_freed(struct amdgpu_device *adev, - struct amdgpu_vm *vm); -int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, - struct amdgpu_sync *sync); -int amdgpu_vm_bo_update(struct amdgpu_device *adev, - struct amdgpu_bo_va *bo_va, - bool clear); -void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, - struct amdgpu_bo *bo); -struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, - struct amdgpu_bo *bo); -struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, - struct amdgpu_vm *vm, - struct amdgpu_bo *bo); -int amdgpu_vm_bo_map(struct amdgpu_device *adev, - struct amdgpu_bo_va *bo_va, - uint64_t addr, uint64_t offset, - uint64_t size, uint32_t flags); -int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, - struct amdgpu_bo_va *bo_va, - uint64_t addr); -void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, - struct amdgpu_bo_va *bo_va); + struct dma_fence **f); /* * context related structures @@ -957,7 +653,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_ctx_ring { uint64_t sequence; - struct fence **fences; + struct dma_fence **fences; struct amd_sched_entity entity; }; @@ -966,7 +662,7 @@ struct amdgpu_ctx { struct amdgpu_device *adev; unsigned reset_counter; spinlock_t ring_lock; - struct fence **fences; + struct dma_fence **fences; struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; bool preamble_presented; }; @@ -982,8 +678,8 @@ struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); int amdgpu_ctx_put(struct amdgpu_ctx *ctx); uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, - struct fence *fence); -struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, + struct dma_fence *fence); +struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, uint64_t seq); int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, @@ -1093,6 +789,16 @@ struct amdgpu_scratch { /* * GFX configurations */ +#define AMDGPU_GFX_MAX_SE 4 +#define AMDGPU_GFX_MAX_SH_PER_SE 2 + +struct amdgpu_rb_config { + uint32_t rb_backend_disable; + uint32_t user_rb_backend_disable; + uint32_t raster_config; + uint32_t raster_config_1; +}; + struct amdgpu_gca_config { unsigned max_shader_engines; unsigned max_tile_pipes; @@ -1121,6 +827,8 @@ struct amdgpu_gca_config { uint32_t tile_mode_array[32]; uint32_t macrotile_mode_array[16]; + + struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; }; struct amdgpu_cu_info { @@ -1133,6 +841,9 @@ struct amdgpu_gfx_funcs { /* get the gpu clock counter */ uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); + void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); + void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); + void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); }; struct amdgpu_gfx { @@ -1181,23 +892,13 @@ struct amdgpu_gfx { int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned size, struct amdgpu_ib *ib); void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, - struct fence *f); + struct dma_fence *f); int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, - struct amdgpu_ib *ib, struct fence *last_vm_update, - struct amdgpu_job *job, struct fence **f); + struct amdgpu_ib *ib, struct dma_fence *last_vm_update, + struct amdgpu_job *job, struct dma_fence **f); int amdgpu_ib_pool_init(struct amdgpu_device *adev); void amdgpu_ib_pool_fini(struct amdgpu_device *adev); int amdgpu_ib_ring_tests(struct amdgpu_device *adev); -int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); -void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); -void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); -void amdgpu_ring_commit(struct amdgpu_ring *ring); -void amdgpu_ring_undo(struct amdgpu_ring *ring); -int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned ring_size, u32 nop, u32 align_mask, - struct amdgpu_irq_src *irq_src, unsigned irq_type, - enum amdgpu_ring_type ring_type); -void amdgpu_ring_fini(struct amdgpu_ring *ring); /* * CS. @@ -1225,7 +926,7 @@ struct amdgpu_cs_parser { struct amdgpu_bo_list *bo_list; struct amdgpu_bo_list_entry vm_pd; struct list_head validated; - struct fence *fence; + struct dma_fence *fence; uint64_t bytes_moved_threshold; uint64_t bytes_moved; struct amdgpu_bo_list_entry *evictable; @@ -1245,7 +946,7 @@ struct amdgpu_job { struct amdgpu_ring *ring; struct amdgpu_sync sync; struct amdgpu_ib *ibs; - struct fence *fence; /* the hw fence */ + struct dma_fence *fence; /* the hw fence */ uint32_t preamble_status; uint32_t num_ibs; void *owner; @@ -1294,354 +995,6 @@ struct amdgpu_wb { int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); - - -enum amdgpu_int_thermal_type { - THERMAL_TYPE_NONE, - THERMAL_TYPE_EXTERNAL, - THERMAL_TYPE_EXTERNAL_GPIO, - THERMAL_TYPE_RV6XX, - THERMAL_TYPE_RV770, - THERMAL_TYPE_ADT7473_WITH_INTERNAL, - THERMAL_TYPE_EVERGREEN, - THERMAL_TYPE_SUMO, - THERMAL_TYPE_NI, - THERMAL_TYPE_SI, - THERMAL_TYPE_EMC2103_WITH_INTERNAL, - THERMAL_TYPE_CI, - THERMAL_TYPE_KV, -}; - -enum amdgpu_dpm_auto_throttle_src { - AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, - AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL -}; - -enum amdgpu_dpm_event_src { - AMDGPU_DPM_EVENT_SRC_ANALOG = 0, - AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, - AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, - AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, - AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 -}; - -#define AMDGPU_MAX_VCE_LEVELS 6 - -enum amdgpu_vce_level { - AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ - AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ - AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ - AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ - AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ - AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ -}; - -struct amdgpu_ps { - u32 caps; /* vbios flags */ - u32 class; /* vbios flags */ - u32 class2; /* vbios flags */ - /* UVD clocks */ - u32 vclk; - u32 dclk; - /* VCE clocks */ - u32 evclk; - u32 ecclk; - bool vce_active; - enum amdgpu_vce_level vce_level; - /* asic priv */ - void *ps_priv; -}; - -struct amdgpu_dpm_thermal { - /* thermal interrupt work */ - struct work_struct work; - /* low temperature threshold */ - int min_temp; - /* high temperature threshold */ - int max_temp; - /* was last interrupt low to high or high to low */ - bool high_to_low; - /* interrupt source */ - struct amdgpu_irq_src irq; -}; - -enum amdgpu_clk_action -{ - AMDGPU_SCLK_UP = 1, - AMDGPU_SCLK_DOWN -}; - -struct amdgpu_blacklist_clocks -{ - u32 sclk; - u32 mclk; - enum amdgpu_clk_action action; -}; - -struct amdgpu_clock_and_voltage_limits { - u32 sclk; - u32 mclk; - u16 vddc; - u16 vddci; -}; - -struct amdgpu_clock_array { - u32 count; - u32 *values; -}; - -struct amdgpu_clock_voltage_dependency_entry { - u32 clk; - u16 v; -}; - -struct amdgpu_clock_voltage_dependency_table { - u32 count; - struct amdgpu_clock_voltage_dependency_entry *entries; -}; - -union amdgpu_cac_leakage_entry { - struct { - u16 vddc; - u32 leakage; - }; - struct { - u16 vddc1; - u16 vddc2; - u16 vddc3; - }; -}; - -struct amdgpu_cac_leakage_table { - u32 count; - union amdgpu_cac_leakage_entry *entries; -}; - -struct amdgpu_phase_shedding_limits_entry { - u16 voltage; - u32 sclk; - u32 mclk; -}; - -struct amdgpu_phase_shedding_limits_table { - u32 count; - struct amdgpu_phase_shedding_limits_entry *entries; -}; - -struct amdgpu_uvd_clock_voltage_dependency_entry { - u32 vclk; - u32 dclk; - u16 v; -}; - -struct amdgpu_uvd_clock_voltage_dependency_table { - u8 count; - struct amdgpu_uvd_clock_voltage_dependency_entry *entries; -}; - -struct amdgpu_vce_clock_voltage_dependency_entry { - u32 ecclk; - u32 evclk; - u16 v; -}; - -struct amdgpu_vce_clock_voltage_dependency_table { - u8 count; - struct amdgpu_vce_clock_voltage_dependency_entry *entries; -}; - -struct amdgpu_ppm_table { - u8 ppm_design; - u16 cpu_core_number; - u32 platform_tdp; - u32 small_ac_platform_tdp; - u32 platform_tdc; - u32 small_ac_platform_tdc; - u32 apu_tdp; - u32 dgpu_tdp; - u32 dgpu_ulv_power; - u32 tj_max; -}; - -struct amdgpu_cac_tdp_table { - u16 tdp; - u16 configurable_tdp; - u16 tdc; - u16 battery_power_limit; - u16 small_power_limit; - u16 low_cac_leakage; - u16 high_cac_leakage; - u16 maximum_power_delivery_limit; -}; - -struct amdgpu_dpm_dynamic_state { - struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; - struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; - struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; - struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; - struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; - struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; - struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; - struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; - struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; - struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; - struct amdgpu_clock_array valid_sclk_values; - struct amdgpu_clock_array valid_mclk_values; - struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; - struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; - u32 mclk_sclk_ratio; - u32 sclk_mclk_delta; - u16 vddc_vddci_delta; - u16 min_vddc_for_pcie_gen2; - struct amdgpu_cac_leakage_table cac_leakage_table; - struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; - struct amdgpu_ppm_table *ppm_table; - struct amdgpu_cac_tdp_table *cac_tdp_table; -}; - -struct amdgpu_dpm_fan { - u16 t_min; - u16 t_med; - u16 t_high; - u16 pwm_min; - u16 pwm_med; - u16 pwm_high; - u8 t_hyst; - u32 cycle_delay; - u16 t_max; - u8 control_mode; - u16 default_max_fan_pwm; - u16 default_fan_output_sensitivity; - u16 fan_output_sensitivity; - bool ucode_fan_control; -}; - -enum amdgpu_pcie_gen { - AMDGPU_PCIE_GEN1 = 0, - AMDGPU_PCIE_GEN2 = 1, - AMDGPU_PCIE_GEN3 = 2, - AMDGPU_PCIE_GEN_INVALID = 0xffff -}; - -enum amdgpu_dpm_forced_level { - AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, - AMDGPU_DPM_FORCED_LEVEL_LOW = 1, - AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, - AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, -}; - -struct amdgpu_vce_state { - /* vce clocks */ - u32 evclk; - u32 ecclk; - /* gpu clocks */ - u32 sclk; - u32 mclk; - u8 clk_idx; - u8 pstate; -}; - -struct amdgpu_dpm_funcs { - int (*get_temperature)(struct amdgpu_device *adev); - int (*pre_set_power_state)(struct amdgpu_device *adev); - int (*set_power_state)(struct amdgpu_device *adev); - void (*post_set_power_state)(struct amdgpu_device *adev); - void (*display_configuration_changed)(struct amdgpu_device *adev); - u32 (*get_sclk)(struct amdgpu_device *adev, bool low); - u32 (*get_mclk)(struct amdgpu_device *adev, bool low); - void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); - void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); - int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); - bool (*vblank_too_short)(struct amdgpu_device *adev); - void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); - void (*powergate_vce)(struct amdgpu_device *adev, bool gate); - void (*enable_bapm)(struct amdgpu_device *adev, bool enable); - void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); - u32 (*get_fan_control_mode)(struct amdgpu_device *adev); - int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); - int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); - int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask); - int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf); - int (*get_sclk_od)(struct amdgpu_device *adev); - int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value); - int (*get_mclk_od)(struct amdgpu_device *adev); - int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value); -}; - -struct amdgpu_dpm { - struct amdgpu_ps *ps; - /* number of valid power states */ - int num_ps; - /* current power state that is active */ - struct amdgpu_ps *current_ps; - /* requested power state */ - struct amdgpu_ps *requested_ps; - /* boot up power state */ - struct amdgpu_ps *boot_ps; - /* default uvd power state */ - struct amdgpu_ps *uvd_ps; - /* vce requirements */ - struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; - enum amdgpu_vce_level vce_level; - enum amd_pm_state_type state; - enum amd_pm_state_type user_state; - u32 platform_caps; - u32 voltage_response_time; - u32 backbias_response_time; - void *priv; - u32 new_active_crtcs; - int new_active_crtc_count; - u32 current_active_crtcs; - int current_active_crtc_count; - struct amdgpu_dpm_dynamic_state dyn_state; - struct amdgpu_dpm_fan fan; - u32 tdp_limit; - u32 near_tdp_limit; - u32 near_tdp_limit_adjusted; - u32 sq_ramping_threshold; - u32 cac_leakage; - u16 tdp_od_limit; - u32 tdp_adjustment; - u16 load_line_slope; - bool power_control; - bool ac_power; - /* special states active */ - bool thermal_active; - bool uvd_active; - bool vce_active; - /* thermal handling */ - struct amdgpu_dpm_thermal thermal; - /* forced levels */ - enum amdgpu_dpm_forced_level forced_level; -}; - -struct amdgpu_pm { - struct mutex mutex; - u32 current_sclk; - u32 current_mclk; - u32 default_sclk; - u32 default_mclk; - struct amdgpu_i2c_chan *i2c_bus; - /* internal thermal controller on rv6xx+ */ - enum amdgpu_int_thermal_type int_thermal_type; - struct device *int_hwmon_dev; - /* fan control parameters */ - bool no_fan; - u8 fan_pulses_per_revolution; - u8 fan_min_rpm; - u8 fan_max_rpm; - /* dpm */ - bool dpm_enabled; - bool sysfs_initialized; - struct amdgpu_dpm dpm; - const struct firmware *fw; /* SMC firmware */ - uint32_t fw_version; - const struct amdgpu_dpm_funcs *funcs; - uint32_t pcie_gen_mask; - uint32_t pcie_mlw_mask; - struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ -}; - void amdgpu_get_pcie_info(struct amdgpu_device *adev); /* @@ -1862,6 +1215,8 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); @@ -1939,14 +1294,6 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); -struct amdgpu_ip_block_status { - bool valid; - bool sw; - bool hw; - bool late_initialized; - bool hang; -}; - struct amdgpu_device { struct device *dev; struct drm_device *ddev; @@ -1985,6 +1332,7 @@ struct amdgpu_device { /* BIOS */ uint8_t *bios; + uint32_t bios_size; bool is_atom_bios; struct amdgpu_bo *stollen_vga_memory; uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; @@ -2102,9 +1450,8 @@ struct amdgpu_device { /* GDS */ struct amdgpu_gds gds; - const struct amdgpu_ip_block_version *ip_blocks; + struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; int num_ip_blocks; - struct amdgpu_ip_block_status *ip_block_status; struct mutex mn_lock; DECLARE_HASHTABLE(mn_hash, 7); @@ -2127,6 +1474,11 @@ struct amdgpu_device { }; +static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) +{ + return container_of(bdev, struct amdgpu_device, mman.bdev); +} + bool amdgpu_device_is_px(struct drm_device *dev); int amdgpu_device_init(struct amdgpu_device *adev, struct drm_device *ddev, @@ -2278,15 +1630,12 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) -#define amdgpu_ring_get_emit_ib_size(r) (r)->funcs->get_emit_ib_size((r)) -#define amdgpu_ring_get_dma_frame_size(r) (r)->funcs->get_dma_frame_size((r)) #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) -#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) @@ -2301,108 +1650,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) -#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) -#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) -#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) -#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) -#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) -#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) -#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) - -#define amdgpu_dpm_read_sensor(adev, idx, value) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \ - -EINVAL) - -#define amdgpu_dpm_get_temperature(adev) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ - (adev)->pm.funcs->get_temperature((adev))) - -#define amdgpu_dpm_set_fan_control_mode(adev, m) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ - (adev)->pm.funcs->set_fan_control_mode((adev), (m))) - -#define amdgpu_dpm_get_fan_control_mode(adev) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ - (adev)->pm.funcs->get_fan_control_mode((adev))) - -#define amdgpu_dpm_set_fan_speed_percent(adev, s) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ - (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) - -#define amdgpu_dpm_get_fan_speed_percent(adev, s) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ - (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) - -#define amdgpu_dpm_get_sclk(adev, l) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ - (adev)->pm.funcs->get_sclk((adev), (l))) - -#define amdgpu_dpm_get_mclk(adev, l) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ - (adev)->pm.funcs->get_mclk((adev), (l))) - - -#define amdgpu_dpm_force_performance_level(adev, l) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ - (adev)->pm.funcs->force_performance_level((adev), (l))) - -#define amdgpu_dpm_powergate_uvd(adev, g) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ - (adev)->pm.funcs->powergate_uvd((adev), (g))) - -#define amdgpu_dpm_powergate_vce(adev, g) \ - ((adev)->pp_enabled ? \ - (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ - (adev)->pm.funcs->powergate_vce((adev), (g))) - -#define amdgpu_dpm_get_current_power_state(adev) \ - (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) - -#define amdgpu_dpm_get_performance_level(adev) \ - (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) - -#define amdgpu_dpm_get_pp_num_states(adev, data) \ - (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) - -#define amdgpu_dpm_get_pp_table(adev, table) \ - (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) - -#define amdgpu_dpm_set_pp_table(adev, buf, size) \ - (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) - -#define amdgpu_dpm_print_clock_levels(adev, type, buf) \ - (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) - -#define amdgpu_dpm_force_clock_level(adev, type, level) \ - (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) - -#define amdgpu_dpm_get_sclk_od(adev) \ - (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle) - -#define amdgpu_dpm_set_sclk_od(adev, value) \ - (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value) - -#define amdgpu_dpm_get_mclk_od(adev) \ - ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) - -#define amdgpu_dpm_set_mclk_od(adev, value) \ - ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) - -#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ - (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) - #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) /* Common functions */ @@ -2433,8 +1682,6 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); -u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev); -int amdgpu_ttm_global_init(struct amdgpu_device *adev); int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); void amdgpu_program_register_sequence(struct amdgpu_device *adev, @@ -2471,6 +1718,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, struct drm_file *file_priv); void amdgpu_driver_preclose_kms(struct drm_device *dev, struct drm_file *file_priv); +int amdgpu_suspend(struct amdgpu_device *adev); int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 892d60fb225b..06879d1dcabd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -265,14 +265,14 @@ static int acp_hw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; - const struct amdgpu_ip_block_version *ip_version = + const struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); - if (!ip_version) + if (!ip_block) return -EINVAL; r = amd_acp_hw_init(adev->acp.cgs_device, - ip_version->major, ip_version->minor); + ip_block->version->major, ip_block->version->minor); /* -ENODEV means board uses AZ rather than ACP */ if (r == -ENODEV) return 0; @@ -395,9 +395,12 @@ static int acp_hw_fini(void *handle) { int i, ret; struct device *dev; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + /* return early if no ACP */ + if (!adev->acp.acp_genpd) + return 0; + for (i = 0; i < ACP_DEVS ; i++) { dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev); @@ -456,7 +459,7 @@ static int acp_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs acp_ip_funcs = { +static const struct amd_ip_funcs acp_ip_funcs = { .name = "acp_ip", .early_init = acp_early_init, .late_init = NULL, @@ -472,3 +475,12 @@ const struct amd_ip_funcs acp_ip_funcs = { .set_clockgating_state = acp_set_clockgating_state, .set_powergating_state = acp_set_powergating_state, }; + +const struct amdgpu_ip_block_version acp_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_ACP, + .major = 2, + .minor = 2, + .rev = 0, + .funcs = &acp_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h index 8a396313c86f..a288ce25c176 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h @@ -37,6 +37,6 @@ struct amdgpu_acp { struct acp_pm_domain *acp_genpd; }; -extern const struct amd_ip_funcs acp_ip_funcs; +extern const struct amdgpu_ip_block_version acp_ip_block; #endif /* __AMDGPU_ACP_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 8e6bf548d689..56a86dd5789e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1115,49 +1115,6 @@ int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, return 0; } -uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev) -{ - GET_ENGINE_CLOCK_PS_ALLOCATION args; - int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); - - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); - return le32_to_cpu(args.ulReturnEngineClock); -} - -uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev) -{ - GET_MEMORY_CLOCK_PS_ALLOCATION args; - int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); - - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); - return le32_to_cpu(args.ulReturnMemoryClock); -} - -void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev, - uint32_t eng_clock) -{ - SET_ENGINE_CLOCK_PS_ALLOCATION args; - int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); - - args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ - - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); -} - -void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, - uint32_t mem_clock) -{ - SET_MEMORY_CLOCK_PS_ALLOCATION args; - int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); - - if (adev->flags & AMD_IS_APU) - return; - - args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ - - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); -} - void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, u32 eng_clock, u32 mem_clock) { @@ -1256,45 +1213,6 @@ int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device * return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); } -void amdgpu_atombios_set_voltage(struct amdgpu_device *adev, - u16 voltage_level, - u8 voltage_type) -{ - union set_voltage args; - int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); - u8 frev, crev, volt_index = voltage_level; - - if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) - return; - - /* 0xff01 is a flag rather then an actual voltage */ - if (voltage_level == 0xff01) - return; - - switch (crev) { - case 1: - args.v1.ucVoltageType = voltage_type; - args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; - args.v1.ucVoltageIndex = volt_index; - break; - case 2: - args.v2.ucVoltageType = voltage_type; - args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; - args.v2.usVoltageLevel = cpu_to_le16(voltage_level); - break; - case 3: - args.v3.ucVoltageType = voltage_type; - args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; - args.v3.usVoltageLevel = cpu_to_le16(voltage_level); - break; - default: - DRM_ERROR("Unknown table version %d, %d\n", frev, crev); - return; - } - - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); -} - int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, u16 *leakage_id) { @@ -1784,6 +1702,19 @@ void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev) WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]); } +void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, + bool hung) +{ + u32 tmp = RREG32(mmBIOS_SCRATCH_3); + + if (hung) + tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; + else + tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; + + WREG32(mmBIOS_SCRATCH_3, tmp); +} + /* Atom needs data in little endian format * so swap as appropriate when copying data to * or from atom. Note that atom operates on diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index 17356151db38..70e9acef5d9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -163,16 +163,6 @@ int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, bool strobe_mode, struct atom_mpll_param *mpll_param); -uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev); -uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev); -void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev, - uint32_t eng_clock); -void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, - uint32_t mem_clock); -void amdgpu_atombios_set_voltage(struct amdgpu_device *adev, - u16 voltage_level, - u8 voltage_type); - void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, u32 eng_clock, u32 mem_clock); @@ -206,6 +196,8 @@ void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock); void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev); void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev); void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev); +void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, + bool hung); void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index dae35a96a694..6c343a933182 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -34,6 +34,7 @@ struct amdgpu_atpx { static struct amdgpu_atpx_priv { bool atpx_detected; + bool bridge_pm_usable; /* handle for device - and atpx */ acpi_handle dhandle; acpi_handle other_handle; @@ -205,7 +206,11 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) atpx->is_hybrid = false; if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) { printk("ATPX Hybrid Graphics\n"); - atpx->functions.power_cntl = false; + /* + * Disable legacy PM methods only when pcie port PM is usable, + * otherwise the device might fail to power off or power on. + */ + atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable; atpx->is_hybrid = true; } @@ -555,17 +560,25 @@ static bool amdgpu_atpx_detect(void) struct pci_dev *pdev = NULL; bool has_atpx = false; int vga_count = 0; + bool d3_supported = false; + struct pci_dev *parent_pdev; while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { vga_count++; has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); + + parent_pdev = pci_upstream_bridge(pdev); + d3_supported |= parent_pdev && parent_pdev->bridge_d3; } while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { vga_count++; has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); + + parent_pdev = pci_upstream_bridge(pdev); + d3_supported |= parent_pdev && parent_pdev->bridge_d3; } if (has_atpx && vga_count == 2) { @@ -573,6 +586,7 @@ static bool amdgpu_atpx_detect(void) printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n", acpi_method_name); amdgpu_atpx_priv.atpx_detected = true; + amdgpu_atpx_priv.bridge_pm_usable = d3_supported; amdgpu_atpx_init(); return true; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c index 345305235349..cc97eee93226 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -33,7 +33,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, { unsigned long start_jiffies; unsigned long end_jiffies; - struct fence *fence = NULL; + struct dma_fence *fence = NULL; int i, r; start_jiffies = jiffies; @@ -43,17 +43,17 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, false); if (r) goto exit_do_move; - r = fence_wait(fence, false); + r = dma_fence_wait(fence, false); if (r) goto exit_do_move; - fence_put(fence); + dma_fence_put(fence); } end_jiffies = jiffies; r = jiffies_to_msecs(end_jiffies - start_jiffies); exit_do_move: if (fence) - fence_put(fence); + dma_fence_put(fence); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 2b6afe123f3d..4f973a9c7b87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -70,10 +70,11 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) return false; } adev->bios = kmalloc(size, GFP_KERNEL); - if (adev->bios == NULL) { + if (!adev->bios) { iounmap(bios); return false; } + adev->bios_size = size; memcpy_fromio(adev->bios, bios, size); iounmap(bios); return true; @@ -103,6 +104,7 @@ bool amdgpu_read_bios(struct amdgpu_device *adev) pci_unmap_rom(adev->pdev, bios); return false; } + adev->bios_size = size; memcpy_fromio(adev->bios, bios, size); pci_unmap_rom(adev->pdev, bios); return true; @@ -135,6 +137,7 @@ static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev) DRM_ERROR("no memory to allocate for BIOS\n"); return false; } + adev->bios_size = len; /* read complete BIOS */ return amdgpu_asic_read_bios_from_rom(adev, adev->bios, len); @@ -159,6 +162,7 @@ static bool amdgpu_read_platform_bios(struct amdgpu_device *adev) if (adev->bios == NULL) { return false; } + adev->bios_size = size; return true; } @@ -273,6 +277,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) kfree(adev->bios); return false; } + adev->bios_size = size; return true; } #else @@ -334,6 +339,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) } adev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); + adev->bios_size = vhdr->ImageLength; ret = !!adev->bios; out_unmap: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index 651115dcce12..c02db01f6583 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -132,7 +132,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, entry->priority = min(info[i].bo_priority, AMDGPU_BO_LIST_MAX_PRIORITY); entry->tv.bo = &entry->robj->tbo; - entry->tv.shared = true; + entry->tv.shared = !entry->robj->prime_shared_count; if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS) gds_obj = entry->robj; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index 7a8bfa34682f..9ada56c16a58 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -146,7 +146,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, switch(type) { case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB: case CGS_GPU_MEM_TYPE__VISIBLE_FB: - flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; domain = AMDGPU_GEM_DOMAIN_VRAM; if (max_offset > adev->mc.real_vram_size) return -EINVAL; @@ -157,7 +158,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, break; case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB: case CGS_GPU_MEM_TYPE__INVISIBLE_FB: - flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; + flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; domain = AMDGPU_GEM_DOMAIN_VRAM; if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { place.fpfn = @@ -240,7 +242,7 @@ static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t h r = amdgpu_bo_reserve(obj, false); if (unlikely(r != 0)) return r; - r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT, + r = amdgpu_bo_pin_restricted(obj, obj->prefered_domains, min_offset, max_offset, mcaddr); amdgpu_bo_unreserve(obj); return r; @@ -624,11 +626,11 @@ static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, int i, r = -1; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].type == block_type) { - r = adev->ip_blocks[i].funcs->set_clockgating_state( + if (adev->ip_blocks[i].version->type == block_type) { + r = adev->ip_blocks[i].version->funcs->set_clockgating_state( (void *)adev, state); break; @@ -645,11 +647,11 @@ static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device, int i, r = -1; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].type == block_type) { - r = adev->ip_blocks[i].funcs->set_powergating_state( + if (adev->ip_blocks[i].version->type == block_type) { + r = adev->ip_blocks[i].version->funcs->set_powergating_state( (void *)adev, state); break; @@ -685,15 +687,21 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) result = AMDGPU_UCODE_ID_CP_MEC1; break; case CGS_UCODE_ID_CP_MEC_JT2: - if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11 - || adev->asic_type == CHIP_POLARIS10) - result = AMDGPU_UCODE_ID_CP_MEC2; - else + /* for VI. JT2 should be the same as JT1, because: + 1, MEC2 and MEC1 use exactly same FW. + 2, JT2 is not pached but JT1 is. + */ + if (adev->asic_type >= CHIP_TOPAZ) result = AMDGPU_UCODE_ID_CP_MEC1; + else + result = AMDGPU_UCODE_ID_CP_MEC2; break; case CGS_UCODE_ID_RLC_G: result = AMDGPU_UCODE_ID_RLC_G; break; + case CGS_UCODE_ID_STORAGE: + result = AMDGPU_UCODE_ID_STORAGE; + break; default: DRM_ERROR("Firmware type not supported\n"); } @@ -715,7 +723,7 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, enum cgs_ucode_id type) { CGS_FUNC_ADEV; - uint16_t fw_version; + uint16_t fw_version = 0; switch (type) { case CGS_UCODE_ID_SDMA0: @@ -745,9 +753,11 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, case CGS_UCODE_ID_RLC_G: fw_version = adev->gfx.rlc_fw_version; break; + case CGS_UCODE_ID_STORAGE: + break; default: DRM_ERROR("firmware type %d do not have version\n", type); - fw_version = 0; + break; } return fw_version; } @@ -776,12 +786,18 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, if ((type == CGS_UCODE_ID_CP_MEC_JT1) || (type == CGS_UCODE_ID_CP_MEC_JT2)) { - gpu_addr += le32_to_cpu(header->jt_offset) << 2; + gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE); data_size = le32_to_cpu(header->jt_size) << 2; } - info->mc_addr = gpu_addr; + + info->kptr = ucode->kaddr; info->image_size = data_size; + info->mc_addr = gpu_addr; info->version = (uint16_t)le32_to_cpu(header->header.ucode_version); + + if (CGS_UCODE_ID_CP_MEC == type) + info->image_size = (header->jt_offset) << 2; + info->fw_version = amdgpu_get_firmware_version(cgs_device, type); info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version); } else { @@ -795,10 +811,19 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, if (!adev->pm.fw) { switch (adev->asic_type) { case CHIP_TOPAZ: - strcpy(fw_name, "amdgpu/topaz_smc.bin"); + if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) || + ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) || + ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) + strcpy(fw_name, "amdgpu/topaz_k_smc.bin"); + else + strcpy(fw_name, "amdgpu/topaz_smc.bin"); break; case CHIP_TONGA: - strcpy(fw_name, "amdgpu/tonga_smc.bin"); + if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) || + ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) + strcpy(fw_name, "amdgpu/tonga_k_smc.bin"); + else + strcpy(fw_name, "amdgpu/tonga_smc.bin"); break; case CHIP_FIJI: strcpy(fw_name, "amdgpu/fiji_smc.bin"); @@ -851,6 +876,12 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, return 0; } +static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device) +{ + CGS_FUNC_ADEV; + return amdgpu_sriov_vf(adev); +} + static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, struct cgs_system_info *sys_info) { @@ -1204,6 +1235,7 @@ static const struct cgs_ops amdgpu_cgs_ops = { amdgpu_cgs_notify_dpm_enabled, amdgpu_cgs_call_acpi_method, amdgpu_cgs_query_system_info, + amdgpu_cgs_is_virtualization_enabled }; static const struct cgs_os_ops amdgpu_cgs_os_ops = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index e3281d4e3e41..8d1cf2d3e663 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -769,7 +769,7 @@ static void amdgpu_connector_unregister(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - if (amdgpu_connector->ddc_bus->has_aux) { + if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); amdgpu_connector->ddc_bus->has_aux = false; } @@ -1517,88 +1517,6 @@ static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { .force = amdgpu_connector_dvi_force, }; -static struct drm_encoder * -amdgpu_connector_virtual_encoder(struct drm_connector *connector) -{ - int enc_id = connector->encoder_ids[0]; - struct drm_encoder *encoder; - int i; - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { - if (connector->encoder_ids[i] == 0) - break; - - encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); - if (!encoder) - continue; - - if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) - return encoder; - } - - /* pick the first one */ - if (enc_id) - return drm_encoder_find(connector->dev, enc_id); - return NULL; -} - -static int amdgpu_connector_virtual_get_modes(struct drm_connector *connector) -{ - struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); - - if (encoder) { - amdgpu_connector_add_common_modes(encoder, connector); - } - - return 0; -} - -static int amdgpu_connector_virtual_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - return MODE_OK; -} - -static int -amdgpu_connector_virtual_dpms(struct drm_connector *connector, int mode) -{ - return 0; -} - -static enum drm_connector_status - -amdgpu_connector_virtual_detect(struct drm_connector *connector, bool force) -{ - return connector_status_connected; -} - -static int -amdgpu_connector_virtual_set_property(struct drm_connector *connector, - struct drm_property *property, - uint64_t val) -{ - return 0; -} - -static void amdgpu_connector_virtual_force(struct drm_connector *connector) -{ - return; -} - -static const struct drm_connector_helper_funcs amdgpu_connector_virtual_helper_funcs = { - .get_modes = amdgpu_connector_virtual_get_modes, - .mode_valid = amdgpu_connector_virtual_mode_valid, - .best_encoder = amdgpu_connector_virtual_encoder, -}; - -static const struct drm_connector_funcs amdgpu_connector_virtual_funcs = { - .dpms = amdgpu_connector_virtual_dpms, - .detect = amdgpu_connector_virtual_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .set_property = amdgpu_connector_virtual_set_property, - .destroy = amdgpu_connector_destroy, - .force = amdgpu_connector_virtual_force, -}; - void amdgpu_connector_add(struct amdgpu_device *adev, uint32_t connector_id, @@ -1983,17 +1901,6 @@ amdgpu_connector_add(struct amdgpu_device *adev, connector->interlace_allowed = false; connector->doublescan_allowed = false; break; - case DRM_MODE_CONNECTOR_VIRTUAL: - amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); - if (!amdgpu_dig_connector) - goto failed; - amdgpu_connector->con_priv = amdgpu_dig_connector; - drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_virtual_funcs, connector_type); - drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_virtual_helper_funcs); - subpixel_order = SubPixelHorizontalRGB; - connector->interlace_allowed = false; - connector->doublescan_allowed = false; - break; } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 82dc8d20e28a..29d6d84d1c28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -355,6 +355,7 @@ static void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, struct amdgpu_bo *bo) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); u64 initial_bytes_moved; uint32_t domain; int r; @@ -372,9 +373,9 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, retry: amdgpu_ttm_placement_from_domain(bo, domain); - initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); + initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); - p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - + p->bytes_moved += atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved; if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { @@ -387,9 +388,9 @@ retry: /* Last resort, try to evict something from the current working set */ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, - struct amdgpu_bo_list_entry *lobj) + struct amdgpu_bo *validated) { - uint32_t domain = lobj->robj->allowed_domains; + uint32_t domain = validated->allowed_domains; int r; if (!p->evictable) @@ -400,11 +401,12 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, struct amdgpu_bo_list_entry *candidate = p->evictable; struct amdgpu_bo *bo = candidate->robj; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); u64 initial_bytes_moved; uint32_t other; /* If we reached our current BO we can forget it */ - if (candidate == lobj) + if (candidate->robj == validated) break; other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); @@ -420,9 +422,9 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, /* Good we can try to move this BO somewhere else */ amdgpu_ttm_placement_from_domain(bo, other); - initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); + initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); - p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - + p->bytes_moved += atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved; if (unlikely(r)) @@ -437,6 +439,23 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, return false; } +static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) +{ + struct amdgpu_cs_parser *p = param; + int r; + + do { + r = amdgpu_cs_bo_validate(p, bo); + } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo)); + if (r) + return r; + + if (bo->shadow) + r = amdgpu_cs_bo_validate(p, bo->shadow); + + return r; +} + static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, struct list_head *validated) { @@ -464,18 +483,10 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, if (p->evictable == lobj) p->evictable = NULL; - do { - r = amdgpu_cs_bo_validate(p, bo); - } while (r == -ENOMEM && amdgpu_cs_try_evict(p, lobj)); + r = amdgpu_cs_validate(p, bo); if (r) return r; - if (bo->shadow) { - r = amdgpu_cs_bo_validate(p, bo); - if (r) - return r; - } - if (binding_userptr) { drm_free_large(lobj->user_pages); lobj->user_pages = NULL; @@ -594,14 +605,19 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, list_splice(&need_pages, &p->validated); } - amdgpu_vm_get_pt_bos(p->adev, &fpriv->vm, &duplicates); - p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev); p->bytes_moved = 0; p->evictable = list_last_entry(&p->validated, struct amdgpu_bo_list_entry, tv.head); + r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm, + amdgpu_cs_validate, p); + if (r) { + DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n"); + goto error_validate; + } + r = amdgpu_cs_list_validate(p, &duplicates); if (r) { DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n"); @@ -720,7 +736,7 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo ttm_eu_backoff_reservation(&parser->ticket, &parser->validated); } - fence_put(parser->fence); + dma_fence_put(parser->fence); if (parser->ctx) amdgpu_ctx_put(parser->ctx); @@ -757,7 +773,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, if (p->bo_list) { for (i = 0; i < p->bo_list->num_entries; i++) { - struct fence *f; + struct dma_fence *f; /* ignore duplicates */ bo = p->bo_list->array[i].robj; @@ -807,13 +823,14 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, /* Only for UVD/VCE VM emulation */ if (ring->funcs->parse_cs) { - p->job->vm = NULL; for (i = 0; i < p->job->num_ibs; i++) { r = amdgpu_ring_parse_cs(ring, p, i); if (r) return r; } - } else { + } + + if (p->job->vm) { p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); r = amdgpu_bo_vm_update_pte(p, vm); @@ -824,16 +841,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, return amdgpu_cs_sync_rings(p); } -static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) -{ - if (r == -EDEADLK) { - r = amdgpu_gpu_reset(adev); - if (!r) - r = -EAGAIN; - } - return r; -} - static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, struct amdgpu_cs_parser *parser) { @@ -902,7 +909,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; kptr += chunk_ib->va_start - offset; - r = amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib); + r = amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib); if (r) { DRM_ERROR("Failed to get ib !\n"); return r; @@ -917,9 +924,9 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, return r; } - ib->gpu_addr = chunk_ib->va_start; } + ib->gpu_addr = chunk_ib->va_start; ib->length_dw = chunk_ib->ib_bytes / 4; ib->flags = chunk_ib->flags; j++; @@ -927,8 +934,8 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, /* UVD & VCE fw doesn't support user fences */ if (parser->job->uf_addr && ( - parser->job->ring->type == AMDGPU_RING_TYPE_UVD || - parser->job->ring->type == AMDGPU_RING_TYPE_VCE)) + parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD || + parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE)) return -EINVAL; return 0; @@ -957,7 +964,7 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, for (j = 0; j < num_deps; ++j) { struct amdgpu_ring *ring; struct amdgpu_ctx *ctx; - struct fence *fence; + struct dma_fence *fence; r = amdgpu_cs_get_ring(adev, deps[j].ip_type, deps[j].ip_instance, @@ -979,7 +986,7 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, } else if (fence) { r = amdgpu_sync_fence(adev, &p->job->sync, fence); - fence_put(fence); + dma_fence_put(fence); amdgpu_ctx_put(ctx); if (r) return r; @@ -1009,7 +1016,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, job->owner = p->filp; job->fence_ctx = entity->fence_context; - p->fence = fence_get(&job->base.s_fence->finished); + p->fence = dma_fence_get(&job->base.s_fence->finished); cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence); job->uf_sequence = cs->out.handle; amdgpu_job_free_resources(job); @@ -1037,29 +1044,29 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) r = amdgpu_cs_parser_init(&parser, data); if (r) { DRM_ERROR("Failed to initialize parser !\n"); - amdgpu_cs_parser_fini(&parser, r, false); - r = amdgpu_cs_handle_lockup(adev, r); - return r; - } - r = amdgpu_cs_parser_bos(&parser, data); - if (r == -ENOMEM) - DRM_ERROR("Not enough memory for command submission!\n"); - else if (r && r != -ERESTARTSYS) - DRM_ERROR("Failed to process the buffer list %d!\n", r); - else if (!r) { - reserved_buffers = true; - r = amdgpu_cs_ib_fill(adev, &parser); + goto out; } - if (!r) { - r = amdgpu_cs_dependencies(adev, &parser); - if (r) - DRM_ERROR("Failed in the dependencies handling %d!\n", r); + r = amdgpu_cs_parser_bos(&parser, data); + if (r) { + if (r == -ENOMEM) + DRM_ERROR("Not enough memory for command submission!\n"); + else if (r != -ERESTARTSYS) + DRM_ERROR("Failed to process the buffer list %d!\n", r); + goto out; } + reserved_buffers = true; + r = amdgpu_cs_ib_fill(adev, &parser); if (r) goto out; + r = amdgpu_cs_dependencies(adev, &parser); + if (r) { + DRM_ERROR("Failed in the dependencies handling %d!\n", r); + goto out; + } + for (i = 0; i < parser.job->num_ibs; i++) trace_amdgpu_cs(&parser, i); @@ -1071,7 +1078,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) out: amdgpu_cs_parser_fini(&parser, r, reserved_buffers); - r = amdgpu_cs_handle_lockup(adev, r); return r; } @@ -1092,7 +1098,7 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); struct amdgpu_ring *ring = NULL; struct amdgpu_ctx *ctx; - struct fence *fence; + struct dma_fence *fence; long r; r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, @@ -1108,8 +1114,8 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, if (IS_ERR(fence)) r = PTR_ERR(fence); else if (fence) { - r = fence_wait_timeout(fence, true, timeout); - fence_put(fence); + r = dma_fence_wait_timeout(fence, true, timeout); + dma_fence_put(fence); } else r = 1; @@ -1124,6 +1130,180 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, } /** + * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence + * + * @adev: amdgpu device + * @filp: file private + * @user: drm_amdgpu_fence copied from user space + */ +static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev, + struct drm_file *filp, + struct drm_amdgpu_fence *user) +{ + struct amdgpu_ring *ring; + struct amdgpu_ctx *ctx; + struct dma_fence *fence; + int r; + + r = amdgpu_cs_get_ring(adev, user->ip_type, user->ip_instance, + user->ring, &ring); + if (r) + return ERR_PTR(r); + + ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id); + if (ctx == NULL) + return ERR_PTR(-EINVAL); + + fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no); + amdgpu_ctx_put(ctx); + + return fence; +} + +/** + * amdgpu_cs_wait_all_fence - wait on all fences to signal + * + * @adev: amdgpu device + * @filp: file private + * @wait: wait parameters + * @fences: array of drm_amdgpu_fence + */ +static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, + struct drm_file *filp, + union drm_amdgpu_wait_fences *wait, + struct drm_amdgpu_fence *fences) +{ + uint32_t fence_count = wait->in.fence_count; + unsigned int i; + long r = 1; + + for (i = 0; i < fence_count; i++) { + struct dma_fence *fence; + unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); + + fence = amdgpu_cs_get_fence(adev, filp, &fences[i]); + if (IS_ERR(fence)) + return PTR_ERR(fence); + else if (!fence) + continue; + + r = dma_fence_wait_timeout(fence, true, timeout); + if (r < 0) + return r; + + if (r == 0) + break; + } + + memset(wait, 0, sizeof(*wait)); + wait->out.status = (r > 0); + + return 0; +} + +/** + * amdgpu_cs_wait_any_fence - wait on any fence to signal + * + * @adev: amdgpu device + * @filp: file private + * @wait: wait parameters + * @fences: array of drm_amdgpu_fence + */ +static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, + struct drm_file *filp, + union drm_amdgpu_wait_fences *wait, + struct drm_amdgpu_fence *fences) +{ + unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); + uint32_t fence_count = wait->in.fence_count; + uint32_t first = ~0; + struct dma_fence **array; + unsigned int i; + long r; + + /* Prepare the fence array */ + array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL); + + if (array == NULL) + return -ENOMEM; + + for (i = 0; i < fence_count; i++) { + struct dma_fence *fence; + + fence = amdgpu_cs_get_fence(adev, filp, &fences[i]); + if (IS_ERR(fence)) { + r = PTR_ERR(fence); + goto err_free_fence_array; + } else if (fence) { + array[i] = fence; + } else { /* NULL, the fence has been already signaled */ + r = 1; + goto out; + } + } + + r = dma_fence_wait_any_timeout(array, fence_count, true, timeout, + &first); + if (r < 0) + goto err_free_fence_array; + +out: + memset(wait, 0, sizeof(*wait)); + wait->out.status = (r > 0); + wait->out.first_signaled = first; + /* set return value 0 to indicate success */ + r = 0; + +err_free_fence_array: + for (i = 0; i < fence_count; i++) + dma_fence_put(array[i]); + kfree(array); + + return r; +} + +/** + * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish + * + * @dev: drm device + * @data: data from userspace + * @filp: file private + */ +int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct amdgpu_device *adev = dev->dev_private; + union drm_amdgpu_wait_fences *wait = data; + uint32_t fence_count = wait->in.fence_count; + struct drm_amdgpu_fence *fences_user; + struct drm_amdgpu_fence *fences; + int r; + + /* Get the fences from userspace */ + fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence), + GFP_KERNEL); + if (fences == NULL) + return -ENOMEM; + + fences_user = (void __user *)(unsigned long)(wait->in.fences); + if (copy_from_user(fences, fences_user, + sizeof(struct drm_amdgpu_fence) * fence_count)) { + r = -EFAULT; + goto err_free_fences; + } + + if (wait->in.wait_all) + r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences); + else + r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences); + +err_free_fences: + kfree(fences); + + return r; +} + +/** * amdgpu_cs_find_bo_va - find bo_va for VM address * * @parser: command submission parser context @@ -1196,6 +1376,15 @@ int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser) r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); if (unlikely(r)) return r; + + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) + continue; + + bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains); + r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + if (unlikely(r)) + return r; } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index a5e2fcbef0f0..400c66ba4c6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -35,7 +35,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) kref_init(&ctx->refcount); spin_lock_init(&ctx->ring_lock); ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS, - sizeof(struct fence*), GFP_KERNEL); + sizeof(struct dma_fence*), GFP_KERNEL); if (!ctx->fences) return -ENOMEM; @@ -55,18 +55,18 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, rq, amdgpu_sched_jobs); if (r) - break; + goto failed; } - if (i < adev->num_rings) { - for (j = 0; j < i; j++) - amd_sched_entity_fini(&adev->rings[j]->sched, - &ctx->rings[j].entity); - kfree(ctx->fences); - ctx->fences = NULL; - return r; - } return 0; + +failed: + for (j = 0; j < i; j++) + amd_sched_entity_fini(&adev->rings[j]->sched, + &ctx->rings[j].entity); + kfree(ctx->fences); + ctx->fences = NULL; + return r; } static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) @@ -79,7 +79,7 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) for (i = 0; i < AMDGPU_MAX_RINGS; ++i) for (j = 0; j < amdgpu_sched_jobs; ++j) - fence_put(ctx->rings[i].fences[j]); + dma_fence_put(ctx->rings[i].fences[j]); kfree(ctx->fences); ctx->fences = NULL; @@ -241,39 +241,39 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx) } uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, - struct fence *fence) + struct dma_fence *fence) { struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; uint64_t seq = cring->sequence; unsigned idx = 0; - struct fence *other = NULL; + struct dma_fence *other = NULL; idx = seq & (amdgpu_sched_jobs - 1); other = cring->fences[idx]; if (other) { signed long r; - r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); + r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); if (r < 0) DRM_ERROR("Error (%ld) waiting for fence!\n", r); } - fence_get(fence); + dma_fence_get(fence); spin_lock(&ctx->ring_lock); cring->fences[idx] = fence; cring->sequence++; spin_unlock(&ctx->ring_lock); - fence_put(other); + dma_fence_put(other); return seq; } -struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, - struct amdgpu_ring *ring, uint64_t seq) +struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, + struct amdgpu_ring *ring, uint64_t seq) { struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; - struct fence *fence; + struct dma_fence *fence; spin_lock(&ctx->ring_lock); @@ -288,7 +288,7 @@ struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, return NULL; } - fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]); + fence = dma_fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]); spin_unlock(&ctx->ring_lock); return fence; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7ca07e7b25c1..cc8aafd9cb0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -264,7 +264,8 @@ static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) if (adev->vram_scratch.robj == NULL) { r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->vram_scratch.robj); if (r) { return r; @@ -442,13 +443,9 @@ void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, static void amdgpu_wb_fini(struct amdgpu_device *adev) { if (adev->wb.wb_obj) { - if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) { - amdgpu_bo_kunmap(adev->wb.wb_obj); - amdgpu_bo_unpin(adev->wb.wb_obj); - amdgpu_bo_unreserve(adev->wb.wb_obj); - } - amdgpu_bo_unref(&adev->wb.wb_obj); - adev->wb.wb = NULL; + amdgpu_bo_free_kernel(&adev->wb.wb_obj, + &adev->wb.gpu_addr, + (void **)&adev->wb.wb); adev->wb.wb_obj = NULL; } } @@ -467,33 +464,14 @@ static int amdgpu_wb_init(struct amdgpu_device *adev) int r; if (adev->wb.wb_obj == NULL) { - r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, - &adev->wb.wb_obj); + r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 4, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, + &adev->wb.wb_obj, &adev->wb.gpu_addr, + (void **)&adev->wb.wb); if (r) { dev_warn(adev->dev, "(%d) create WB bo failed\n", r); return r; } - r = amdgpu_bo_reserve(adev->wb.wb_obj, false); - if (unlikely(r != 0)) { - amdgpu_wb_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT, - &adev->wb.gpu_addr); - if (r) { - amdgpu_bo_unreserve(adev->wb.wb_obj); - dev_warn(adev->dev, "(%d) pin WB bo failed\n", r); - amdgpu_wb_fini(adev); - return r; - } - r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb); - amdgpu_bo_unreserve(adev->wb.wb_obj); - if (r) { - dev_warn(adev->dev, "(%d) map WB bo failed\n", r); - amdgpu_wb_fini(adev); - return r; - } adev->wb.num_wb = AMDGPU_MAX_WB; memset(&adev->wb.used, 0, sizeof(adev->wb.used)); @@ -658,12 +636,10 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) return false; if (amdgpu_passthrough(adev)) { - /* for FIJI: In whole GPU pass-through virtualization case - * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH) - * so amdgpu_card_posted return false and driver will incorrectly skip vPost. - * but if we force vPost do in pass-through case, the driver reload will hang. - * whether doing vPost depends on amdgpu_card_posted if smc version is above - * 00160e00 for FIJI. + /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot + * some old smc fw still need driver do vPost otherwise gpu hang, while + * those smc fw version above 22.15 doesn't have this flaw, so we force + * vpost executed for smc version below 22.15 */ if (adev->asic_type == CHIP_FIJI) { int err; @@ -674,22 +650,11 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) return true; fw_ver = *((uint32_t *)adev->pm.fw->data + 69); - if (fw_ver >= 0x00160e00) - return !amdgpu_card_posted(adev); + if (fw_ver < 0x00160e00) + return true; } - } else { - /* in bare-metal case, amdgpu_card_posted return false - * after system reboot/boot, and return true if driver - * reloaded. - * we shouldn't do vPost after driver reload otherwise GPU - * could hang. - */ - if (amdgpu_card_posted(adev)) - return false; } - - /* we assume vPost is neede for all other cases */ - return true; + return !amdgpu_card_posted(adev); } /** @@ -1051,6 +1016,13 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_vm_block_size); amdgpu_vm_block_size = 9; } + + if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || + !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { + dev_warn(adev->dev, "invalid VRAM page split (%d)\n", + amdgpu_vram_page_split); + amdgpu_vram_page_split = 1024; + } } /** @@ -1125,11 +1097,11 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, int i, r = 0; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].type == block_type) { - r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, - state); + if (adev->ip_blocks[i].version->type == block_type) { + r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, + state); if (r) return r; break; @@ -1145,11 +1117,11 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev, int i, r = 0; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].type == block_type) { - r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev, - state); + if (adev->ip_blocks[i].version->type == block_type) { + r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, + state); if (r) return r; break; @@ -1164,10 +1136,10 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev, int i, r; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].type == block_type) { - r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev); + if (adev->ip_blocks[i].version->type == block_type) { + r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); if (r) return r; break; @@ -1183,23 +1155,22 @@ bool amdgpu_is_idle(struct amdgpu_device *adev, int i; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].type == block_type) - return adev->ip_blocks[i].funcs->is_idle((void *)adev); + if (adev->ip_blocks[i].version->type == block_type) + return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); } return true; } -const struct amdgpu_ip_block_version * amdgpu_get_ip_block( - struct amdgpu_device *adev, - enum amd_ip_block_type type) +struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, + enum amd_ip_block_type type) { int i; for (i = 0; i < adev->num_ip_blocks; i++) - if (adev->ip_blocks[i].type == type) + if (adev->ip_blocks[i].version->type == type) return &adev->ip_blocks[i]; return NULL; @@ -1220,38 +1191,75 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, enum amd_ip_block_type type, u32 major, u32 minor) { - const struct amdgpu_ip_block_version *ip_block; - ip_block = amdgpu_get_ip_block(adev, type); + struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); - if (ip_block && ((ip_block->major > major) || - ((ip_block->major == major) && - (ip_block->minor >= minor)))) + if (ip_block && ((ip_block->version->major > major) || + ((ip_block->version->major == major) && + (ip_block->version->minor >= minor)))) return 0; return 1; } -static void amdgpu_whether_enable_virtual_display(struct amdgpu_device *adev) +/** + * amdgpu_ip_block_add + * + * @adev: amdgpu_device pointer + * @ip_block_version: pointer to the IP to add + * + * Adds the IP block driver information to the collection of IPs + * on the asic. + */ +int amdgpu_ip_block_add(struct amdgpu_device *adev, + const struct amdgpu_ip_block_version *ip_block_version) +{ + if (!ip_block_version) + return -EINVAL; + + adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; + + return 0; +} + +static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) { adev->enable_virtual_display = false; if (amdgpu_virtual_display) { struct drm_device *ddev = adev->ddev; const char *pci_address_name = pci_name(ddev->pdev); - char *pciaddstr, *pciaddstr_tmp, *pciaddname; + char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); pciaddstr_tmp = pciaddstr; - while ((pciaddname = strsep(&pciaddstr_tmp, ";"))) { + while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { + pciaddname = strsep(&pciaddname_tmp, ","); if (!strcmp(pci_address_name, pciaddname)) { + long num_crtc; + int res = -1; + adev->enable_virtual_display = true; + + if (pciaddname_tmp) + res = kstrtol(pciaddname_tmp, 10, + &num_crtc); + + if (!res) { + if (num_crtc < 1) + num_crtc = 1; + if (num_crtc > 6) + num_crtc = 6; + adev->mode_info.num_crtc = num_crtc; + } else { + adev->mode_info.num_crtc = 1; + } break; } } - DRM_INFO("virtual display string:%s, %s:virtual_display:%d\n", - amdgpu_virtual_display, pci_address_name, - adev->enable_virtual_display); + DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", + amdgpu_virtual_display, pci_address_name, + adev->enable_virtual_display, adev->mode_info.num_crtc); kfree(pciaddstr); } @@ -1261,7 +1269,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev) { int i, r; - amdgpu_whether_enable_virtual_display(adev); + amdgpu_device_enable_virtual_display(adev); switch (adev->asic_type) { case CHIP_TOPAZ: @@ -1313,33 +1321,24 @@ static int amdgpu_early_init(struct amdgpu_device *adev) return -EINVAL; } - adev->ip_block_status = kcalloc(adev->num_ip_blocks, - sizeof(struct amdgpu_ip_block_status), GFP_KERNEL); - if (adev->ip_block_status == NULL) - return -ENOMEM; - - if (adev->ip_blocks == NULL) { - DRM_ERROR("No IP blocks found!\n"); - return r; - } - for (i = 0; i < adev->num_ip_blocks; i++) { if ((amdgpu_ip_block_mask & (1 << i)) == 0) { DRM_ERROR("disabled ip block: %d\n", i); - adev->ip_block_status[i].valid = false; + adev->ip_blocks[i].status.valid = false; } else { - if (adev->ip_blocks[i].funcs->early_init) { - r = adev->ip_blocks[i].funcs->early_init((void *)adev); + if (adev->ip_blocks[i].version->funcs->early_init) { + r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); if (r == -ENOENT) { - adev->ip_block_status[i].valid = false; + adev->ip_blocks[i].status.valid = false; } else if (r) { - DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_ERROR("early_init of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); return r; } else { - adev->ip_block_status[i].valid = true; + adev->ip_blocks[i].status.valid = true; } } else { - adev->ip_block_status[i].valid = true; + adev->ip_blocks[i].status.valid = true; } } } @@ -1355,22 +1354,23 @@ static int amdgpu_init(struct amdgpu_device *adev) int i, r; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - r = adev->ip_blocks[i].funcs->sw_init((void *)adev); + r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); if (r) { - DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_ERROR("sw_init of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); return r; } - adev->ip_block_status[i].sw = true; + adev->ip_blocks[i].status.sw = true; /* need to do gmc hw init early so we can allocate gpu mem */ - if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { r = amdgpu_vram_scratch_init(adev); if (r) { DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); return r; } - r = adev->ip_blocks[i].funcs->hw_init((void *)adev); + r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); if (r) { DRM_ERROR("hw_init %d failed %d\n", i, r); return r; @@ -1380,22 +1380,23 @@ static int amdgpu_init(struct amdgpu_device *adev) DRM_ERROR("amdgpu_wb_init failed %d\n", r); return r; } - adev->ip_block_status[i].hw = true; + adev->ip_blocks[i].status.hw = true; } } for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].sw) + if (!adev->ip_blocks[i].status.sw) continue; /* gmc hw init is done early */ - if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) continue; - r = adev->ip_blocks[i].funcs->hw_init((void *)adev); + r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); if (r) { - DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_ERROR("hw_init of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); return r; } - adev->ip_block_status[i].hw = true; + adev->ip_blocks[i].status.hw = true; } return 0; @@ -1406,25 +1407,26 @@ static int amdgpu_late_init(struct amdgpu_device *adev) int i = 0, r; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].funcs->late_init) { - r = adev->ip_blocks[i].funcs->late_init((void *)adev); + if (adev->ip_blocks[i].version->funcs->late_init) { + r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); if (r) { - DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_ERROR("late_init of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); return r; } - adev->ip_block_status[i].late_initialized = true; + adev->ip_blocks[i].status.late_initialized = true; } /* skip CG for VCE/UVD, it's handled specially */ - if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD && - adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) { + if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && + adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { /* enable clockgating to save power */ - r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, - AMD_CG_STATE_GATE); + r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, + AMD_CG_STATE_GATE); if (r) { DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", - adev->ip_blocks[i].funcs->name, r); + adev->ip_blocks[i].version->funcs->name, r); return r; } } @@ -1439,74 +1441,83 @@ static int amdgpu_fini(struct amdgpu_device *adev) /* need to disable SMC first */ for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].hw) + if (!adev->ip_blocks[i].status.hw) continue; - if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) { + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { /* ungate blocks before hw fini so that we can shutdown the blocks safely */ - r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, - AMD_CG_STATE_UNGATE); + r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, + AMD_CG_STATE_UNGATE); if (r) { DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", - adev->ip_blocks[i].funcs->name, r); + adev->ip_blocks[i].version->funcs->name, r); return r; } - r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); + r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); /* XXX handle errors */ if (r) { DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", - adev->ip_blocks[i].funcs->name, r); + adev->ip_blocks[i].version->funcs->name, r); } - adev->ip_block_status[i].hw = false; + adev->ip_blocks[i].status.hw = false; break; } } for (i = adev->num_ip_blocks - 1; i >= 0; i--) { - if (!adev->ip_block_status[i].hw) + if (!adev->ip_blocks[i].status.hw) continue; - if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { amdgpu_wb_fini(adev); amdgpu_vram_scratch_fini(adev); } - /* ungate blocks before hw fini so that we can shutdown the blocks safely */ - r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, - AMD_CG_STATE_UNGATE); - if (r) { - DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); - return r; + + if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && + adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { + /* ungate blocks before hw fini so that we can shutdown the blocks safely */ + r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, + AMD_CG_STATE_UNGATE); + if (r) { + DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + return r; + } } - r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); + + r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); /* XXX handle errors */ if (r) { - DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); } - adev->ip_block_status[i].hw = false; + + adev->ip_blocks[i].status.hw = false; } for (i = adev->num_ip_blocks - 1; i >= 0; i--) { - if (!adev->ip_block_status[i].sw) + if (!adev->ip_blocks[i].status.sw) continue; - r = adev->ip_blocks[i].funcs->sw_fini((void *)adev); + r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); /* XXX handle errors */ if (r) { - DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); } - adev->ip_block_status[i].sw = false; - adev->ip_block_status[i].valid = false; + adev->ip_blocks[i].status.sw = false; + adev->ip_blocks[i].status.valid = false; } for (i = adev->num_ip_blocks - 1; i >= 0; i--) { - if (!adev->ip_block_status[i].late_initialized) + if (!adev->ip_blocks[i].status.late_initialized) continue; - if (adev->ip_blocks[i].funcs->late_fini) - adev->ip_blocks[i].funcs->late_fini((void *)adev); - adev->ip_block_status[i].late_initialized = false; + if (adev->ip_blocks[i].version->funcs->late_fini) + adev->ip_blocks[i].version->funcs->late_fini((void *)adev); + adev->ip_blocks[i].status.late_initialized = false; } return 0; } -static int amdgpu_suspend(struct amdgpu_device *adev) +int amdgpu_suspend(struct amdgpu_device *adev) { int i, r; @@ -1518,21 +1529,23 @@ static int amdgpu_suspend(struct amdgpu_device *adev) } for (i = adev->num_ip_blocks - 1; i >= 0; i--) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; /* ungate blocks so that suspend can properly shut them down */ if (i != AMD_IP_BLOCK_TYPE_SMC) { - r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, - AMD_CG_STATE_UNGATE); + r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, + AMD_CG_STATE_UNGATE); if (r) { - DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); } } /* XXX handle errors */ - r = adev->ip_blocks[i].funcs->suspend(adev); + r = adev->ip_blocks[i].version->funcs->suspend(adev); /* XXX handle errors */ if (r) { - DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_ERROR("suspend of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); } } @@ -1544,11 +1557,12 @@ static int amdgpu_resume(struct amdgpu_device *adev) int i, r; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - r = adev->ip_blocks[i].funcs->resume(adev); + r = adev->ip_blocks[i].version->funcs->resume(adev); if (r) { - DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); + DRM_ERROR("resume of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); return r; } } @@ -1599,7 +1613,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->vm_manager.vm_pte_funcs = NULL; adev->vm_manager.vm_pte_num_rings = 0; adev->gart.gart_funcs = NULL; - adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); + adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); adev->smc_rreg = &amdgpu_invalid_rreg; adev->smc_wreg = &amdgpu_invalid_wreg; @@ -1859,8 +1873,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev) amdgpu_fence_driver_fini(adev); amdgpu_fbdev_fini(adev); r = amdgpu_fini(adev); - kfree(adev->ip_block_status); - adev->ip_block_status = NULL; adev->accel_working = false; /* free i2c buses */ amdgpu_i2c_fini(adev); @@ -1956,7 +1968,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) r = amdgpu_suspend(adev); - /* evict remaining vram memory */ + /* evict remaining vram memory + * This second call to evict vram is to evict the gart page table + * using the CPU. + */ amdgpu_bo_evict_vram(adev); amdgpu_atombios_scratch_regs_save(adev); @@ -2098,13 +2113,13 @@ static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) bool asic_hang = false; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_blocks[i].funcs->check_soft_reset) - adev->ip_block_status[i].hang = - adev->ip_blocks[i].funcs->check_soft_reset(adev); - if (adev->ip_block_status[i].hang) { - DRM_INFO("IP block:%d is hang!\n", i); + if (adev->ip_blocks[i].version->funcs->check_soft_reset) + adev->ip_blocks[i].status.hang = + adev->ip_blocks[i].version->funcs->check_soft_reset(adev); + if (adev->ip_blocks[i].status.hang) { + DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); asic_hang = true; } } @@ -2116,11 +2131,11 @@ static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) int i, r = 0; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_block_status[i].hang && - adev->ip_blocks[i].funcs->pre_soft_reset) { - r = adev->ip_blocks[i].funcs->pre_soft_reset(adev); + if (adev->ip_blocks[i].status.hang && + adev->ip_blocks[i].version->funcs->pre_soft_reset) { + r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); if (r) return r; } @@ -2134,13 +2149,13 @@ static bool amdgpu_need_full_reset(struct amdgpu_device *adev) int i; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) || - (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) || - (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) || - (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) { - if (adev->ip_block_status[i].hang) { + if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || + (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || + (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || + (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { + if (adev->ip_blocks[i].status.hang) { DRM_INFO("Some block need full reset!\n"); return true; } @@ -2154,11 +2169,11 @@ static int amdgpu_soft_reset(struct amdgpu_device *adev) int i, r = 0; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_block_status[i].hang && - adev->ip_blocks[i].funcs->soft_reset) { - r = adev->ip_blocks[i].funcs->soft_reset(adev); + if (adev->ip_blocks[i].status.hang && + adev->ip_blocks[i].version->funcs->soft_reset) { + r = adev->ip_blocks[i].version->funcs->soft_reset(adev); if (r) return r; } @@ -2172,11 +2187,11 @@ static int amdgpu_post_soft_reset(struct amdgpu_device *adev) int i, r = 0; for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_block_status[i].valid) + if (!adev->ip_blocks[i].status.valid) continue; - if (adev->ip_block_status[i].hang && - adev->ip_blocks[i].funcs->post_soft_reset) - r = adev->ip_blocks[i].funcs->post_soft_reset(adev); + if (adev->ip_blocks[i].status.hang && + adev->ip_blocks[i].version->funcs->post_soft_reset) + r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); if (r) return r; } @@ -2195,7 +2210,7 @@ bool amdgpu_need_backup(struct amdgpu_device *adev) static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, struct amdgpu_ring *ring, struct amdgpu_bo *bo, - struct fence **fence) + struct dma_fence **fence) { uint32_t domain; int r; @@ -2311,30 +2326,30 @@ retry: if (need_full_reset && amdgpu_need_backup(adev)) { struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; struct amdgpu_bo *bo, *tmp; - struct fence *fence = NULL, *next = NULL; + struct dma_fence *fence = NULL, *next = NULL; DRM_INFO("recover vram bo from shadow\n"); mutex_lock(&adev->shadow_list_lock); list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); if (fence) { - r = fence_wait(fence, false); + r = dma_fence_wait(fence, false); if (r) { WARN(r, "recovery from shadow isn't comleted\n"); break; } } - fence_put(fence); + dma_fence_put(fence); fence = next; } mutex_unlock(&adev->shadow_list_lock); if (fence) { - r = fence_wait(fence, false); + r = dma_fence_wait(fence, false); if (r) WARN(r, "recovery from shadow isn't comleted\n"); } - fence_put(fence); + dma_fence_put(fence); } for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; @@ -2484,9 +2499,6 @@ int amdgpu_debugfs_add_files(struct amdgpu_device *adev, adev->debugfs_count = i; #if defined(CONFIG_DEBUG_FS) drm_debugfs_create_files(files, nfiles, - adev->ddev->control->debugfs_root, - adev->ddev->control); - drm_debugfs_create_files(files, nfiles, adev->ddev->primary->debugfs_root, adev->ddev->primary); #endif @@ -2501,9 +2513,6 @@ static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev) for (i = 0; i < adev->debugfs_count; i++) { drm_debugfs_remove_files(adev->debugfs[i].files, adev->debugfs[i].num_files, - adev->ddev->control); - drm_debugfs_remove_files(adev->debugfs[i].files, - adev->debugfs[i].num_files, adev->ddev->primary); } #endif @@ -2530,6 +2539,13 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, se_bank = (*pos >> 24) & 0x3FF; sh_bank = (*pos >> 34) & 0x3FF; instance_bank = (*pos >> 44) & 0x3FF; + + if (se_bank == 0x3FF) + se_bank = 0xFFFFFFFF; + if (sh_bank == 0x3FF) + sh_bank = 0xFFFFFFFF; + if (instance_bank == 0x3FF) + instance_bank = 0xFFFFFFFF; use_bank = 1; } else { use_bank = 0; @@ -2538,8 +2554,8 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, *pos &= 0x3FFFF; if (use_bank) { - if (sh_bank >= adev->gfx.config.max_sh_per_se || - se_bank >= adev->gfx.config.max_shader_engines) + if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || + (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) return -EINVAL; mutex_lock(&adev->grbm_idx_mutex); amdgpu_gfx_select_se_sh(adev, se_bank, @@ -2586,10 +2602,45 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, struct amdgpu_device *adev = f->f_inode->i_private; ssize_t result = 0; int r; + bool pm_pg_lock, use_bank; + unsigned instance_bank, sh_bank, se_bank; if (size & 0x3 || *pos & 0x3) return -EINVAL; + /* are we reading registers for which a PG lock is necessary? */ + pm_pg_lock = (*pos >> 23) & 1; + + if (*pos & (1ULL << 62)) { + se_bank = (*pos >> 24) & 0x3FF; + sh_bank = (*pos >> 34) & 0x3FF; + instance_bank = (*pos >> 44) & 0x3FF; + + if (se_bank == 0x3FF) + se_bank = 0xFFFFFFFF; + if (sh_bank == 0x3FF) + sh_bank = 0xFFFFFFFF; + if (instance_bank == 0x3FF) + instance_bank = 0xFFFFFFFF; + use_bank = 1; + } else { + use_bank = 0; + } + + *pos &= 0x3FFFF; + + if (use_bank) { + if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || + (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) + return -EINVAL; + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, se_bank, + sh_bank, instance_bank); + } + + if (pm_pg_lock) + mutex_lock(&adev->pm.mutex); + while (size) { uint32_t value; @@ -2608,6 +2659,14 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, size -= 4; } + if (use_bank) { + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + } + + if (pm_pg_lock) + mutex_unlock(&adev->pm.mutex); + return result; } @@ -2870,6 +2929,116 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, return !r ? 4 : r; } +static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + int r, x; + ssize_t result=0; + uint32_t offset, se, sh, cu, wave, simd, data[32]; + + if (size & 3 || *pos & 3) + return -EINVAL; + + /* decode offset */ + offset = (*pos & 0x7F); + se = ((*pos >> 7) & 0xFF); + sh = ((*pos >> 15) & 0xFF); + cu = ((*pos >> 23) & 0xFF); + wave = ((*pos >> 31) & 0xFF); + simd = ((*pos >> 37) & 0xFF); + + /* switch to the specific se/sh/cu */ + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, se, sh, cu); + + x = 0; + if (adev->gfx.funcs->read_wave_data) + adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); + + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + mutex_unlock(&adev->grbm_idx_mutex); + + if (!x) + return -EINVAL; + + while (size && (offset < x * 4)) { + uint32_t value; + + value = data[offset >> 2]; + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + offset += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + int r; + ssize_t result = 0; + uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; + + if (size & 3 || *pos & 3) + return -EINVAL; + + /* decode offset */ + offset = (*pos & 0xFFF); /* in dwords */ + se = ((*pos >> 12) & 0xFF); + sh = ((*pos >> 20) & 0xFF); + cu = ((*pos >> 28) & 0xFF); + wave = ((*pos >> 36) & 0xFF); + simd = ((*pos >> 44) & 0xFF); + thread = ((*pos >> 52) & 0xFF); + bank = ((*pos >> 60) & 1); + + data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + /* switch to the specific se/sh/cu */ + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, se, sh, cu); + + if (bank == 0) { + if (adev->gfx.funcs->read_wave_vgprs) + adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); + } else { + if (adev->gfx.funcs->read_wave_sgprs) + adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); + } + + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + mutex_unlock(&adev->grbm_idx_mutex); + + while (size) { + uint32_t value; + + value = data[offset++]; + r = put_user(value, (uint32_t *)buf); + if (r) { + result = r; + goto err; + } + + result += 4; + buf += 4; + size -= 4; + } + +err: + kfree(data); + return result; +} + static const struct file_operations amdgpu_debugfs_regs_fops = { .owner = THIS_MODULE, .read = amdgpu_debugfs_regs_read, @@ -2907,6 +3076,17 @@ static const struct file_operations amdgpu_debugfs_sensors_fops = { .llseek = default_llseek }; +static const struct file_operations amdgpu_debugfs_wave_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_wave_read, + .llseek = default_llseek +}; +static const struct file_operations amdgpu_debugfs_gpr_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_gpr_read, + .llseek = default_llseek +}; + static const struct file_operations *debugfs_regs[] = { &amdgpu_debugfs_regs_fops, &amdgpu_debugfs_regs_didt_fops, @@ -2914,6 +3094,8 @@ static const struct file_operations *debugfs_regs[] = { &amdgpu_debugfs_regs_smc_fops, &amdgpu_debugfs_gca_config_fops, &amdgpu_debugfs_sensors_fops, + &amdgpu_debugfs_wave_fops, + &amdgpu_debugfs_gpr_fops, }; static const char *debugfs_regs_names[] = { @@ -2923,6 +3105,8 @@ static const char *debugfs_regs_names[] = { "amdgpu_regs_smc", "amdgpu_gca_config", "amdgpu_sensors", + "amdgpu_wave", + "amdgpu_gpr", }; static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 083e2b429872..581601ca6b89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -35,29 +35,29 @@ #include <drm/drm_crtc_helper.h> #include <drm/drm_edid.h> -static void amdgpu_flip_callback(struct fence *f, struct fence_cb *cb) +static void amdgpu_flip_callback(struct dma_fence *f, struct dma_fence_cb *cb) { struct amdgpu_flip_work *work = container_of(cb, struct amdgpu_flip_work, cb); - fence_put(f); + dma_fence_put(f); schedule_work(&work->flip_work.work); } static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work, - struct fence **f) + struct dma_fence **f) { - struct fence *fence= *f; + struct dma_fence *fence= *f; if (fence == NULL) return false; *f = NULL; - if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) + if (!dma_fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) return true; - fence_put(fence); + dma_fence_put(fence); return false; } @@ -68,9 +68,9 @@ static void amdgpu_flip_work_func(struct work_struct *__work) struct amdgpu_flip_work *work = container_of(delayed_work, struct amdgpu_flip_work, flip_work); struct amdgpu_device *adev = work->adev; - struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; + struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; - struct drm_crtc *crtc = &amdgpuCrtc->base; + struct drm_crtc *crtc = &amdgpu_crtc->base; unsigned long flags; unsigned i; int vpos, hpos; @@ -85,14 +85,14 @@ static void amdgpu_flip_work_func(struct work_struct *__work) /* Wait until we're out of the vertical blank period before the one * targeted by the flip */ - if (amdgpuCrtc->enabled && + if (amdgpu_crtc->enabled && (amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, &vpos, &hpos, NULL, NULL, &crtc->hwmode) & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && (int)(work->target_vblank - - amdgpu_get_vblank_counter_kms(adev->ddev, amdgpuCrtc->crtc_id)) > 0) { + amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) { schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); return; } @@ -104,12 +104,12 @@ static void amdgpu_flip_work_func(struct work_struct *__work) adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); /* Set the flip status */ - amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; + amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; spin_unlock_irqrestore(&crtc->dev->event_lock, flags); DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", - amdgpuCrtc->crtc_id, amdgpuCrtc, work); + amdgpu_crtc->crtc_id, amdgpu_crtc, work); } @@ -187,7 +187,7 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc, goto cleanup; } - r = amdgpu_bo_pin_restricted(new_abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); + r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, &base); if (unlikely(r != 0)) { r = -EINVAL; DRM_ERROR("failed to pin new abo buffer before flip\n"); @@ -244,9 +244,9 @@ unreserve: cleanup: amdgpu_bo_unref(&work->old_abo); - fence_put(work->excl); + dma_fence_put(work->excl); for (i = 0; i < work->shared_count; ++i) - fence_put(work->shared[i]); + dma_fence_put(work->shared[i]); kfree(work->shared); kfree(work); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 14f57d9915e3..6ca0333ca4c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -553,9 +553,10 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) entry = (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *) ((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record)); } - for (i = 0; i < states->numEntries; i++) { - if (i >= AMDGPU_MAX_VCE_LEVELS) - break; + adev->pm.dpm.num_of_vce_states = + states->numEntries > AMD_MAX_VCE_LEVELS ? + AMD_MAX_VCE_LEVELS : states->numEntries; + for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { vce_clk = (VCEClockInfo *) ((u8 *)&array->entries[0] + (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); @@ -955,3 +956,12 @@ u8 amdgpu_encode_pci_lane_width(u32 lanes) return encoded_lanes[lanes]; } + +struct amd_vce_state* +amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx) +{ + if (idx < adev->pm.dpm.num_of_vce_states) + return &adev->pm.dpm.vce_states[idx]; + + return NULL; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index 3738a96c2619..955d6f21e2b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -23,6 +23,453 @@ #ifndef __AMDGPU_DPM_H__ #define __AMDGPU_DPM_H__ +enum amdgpu_int_thermal_type { + THERMAL_TYPE_NONE, + THERMAL_TYPE_EXTERNAL, + THERMAL_TYPE_EXTERNAL_GPIO, + THERMAL_TYPE_RV6XX, + THERMAL_TYPE_RV770, + THERMAL_TYPE_ADT7473_WITH_INTERNAL, + THERMAL_TYPE_EVERGREEN, + THERMAL_TYPE_SUMO, + THERMAL_TYPE_NI, + THERMAL_TYPE_SI, + THERMAL_TYPE_EMC2103_WITH_INTERNAL, + THERMAL_TYPE_CI, + THERMAL_TYPE_KV, +}; + +enum amdgpu_dpm_auto_throttle_src { + AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, + AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL +}; + +enum amdgpu_dpm_event_src { + AMDGPU_DPM_EVENT_SRC_ANALOG = 0, + AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, + AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, + AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, + AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 +}; + +#define SCLK_DEEP_SLEEP_MASK 0x8 + +struct amdgpu_ps { + u32 caps; /* vbios flags */ + u32 class; /* vbios flags */ + u32 class2; /* vbios flags */ + /* UVD clocks */ + u32 vclk; + u32 dclk; + /* VCE clocks */ + u32 evclk; + u32 ecclk; + bool vce_active; + enum amd_vce_level vce_level; + /* asic priv */ + void *ps_priv; +}; + +struct amdgpu_dpm_thermal { + /* thermal interrupt work */ + struct work_struct work; + /* low temperature threshold */ + int min_temp; + /* high temperature threshold */ + int max_temp; + /* was last interrupt low to high or high to low */ + bool high_to_low; + /* interrupt source */ + struct amdgpu_irq_src irq; +}; + +enum amdgpu_clk_action +{ + AMDGPU_SCLK_UP = 1, + AMDGPU_SCLK_DOWN +}; + +struct amdgpu_blacklist_clocks +{ + u32 sclk; + u32 mclk; + enum amdgpu_clk_action action; +}; + +struct amdgpu_clock_and_voltage_limits { + u32 sclk; + u32 mclk; + u16 vddc; + u16 vddci; +}; + +struct amdgpu_clock_array { + u32 count; + u32 *values; +}; + +struct amdgpu_clock_voltage_dependency_entry { + u32 clk; + u16 v; +}; + +struct amdgpu_clock_voltage_dependency_table { + u32 count; + struct amdgpu_clock_voltage_dependency_entry *entries; +}; + +union amdgpu_cac_leakage_entry { + struct { + u16 vddc; + u32 leakage; + }; + struct { + u16 vddc1; + u16 vddc2; + u16 vddc3; + }; +}; + +struct amdgpu_cac_leakage_table { + u32 count; + union amdgpu_cac_leakage_entry *entries; +}; + +struct amdgpu_phase_shedding_limits_entry { + u16 voltage; + u32 sclk; + u32 mclk; +}; + +struct amdgpu_phase_shedding_limits_table { + u32 count; + struct amdgpu_phase_shedding_limits_entry *entries; +}; + +struct amdgpu_uvd_clock_voltage_dependency_entry { + u32 vclk; + u32 dclk; + u16 v; +}; + +struct amdgpu_uvd_clock_voltage_dependency_table { + u8 count; + struct amdgpu_uvd_clock_voltage_dependency_entry *entries; +}; + +struct amdgpu_vce_clock_voltage_dependency_entry { + u32 ecclk; + u32 evclk; + u16 v; +}; + +struct amdgpu_vce_clock_voltage_dependency_table { + u8 count; + struct amdgpu_vce_clock_voltage_dependency_entry *entries; +}; + +struct amdgpu_ppm_table { + u8 ppm_design; + u16 cpu_core_number; + u32 platform_tdp; + u32 small_ac_platform_tdp; + u32 platform_tdc; + u32 small_ac_platform_tdc; + u32 apu_tdp; + u32 dgpu_tdp; + u32 dgpu_ulv_power; + u32 tj_max; +}; + +struct amdgpu_cac_tdp_table { + u16 tdp; + u16 configurable_tdp; + u16 tdc; + u16 battery_power_limit; + u16 small_power_limit; + u16 low_cac_leakage; + u16 high_cac_leakage; + u16 maximum_power_delivery_limit; +}; + +struct amdgpu_dpm_dynamic_state { + struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; + struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; + struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; + struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; + struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; + struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; + struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; + struct amdgpu_clock_array valid_sclk_values; + struct amdgpu_clock_array valid_mclk_values; + struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; + struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; + u32 mclk_sclk_ratio; + u32 sclk_mclk_delta; + u16 vddc_vddci_delta; + u16 min_vddc_for_pcie_gen2; + struct amdgpu_cac_leakage_table cac_leakage_table; + struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; + struct amdgpu_ppm_table *ppm_table; + struct amdgpu_cac_tdp_table *cac_tdp_table; +}; + +struct amdgpu_dpm_fan { + u16 t_min; + u16 t_med; + u16 t_high; + u16 pwm_min; + u16 pwm_med; + u16 pwm_high; + u8 t_hyst; + u32 cycle_delay; + u16 t_max; + u8 control_mode; + u16 default_max_fan_pwm; + u16 default_fan_output_sensitivity; + u16 fan_output_sensitivity; + bool ucode_fan_control; +}; + +enum amdgpu_pcie_gen { + AMDGPU_PCIE_GEN1 = 0, + AMDGPU_PCIE_GEN2 = 1, + AMDGPU_PCIE_GEN3 = 2, + AMDGPU_PCIE_GEN_INVALID = 0xffff +}; + +enum amdgpu_dpm_forced_level { + AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, + AMDGPU_DPM_FORCED_LEVEL_LOW = 1, + AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, + AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, +}; + +struct amdgpu_dpm_funcs { + int (*get_temperature)(struct amdgpu_device *adev); + int (*pre_set_power_state)(struct amdgpu_device *adev); + int (*set_power_state)(struct amdgpu_device *adev); + void (*post_set_power_state)(struct amdgpu_device *adev); + void (*display_configuration_changed)(struct amdgpu_device *adev); + u32 (*get_sclk)(struct amdgpu_device *adev, bool low); + u32 (*get_mclk)(struct amdgpu_device *adev, bool low); + void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); + void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); + int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); + bool (*vblank_too_short)(struct amdgpu_device *adev); + void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); + void (*powergate_vce)(struct amdgpu_device *adev, bool gate); + void (*enable_bapm)(struct amdgpu_device *adev, bool enable); + void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); + u32 (*get_fan_control_mode)(struct amdgpu_device *adev); + int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); + int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); + int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask); + int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf); + int (*get_sclk_od)(struct amdgpu_device *adev); + int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value); + int (*get_mclk_od)(struct amdgpu_device *adev); + int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value); + int (*check_state_equal)(struct amdgpu_device *adev, + struct amdgpu_ps *cps, + struct amdgpu_ps *rps, + bool *equal); + + struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx); +}; + +#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) +#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) +#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) +#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) +#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) +#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) +#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) + +#define amdgpu_dpm_read_sensor(adev, idx, value) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \ + -EINVAL) + +#define amdgpu_dpm_get_temperature(adev) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ + (adev)->pm.funcs->get_temperature((adev))) + +#define amdgpu_dpm_set_fan_control_mode(adev, m) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ + (adev)->pm.funcs->set_fan_control_mode((adev), (m))) + +#define amdgpu_dpm_get_fan_control_mode(adev) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ + (adev)->pm.funcs->get_fan_control_mode((adev))) + +#define amdgpu_dpm_set_fan_speed_percent(adev, s) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ + (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) + +#define amdgpu_dpm_get_fan_speed_percent(adev, s) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ + (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) + +#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \ + -EINVAL) + +#define amdgpu_dpm_get_sclk(adev, l) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ + (adev)->pm.funcs->get_sclk((adev), (l))) + +#define amdgpu_dpm_get_mclk(adev, l) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ + (adev)->pm.funcs->get_mclk((adev), (l))) + + +#define amdgpu_dpm_force_performance_level(adev, l) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ + (adev)->pm.funcs->force_performance_level((adev), (l))) + +#define amdgpu_dpm_powergate_uvd(adev, g) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ + (adev)->pm.funcs->powergate_uvd((adev), (g))) + +#define amdgpu_dpm_powergate_vce(adev, g) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ + (adev)->pm.funcs->powergate_vce((adev), (g))) + +#define amdgpu_dpm_get_current_power_state(adev) \ + (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) + +#define amdgpu_dpm_get_performance_level(adev) \ + (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) + +#define amdgpu_dpm_get_pp_num_states(adev, data) \ + (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) + +#define amdgpu_dpm_get_pp_table(adev, table) \ + (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) + +#define amdgpu_dpm_set_pp_table(adev, buf, size) \ + (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) + +#define amdgpu_dpm_print_clock_levels(adev, type, buf) \ + (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) + +#define amdgpu_dpm_force_clock_level(adev, type, level) \ + (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) + +#define amdgpu_dpm_get_sclk_od(adev) \ + (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle) + +#define amdgpu_dpm_set_sclk_od(adev, value) \ + (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value) + +#define amdgpu_dpm_get_mclk_od(adev) \ + ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) + +#define amdgpu_dpm_set_mclk_od(adev, value) \ + ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) + +#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ + (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) + +#define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal)) + +#define amdgpu_dpm_get_vce_clock_state(adev, i) \ + ((adev)->pp_enabled ? \ + (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \ + (adev)->pm.funcs->get_vce_clock_state((adev), (i))) + +struct amdgpu_dpm { + struct amdgpu_ps *ps; + /* number of valid power states */ + int num_ps; + /* current power state that is active */ + struct amdgpu_ps *current_ps; + /* requested power state */ + struct amdgpu_ps *requested_ps; + /* boot up power state */ + struct amdgpu_ps *boot_ps; + /* default uvd power state */ + struct amdgpu_ps *uvd_ps; + /* vce requirements */ + u32 num_of_vce_states; + struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; + enum amd_vce_level vce_level; + enum amd_pm_state_type state; + enum amd_pm_state_type user_state; + enum amd_pm_state_type last_state; + enum amd_pm_state_type last_user_state; + u32 platform_caps; + u32 voltage_response_time; + u32 backbias_response_time; + void *priv; + u32 new_active_crtcs; + int new_active_crtc_count; + u32 current_active_crtcs; + int current_active_crtc_count; + struct amdgpu_dpm_dynamic_state dyn_state; + struct amdgpu_dpm_fan fan; + u32 tdp_limit; + u32 near_tdp_limit; + u32 near_tdp_limit_adjusted; + u32 sq_ramping_threshold; + u32 cac_leakage; + u16 tdp_od_limit; + u32 tdp_adjustment; + u16 load_line_slope; + bool power_control; + bool ac_power; + /* special states active */ + bool thermal_active; + bool uvd_active; + bool vce_active; + /* thermal handling */ + struct amdgpu_dpm_thermal thermal; + /* forced levels */ + enum amdgpu_dpm_forced_level forced_level; +}; + +struct amdgpu_pm { + struct mutex mutex; + u32 current_sclk; + u32 current_mclk; + u32 default_sclk; + u32 default_mclk; + struct amdgpu_i2c_chan *i2c_bus; + /* internal thermal controller on rv6xx+ */ + enum amdgpu_int_thermal_type int_thermal_type; + struct device *int_hwmon_dev; + /* fan control parameters */ + bool no_fan; + u8 fan_pulses_per_revolution; + u8 fan_min_rpm; + u8 fan_max_rpm; + /* dpm */ + bool dpm_enabled; + bool sysfs_initialized; + struct amdgpu_dpm dpm; + const struct firmware *fw; /* SMC firmware */ + uint32_t fw_version; + const struct amdgpu_dpm_funcs *funcs; + uint32_t pcie_gen_mask; + uint32_t pcie_mlw_mask; + struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ +}; + #define R600_SSTU_DFLT 0 #define R600_SST_DFLT 0x00C8 @@ -82,4 +529,7 @@ u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev, u16 default_lanes); u8 amdgpu_encode_pci_lane_width(u32 lanes); +struct amd_vce_state* +amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 71ed27eb3dde..8cb937b2bfcc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -58,9 +58,10 @@ * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. * - 3.7.0 - Add support for VCE clock list packet * - 3.8.0 - Add support raster config init in the kernel + * - 3.9.0 - Add support for memory query info about VRAM and GTT. */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 8 +#define KMS_DRIVER_MINOR 9 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; @@ -85,12 +86,13 @@ int amdgpu_vm_size = 64; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; +int amdgpu_vram_page_split = 1024; int amdgpu_exp_hw_support = 0; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; int amdgpu_powerplay = -1; -int amdgpu_powercontainment = 1; -int amdgpu_sclk_deep_sleep_en = 1; +int amdgpu_no_evict = 0; +int amdgpu_direct_gma_size = 0; unsigned amdgpu_pcie_gen_cap = 0; unsigned amdgpu_pcie_lane_cap = 0; unsigned amdgpu_cg_mask = 0xffffffff; @@ -165,6 +167,9 @@ module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); +MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)"); +module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); + MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); @@ -177,14 +182,14 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); module_param_named(powerplay, amdgpu_powerplay, int, 0444); -MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)"); -module_param_named(powercontainment, amdgpu_powercontainment, int, 0444); - MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444); -MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)"); -module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444); +MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); +module_param_named(no_evict, amdgpu_no_evict, int, 0444); + +MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); +module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); @@ -201,7 +206,8 @@ module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); -MODULE_PARM_DESC(virtual_display, "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x;xxxx:xx:xx.x)"); +MODULE_PARM_DESC(virtual_display, + "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); static const struct pci_device_id pciidlist[] = { @@ -381,6 +387,7 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, /* fiji */ {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, + {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, /* carrizo */ {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, @@ -479,12 +486,15 @@ amdgpu_pci_remove(struct pci_dev *pdev) static void amdgpu_pci_shutdown(struct pci_dev *pdev) { + struct drm_device *dev = pci_get_drvdata(pdev); + struct amdgpu_device *adev = dev->dev_private; + /* if we are running in a VM, make sure the device * torn down properly on reboot/shutdown. * unfortunately we can't detect certain * hypervisors so just do this all the time. */ - amdgpu_pci_remove(pdev); + amdgpu_suspend(adev); } static int amdgpu_pmops_suspend(struct device *dev) @@ -735,8 +745,20 @@ static struct pci_driver amdgpu_kms_pci_driver = { static int __init amdgpu_init(void) { - amdgpu_sync_init(); - amdgpu_fence_slab_init(); + int r; + + r = amdgpu_sync_init(); + if (r) + goto error_sync; + + r = amdgpu_fence_slab_init(); + if (r) + goto error_fence; + + r = amd_sched_fence_slab_init(); + if (r) + goto error_sched; + if (vgacon_text_force()) { DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); return -EINVAL; @@ -748,6 +770,15 @@ static int __init amdgpu_init(void) amdgpu_register_atpx_handler(); /* let modprobe override vga console setting */ return drm_pci_init(driver, pdriver); + +error_sched: + amdgpu_fence_slab_fini(); + +error_fence: + amdgpu_sync_fini(); + +error_sync: + return r; } static void __exit amdgpu_exit(void) @@ -756,6 +787,7 @@ static void __exit amdgpu_exit(void) drm_pci_exit(driver, pdriver); amdgpu_unregister_atpx_handler(); amdgpu_sync_fini(); + amd_sched_fence_slab_fini(); amdgpu_fence_slab_fini(); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 9fb8aa4d6bae..24629bec181a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -75,27 +75,21 @@ amdgpufb_release(struct fb_info *info, int user) static struct fb_ops amdgpufb_ops = { .owner = THIS_MODULE, + DRM_FB_HELPER_DEFAULT_OPS, .fb_open = amdgpufb_open, .fb_release = amdgpufb_release, - .fb_check_var = drm_fb_helper_check_var, - .fb_set_par = drm_fb_helper_set_par, .fb_fillrect = drm_fb_helper_cfb_fillrect, .fb_copyarea = drm_fb_helper_cfb_copyarea, .fb_imageblit = drm_fb_helper_cfb_imageblit, - .fb_pan_display = drm_fb_helper_pan_display, - .fb_blank = drm_fb_helper_blank, - .fb_setcmap = drm_fb_helper_setcmap, - .fb_debug_enter = drm_fb_helper_debug_enter, - .fb_debug_leave = drm_fb_helper_debug_leave, }; -int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled) +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) { int aligned = width; int pitch_mask = 0; - switch (bpp / 8) { + switch (cpp) { case 1: pitch_mask = 255; break; @@ -110,7 +104,7 @@ int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tile aligned += pitch_mask; aligned &= ~pitch_mask; - return aligned; + return aligned * cpp; } static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) @@ -139,20 +133,21 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, int ret; int aligned_size, size; int height = mode_cmd->height; - u32 bpp, depth; + u32 cpp; - drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); + cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0); /* need to align pitch with crtc limits */ - mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, bpp, - fb_tiled) * ((bpp + 1) / 8); + mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, + fb_tiled); height = ALIGN(mode_cmd->height, 8); size = mode_cmd->pitches[0] * height; aligned_size = ALIGN(size, PAGE_SIZE); ret = amdgpu_gem_object_create(adev, aligned_size, 0, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, true, &gobj); if (ret) { printk(KERN_ERR "failed to allocate framebuffer (%d)\n", @@ -176,7 +171,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, } - ret = amdgpu_bo_pin_restricted(abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL); + ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL); if (ret) { amdgpu_bo_unreserve(abo); goto out_unref; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 77b34ec92632..7b60fb79c3a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -48,7 +48,7 @@ */ struct amdgpu_fence { - struct fence base; + struct dma_fence base; /* RB, DMA, etc. */ struct amdgpu_ring *ring; @@ -74,8 +74,8 @@ void amdgpu_fence_slab_fini(void) /* * Cast helper */ -static const struct fence_ops amdgpu_fence_ops; -static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) +static const struct dma_fence_ops amdgpu_fence_ops; +static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) { struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); @@ -131,11 +131,11 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring) * Emits a fence command on the requested ring (all asics). * Returns 0 on success, -ENOMEM on failure. */ -int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f) +int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f) { struct amdgpu_device *adev = ring->adev; struct amdgpu_fence *fence; - struct fence *old, **ptr; + struct dma_fence *old, **ptr; uint32_t seq; fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); @@ -144,10 +144,10 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f) seq = ++ring->fence_drv.sync_seq; fence->ring = ring; - fence_init(&fence->base, &amdgpu_fence_ops, - &ring->fence_drv.lock, - adev->fence_context + ring->idx, - seq); + dma_fence_init(&fence->base, &amdgpu_fence_ops, + &ring->fence_drv.lock, + adev->fence_context + ring->idx, + seq); amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, seq, AMDGPU_FENCE_FLAG_INT); @@ -156,12 +156,12 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f) * emitting the fence would mess up the hardware ring buffer. */ old = rcu_dereference_protected(*ptr, 1); - if (old && !fence_is_signaled(old)) { + if (old && !dma_fence_is_signaled(old)) { DRM_INFO("rcu slot is busy\n"); - fence_wait(old, false); + dma_fence_wait(old, false); } - rcu_assign_pointer(*ptr, fence_get(&fence->base)); + rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); *f = &fence->base; @@ -212,7 +212,7 @@ void amdgpu_fence_process(struct amdgpu_ring *ring) seq &= drv->num_fences_mask; do { - struct fence *fence, **ptr; + struct dma_fence *fence, **ptr; ++last_seq; last_seq &= drv->num_fences_mask; @@ -225,13 +225,13 @@ void amdgpu_fence_process(struct amdgpu_ring *ring) if (!fence) continue; - r = fence_signal(fence); + r = dma_fence_signal(fence); if (!r) - FENCE_TRACE(fence, "signaled from irq context\n"); + DMA_FENCE_TRACE(fence, "signaled from irq context\n"); else BUG(); - fence_put(fence); + dma_fence_put(fence); } while (last_seq != seq); } @@ -261,7 +261,7 @@ static void amdgpu_fence_fallback(unsigned long arg) int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) { uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq); - struct fence *fence, **ptr; + struct dma_fence *fence, **ptr; int r; if (!seq) @@ -270,14 +270,14 @@ int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; rcu_read_lock(); fence = rcu_dereference(*ptr); - if (!fence || !fence_get_rcu(fence)) { + if (!fence || !dma_fence_get_rcu(fence)) { rcu_read_unlock(); return 0; } rcu_read_unlock(); - r = fence_wait(fence, false); - fence_put(fence); + r = dma_fence_wait(fence, false); + dma_fence_put(fence); return r; } @@ -382,24 +382,27 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, if (!ring->fence_drv.fences) return -ENOMEM; - timeout = msecs_to_jiffies(amdgpu_lockup_timeout); - if (timeout == 0) { - /* - * FIXME: - * Delayed workqueue cannot use it directly, - * so the scheduler will not use delayed workqueue if - * MAX_SCHEDULE_TIMEOUT is set. - * Currently keep it simple and silly. - */ - timeout = MAX_SCHEDULE_TIMEOUT; - } - r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, - num_hw_submission, - timeout, ring->name); - if (r) { - DRM_ERROR("Failed to create scheduler on ring %s.\n", - ring->name); - return r; + /* No need to setup the GPU scheduler for KIQ ring */ + if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { + timeout = msecs_to_jiffies(amdgpu_lockup_timeout); + if (timeout == 0) { + /* + * FIXME: + * Delayed workqueue cannot use it directly, + * so the scheduler will not use delayed workqueue if + * MAX_SCHEDULE_TIMEOUT is set. + * Currently keep it simple and silly. + */ + timeout = MAX_SCHEDULE_TIMEOUT; + } + r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, + num_hw_submission, + timeout, ring->name); + if (r) { + DRM_ERROR("Failed to create scheduler on ring %s.\n", + ring->name); + return r; + } } return 0; @@ -453,7 +456,7 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) amd_sched_fini(&ring->sched); del_timer_sync(&ring->fence_drv.fallback_timer); for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) - fence_put(ring->fence_drv.fences[j]); + dma_fence_put(ring->fence_drv.fences[j]); kfree(ring->fence_drv.fences); ring->fence_drv.fences = NULL; ring->fence_drv.initialized = false; @@ -542,12 +545,12 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) * Common fence implementation */ -static const char *amdgpu_fence_get_driver_name(struct fence *fence) +static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) { return "amdgpu"; } -static const char *amdgpu_fence_get_timeline_name(struct fence *f) +static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) { struct amdgpu_fence *fence = to_amdgpu_fence(f); return (const char *)fence->ring->name; @@ -561,7 +564,7 @@ static const char *amdgpu_fence_get_timeline_name(struct fence *f) * to fence_queue that checks if this fence is signaled, and if so it * signals the fence and removes itself. */ -static bool amdgpu_fence_enable_signaling(struct fence *f) +static bool amdgpu_fence_enable_signaling(struct dma_fence *f) { struct amdgpu_fence *fence = to_amdgpu_fence(f); struct amdgpu_ring *ring = fence->ring; @@ -569,7 +572,7 @@ static bool amdgpu_fence_enable_signaling(struct fence *f) if (!timer_pending(&ring->fence_drv.fallback_timer)) amdgpu_fence_schedule_fallback(ring); - FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); + DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); return true; } @@ -583,7 +586,7 @@ static bool amdgpu_fence_enable_signaling(struct fence *f) */ static void amdgpu_fence_free(struct rcu_head *rcu) { - struct fence *f = container_of(rcu, struct fence, rcu); + struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); struct amdgpu_fence *fence = to_amdgpu_fence(f); kmem_cache_free(amdgpu_fence_slab, fence); } @@ -596,16 +599,16 @@ static void amdgpu_fence_free(struct rcu_head *rcu) * This function is called when the reference count becomes zero. * It just RCU schedules freeing up the fence. */ -static void amdgpu_fence_release(struct fence *f) +static void amdgpu_fence_release(struct dma_fence *f) { call_rcu(&f->rcu, amdgpu_fence_free); } -static const struct fence_ops amdgpu_fence_ops = { +static const struct dma_fence_ops amdgpu_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_fence_get_timeline_name, .enable_signaling = amdgpu_fence_enable_signaling, - .wait = fence_default_wait, + .wait = dma_fence_default_wait, .release = amdgpu_fence_release, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 21a1242fc13b..964d2a946ed5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -126,7 +126,8 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) if (adev->gart.robj == NULL) { r = amdgpu_bo_create(adev, adev->gart.table_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->gart.robj); if (r) { return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index a7ea9a3b454e..cd62f6ffde2a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -116,10 +116,11 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev) * Call from drm_gem_handle_create which appear in both new and open ioctl * case. */ -int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv) { struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); - struct amdgpu_device *adev = abo->adev; + struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; @@ -142,7 +143,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - struct amdgpu_device *adev = bo->adev; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -407,10 +408,8 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, return -ENOENT; } robj = gem_to_amdgpu_bo(gobj); - if (timeout == 0) - ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true); - else - ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout); + ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, + timeout); /* ret == 0 means not signaled, * ret > 0 means signaled @@ -470,6 +469,16 @@ out: return r; } +static int amdgpu_gem_va_check(void *param, struct amdgpu_bo *bo) +{ + unsigned domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); + + /* if anything is swapped out don't swap it in here, + just abort and wait for the next CS */ + + return domain == AMDGPU_GEM_DOMAIN_CPU ? -ERESTARTSYS : 0; +} + /** * amdgpu_gem_va_update_vm -update the bo_va in its VM * @@ -480,7 +489,8 @@ out: * vital here, so they are not reported back to userspace. */ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, - struct amdgpu_bo_va *bo_va, uint32_t operation) + struct amdgpu_bo_va *bo_va, + uint32_t operation) { struct ttm_validate_buffer tv, *entry; struct amdgpu_bo_list_entry vm_pd; @@ -503,7 +513,6 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, if (r) goto error_print; - amdgpu_vm_get_pt_bos(adev, bo_va->vm, &duplicates); list_for_each_entry(entry, &list, head) { domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); /* if anything is swapped out don't swap it in here, @@ -511,13 +520,10 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, if (domain == AMDGPU_GEM_DOMAIN_CPU) goto error_unreserve; } - list_for_each_entry(entry, &duplicates, head) { - domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); - /* if anything is swapped out don't swap it in here, - just abort and wait for the next CS */ - if (domain == AMDGPU_GEM_DOMAIN_CPU) - goto error_unreserve; - } + r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check, + NULL); + if (r) + goto error_unreserve; r = amdgpu_vm_update_page_directory(adev, bo_va->vm); if (r) @@ -538,8 +544,6 @@ error_print: DRM_ERROR("Couldn't update BO_VA (%d)\n", r); } - - int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -549,7 +553,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_bo *abo; struct amdgpu_bo_va *bo_va; - struct ttm_validate_buffer tv, tv_pd; + struct amdgpu_bo_list_entry vm_pd; + struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct list_head list, duplicates; uint32_t invalid_flags, va_flags = 0; @@ -594,9 +599,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, tv.shared = true; list_add(&tv.head, &list); - tv_pd.bo = &fpriv->vm.page_directory->tbo; - tv_pd.shared = true; - list_add(&tv_pd.head, &list); + amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); if (r) { @@ -704,7 +707,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, uint32_t handle; int r; - args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); + args->pitch = amdgpu_align_pitch(adev, args->width, + DIV_ROUND_UP(args->bpp, 8), 0); args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index a074edd95c70..01a42b6a69a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -24,6 +24,7 @@ */ #include <drm/drmP.h> #include "amdgpu.h" +#include "amdgpu_gfx.h" /* * GPU scratch registers helpers function. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 51321e154c09..e02044086445 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -27,6 +27,7 @@ int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); -unsigned amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh); +void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, + unsigned max_sh); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index f86c84427778..00f46b0e076d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -164,10 +164,13 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, spin_unlock(&mgr->lock); node = kzalloc(sizeof(*node), GFP_KERNEL); - if (!node) - return -ENOMEM; + if (!node) { + r = -ENOMEM; + goto err_out; + } node->start = AMDGPU_BO_INVALID_OFFSET; + node->size = mem->num_pages; mem->mm_node = node; if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) { @@ -175,12 +178,20 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, if (unlikely(r)) { kfree(node); mem->mm_node = NULL; + r = 0; + goto err_out; } } else { mem->start = node->start; } return 0; +err_out: + spin_lock(&mgr->lock); + mgr->available += mem->num_pages; + spin_unlock(&mgr->lock); + + return r; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 6a6c86c9c169..216a9572d946 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -89,7 +89,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, * Free an IB (all asics). */ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, - struct fence *f) + struct dma_fence *f) { amdgpu_sa_bo_free(adev, &ib->sa_bo, f); } @@ -116,8 +116,8 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, * to SI there was just a DE IB. */ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, - struct amdgpu_ib *ibs, struct fence *last_vm_update, - struct amdgpu_job *job, struct fence **f) + struct amdgpu_ib *ibs, struct dma_fence *last_vm_update, + struct amdgpu_job *job, struct dma_fence **f) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib *ib = &ibs[0]; @@ -152,8 +152,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, return -EINVAL; } - alloc_size = amdgpu_ring_get_dma_frame_size(ring) + - num_ibs * amdgpu_ring_get_emit_ib_size(ring); + alloc_size = ring->funcs->emit_frame_size + num_ibs * + ring->funcs->emit_ib_size; r = amdgpu_ring_alloc(ring, alloc_size); if (r) { @@ -161,7 +161,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, return r; } - if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec) + if (ring->funcs->init_cond_exec) patch_offset = amdgpu_ring_init_cond_exec(ring); if (vm) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 9fa809876339..fb902932f571 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -424,15 +424,6 @@ int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, return 0; } -bool amdgpu_irq_get_delayed(struct amdgpu_device *adev, - struct amdgpu_irq_src *src, - unsigned type) -{ - if ((type >= src->num_types) || !src->enabled_types) - return false; - return atomic_inc_return(&src->enabled_types[type]) == 1; -} - /** * amdgpu_irq_put - disable interrupt * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index f016464035b8..1642f4108297 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -88,9 +88,6 @@ int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type); int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type); -bool amdgpu_irq_get_delayed(struct amdgpu_device *adev, - struct amdgpu_irq_src *src, - unsigned type); int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type); bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 8c5807994073..a0de6286c453 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -81,7 +81,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, void amdgpu_job_free_resources(struct amdgpu_job *job) { - struct fence *f; + struct dma_fence *f; unsigned i; /* use sched fence if available */ @@ -95,7 +95,7 @@ static void amdgpu_job_free_cb(struct amd_sched_job *s_job) { struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base); - fence_put(job->fence); + dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); kfree(job); } @@ -104,14 +104,14 @@ void amdgpu_job_free(struct amdgpu_job *job) { amdgpu_job_free_resources(job); - fence_put(job->fence); + dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); kfree(job); } int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, struct amd_sched_entity *entity, void *owner, - struct fence **f) + struct dma_fence **f) { int r; job->ring = ring; @@ -125,19 +125,19 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, job->owner = owner; job->fence_ctx = entity->fence_context; - *f = fence_get(&job->base.s_fence->finished); + *f = dma_fence_get(&job->base.s_fence->finished); amdgpu_job_free_resources(job); amd_sched_entity_push_job(&job->base); return 0; } -static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) +static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) { struct amdgpu_job *job = to_amdgpu_job(sched_job); struct amdgpu_vm *vm = job->vm; - struct fence *fence = amdgpu_sync_get_fence(&job->sync); + struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync); if (fence == NULL && vm && !job->vm_id) { struct amdgpu_ring *ring = job->ring; @@ -155,9 +155,9 @@ static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) return fence; } -static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job) +static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) { - struct fence *fence = NULL; + struct dma_fence *fence = NULL; struct amdgpu_job *job; int r; @@ -176,8 +176,8 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job) DRM_ERROR("Error scheduling IBs (%d)\n", r); /* if gpu reset, hw fence will be replaced here */ - fence_put(job->fence); - job->fence = fence_get(fence); + dma_fence_put(job->fence); + job->fence = dma_fence_get(fence); amdgpu_job_free_resources(job); return fence; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 203d98b00555..9af87eaf8ee3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -99,6 +99,8 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) if ((amdgpu_runtime_pm != 0) && amdgpu_has_atpx() && + (amdgpu_is_atpx_hybrid() || + amdgpu_has_atpx_dgpu_power_cntl()) && ((flags & AMD_IS_APU) == 0)) flags |= AMD_IS_PX; @@ -306,10 +308,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file } for (i = 0; i < adev->num_ip_blocks; i++) { - if (adev->ip_blocks[i].type == type && - adev->ip_block_status[i].valid) { - ip.hw_ip_version_major = adev->ip_blocks[i].major; - ip.hw_ip_version_minor = adev->ip_blocks[i].minor; + if (adev->ip_blocks[i].version->type == type && + adev->ip_blocks[i].status.valid) { + ip.hw_ip_version_major = adev->ip_blocks[i].version->major; + ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor; ip.capabilities_flags = 0; ip.available_rings = ring_mask; ip.ib_start_alignment = ib_start_alignment; @@ -345,8 +347,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file } for (i = 0; i < adev->num_ip_blocks; i++) - if (adev->ip_blocks[i].type == type && - adev->ip_block_status[i].valid && + if (adev->ip_blocks[i].version->type == type && + adev->ip_blocks[i].status.valid && count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) count++; @@ -411,6 +413,36 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file return copy_to_user(out, &vram_gtt, min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; } + case AMDGPU_INFO_MEMORY: { + struct drm_amdgpu_memory_info mem; + + memset(&mem, 0, sizeof(mem)); + mem.vram.total_heap_size = adev->mc.real_vram_size; + mem.vram.usable_heap_size = + adev->mc.real_vram_size - adev->vram_pin_size; + mem.vram.heap_usage = atomic64_read(&adev->vram_usage); + mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; + + mem.cpu_accessible_vram.total_heap_size = + adev->mc.visible_vram_size; + mem.cpu_accessible_vram.usable_heap_size = + adev->mc.visible_vram_size - + (adev->vram_pin_size - adev->invisible_pin_size); + mem.cpu_accessible_vram.heap_usage = + atomic64_read(&adev->vram_vis_usage); + mem.cpu_accessible_vram.max_allocation = + mem.cpu_accessible_vram.usable_heap_size * 3 / 4; + + mem.gtt.total_heap_size = adev->mc.gtt_size; + mem.gtt.usable_heap_size = + adev->mc.gtt_size - adev->gart_pin_size; + mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); + mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; + + return copy_to_user(out, &mem, + min((size_t)size, sizeof(mem))) + ? -EFAULT : 0; + } case AMDGPU_INFO_READ_MMR_REG: { unsigned n, alloc_size; uint32_t *regs; @@ -473,6 +505,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.ids_flags = 0; if (adev->flags & AMD_IS_APU) dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; + if (amdgpu_sriov_vf(adev)) + dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); @@ -492,6 +526,50 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file return copy_to_user(out, &dev_info, min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; } + case AMDGPU_INFO_VCE_CLOCK_TABLE: { + unsigned i; + struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; + struct amd_vce_state *vce_state; + + for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { + vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); + if (vce_state) { + vce_clk_table.entries[i].sclk = vce_state->sclk; + vce_clk_table.entries[i].mclk = vce_state->mclk; + vce_clk_table.entries[i].eclk = vce_state->evclk; + vce_clk_table.num_valid_entries++; + } + } + + return copy_to_user(out, &vce_clk_table, + min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; + } + case AMDGPU_INFO_VBIOS: { + uint32_t bios_size = adev->bios_size; + + switch (info->vbios_info.type) { + case AMDGPU_INFO_VBIOS_SIZE: + return copy_to_user(out, &bios_size, + min((size_t)size, sizeof(bios_size))) + ? -EFAULT : 0; + case AMDGPU_INFO_VBIOS_IMAGE: { + uint8_t *bios; + uint32_t bios_offset = info->vbios_info.offset; + + if (bios_offset >= bios_size) + return -EINVAL; + + bios = adev->bios + bios_offset; + return copy_to_user(out, bios, + min((size_t)size, (size_t)(bios_size - bios_offset))) + ? -EFAULT : 0; + } + default: + DRM_DEBUG_KMS("Invalid request %d\n", + info->vbios_info.type); + return -EINVAL; + } + } default: DRM_DEBUG_KMS("Invalid request %d\n", info->query); return -EINVAL; @@ -773,6 +851,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c index 32fa7b7913f7..7ea3cacf9f9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c @@ -285,7 +285,7 @@ free_rmn: int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) { unsigned long end = addr + amdgpu_bo_size(bo) - 1; - struct amdgpu_device *adev = bo->adev; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_mn *rmn; struct amdgpu_mn_node *node = NULL; struct list_head bos; @@ -340,7 +340,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) */ void amdgpu_mn_unregister(struct amdgpu_bo *bo) { - struct amdgpu_device *adev = bo->adev; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_mn *rmn; struct list_head *head; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 7b0eff7d060b..202b4176b74e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -271,8 +271,6 @@ struct amdgpu_display_funcs { u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); /* wait for vblank */ void (*vblank_wait)(struct amdgpu_device *adev, int crtc); - /* is dce hung */ - bool (*is_display_hung)(struct amdgpu_device *adev); /* set backlight level */ void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, u8 level); @@ -341,8 +339,6 @@ struct amdgpu_mode_info { int num_dig; /* number of dig blocks */ int disp_priority; const struct amdgpu_display_funcs *funcs; - struct hrtimer vblank_timer; - enum amdgpu_interrupt_state vsync_timer_enabled; }; #define AMDGPU_MAX_BL_LEVEL 0xFF @@ -413,6 +409,9 @@ struct amdgpu_crtc { u32 wm_high; u32 lb_vblank_lead_lines; struct drm_display_mode hw_mode; + /* for virtual dce */ + struct hrtimer vblank_timer; + enum amdgpu_interrupt_state vsync_timer_enabled; }; struct amdgpu_encoder_atom_dig { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f3efb1c5dae9..bf79b73e1538 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -88,18 +88,19 @@ static void amdgpu_update_memory_usage(struct amdgpu_device *adev, static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) { + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); struct amdgpu_bo *bo; bo = container_of(tbo, struct amdgpu_bo, tbo); - amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL); + amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL); drm_gem_object_release(&bo->gem_base); amdgpu_bo_unref(&bo->parent); if (!list_empty(&bo->shadow_list)) { - mutex_lock(&bo->adev->shadow_list_lock); + mutex_lock(&adev->shadow_list_lock); list_del_init(&bo->shadow_list); - mutex_unlock(&bo->adev->shadow_list_lock); + mutex_unlock(&adev->shadow_list_lock); } kfree(bo->metadata); kfree(bo); @@ -121,20 +122,14 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, if (domain & AMDGPU_GEM_DOMAIN_VRAM) { unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT; + unsigned lpfn = 0; - if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && - !(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && - adev->mc.visible_vram_size < adev->mc.real_vram_size) { - places[c].fpfn = visible_pfn; - places[c].lpfn = 0; - places[c].flags = TTM_PL_FLAG_WC | - TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM | - TTM_PL_FLAG_TOPDOWN; - c++; - } + /* This forces a reallocation if the flag wasn't set before */ + if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) + lpfn = adev->mc.real_vram_size >> PAGE_SHIFT; places[c].fpfn = 0; - places[c].lpfn = 0; + places[c].lpfn = lpfn; places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM; if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) @@ -205,8 +200,10 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) { - amdgpu_ttm_placement_init(abo->adev, &abo->placement, - abo->placements, domain, abo->flags); + struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); + + amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements, + domain, abo->flags); } static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, @@ -245,7 +242,8 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev, int r; r = amdgpu_bo_create(adev, size, align, true, domain, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, bo_ptr); if (r) { dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r); @@ -351,7 +349,6 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, kfree(bo); return r; } - bo->adev = adev; INIT_LIST_HEAD(&bo->shadow_list); INIT_LIST_HEAD(&bo->va); bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | @@ -374,39 +371,36 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, amdgpu_fill_placement_to_bo(bo, placement); /* Kernel allocation are uninterruptible */ + + if (!resv) { + bool locked; + + reservation_object_init(&bo->tbo.ttm_resv); + locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock); + WARN_ON(!locked); + } r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, &bo->placement, page_align, !kernel, NULL, - acc_size, sg, resv, &amdgpu_ttm_bo_destroy); - if (unlikely(r != 0)) { + acc_size, sg, resv ? resv : &bo->tbo.ttm_resv, + &amdgpu_ttm_bo_destroy); + if (unlikely(r != 0)) return r; - } if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { - struct fence *fence; - - if (adev->mman.buffer_funcs_ring == NULL || - !adev->mman.buffer_funcs_ring->ready) { - r = -EBUSY; - goto fail_free; - } - - r = amdgpu_bo_reserve(bo, false); - if (unlikely(r != 0)) - goto fail_free; + struct dma_fence *fence; - amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); - if (unlikely(r != 0)) + r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); + if (unlikely(r)) goto fail_unreserve; - amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); amdgpu_bo_fence(bo, fence, false); - amdgpu_bo_unreserve(bo); - fence_put(bo->tbo.moving); - bo->tbo.moving = fence_get(fence); - fence_put(fence); + dma_fence_put(bo->tbo.moving); + bo->tbo.moving = dma_fence_get(fence); + dma_fence_put(fence); } + if (!resv) + ww_mutex_unlock(&bo->tbo.resv->lock); *bo_ptr = bo; trace_amdgpu_bo_create(bo); @@ -414,8 +408,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, return 0; fail_unreserve: - amdgpu_bo_unreserve(bo); -fail_free: + ww_mutex_unlock(&bo->tbo.resv->lock); amdgpu_bo_unref(&bo); return r; } @@ -491,7 +484,7 @@ int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, struct amdgpu_ring *ring, struct amdgpu_bo *bo, struct reservation_object *resv, - struct fence **fence, + struct dma_fence **fence, bool direct) { @@ -523,7 +516,7 @@ int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, struct amdgpu_ring *ring, struct amdgpu_bo *bo, struct reservation_object *resv, - struct fence **fence, + struct dma_fence **fence, bool direct) { @@ -616,6 +609,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 min_offset, u64 max_offset, u64 *gpu_addr) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); int r, i; unsigned fpfn, lpfn; @@ -643,18 +637,20 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, return 0; } + + bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; amdgpu_ttm_placement_from_domain(bo, domain); for (i = 0; i < bo->placement.num_placement; i++) { /* force to pin into visible video ram */ if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && (!max_offset || max_offset > - bo->adev->mc.visible_vram_size)) { + adev->mc.visible_vram_size)) { if (WARN_ON_ONCE(min_offset > - bo->adev->mc.visible_vram_size)) + adev->mc.visible_vram_size)) return -EINVAL; fpfn = min_offset >> PAGE_SHIFT; - lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT; + lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; } else { fpfn = min_offset >> PAGE_SHIFT; lpfn = max_offset >> PAGE_SHIFT; @@ -669,12 +665,12 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); if (unlikely(r)) { - dev_err(bo->adev->dev, "%p pin failed\n", bo); + dev_err(adev->dev, "%p pin failed\n", bo); goto error; } r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); if (unlikely(r)) { - dev_err(bo->adev->dev, "%p bind failed\n", bo); + dev_err(adev->dev, "%p bind failed\n", bo); goto error; } @@ -682,11 +678,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, if (gpu_addr != NULL) *gpu_addr = amdgpu_bo_gpu_offset(bo); if (domain == AMDGPU_GEM_DOMAIN_VRAM) { - bo->adev->vram_pin_size += amdgpu_bo_size(bo); + adev->vram_pin_size += amdgpu_bo_size(bo); if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) - bo->adev->invisible_pin_size += amdgpu_bo_size(bo); + adev->invisible_pin_size += amdgpu_bo_size(bo); } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { - bo->adev->gart_pin_size += amdgpu_bo_size(bo); + adev->gart_pin_size += amdgpu_bo_size(bo); } error: @@ -700,10 +696,11 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) int amdgpu_bo_unpin(struct amdgpu_bo *bo) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); int r, i; if (!bo->pin_count) { - dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo); + dev_warn(adev->dev, "%p unpin not necessary\n", bo); return 0; } bo->pin_count--; @@ -715,16 +712,16 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo) } r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); if (unlikely(r)) { - dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo); + dev_err(adev->dev, "%p validate failed for unpin\n", bo); goto error; } if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { - bo->adev->vram_pin_size -= amdgpu_bo_size(bo); + adev->vram_pin_size -= amdgpu_bo_size(bo); if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) - bo->adev->invisible_pin_size -= amdgpu_bo_size(bo); + adev->invisible_pin_size -= amdgpu_bo_size(bo); } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { - bo->adev->gart_pin_size -= amdgpu_bo_size(bo); + adev->gart_pin_size -= amdgpu_bo_size(bo); } error: @@ -854,6 +851,7 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_bo *abo; struct ttm_mem_reg *old_mem = &bo->mem; @@ -861,21 +859,21 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, return; abo = container_of(bo, struct amdgpu_bo, tbo); - amdgpu_vm_bo_invalidate(abo->adev, abo); + amdgpu_vm_bo_invalidate(adev, abo); /* update statistics */ if (!new_mem) return; /* move_notify is called before move happens */ - amdgpu_update_memory_usage(abo->adev, &bo->mem, new_mem); + amdgpu_update_memory_usage(adev, &bo->mem, new_mem); trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); } int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) { - struct amdgpu_device *adev; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_bo *abo; unsigned long offset, size, lpfn; int i, r; @@ -884,13 +882,14 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) return 0; abo = container_of(bo, struct amdgpu_bo, tbo); - adev = abo->adev; if (bo->mem.mem_type != TTM_PL_VRAM) return 0; size = bo->mem.num_pages << PAGE_SHIFT; offset = bo->mem.start << PAGE_SHIFT; - if ((offset + size) <= adev->mc.visible_vram_size) + /* TODO: figure out how to map scattered VRAM to the CPU */ + if ((offset + size) <= adev->mc.visible_vram_size && + (abo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) return 0; /* Can't move a pinned BO to visible VRAM */ @@ -898,6 +897,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) return -EINVAL; /* hurrah the memory is not visible ! */ + abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; for (i = 0; i < abo->placement.num_placement; i++) { @@ -931,7 +931,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) * @shared: true if fence should be added shared * */ -void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, +void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, bool shared) { struct reservation_object *resv = bo->tbo.resv; @@ -959,6 +959,8 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && !bo->pin_count); WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); + WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && + !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); return bo->tbo.offset; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 8255034d73eb..5cbf59ec0f68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -71,12 +71,13 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) */ static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); int r; r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) - dev_err(bo->adev->dev, "%p reserve failed\n", bo); + dev_err(adev->dev, "%p reserve failed\n", bo); return r; } return 0; @@ -156,19 +157,19 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem); int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); -void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, +void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, bool shared); u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, struct amdgpu_ring *ring, struct amdgpu_bo *bo, struct reservation_object *resv, - struct fence **fence, bool direct); + struct dma_fence **fence, bool direct); int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, struct amdgpu_ring *ring, struct amdgpu_bo *bo, struct reservation_object *resv, - struct fence **fence, + struct dma_fence **fence, bool direct); @@ -200,7 +201,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, unsigned size, unsigned align); void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, - struct fence *fence); + struct dma_fence *fence); #if defined(CONFIG_DEBUG_FS) void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, struct seq_file *m); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index accc908bdc88..723ae682bf25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -737,6 +737,21 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, return sprintf(buf, "%i\n", speed); } +static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int err; + u32 speed; + + err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); + if (err) + return err; + + return sprintf(buf, "%i\n", speed); +} + static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); @@ -744,6 +759,7 @@ static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); +static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_temp1_input.dev_attr.attr, @@ -753,6 +769,7 @@ static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_pwm1_enable.dev_attr.attr, &sensor_dev_attr_pwm1_min.dev_attr.attr, &sensor_dev_attr_pwm1_max.dev_attr.attr, + &sensor_dev_attr_fan1_input.dev_attr.attr, NULL }; @@ -804,6 +821,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) return 0; + /* requires powerplay */ + if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr) + return 0; + return effective_mode; } @@ -986,10 +1007,10 @@ restart_search: static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) { - int i; struct amdgpu_ps *ps; enum amd_pm_state_type dpm_state; int ret; + bool equal; /* if dpm init failed */ if (!adev->pm.dpm_enabled) @@ -1009,46 +1030,6 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) else return; - /* no need to reprogram if nothing changed unless we are on BTC+ */ - if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) { - /* vce just modifies an existing state so force a change */ - if (ps->vce_active != adev->pm.dpm.vce_active) - goto force; - if (adev->flags & AMD_IS_APU) { - /* for APUs if the num crtcs changed but state is the same, - * all we need to do is update the display configuration. - */ - if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) { - /* update display watermarks based on new power state */ - amdgpu_display_bandwidth_update(adev); - /* update displays */ - amdgpu_dpm_display_configuration_changed(adev); - adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; - adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; - } - return; - } else { - /* for BTC+ if the num crtcs hasn't changed and state is the same, - * nothing to do, if the num crtcs is > 1 and state is the same, - * update display configuration. - */ - if (adev->pm.dpm.new_active_crtcs == - adev->pm.dpm.current_active_crtcs) { - return; - } else if ((adev->pm.dpm.current_active_crtc_count > 1) && - (adev->pm.dpm.new_active_crtc_count > 1)) { - /* update display watermarks based on new power state */ - amdgpu_display_bandwidth_update(adev); - /* update displays */ - amdgpu_dpm_display_configuration_changed(adev); - adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; - adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; - return; - } - } - } - -force: if (amdgpu_dpm == 1) { printk("switching from power state:\n"); amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); @@ -1059,31 +1040,21 @@ force: /* update whether vce is active */ ps->vce_active = adev->pm.dpm.vce_active; + amdgpu_dpm_display_configuration_changed(adev); + ret = amdgpu_dpm_pre_set_power_state(adev); if (ret) return; - /* update display watermarks based on new power state */ - amdgpu_display_bandwidth_update(adev); + if ((0 != amgdpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))) + equal = false; - /* wait for the rings to drain */ - for (i = 0; i < AMDGPU_MAX_RINGS; i++) { - struct amdgpu_ring *ring = adev->rings[i]; - if (ring && ring->ready) - amdgpu_fence_wait_empty(ring); - } + if (equal) + return; - /* program the new power state */ amdgpu_dpm_set_power_state(adev); - - /* update current power state */ - adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps; - amdgpu_dpm_post_set_power_state(adev); - /* update displays */ - amdgpu_dpm_display_configuration_changed(adev); - adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; @@ -1135,7 +1106,7 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) mutex_lock(&adev->pm.mutex); adev->pm.dpm.vce_active = true; /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL; + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; mutex_unlock(&adev->pm.mutex); } else { mutex_lock(&adev->pm.mutex); @@ -1276,20 +1247,20 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) struct drm_device *ddev = adev->ddev; struct drm_crtc *crtc; struct amdgpu_crtc *amdgpu_crtc; + int i = 0; if (!adev->pm.dpm_enabled) return; - if (adev->pp_enabled) { - int i = 0; + amdgpu_display_bandwidth_update(adev); - amdgpu_display_bandwidth_update(adev); - for (i = 0; i < AMDGPU_MAX_RINGS; i++) { - struct amdgpu_ring *ring = adev->rings[i]; - if (ring && ring->ready) - amdgpu_fence_wait_empty(ring); - } + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + if (ring && ring->ready) + amdgpu_fence_wait_empty(ring); + } + if (adev->pp_enabled) { amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL); } else { mutex_lock(&adev->pm.mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index 7532ff822aa7..fc592c2b0e16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -155,9 +155,6 @@ static int amdgpu_pp_sw_init(void *handle) ret = adev->powerplay.ip_funcs->sw_init( adev->powerplay.pp_handle); - if (adev->pp_enabled) - adev->pm.dpm_enabled = true; - return ret; } @@ -187,6 +184,9 @@ static int amdgpu_pp_hw_init(void *handle) ret = adev->powerplay.ip_funcs->hw_init( adev->powerplay.pp_handle); + if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev)) + adev->pm.dpm_enabled = true; + return ret; } @@ -299,7 +299,7 @@ static int amdgpu_pp_soft_reset(void *handle) return ret; } -const struct amd_ip_funcs amdgpu_pp_ip_funcs = { +static const struct amd_ip_funcs amdgpu_pp_ip_funcs = { .name = "amdgpu_powerplay", .early_init = amdgpu_pp_early_init, .late_init = amdgpu_pp_late_init, @@ -316,3 +316,12 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = { .set_clockgating_state = amdgpu_pp_set_clockgating_state, .set_powergating_state = amdgpu_pp_set_powergating_state, }; + +const struct amdgpu_ip_block_version amdgpu_pp_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &amdgpu_pp_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h index da5cf47cfd99..c0c4bfdcdb14 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.h @@ -23,11 +23,11 @@ * */ -#ifndef __AMDGPU_POPWERPLAY_H__ -#define __AMDGPU_POPWERPLAY_H__ +#ifndef __AMDGPU_POWERPLAY_H__ +#define __AMDGPU_POWERPLAY_H__ #include "amd_shared.h" -extern const struct amd_ip_funcs amdgpu_pp_ip_funcs; +extern const struct amdgpu_ip_block_version amdgpu_pp_ip_block; -#endif /* __AMDSOC_DM_H__ */ +#endif /* __AMDGPU_POWERPLAY_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c index 7700dc22f243..3826d5aea0a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c @@ -74,20 +74,36 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, if (ret) return ERR_PTR(ret); + bo->prime_shared_count = 1; return &bo->gem_base; } int amdgpu_gem_prime_pin(struct drm_gem_object *obj) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - int ret = 0; + long ret = 0; ret = amdgpu_bo_reserve(bo, false); if (unlikely(ret != 0)) return ret; + /* + * Wait for all shared fences to complete before we switch to future + * use of exclusive fence on this prime shared bo. + */ + ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false, + MAX_SCHEDULE_TIMEOUT); + if (unlikely(ret < 0)) { + DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); + amdgpu_bo_unreserve(bo); + return ret; + } + /* pin buffer into GTT */ ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL); + if (likely(ret == 0)) + bo->prime_shared_count++; + amdgpu_bo_unreserve(bo); return ret; } @@ -102,6 +118,8 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) return; amdgpu_bo_unpin(bo); + if (bo->prime_shared_count) + bo->prime_shared_count--; amdgpu_bo_unreserve(bo); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 3cb5e903cd62..4c992826d2d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) { /* Align requested size with padding so unlock_commit can * pad safely */ - ndw = (ndw + ring->align_mask) & ~ring->align_mask; + ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; /* Make sure we aren't trying to allocate more space * than the maximum for one submission @@ -94,7 +94,7 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) int i; for (i = 0; i < count; i++) - amdgpu_ring_write(ring, ring->nop); + amdgpu_ring_write(ring, ring->funcs->nop); } /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ -106,8 +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) */ void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { - while (ib->length_dw & ring->align_mask) - ib->ptr[ib->length_dw++] = ring->nop; + while (ib->length_dw & ring->funcs->align_mask) + ib->ptr[ib->length_dw++] = ring->funcs->nop; } /** @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) uint32_t count; /* We pad to match fetch size */ - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); - count %= ring->align_mask + 1; + count = ring->funcs->align_mask + 1 - + (ring->wptr & ring->funcs->align_mask); + count %= ring->funcs->align_mask + 1; ring->funcs->insert_nop(ring, count); mb(); @@ -163,9 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) * Returns 0 on success, error on failure. */ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned max_dw, u32 nop, u32 align_mask, - struct amdgpu_irq_src *irq_src, unsigned irq_type, - enum amdgpu_ring_type ring_type) + unsigned max_dw, struct amdgpu_irq_src *irq_src, + unsigned irq_type) { int r; @@ -216,9 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, ring->ring_size = roundup_pow_of_two(max_dw * 4 * amdgpu_sched_hw_submission); - ring->align_mask = align_mask; - ring->nop = nop; - ring->type = ring_type; /* Allocate ring buffer */ if (ring->ring_obj == NULL) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h new file mode 100644 index 000000000000..574f0b79c690 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -0,0 +1,186 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ +#ifndef __AMDGPU_RING_H__ +#define __AMDGPU_RING_H__ + +#include "gpu_scheduler.h" + +/* max number of rings */ +#define AMDGPU_MAX_RINGS 16 +#define AMDGPU_MAX_GFX_RINGS 1 +#define AMDGPU_MAX_COMPUTE_RINGS 8 +#define AMDGPU_MAX_VCE_RINGS 3 + +/* some special values for the owner field */ +#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) +#define AMDGPU_FENCE_OWNER_VM ((void*)1ul) + +#define AMDGPU_FENCE_FLAG_64BIT (1 << 0) +#define AMDGPU_FENCE_FLAG_INT (1 << 1) + +enum amdgpu_ring_type { + AMDGPU_RING_TYPE_GFX, + AMDGPU_RING_TYPE_COMPUTE, + AMDGPU_RING_TYPE_SDMA, + AMDGPU_RING_TYPE_UVD, + AMDGPU_RING_TYPE_VCE, + AMDGPU_RING_TYPE_KIQ +}; + +struct amdgpu_device; +struct amdgpu_ring; +struct amdgpu_ib; +struct amdgpu_cs_parser; + +/* + * Fences. + */ +struct amdgpu_fence_driver { + uint64_t gpu_addr; + volatile uint32_t *cpu_addr; + /* sync_seq is protected by ring emission lock */ + uint32_t sync_seq; + atomic_t last_seq; + bool initialized; + struct amdgpu_irq_src *irq_src; + unsigned irq_type; + struct timer_list fallback_timer; + unsigned num_fences_mask; + spinlock_t lock; + struct dma_fence **fences; +}; + +int amdgpu_fence_driver_init(struct amdgpu_device *adev); +void amdgpu_fence_driver_fini(struct amdgpu_device *adev); +void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); + +int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, + unsigned num_hw_submission); +int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq_src, + unsigned irq_type); +void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); +void amdgpu_fence_driver_resume(struct amdgpu_device *adev); +int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence); +void amdgpu_fence_process(struct amdgpu_ring *ring); +int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); +unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); + +/* + * Rings. + */ + +/* provided by hw blocks that expose a ring buffer for commands */ +struct amdgpu_ring_funcs { + enum amdgpu_ring_type type; + uint32_t align_mask; + u32 nop; + + /* ring read/write ptr handling */ + u32 (*get_rptr)(struct amdgpu_ring *ring); + u32 (*get_wptr)(struct amdgpu_ring *ring); + void (*set_wptr)(struct amdgpu_ring *ring); + /* validating and patching of IBs */ + int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); + /* constants to calculate how many DW are needed for an emit */ + unsigned emit_frame_size; + unsigned emit_ib_size; + /* command emit functions */ + void (*emit_ib)(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch); + void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, + uint64_t seq, unsigned flags); + void (*emit_pipeline_sync)(struct amdgpu_ring *ring); + void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, + uint64_t pd_addr); + void (*emit_hdp_flush)(struct amdgpu_ring *ring); + void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); + void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size); + /* testing functions */ + int (*test_ring)(struct amdgpu_ring *ring); + int (*test_ib)(struct amdgpu_ring *ring, long timeout); + /* insert NOP packets */ + void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); + /* pad the indirect buffer to the necessary number of dw */ + void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); + unsigned (*init_cond_exec)(struct amdgpu_ring *ring); + void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); + /* note usage for clock and power gating */ + void (*begin_use)(struct amdgpu_ring *ring); + void (*end_use)(struct amdgpu_ring *ring); + void (*emit_switch_buffer) (struct amdgpu_ring *ring); + void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); +}; + +struct amdgpu_ring { + struct amdgpu_device *adev; + const struct amdgpu_ring_funcs *funcs; + struct amdgpu_fence_driver fence_drv; + struct amd_gpu_scheduler sched; + + struct amdgpu_bo *ring_obj; + volatile uint32_t *ring; + unsigned rptr_offs; + unsigned wptr; + unsigned wptr_old; + unsigned ring_size; + unsigned max_dw; + int count_dw; + uint64_t gpu_addr; + uint32_t ptr_mask; + bool ready; + u32 idx; + u32 me; + u32 pipe; + u32 queue; + struct amdgpu_bo *mqd_obj; + u32 doorbell_index; + bool use_doorbell; + unsigned wptr_offs; + unsigned fence_offs; + uint64_t current_ctx; + char name[16]; + unsigned cond_exe_offs; + u64 cond_exe_gpu_addr; + volatile u32 *cond_exe_cpu_addr; +#if defined(CONFIG_DEBUG_FS) + struct dentry *ent; +#endif +}; + +int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); +void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); +void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); +void amdgpu_ring_commit(struct amdgpu_ring *ring); +void amdgpu_ring_undo(struct amdgpu_ring *ring); +int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, + unsigned ring_size, struct amdgpu_irq_src *irq_src, + unsigned irq_type); +void amdgpu_ring_fini(struct amdgpu_ring *ring); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c index d8af37a845f4..de9f919ae336 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c @@ -147,7 +147,7 @@ static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo) } list_del_init(&sa_bo->olist); list_del_init(&sa_bo->flist); - fence_put(sa_bo->fence); + dma_fence_put(sa_bo->fence); kfree(sa_bo); } @@ -161,7 +161,7 @@ static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager) sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist); list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) { if (sa_bo->fence == NULL || - !fence_is_signaled(sa_bo->fence)) { + !dma_fence_is_signaled(sa_bo->fence)) { return; } amdgpu_sa_bo_remove_locked(sa_bo); @@ -244,7 +244,7 @@ static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager, } static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, - struct fence **fences, + struct dma_fence **fences, unsigned *tries) { struct amdgpu_sa_bo *best_bo = NULL; @@ -272,7 +272,7 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, sa_bo = list_first_entry(&sa_manager->flist[i], struct amdgpu_sa_bo, flist); - if (!fence_is_signaled(sa_bo->fence)) { + if (!dma_fence_is_signaled(sa_bo->fence)) { fences[i] = sa_bo->fence; continue; } @@ -314,7 +314,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, struct amdgpu_sa_bo **sa_bo, unsigned size, unsigned align) { - struct fence *fences[AMDGPU_SA_NUM_FENCE_LISTS]; + struct dma_fence *fences[AMDGPU_SA_NUM_FENCE_LISTS]; unsigned tries[AMDGPU_SA_NUM_FENCE_LISTS]; unsigned count; int i, r; @@ -327,9 +327,8 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, return -EINVAL; *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL); - if ((*sa_bo) == NULL) { + if (!(*sa_bo)) return -ENOMEM; - } (*sa_bo)->manager = sa_manager; (*sa_bo)->fence = NULL; INIT_LIST_HEAD(&(*sa_bo)->olist); @@ -356,14 +355,15 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, for (i = 0, count = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) if (fences[i]) - fences[count++] = fence_get(fences[i]); + fences[count++] = dma_fence_get(fences[i]); if (count) { spin_unlock(&sa_manager->wq.lock); - t = fence_wait_any_timeout(fences, count, false, - MAX_SCHEDULE_TIMEOUT); + t = dma_fence_wait_any_timeout(fences, count, false, + MAX_SCHEDULE_TIMEOUT, + NULL); for (i = 0; i < count; ++i) - fence_put(fences[i]); + dma_fence_put(fences[i]); r = (t > 0) ? 0 : t; spin_lock(&sa_manager->wq.lock); @@ -384,7 +384,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, } void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, - struct fence *fence) + struct dma_fence *fence) { struct amdgpu_sa_manager *sa_manager; @@ -394,10 +394,10 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, sa_manager = (*sa_bo)->manager; spin_lock(&sa_manager->wq.lock); - if (fence && !fence_is_signaled(fence)) { + if (fence && !dma_fence_is_signaled(fence)) { uint32_t idx; - (*sa_bo)->fence = fence_get(fence); + (*sa_bo)->fence = dma_fence_get(fence); idx = fence->context % AMDGPU_SA_NUM_FENCE_LISTS; list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]); } else { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 5c8d3022fb87..ed814e6d0207 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -34,7 +34,7 @@ struct amdgpu_sync_entry { struct hlist_node node; - struct fence *fence; + struct dma_fence *fence; }; static struct kmem_cache *amdgpu_sync_slab; @@ -60,7 +60,8 @@ void amdgpu_sync_create(struct amdgpu_sync *sync) * * Test if the fence was issued by us. */ -static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f) +static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, + struct dma_fence *f) { struct amd_sched_fence *s_fence = to_amd_sched_fence(f); @@ -81,7 +82,7 @@ static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f) * * Extract who originally created the fence. */ -static void *amdgpu_sync_get_owner(struct fence *f) +static void *amdgpu_sync_get_owner(struct dma_fence *f) { struct amd_sched_fence *s_fence = to_amd_sched_fence(f); @@ -99,13 +100,14 @@ static void *amdgpu_sync_get_owner(struct fence *f) * * Either keep the existing fence or the new one, depending which one is later. */ -static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence) +static void amdgpu_sync_keep_later(struct dma_fence **keep, + struct dma_fence *fence) { - if (*keep && fence_is_later(*keep, fence)) + if (*keep && dma_fence_is_later(*keep, fence)) return; - fence_put(*keep); - *keep = fence_get(fence); + dma_fence_put(*keep); + *keep = dma_fence_get(fence); } /** @@ -117,7 +119,7 @@ static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence) * Tries to add the fence to an existing hash entry. Returns true when an entry * was found, false otherwise. */ -static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct fence *f) +static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f) { struct amdgpu_sync_entry *e; @@ -139,7 +141,7 @@ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct fence *f) * */ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, - struct fence *f) + struct dma_fence *f) { struct amdgpu_sync_entry *e; @@ -158,7 +160,7 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, return -ENOMEM; hash_add(sync->fences, &e->node, f->context); - e->fence = fence_get(f); + e->fence = dma_fence_get(f); return 0; } @@ -177,7 +179,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, void *owner) { struct reservation_object_list *flist; - struct fence *f; + struct dma_fence *f; void *fence_owner; unsigned i; int r = 0; @@ -231,15 +233,15 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, * Returns the next fence not signaled yet without removing it from the sync * object. */ -struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, - struct amdgpu_ring *ring) +struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, + struct amdgpu_ring *ring) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; int i; hash_for_each_safe(sync->fences, i, tmp, e, node) { - struct fence *f = e->fence; + struct dma_fence *f = e->fence; struct amd_sched_fence *s_fence = to_amd_sched_fence(f); if (ring && s_fence) { @@ -247,16 +249,16 @@ struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, * when they are scheduled. */ if (s_fence->sched == &ring->sched) { - if (fence_is_signaled(&s_fence->scheduled)) + if (dma_fence_is_signaled(&s_fence->scheduled)) continue; return &s_fence->scheduled; } } - if (fence_is_signaled(f)) { + if (dma_fence_is_signaled(f)) { hash_del(&e->node); - fence_put(f); + dma_fence_put(f); kmem_cache_free(amdgpu_sync_slab, e); continue; } @@ -274,11 +276,11 @@ struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, * * Get and removes the next fence from the sync object not signaled yet. */ -struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) +struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; - struct fence *f; + struct dma_fence *f; int i; hash_for_each_safe(sync->fences, i, tmp, e, node) { @@ -288,10 +290,10 @@ struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) hash_del(&e->node); kmem_cache_free(amdgpu_sync_slab, e); - if (!fence_is_signaled(f)) + if (!dma_fence_is_signaled(f)) return f; - fence_put(f); + dma_fence_put(f); } return NULL; } @@ -311,11 +313,11 @@ void amdgpu_sync_free(struct amdgpu_sync *sync) hash_for_each_safe(sync->fences, i, tmp, e, node) { hash_del(&e->node); - fence_put(e->fence); + dma_fence_put(e->fence); kmem_cache_free(amdgpu_sync_slab, e); } - fence_put(sync->last_vm_update); + dma_fence_put(sync->last_vm_update); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h new file mode 100644 index 000000000000..605be266e07f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h @@ -0,0 +1,56 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ +#ifndef __AMDGPU_SYNC_H__ +#define __AMDGPU_SYNC_H__ + +#include <linux/hashtable.h> + +struct dma_fence; +struct reservation_object; +struct amdgpu_device; +struct amdgpu_ring; + +/* + * Container for fences used to sync command submissions. + */ +struct amdgpu_sync { + DECLARE_HASHTABLE(fences, 4); + struct dma_fence *last_vm_update; +}; + +void amdgpu_sync_create(struct amdgpu_sync *sync); +int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, + struct dma_fence *f); +int amdgpu_sync_resv(struct amdgpu_device *adev, + struct amdgpu_sync *sync, + struct reservation_object *resv, + void *owner); +struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, + struct amdgpu_ring *ring); +struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); +void amdgpu_sync_free(struct amdgpu_sync *sync); +int amdgpu_sync_init(void); +void amdgpu_sync_fini(void); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c index b827c75e95de..e05a24325eeb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c @@ -78,7 +78,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) void *gtt_map, *vram_map; void **gtt_start, **gtt_end; void **vram_start, **vram_end; - struct fence *fence = NULL; + struct dma_fence *fence = NULL; r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, @@ -118,13 +118,13 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) goto out_lclean_unpin; } - r = fence_wait(fence, false); + r = dma_fence_wait(fence, false); if (r) { DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); goto out_lclean_unpin; } - fence_put(fence); + dma_fence_put(fence); r = amdgpu_bo_kmap(vram_obj, &vram_map); if (r) { @@ -163,13 +163,13 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) goto out_lclean_unpin; } - r = fence_wait(fence, false); + r = dma_fence_wait(fence, false); if (r) { DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); goto out_lclean_unpin; } - fence_put(fence); + dma_fence_put(fence); r = amdgpu_bo_kmap(gtt_obj[i], >t_map); if (r) { @@ -216,7 +216,7 @@ out_lclean: amdgpu_bo_unref(>t_obj[i]); } if (fence) - fence_put(fence); + dma_fence_put(fence); break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 067e5e683bb3..bb964a8ff938 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -104,7 +104,7 @@ TRACE_EVENT(amdgpu_cs_ioctl, __field(struct amdgpu_device *, adev) __field(struct amd_sched_job *, sched_job) __field(struct amdgpu_ib *, ib) - __field(struct fence *, fence) + __field(struct dma_fence *, fence) __field(char *, ring_name) __field(u32, num_ibs) ), @@ -129,7 +129,7 @@ TRACE_EVENT(amdgpu_sched_run_job, __field(struct amdgpu_device *, adev) __field(struct amd_sched_job *, sched_job) __field(struct amdgpu_ib *, ib) - __field(struct fence *, fence) + __field(struct dma_fence *, fence) __field(char *, ring_name) __field(u32, num_ibs) ), diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index dcaf691f56b5..bc70f80260d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -34,7 +34,6 @@ #include <ttm/ttm_placement.h> #include <ttm/ttm_module.h> #include <ttm/ttm_page_alloc.h> -#include <ttm/ttm_memory.h> #include <drm/drmP.h> #include <drm/amdgpu_drm.h> #include <linux/seq_file.h> @@ -51,16 +50,6 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); -static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev) -{ - struct amdgpu_mman *mman; - struct amdgpu_device *adev; - - mman = container_of(bdev, struct amdgpu_mman, bdev); - adev = container_of(mman, struct amdgpu_device, mman); - return adev; -} - /* * Global memory. @@ -75,7 +64,7 @@ static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref) ttm_mem_global_release(ref->object); } -int amdgpu_ttm_global_init(struct amdgpu_device *adev) +static int amdgpu_ttm_global_init(struct amdgpu_device *adev) { struct drm_global_reference *global_ref; struct amdgpu_ring *ring; @@ -150,7 +139,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, { struct amdgpu_device *adev; - adev = amdgpu_get_adev(bdev); + adev = amdgpu_ttm_adev(bdev); switch (type) { case TTM_PL_SYSTEM: @@ -168,7 +157,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, break; case TTM_PL_VRAM: /* "On-card" video ram */ - man->func = &ttm_bo_manager_func; + man->func = &amdgpu_vram_mgr_func; man->gpu_offset = adev->mc.vram_start; man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_MAPPABLE; @@ -195,6 +184,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, static void amdgpu_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *placement) { + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_bo *abo; static struct ttm_place placements = { .fpfn = 0, @@ -213,7 +203,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, abo = container_of(bo, struct amdgpu_bo, tbo); switch (bo->mem.mem_type) { case TTM_PL_VRAM: - if (abo->adev->mman.buffer_funcs_ring->ready == false) { + if (adev->mman.buffer_funcs_ring->ready == false) { amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); } else { amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); @@ -229,7 +219,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, * allocating address space for the BO. */ abo->placements[i].lpfn = - abo->adev->mc.gtt_size >> PAGE_SHIFT; + adev->mc.gtt_size >> PAGE_SHIFT; } } break; @@ -260,63 +250,115 @@ static void amdgpu_move_null(struct ttm_buffer_object *bo, new_mem->mm_node = NULL; } -static int amdgpu_move_blit(struct ttm_buffer_object *bo, - bool evict, bool no_wait_gpu, - struct ttm_mem_reg *new_mem, - struct ttm_mem_reg *old_mem) +static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo, + struct drm_mm_node *mm_node, + struct ttm_mem_reg *mem, + uint64_t *addr) { - struct amdgpu_device *adev; - struct amdgpu_ring *ring; - uint64_t old_start, new_start; - struct fence *fence; int r; - adev = amdgpu_get_adev(bo->bdev); - ring = adev->mman.buffer_funcs_ring; - - switch (old_mem->mem_type) { + switch (mem->mem_type) { case TTM_PL_TT: - r = amdgpu_ttm_bind(bo, old_mem); + r = amdgpu_ttm_bind(bo, mem); if (r) return r; case TTM_PL_VRAM: - old_start = (u64)old_mem->start << PAGE_SHIFT; - old_start += bo->bdev->man[old_mem->mem_type].gpu_offset; + *addr = mm_node->start << PAGE_SHIFT; + *addr += bo->bdev->man[mem->mem_type].gpu_offset; break; default: - DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); + DRM_ERROR("Unknown placement %d\n", mem->mem_type); return -EINVAL; } - switch (new_mem->mem_type) { - case TTM_PL_TT: - r = amdgpu_ttm_bind(bo, new_mem); - if (r) - return r; - case TTM_PL_VRAM: - new_start = (u64)new_mem->start << PAGE_SHIFT; - new_start += bo->bdev->man[new_mem->mem_type].gpu_offset; - break; - default: - DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); - return -EINVAL; - } + return 0; +} + +static int amdgpu_move_blit(struct ttm_buffer_object *bo, + bool evict, bool no_wait_gpu, + struct ttm_mem_reg *new_mem, + struct ttm_mem_reg *old_mem) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); + struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + + struct drm_mm_node *old_mm, *new_mm; + uint64_t old_start, old_size, new_start, new_size; + unsigned long num_pages; + struct dma_fence *fence = NULL; + int r; + + BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); + if (!ring->ready) { DRM_ERROR("Trying to move memory with ring turned off.\n"); return -EINVAL; } - BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); + old_mm = old_mem->mm_node; + r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start); + if (r) + return r; + old_size = old_mm->size; + - r = amdgpu_copy_buffer(ring, old_start, new_start, - new_mem->num_pages * PAGE_SIZE, /* bytes */ - bo->resv, &fence, false); + new_mm = new_mem->mm_node; + r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start); if (r) return r; + new_size = new_mm->size; + + num_pages = new_mem->num_pages; + while (num_pages) { + unsigned long cur_pages = min(old_size, new_size); + struct dma_fence *next; + + r = amdgpu_copy_buffer(ring, old_start, new_start, + cur_pages * PAGE_SIZE, + bo->resv, &next, false); + if (r) + goto error; + + dma_fence_put(fence); + fence = next; + + num_pages -= cur_pages; + if (!num_pages) + break; + + old_size -= cur_pages; + if (!old_size) { + r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem, + &old_start); + if (r) + goto error; + old_size = old_mm->size; + } else { + old_start += cur_pages * PAGE_SIZE; + } + + new_size -= cur_pages; + if (!new_size) { + r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem, + &new_start); + if (r) + goto error; + + new_size = new_mm->size; + } else { + new_start += cur_pages * PAGE_SIZE; + } + } r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); - fence_put(fence); + dma_fence_put(fence); + return r; + +error: + if (fence) + dma_fence_wait(fence, false); + dma_fence_put(fence); return r; } @@ -332,7 +374,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, struct ttm_placement placement; int r; - adev = amdgpu_get_adev(bo->bdev); + adev = amdgpu_ttm_adev(bo->bdev); tmp_mem = *new_mem; tmp_mem.mm_node = NULL; placement.num_placement = 1; @@ -379,7 +421,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, struct ttm_place placements; int r; - adev = amdgpu_get_adev(bo->bdev); + adev = amdgpu_ttm_adev(bo->bdev); tmp_mem = *new_mem; tmp_mem.mm_node = NULL; placement.num_placement = 1; @@ -422,7 +464,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, if (WARN_ON_ONCE(abo->pin_count > 0)) return -EINVAL; - adev = amdgpu_get_adev(bo->bdev); + adev = amdgpu_ttm_adev(bo->bdev); /* remember the eviction */ if (evict) @@ -475,7 +517,7 @@ memcpy: static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) { struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; - struct amdgpu_device *adev = amdgpu_get_adev(bdev); + struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); mem->bus.addr = NULL; mem->bus.offset = 0; @@ -607,7 +649,7 @@ release_pages: /* prepare the sg table with the user pages */ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) { - struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); + struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); struct amdgpu_ttm_tt *gtt = (void *)ttm; unsigned nents; int r; @@ -639,7 +681,7 @@ release_sg: static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) { - struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); + struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); struct amdgpu_ttm_tt *gtt = (void *)ttm; struct sg_page_iter sg_iter; @@ -799,7 +841,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, struct amdgpu_device *adev; struct amdgpu_ttm_tt *gtt; - adev = amdgpu_get_adev(bdev); + adev = amdgpu_ttm_adev(bdev); gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); if (gtt == NULL) { @@ -843,7 +885,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) return 0; } - adev = amdgpu_get_adev(ttm->bdev); + adev = amdgpu_ttm_adev(ttm->bdev); #ifdef CONFIG_SWIOTLB if (swiotlb_nr_tbl()) { @@ -889,7 +931,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) if (slave) return; - adev = amdgpu_get_adev(ttm->bdev); + adev = amdgpu_ttm_adev(ttm->bdev); #ifdef CONFIG_SWIOTLB if (swiotlb_nr_tbl()) { @@ -1012,7 +1054,7 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo) { - struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev); + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); unsigned i, j; for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) { @@ -1029,7 +1071,7 @@ static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo) static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo) { - struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev); + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); unsigned log2_size = min(ilog2(tbo->num_pages), AMDGPU_TTM_LRU_SIZE - 1); @@ -1060,12 +1102,37 @@ static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo) return res; } +static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, + const struct ttm_place *place) +{ + if (bo->mem.mem_type == TTM_PL_VRAM && + bo->mem.start == AMDGPU_BO_INVALID_OFFSET) { + unsigned long num_pages = bo->mem.num_pages; + struct drm_mm_node *node = bo->mem.mm_node; + + /* Check each drm MM node individually */ + while (num_pages) { + if (place->fpfn < (node->start + node->size) && + !(place->lpfn && place->lpfn <= node->start)) + return true; + + num_pages -= node->size; + ++node; + } + + return false; + } + + return ttm_bo_eviction_valuable(bo, place); +} + static struct ttm_bo_driver amdgpu_bo_driver = { .ttm_tt_create = &amdgpu_ttm_tt_create, .ttm_tt_populate = &amdgpu_ttm_tt_populate, .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, .invalidate_caches = &amdgpu_invalidate_caches, .init_mem_type = &amdgpu_init_mem_type, + .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, .evict_flags = &amdgpu_evict_flags, .move = &amdgpu_bo_move, .verify_access = &amdgpu_verify_access, @@ -1083,6 +1150,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) unsigned i, j; int r; + r = amdgpu_ttm_global_init(adev); + if (r) { + return r; + } /* No others user of address space so set it to 0 */ r = ttm_bo_device_init(&adev->mman.bdev, adev->mman.bo_global_ref.ref.object, @@ -1119,7 +1190,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->stollen_vga_memory); if (r) { return r; @@ -1247,7 +1319,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t dst_offset, uint32_t byte_count, struct reservation_object *resv, - struct fence **fence, bool direct_submit) + struct dma_fence **fence, bool direct_submit) { struct amdgpu_device *adev = ring->adev; struct amdgpu_job *job; @@ -1294,7 +1366,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, if (direct_submit) { r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, NULL, fence); - job->fence = fence_get(*fence); + job->fence = dma_fence_get(*fence); if (r) DRM_ERROR("Error scheduling IBs (%d)\n", r); amdgpu_job_free(job); @@ -1313,28 +1385,40 @@ error_free: } int amdgpu_fill_buffer(struct amdgpu_bo *bo, - uint32_t src_data, - struct reservation_object *resv, - struct fence **fence) + uint32_t src_data, + struct reservation_object *resv, + struct dma_fence **fence) { - struct amdgpu_device *adev = bo->adev; - struct amdgpu_job *job; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - uint32_t max_bytes, byte_count; - uint64_t dst_offset; + struct drm_mm_node *mm_node; + unsigned long num_pages; unsigned int num_loops, num_dw; - unsigned int i; + + struct amdgpu_job *job; int r; - byte_count = bo->tbo.num_pages << PAGE_SHIFT; - max_bytes = adev->mman.buffer_funcs->fill_max_bytes; - num_loops = DIV_ROUND_UP(byte_count, max_bytes); + if (!ring->ready) { + DRM_ERROR("Trying to clear memory with ring turned off.\n"); + return -EINVAL; + } + + num_pages = bo->tbo.num_pages; + mm_node = bo->tbo.mem.mm_node; + num_loops = 0; + while (num_pages) { + uint32_t byte_count = mm_node->size << PAGE_SHIFT; + + num_loops += DIV_ROUND_UP(byte_count, max_bytes); + num_pages -= mm_node->size; + ++mm_node; + } num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; /* for IB padding */ - while (num_dw & 0x7) - num_dw++; + num_dw += 64; r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); if (r) @@ -1342,28 +1426,43 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, if (resv) { r = amdgpu_sync_resv(adev, &job->sync, resv, - AMDGPU_FENCE_OWNER_UNDEFINED); + AMDGPU_FENCE_OWNER_UNDEFINED); if (r) { DRM_ERROR("sync failed (%d).\n", r); goto error_free; } } - dst_offset = bo->tbo.mem.start << PAGE_SHIFT; - for (i = 0; i < num_loops; i++) { - uint32_t cur_size_in_bytes = min(byte_count, max_bytes); + num_pages = bo->tbo.num_pages; + mm_node = bo->tbo.mem.mm_node; - amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, - dst_offset, cur_size_in_bytes); + while (num_pages) { + uint32_t byte_count = mm_node->size << PAGE_SHIFT; + uint64_t dst_addr; - dst_offset += cur_size_in_bytes; - byte_count -= cur_size_in_bytes; + r = amdgpu_mm_node_addr(&bo->tbo, mm_node, + &bo->tbo.mem, &dst_addr); + if (r) + return r; + + while (byte_count) { + uint32_t cur_size_in_bytes = min(byte_count, max_bytes); + + amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, + dst_addr, cur_size_in_bytes); + + dst_addr += cur_size_in_bytes; + byte_count -= cur_size_in_bytes; + } + + num_pages -= mm_node->size; + ++mm_node; } amdgpu_ring_pad_ib(ring, &job->ibs[0]); WARN_ON(job->ibs[0].length_dw > num_dw); r = amdgpu_job_submit(job, ring, &adev->mman.entity, - AMDGPU_FENCE_OWNER_UNDEFINED, fence); + AMDGPU_FENCE_OWNER_UNDEFINED, fence); if (r) goto error_free; @@ -1554,8 +1653,3 @@ static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) #endif } - -u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev) -{ - return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object); -} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 9812c805326c..98ee384f0fca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -66,6 +66,7 @@ struct amdgpu_mman { }; extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func; +extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func; int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, struct ttm_buffer_object *tbo, @@ -77,11 +78,11 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t dst_offset, uint32_t byte_count, struct reservation_object *resv, - struct fence **fence, bool direct_submit); + struct dma_fence **fence, bool direct_submit); int amdgpu_fill_buffer(struct amdgpu_bo *bo, uint32_t src_data, struct reservation_object *resv, - struct fence **fence); + struct dma_fence **fence); int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); bool amdgpu_ttm_is_bound(struct ttm_tt *ttm); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index cb3d252f3c78..0f0b38191fac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -228,6 +228,9 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode, ucode->mc_addr = mc_addr; ucode->kaddr = kptr; + if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) + return 0; + header = (const struct common_firmware_header *)ucode->fw->data; memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + le32_to_cpu(header->ucode_array_offset_bytes)), @@ -236,6 +239,31 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode, return 0; } +static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, + uint64_t mc_addr, void *kptr) +{ + const struct gfx_firmware_header_v1_0 *header = NULL; + const struct common_firmware_header *comm_hdr = NULL; + uint8_t* src_addr = NULL; + uint8_t* dst_addr = NULL; + + if (NULL == ucode->fw) + return 0; + + comm_hdr = (const struct common_firmware_header *)ucode->fw->data; + header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + dst_addr = ucode->kaddr + + ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), + PAGE_SIZE); + src_addr = (uint8_t *)ucode->fw->data + + le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + + (le32_to_cpu(header->jt_offset) * 4); + memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); + + return 0; +} + + int amdgpu_ucode_init_bo(struct amdgpu_device *adev) { struct amdgpu_bo **bo = &adev->firmware.fw_buf; @@ -247,7 +275,8 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) const struct common_firmware_header *header = NULL; err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, bo); + amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, + 0, NULL, NULL, bo); if (err) { dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); goto failed; @@ -259,7 +288,8 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) goto failed_reserve; } - err = amdgpu_bo_pin(*bo, AMDGPU_GEM_DOMAIN_GTT, &fw_mc_addr); + err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, + &fw_mc_addr); if (err) { dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); goto failed_pin; @@ -279,6 +309,13 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) header = (const struct common_firmware_header *)ucode->fw->data; amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset, fw_buf_ptr + fw_offset); + if (i == AMDGPU_UCODE_ID_CP_MEC1) { + const struct gfx_firmware_header_v1_0 *cp_hdr; + cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset, + fw_buf_ptr + fw_offset); + fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); + } fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index e468be4e28fa..a8a4230729f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -130,6 +130,7 @@ enum AMDGPU_UCODE_ID { AMDGPU_UCODE_ID_CP_MEC1, AMDGPU_UCODE_ID_CP_MEC2, AMDGPU_UCODE_ID_RLC_G, + AMDGPU_UCODE_ID_STORAGE, AMDGPU_UCODE_ID_MAXIMUM, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index e3281cacc586..a81dfaeeb8c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -333,7 +333,7 @@ void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) for (i = 0; i < adev->uvd.max_handles; ++i) { uint32_t handle = atomic_read(&adev->uvd.handles[i]); if (handle != 0 && adev->uvd.filp[i] == filp) { - struct fence *fence; + struct dma_fence *fence; r = amdgpu_uvd_get_destroy_msg(ring, handle, false, &fence); @@ -342,8 +342,8 @@ void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) continue; } - fence_wait(fence, false); - fence_put(fence); + dma_fence_wait(fence, false); + dma_fence_put(fence); adev->uvd.filp[i] = NULL; atomic_set(&adev->uvd.handles[i], 0); @@ -360,6 +360,18 @@ static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) } } +static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) +{ + uint32_t lo, hi; + uint64_t addr; + + lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); + hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); + addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); + + return addr; +} + /** * amdgpu_uvd_cs_pass1 - first parsing round * @@ -372,14 +384,10 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) { struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; - uint32_t cmd, lo, hi; - uint64_t addr; + uint32_t cmd; + uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); int r = 0; - lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); - hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); - addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); - mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); if (mapping == NULL) { DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); @@ -698,18 +706,16 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) { struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; - uint32_t cmd, lo, hi; + uint32_t cmd; uint64_t start, end; - uint64_t addr; + uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); int r; - lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); - hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); - addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); - mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); - if (mapping == NULL) + if (mapping == NULL) { + DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); return -EINVAL; + } start = amdgpu_bo_gpu_offset(bo); @@ -876,6 +882,9 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; int r; + parser->job->vm = NULL; + ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); + if (ib->length_dw % 16) { DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", ib->length_dw); @@ -890,10 +899,13 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) ctx.buf_sizes = buf_sizes; ctx.ib_idx = ib_idx; - /* first round, make sure the buffers are actually in the UVD segment */ - r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); - if (r) - return r; + /* first round only required on chips without UVD 64 bit address support */ + if (!parser->adev->uvd.address_64_bit) { + /* first round, make sure the buffers are actually in the UVD segment */ + r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); + if (r) + return r; + } /* second round, patch buffer addresses into the command stream */ r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); @@ -909,14 +921,14 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) } static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, - bool direct, struct fence **fence) + bool direct, struct dma_fence **fence) { struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct list_head head; struct amdgpu_job *job; struct amdgpu_ib *ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; struct amdgpu_device *adev = ring->adev; uint64_t addr; int i, r; @@ -931,7 +943,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, if (r) return r; - if (!bo->adev->uvd.address_64_bit) { + if (!ring->adev->uvd.address_64_bit) { amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); amdgpu_uvd_force_into_uvd_segment(bo); } @@ -960,7 +972,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, if (direct) { r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); - job->fence = fence_get(f); + job->fence = dma_fence_get(f); if (r) goto err_free; @@ -975,9 +987,9 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, ttm_eu_fence_buffer_objects(&ticket, &head, f); if (fence) - *fence = fence_get(f); + *fence = dma_fence_get(f); amdgpu_bo_unref(&bo); - fence_put(f); + dma_fence_put(f); return 0; @@ -993,7 +1005,7 @@ err: crash the vcpu so just try to emmit a dummy create/destroy msg to avoid this */ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, - struct fence **fence) + struct dma_fence **fence) { struct amdgpu_device *adev = ring->adev; struct amdgpu_bo *bo; @@ -1002,7 +1014,8 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &bo); if (r) return r; @@ -1042,7 +1055,7 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, } int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, - bool direct, struct fence **fence) + bool direct, struct dma_fence **fence) { struct amdgpu_device *adev = ring->adev; struct amdgpu_bo *bo; @@ -1051,7 +1064,8 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &bo); if (r) return r; @@ -1128,7 +1142,7 @@ void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) */ int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) { - struct fence *fence; + struct dma_fence *fence; long r; r = amdgpu_uvd_get_create_msg(ring, 1, NULL); @@ -1143,7 +1157,7 @@ int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) goto error; } - r = fence_wait_timeout(fence, false, timeout); + r = dma_fence_wait_timeout(fence, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out.\n"); r = -ETIMEDOUT; @@ -1154,7 +1168,7 @@ int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = 0; } - fence_put(fence); + dma_fence_put(fence); error: return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h index c850009602d1..6249ba1bde2a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h @@ -29,9 +29,9 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev); int amdgpu_uvd_suspend(struct amdgpu_device *adev); int amdgpu_uvd_resume(struct amdgpu_device *adev); int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, - struct fence **fence); + struct dma_fence **fence); int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, - bool direct, struct fence **fence); + bool direct, struct dma_fence **fence); void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp); int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 7fe8fd884f06..69b66b9e7f57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -157,7 +157,8 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->vce.vcpu_bo); if (r) { dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r); @@ -395,12 +396,12 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp) * Open up a stream for HW test */ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, - struct fence **fence) + struct dma_fence **fence) { const unsigned ib_size_dw = 1024; struct amdgpu_job *job; struct amdgpu_ib *ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; uint64_t dummy; int i, r; @@ -450,14 +451,14 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, ib->ptr[i] = 0x0; r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); - job->fence = fence_get(f); + job->fence = dma_fence_get(f); if (r) goto err; amdgpu_job_free(job); if (fence) - *fence = fence_get(f); - fence_put(f); + *fence = dma_fence_get(f); + dma_fence_put(f); return 0; err: @@ -476,12 +477,12 @@ err: * Close up a stream for HW test or if userspace failed to do so */ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, - bool direct, struct fence **fence) + bool direct, struct dma_fence **fence) { const unsigned ib_size_dw = 1024; struct amdgpu_job *job; struct amdgpu_ib *ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); @@ -513,7 +514,7 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, if (direct) { r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f); - job->fence = fence_get(f); + job->fence = dma_fence_get(f); if (r) goto err; @@ -526,8 +527,8 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, } if (fence) - *fence = fence_get(f); - fence_put(f); + *fence = dma_fence_get(f); + dma_fence_put(f); return 0; err: @@ -641,6 +642,9 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) uint32_t *size = &tmp; int i, r, idx = 0; + p->job->vm = NULL; + ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); + r = amdgpu_cs_sysvm_access_required(p); if (r) return r; @@ -788,6 +792,96 @@ out: } /** + * amdgpu_vce_cs_parse_vm - parse the command stream in VM mode + * + * @p: parser context + * + */ +int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx) +{ + struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; + int session_idx = -1; + uint32_t destroyed = 0; + uint32_t created = 0; + uint32_t allocated = 0; + uint32_t tmp, handle = 0; + int i, r = 0, idx = 0; + + while (idx < ib->length_dw) { + uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); + uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); + + if ((len < 8) || (len & 3)) { + DRM_ERROR("invalid VCE command length (%d)!\n", len); + r = -EINVAL; + goto out; + } + + switch (cmd) { + case 0x00000001: /* session */ + handle = amdgpu_get_ib_value(p, ib_idx, idx + 2); + session_idx = amdgpu_vce_validate_handle(p, handle, + &allocated); + if (session_idx < 0) { + r = session_idx; + goto out; + } + break; + + case 0x01000001: /* create */ + created |= 1 << session_idx; + if (destroyed & (1 << session_idx)) { + destroyed &= ~(1 << session_idx); + allocated |= 1 << session_idx; + + } else if (!(allocated & (1 << session_idx))) { + DRM_ERROR("Handle already in use!\n"); + r = -EINVAL; + goto out; + } + + break; + + case 0x02000001: /* destroy */ + destroyed |= 1 << session_idx; + break; + + default: + break; + } + + if (session_idx == -1) { + DRM_ERROR("no session command at start of IB\n"); + r = -EINVAL; + goto out; + } + + idx += len / 4; + } + + if (allocated & ~created) { + DRM_ERROR("New session without create command!\n"); + r = -ENOENT; + } + +out: + if (!r) { + /* No error, free all destroyed handle slots */ + tmp = destroyed; + amdgpu_ib_free(p->adev, ib, NULL); + } else { + /* Error during parsing, free all allocated handle slots */ + tmp = allocated; + } + + for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) + if (tmp & (1 << i)) + atomic_set(&p->adev->vce.handles[i], 0); + + return r; +} + +/** * amdgpu_vce_ring_emit_ib - execute indirect buffer * * @ring: engine to use @@ -823,18 +917,6 @@ void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, amdgpu_ring_write(ring, VCE_CMD_END); } -unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 4; /* amdgpu_vce_ring_emit_ib */ -} - -unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 6; /* amdgpu_vce_ring_emit_fence x1 no user fence */ -} - /** * amdgpu_vce_ring_test_ring - test if VCE ring is working * @@ -883,7 +965,7 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) */ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) { - struct fence *fence = NULL; + struct dma_fence *fence = NULL; long r; /* skip vce ring1/2 ib test for now, since it's not reliable */ @@ -902,7 +984,7 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) goto error; } - r = fence_wait_timeout(fence, false, timeout); + r = dma_fence_wait_timeout(fence, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out.\n"); r = -ETIMEDOUT; @@ -913,6 +995,6 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = 0; } error: - fence_put(fence); + dma_fence_put(fence); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 12729d2852df..d98041f7508d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -29,11 +29,12 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev); int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, - struct fence **fence); + struct dma_fence **fence); int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, - bool direct, struct fence **fence); + bool direct, struct dma_fence **fence); void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); +int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx); void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, unsigned vm_id, bool ctx_switch); void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 968c4260d7a7..1dda9321bd5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -25,7 +25,7 @@ * Alex Deucher * Jerome Glisse */ -#include <linux/fence-array.h> +#include <linux/dma-fence-array.h> #include <drm/drmP.h> #include <drm/amdgpu_drm.h> #include "amdgpu.h" @@ -116,38 +116,43 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, } /** - * amdgpu_vm_get_bos - add the vm BOs to a duplicates list + * amdgpu_vm_validate_pt_bos - validate the page table BOs * * @adev: amdgpu device pointer * @vm: vm providing the BOs - * @duplicates: head of duplicates list + * @validate: callback to do the validation + * @param: parameter for the validation callback * - * Add the page directory to the BO duplicates list - * for command submission. + * Validate the page table BOs on command submission if neccessary. */ -void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, - struct list_head *duplicates) +int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, + int (*validate)(void *p, struct amdgpu_bo *bo), + void *param) { uint64_t num_evictions; unsigned i; + int r; /* We only need to validate the page tables * if they aren't already valid. */ num_evictions = atomic64_read(&adev->num_evictions); if (num_evictions == vm->last_eviction_counter) - return; + return 0; /* add the vm page table to the list */ for (i = 0; i <= vm->max_pde_used; ++i) { - struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; + struct amdgpu_bo *bo = vm->page_tables[i].bo; - if (!entry->robj) + if (!bo) continue; - list_add(&entry->tv.head, duplicates); + r = validate(param, bo); + if (r) + return r; } + return 0; } /** @@ -166,12 +171,12 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, spin_lock(&glob->lru_lock); for (i = 0; i <= vm->max_pde_used; ++i) { - struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; + struct amdgpu_bo *bo = vm->page_tables[i].bo; - if (!entry->robj) + if (!bo) continue; - ttm_bo_move_to_lru_tail(&entry->robj->tbo); + ttm_bo_move_to_lru_tail(&bo->tbo); } spin_unlock(&glob->lru_lock); } @@ -194,14 +199,14 @@ static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev, * Allocate an id for the vm, adding fences to the sync obj as necessary. */ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, - struct amdgpu_sync *sync, struct fence *fence, + struct amdgpu_sync *sync, struct dma_fence *fence, struct amdgpu_job *job) { struct amdgpu_device *adev = ring->adev; uint64_t fence_context = adev->fence_context + ring->idx; - struct fence *updates = sync->last_vm_update; + struct dma_fence *updates = sync->last_vm_update; struct amdgpu_vm_id *id, *idle; - struct fence **fences; + struct dma_fence **fences; unsigned i; int r = 0; @@ -225,17 +230,17 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, if (&idle->list == &adev->vm_manager.ids_lru) { u64 fence_context = adev->vm_manager.fence_context + ring->idx; unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; - struct fence_array *array; + struct dma_fence_array *array; unsigned j; for (j = 0; j < i; ++j) - fence_get(fences[j]); + dma_fence_get(fences[j]); - array = fence_array_create(i, fences, fence_context, + array = dma_fence_array_create(i, fences, fence_context, seqno, true); if (!array) { for (j = 0; j < i; ++j) - fence_put(fences[j]); + dma_fence_put(fences[j]); kfree(fences); r = -ENOMEM; goto error; @@ -243,7 +248,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, r = amdgpu_sync_fence(ring->adev, sync, &array->base); - fence_put(&array->base); + dma_fence_put(&array->base); if (r) goto error; @@ -257,7 +262,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, /* Check if we can use a VMID already assigned to this VM */ i = ring->idx; do { - struct fence *flushed; + struct dma_fence *flushed; id = vm->ids[i++]; if (i == AMDGPU_MAX_RINGS) @@ -279,12 +284,12 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, continue; if (id->last_flush->context != fence_context && - !fence_is_signaled(id->last_flush)) + !dma_fence_is_signaled(id->last_flush)) continue; flushed = id->flushed_updates; if (updates && - (!flushed || fence_is_later(updates, flushed))) + (!flushed || dma_fence_is_later(updates, flushed))) continue; /* Good we can use this VMID. Remember this submission as @@ -315,14 +320,14 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, if (r) goto error; - fence_put(id->first); - id->first = fence_get(fence); + dma_fence_put(id->first); + id->first = dma_fence_get(fence); - fence_put(id->last_flush); + dma_fence_put(id->last_flush); id->last_flush = NULL; - fence_put(id->flushed_updates); - id->flushed_updates = fence_get(updates); + dma_fence_put(id->flushed_updates); + id->flushed_updates = dma_fence_get(updates); id->pd_gpu_addr = job->vm_pd_addr; id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); @@ -341,9 +346,9 @@ error: static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - const struct amdgpu_ip_block_version *ip_block; + const struct amdgpu_ip_block *ip_block; - if (ring->type != AMDGPU_RING_TYPE_COMPUTE) + if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) /* only compute rings */ return false; @@ -351,10 +356,10 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) if (!ip_block) return false; - if (ip_block->major <= 7) { + if (ip_block->version->major <= 7) { /* gfx7 has no workaround */ return true; - } else if (ip_block->major == 8) { + } else if (ip_block->version->major == 8) { if (adev->gfx.mec_fw_version >= 673) /* gfx8 is fixed in MEC firmware 673 */ return false; @@ -393,7 +398,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) if (ring->funcs->emit_vm_flush && (job->vm_needs_flush || amdgpu_vm_is_gpu_reset(adev, id))) { - struct fence *fence; + struct dma_fence *fence; trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id); amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); @@ -403,7 +408,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job) return r; mutex_lock(&adev->vm_manager.lock); - fence_put(id->last_flush); + dma_fence_put(id->last_flush); id->last_flush = fence; mutex_unlock(&adev->vm_manager.lock); } @@ -525,70 +530,6 @@ static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, } /** - * amdgpu_vm_clear_bo - initially clear the page dir/table - * - * @adev: amdgpu_device pointer - * @bo: bo to clear - * - * need to reserve bo first before calling it. - */ -static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, - struct amdgpu_vm *vm, - struct amdgpu_bo *bo) -{ - struct amdgpu_ring *ring; - struct fence *fence = NULL; - struct amdgpu_job *job; - struct amdgpu_pte_update_params params; - unsigned entries; - uint64_t addr; - int r; - - ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); - - r = reservation_object_reserve_shared(bo->tbo.resv); - if (r) - return r; - - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); - if (r) - goto error; - - r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); - if (r) - goto error; - - addr = amdgpu_bo_gpu_offset(bo); - entries = amdgpu_bo_size(bo) / 8; - - r = amdgpu_job_alloc_with_ib(adev, 64, &job); - if (r) - goto error; - - memset(¶ms, 0, sizeof(params)); - params.adev = adev; - params.ib = &job->ibs[0]; - amdgpu_vm_do_set_ptes(¶ms, addr, 0, entries, 0, 0); - amdgpu_ring_pad_ib(ring, &job->ibs[0]); - - WARN_ON(job->ibs[0].length_dw > 64); - r = amdgpu_job_submit(job, ring, &vm->entity, - AMDGPU_FENCE_OWNER_VM, &fence); - if (r) - goto error_free; - - amdgpu_bo_fence(bo, fence, true); - fence_put(fence); - return 0; - -error_free: - amdgpu_job_free(job); - -error: - return r; -} - -/** * amdgpu_vm_map_gart - Resolve gart mapping of addr * * @pages_addr: optional DMA address to use for lookup @@ -612,32 +553,35 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) return result; } -static int amdgpu_vm_update_pd_or_shadow(struct amdgpu_device *adev, - struct amdgpu_vm *vm, - bool shadow) +/* + * amdgpu_vm_update_pdes - make sure that page directory is valid + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * @start: start of GPU address range + * @end: end of GPU address range + * + * Allocates new page tables if necessary + * and updates the page directory. + * Returns 0 for success, error for failure. + */ +int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, + struct amdgpu_vm *vm) { + struct amdgpu_bo *shadow; struct amdgpu_ring *ring; - struct amdgpu_bo *pd = shadow ? vm->page_directory->shadow : - vm->page_directory; - uint64_t pd_addr; + uint64_t pd_addr, shadow_addr; uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; - uint64_t last_pde = ~0, last_pt = ~0; + uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; unsigned count = 0, pt_idx, ndw; struct amdgpu_job *job; struct amdgpu_pte_update_params params; - struct fence *fence = NULL; + struct dma_fence *fence = NULL; int r; - if (!pd) - return 0; - - r = amdgpu_ttm_bind(&pd->tbo, &pd->tbo.mem); - if (r) - return r; - - pd_addr = amdgpu_bo_gpu_offset(pd); ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); + shadow = vm->page_directory->shadow; /* padding, etc. */ ndw = 64; @@ -645,6 +589,17 @@ static int amdgpu_vm_update_pd_or_shadow(struct amdgpu_device *adev, /* assume the worst case */ ndw += vm->max_pde_used * 6; + pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); + if (shadow) { + r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); + if (r) + return r; + shadow_addr = amdgpu_bo_gpu_offset(shadow); + ndw *= 2; + } else { + shadow_addr = 0; + } + r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); if (r) return r; @@ -655,30 +610,26 @@ static int amdgpu_vm_update_pd_or_shadow(struct amdgpu_device *adev, /* walk over the address space and update the page directory */ for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { - struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; + struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo; uint64_t pde, pt; if (bo == NULL) continue; if (bo->shadow) { - struct amdgpu_bo *shadow = bo->shadow; + struct amdgpu_bo *pt_shadow = bo->shadow; - r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); + r = amdgpu_ttm_bind(&pt_shadow->tbo, + &pt_shadow->tbo.mem); if (r) return r; } pt = amdgpu_bo_gpu_offset(bo); - if (!shadow) { - if (vm->page_tables[pt_idx].addr == pt) - continue; - vm->page_tables[pt_idx].addr = pt; - } else { - if (vm->page_tables[pt_idx].shadow_addr == pt) - continue; - vm->page_tables[pt_idx].shadow_addr = pt; - } + if (vm->page_tables[pt_idx].addr == pt) + continue; + + vm->page_tables[pt_idx].addr = pt; pde = pd_addr + pt_idx * 8; if (((last_pde + 8 * count) != pde) || @@ -686,6 +637,13 @@ static int amdgpu_vm_update_pd_or_shadow(struct amdgpu_device *adev, (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { if (count) { + if (shadow) + amdgpu_vm_do_set_ptes(¶ms, + last_shadow, + last_pt, count, + incr, + AMDGPU_PTE_VALID); + amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt, count, incr, AMDGPU_PTE_VALID); @@ -693,34 +651,44 @@ static int amdgpu_vm_update_pd_or_shadow(struct amdgpu_device *adev, count = 1; last_pde = pde; + last_shadow = shadow_addr + pt_idx * 8; last_pt = pt; } else { ++count; } } - if (count) + if (count) { + if (vm->page_directory->shadow) + amdgpu_vm_do_set_ptes(¶ms, last_shadow, last_pt, + count, incr, AMDGPU_PTE_VALID); + amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt, count, incr, AMDGPU_PTE_VALID); + } - if (params.ib->length_dw != 0) { - amdgpu_ring_pad_ib(ring, params.ib); - amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, + if (params.ib->length_dw == 0) { + amdgpu_job_free(job); + return 0; + } + + amdgpu_ring_pad_ib(ring, params.ib); + amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, + AMDGPU_FENCE_OWNER_VM); + if (shadow) + amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv, AMDGPU_FENCE_OWNER_VM); - WARN_ON(params.ib->length_dw > ndw); - r = amdgpu_job_submit(job, ring, &vm->entity, - AMDGPU_FENCE_OWNER_VM, &fence); - if (r) - goto error_free; - amdgpu_bo_fence(pd, fence, true); - fence_put(vm->page_directory_fence); - vm->page_directory_fence = fence_get(fence); - fence_put(fence); + WARN_ON(params.ib->length_dw > ndw); + r = amdgpu_job_submit(job, ring, &vm->entity, + AMDGPU_FENCE_OWNER_VM, &fence); + if (r) + goto error_free; - } else { - amdgpu_job_free(job); - } + amdgpu_bo_fence(vm->page_directory, fence, true); + dma_fence_put(vm->page_directory_fence); + vm->page_directory_fence = dma_fence_get(fence); + dma_fence_put(fence); return 0; @@ -729,29 +697,6 @@ error_free: return r; } -/* - * amdgpu_vm_update_pdes - make sure that page directory is valid - * - * @adev: amdgpu_device pointer - * @vm: requested vm - * @start: start of GPU address range - * @end: end of GPU address range - * - * Allocates new page tables if necessary - * and updates the page directory. - * Returns 0 for success, error for failure. - */ -int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, - struct amdgpu_vm *vm) -{ - int r; - - r = amdgpu_vm_update_pd_or_shadow(adev, vm, true); - if (r) - return r; - return amdgpu_vm_update_pd_or_shadow(adev, vm, false); -} - /** * amdgpu_vm_update_ptes - make sure that page tables are valid * @@ -781,11 +726,11 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, /* initialize the variables */ addr = start; pt_idx = addr >> amdgpu_vm_block_size; - pt = vm->page_tables[pt_idx].entry.robj; + pt = vm->page_tables[pt_idx].bo; if (params->shadow) { if (!pt->shadow) return; - pt = vm->page_tables[pt_idx].entry.robj->shadow; + pt = pt->shadow; } if ((addr & ~mask) == (end & ~mask)) nptes = end - addr; @@ -804,11 +749,11 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, /* walk over the address space and update the page tables */ while (addr < end) { pt_idx = addr >> amdgpu_vm_block_size; - pt = vm->page_tables[pt_idx].entry.robj; + pt = vm->page_tables[pt_idx].bo; if (params->shadow) { if (!pt->shadow) return; - pt = vm->page_tables[pt_idx].entry.robj->shadow; + pt = pt->shadow; } if ((addr & ~mask) == (end & ~mask)) @@ -929,20 +874,20 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, * Returns 0 for success, -EINVAL for failure. */ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, - struct fence *exclusive, + struct dma_fence *exclusive, uint64_t src, dma_addr_t *pages_addr, struct amdgpu_vm *vm, uint64_t start, uint64_t last, uint32_t flags, uint64_t addr, - struct fence **fence) + struct dma_fence **fence) { struct amdgpu_ring *ring; void *owner = AMDGPU_FENCE_OWNER_VM; unsigned nptes, ncmds, ndw; struct amdgpu_job *job; struct amdgpu_pte_update_params params; - struct fence *f = NULL; + struct dma_fence *f = NULL; int r; memset(¶ms, 0, sizeof(params)); @@ -1045,10 +990,10 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, amdgpu_bo_fence(vm->page_directory, f, true); if (fence) { - fence_put(*fence); - *fence = fence_get(f); + dma_fence_put(*fence); + *fence = dma_fence_get(f); } - fence_put(f); + dma_fence_put(f); return 0; error_free: @@ -1065,8 +1010,8 @@ error_free: * @pages_addr: DMA addresses to use for mapping * @vm: requested vm * @mapping: mapped range and flags to use for the update - * @addr: addr to set the area to * @flags: HW flags for the mapping + * @nodes: array of drm_mm_nodes with the MC addresses * @fence: optional resulting fence * * Split the mapping into smaller chunks so that each update fits @@ -1074,17 +1019,16 @@ error_free: * Returns 0 for success, -EINVAL for failure. */ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, - struct fence *exclusive, + struct dma_fence *exclusive, uint32_t gtt_flags, dma_addr_t *pages_addr, struct amdgpu_vm *vm, struct amdgpu_bo_va_mapping *mapping, - uint32_t flags, uint64_t addr, - struct fence **fence) + uint32_t flags, + struct drm_mm_node *nodes, + struct dma_fence **fence) { - const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; - - uint64_t src = 0, start = mapping->it.start; + uint64_t pfn, src = 0, start = mapping->it.start; int r; /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here @@ -1097,23 +1041,40 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, trace_amdgpu_vm_bo_update(mapping); - if (pages_addr) { - if (flags == gtt_flags) - src = adev->gart.table_addr + (addr >> 12) * 8; - addr = 0; + pfn = mapping->offset >> PAGE_SHIFT; + if (nodes) { + while (pfn >= nodes->size) { + pfn -= nodes->size; + ++nodes; + } } - addr += mapping->offset; - if (!pages_addr || src) - return amdgpu_vm_bo_update_mapping(adev, exclusive, - src, pages_addr, vm, - start, mapping->it.last, - flags, addr, fence); + do { + uint64_t max_entries; + uint64_t addr, last; - while (start != mapping->it.last + 1) { - uint64_t last; + if (nodes) { + addr = nodes->start << PAGE_SHIFT; + max_entries = (nodes->size - pfn) * + (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); + } else { + addr = 0; + max_entries = S64_MAX; + } - last = min((uint64_t)mapping->it.last, start + max_size - 1); + if (pages_addr) { + if (flags == gtt_flags) + src = adev->gart.table_addr + + (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8; + else + max_entries = min(max_entries, 16ull * 1024ull); + addr = 0; + } else if (flags & AMDGPU_PTE_VALID) { + addr += adev->vm_manager.vram_base_offset; + } + addr += pfn << PAGE_SHIFT; + + last = min((uint64_t)mapping->it.last, start + max_entries - 1); r = amdgpu_vm_bo_update_mapping(adev, exclusive, src, pages_addr, vm, start, last, flags, addr, @@ -1121,9 +1082,14 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, if (r) return r; + pfn += last - start + 1; + if (nodes && nodes->size == pfn) { + pfn = 0; + ++nodes; + } start = last + 1; - addr += max_size * AMDGPU_GPU_PAGE_SIZE; - } + + } while (unlikely(start != mapping->it.last + 1)); return 0; } @@ -1147,40 +1113,30 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, dma_addr_t *pages_addr = NULL; uint32_t gtt_flags, flags; struct ttm_mem_reg *mem; - struct fence *exclusive; - uint64_t addr; + struct drm_mm_node *nodes; + struct dma_fence *exclusive; int r; if (clear) { mem = NULL; - addr = 0; + nodes = NULL; exclusive = NULL; } else { struct ttm_dma_tt *ttm; mem = &bo_va->bo->tbo.mem; - addr = (u64)mem->start << PAGE_SHIFT; - switch (mem->mem_type) { - case TTM_PL_TT: + nodes = mem->mm_node; + if (mem->mem_type == TTM_PL_TT) { ttm = container_of(bo_va->bo->tbo.ttm, struct ttm_dma_tt, ttm); pages_addr = ttm->dma_address; - break; - - case TTM_PL_VRAM: - addr += adev->vm_manager.vram_base_offset; - break; - - default: - break; } - exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); } flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && - adev == bo_va->bo->adev) ? flags : 0; + adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? flags : 0; spin_lock(&vm->status_lock); if (!list_empty(&bo_va->vm_status)) @@ -1190,7 +1146,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, list_for_each_entry(mapping, &bo_va->invalids, list) { r = amdgpu_vm_bo_split_mapping(adev, exclusive, gtt_flags, pages_addr, vm, - mapping, flags, addr, + mapping, flags, nodes, &bo_va->last_pt_update); if (r) return r; @@ -1405,18 +1361,18 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, /* walk over the address space and allocate the page tables */ for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { struct reservation_object *resv = vm->page_directory->tbo.resv; - struct amdgpu_bo_list_entry *entry; struct amdgpu_bo *pt; - entry = &vm->page_tables[pt_idx].entry; - if (entry->robj) + if (vm->page_tables[pt_idx].bo) continue; r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, AMDGPU_GPU_PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_NO_CPU_ACCESS | - AMDGPU_GEM_CREATE_SHADOW, + AMDGPU_GEM_CREATE_SHADOW | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED, NULL, resv, &pt); if (r) goto error_free; @@ -1426,27 +1382,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, */ pt->parent = amdgpu_bo_ref(vm->page_directory); - r = amdgpu_vm_clear_bo(adev, vm, pt); - if (r) { - amdgpu_bo_unref(&pt->shadow); - amdgpu_bo_unref(&pt); - goto error_free; - } - - if (pt->shadow) { - r = amdgpu_vm_clear_bo(adev, vm, pt->shadow); - if (r) { - amdgpu_bo_unref(&pt->shadow); - amdgpu_bo_unref(&pt); - goto error_free; - } - } - - entry->robj = pt; - entry->priority = 0; - entry->tv.bo = &entry->robj->tbo; - entry->tv.shared = true; - entry->user_pages = NULL; + vm->page_tables[pt_idx].bo = pt; vm->page_tables[pt_idx].addr = 0; } @@ -1547,7 +1483,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, kfree(mapping); } - fence_put(bo_va->last_pt_update); + dma_fence_put(bo_va->last_pt_update); kfree(bo_va); } @@ -1626,7 +1562,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) r = amdgpu_bo_create(adev, pd_size, align, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_NO_CPU_ACCESS | - AMDGPU_GEM_CREATE_SHADOW, + AMDGPU_GEM_CREATE_SHADOW | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED, NULL, NULL, &vm->page_directory); if (r) goto error_free_sched_entity; @@ -1635,24 +1573,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) if (r) goto error_free_page_directory; - r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); - if (r) - goto error_unreserve; - - if (vm->page_directory->shadow) { - r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory->shadow); - if (r) - goto error_unreserve; - } - vm->last_eviction_counter = atomic64_read(&adev->num_evictions); amdgpu_bo_unreserve(vm->page_directory); return 0; -error_unreserve: - amdgpu_bo_unreserve(vm->page_directory); - error_free_page_directory: amdgpu_bo_unref(&vm->page_directory->shadow); amdgpu_bo_unref(&vm->page_directory); @@ -1697,7 +1622,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) } for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) { - struct amdgpu_bo *pt = vm->page_tables[i].entry.robj; + struct amdgpu_bo *pt = vm->page_tables[i].bo; if (!pt) continue; @@ -1709,7 +1634,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) amdgpu_bo_unref(&vm->page_directory->shadow); amdgpu_bo_unref(&vm->page_directory); - fence_put(vm->page_directory_fence); + dma_fence_put(vm->page_directory_fence); } /** @@ -1733,7 +1658,8 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) &adev->vm_manager.ids_lru); } - adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); + adev->vm_manager.fence_context = + dma_fence_context_alloc(AMDGPU_MAX_RINGS); for (i = 0; i < AMDGPU_MAX_RINGS; ++i) adev->vm_manager.seqno[i] = 0; @@ -1755,9 +1681,9 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) for (i = 0; i < AMDGPU_NUM_VM; ++i) { struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; - fence_put(adev->vm_manager.ids[i].first); + dma_fence_put(adev->vm_manager.ids[i].first); amdgpu_sync_free(&adev->vm_manager.ids[i].active); - fence_put(id->flushed_updates); - fence_put(id->last_flush); + dma_fence_put(id->flushed_updates); + dma_fence_put(id->last_flush); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h new file mode 100644 index 000000000000..adbc2f5e5c7f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -0,0 +1,205 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ +#ifndef __AMDGPU_VM_H__ +#define __AMDGPU_VM_H__ + +#include <linux/rbtree.h> + +#include "gpu_scheduler.h" +#include "amdgpu_sync.h" +#include "amdgpu_ring.h" + +struct amdgpu_bo_va; +struct amdgpu_job; +struct amdgpu_bo_list_entry; + +/* + * GPUVM handling + */ + +/* maximum number of VMIDs */ +#define AMDGPU_NUM_VM 16 + +/* Maximum number of PTEs the hardware can write with one command */ +#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF + +/* number of entries in page table */ +#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) + +/* PTBs (Page Table Blocks) need to be aligned to 32K */ +#define AMDGPU_VM_PTB_ALIGN_SIZE 32768 + +/* LOG2 number of continuous pages for the fragment field */ +#define AMDGPU_LOG2_PAGES_PER_FRAG 4 + +#define AMDGPU_PTE_VALID (1 << 0) +#define AMDGPU_PTE_SYSTEM (1 << 1) +#define AMDGPU_PTE_SNOOPED (1 << 2) + +/* VI only */ +#define AMDGPU_PTE_EXECUTABLE (1 << 4) + +#define AMDGPU_PTE_READABLE (1 << 5) +#define AMDGPU_PTE_WRITEABLE (1 << 6) + +#define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7) + +/* How to programm VM fault handling */ +#define AMDGPU_VM_FAULT_STOP_NEVER 0 +#define AMDGPU_VM_FAULT_STOP_FIRST 1 +#define AMDGPU_VM_FAULT_STOP_ALWAYS 2 + +struct amdgpu_vm_pt { + struct amdgpu_bo *bo; + uint64_t addr; +}; + +struct amdgpu_vm { + /* tree of virtual addresses mapped */ + struct rb_root va; + + /* protecting invalidated */ + spinlock_t status_lock; + + /* BOs moved, but not yet updated in the PT */ + struct list_head invalidated; + + /* BOs cleared in the PT because of a move */ + struct list_head cleared; + + /* BO mappings freed, but not yet updated in the PT */ + struct list_head freed; + + /* contains the page directory */ + struct amdgpu_bo *page_directory; + unsigned max_pde_used; + struct dma_fence *page_directory_fence; + uint64_t last_eviction_counter; + + /* array of page tables, one for each page directory entry */ + struct amdgpu_vm_pt *page_tables; + + /* for id and flush management per ring */ + struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; + + /* protecting freed */ + spinlock_t freed_lock; + + /* Scheduler entity for page table updates */ + struct amd_sched_entity entity; + + /* client id */ + u64 client_id; +}; + +struct amdgpu_vm_id { + struct list_head list; + struct dma_fence *first; + struct amdgpu_sync active; + struct dma_fence *last_flush; + atomic64_t owner; + + uint64_t pd_gpu_addr; + /* last flushed PD/PT update */ + struct dma_fence *flushed_updates; + + uint32_t current_gpu_reset_count; + + uint32_t gds_base; + uint32_t gds_size; + uint32_t gws_base; + uint32_t gws_size; + uint32_t oa_base; + uint32_t oa_size; +}; + +struct amdgpu_vm_manager { + /* Handling of VMIDs */ + struct mutex lock; + unsigned num_ids; + struct list_head ids_lru; + struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; + + /* Handling of VM fences */ + u64 fence_context; + unsigned seqno[AMDGPU_MAX_RINGS]; + + uint32_t max_pfn; + /* vram base address for page table entry */ + u64 vram_base_offset; + /* is vm enabled? */ + bool enabled; + /* vm pte handling */ + const struct amdgpu_vm_pte_funcs *vm_pte_funcs; + struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; + unsigned vm_pte_num_rings; + atomic_t vm_pte_next_ring; + /* client id counter */ + atomic64_t client_counter; +}; + +void amdgpu_vm_manager_init(struct amdgpu_device *adev); +void amdgpu_vm_manager_fini(struct amdgpu_device *adev); +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); +void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); +void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, + struct list_head *validated, + struct amdgpu_bo_list_entry *entry); +int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, + int (*callback)(void *p, struct amdgpu_bo *bo), + void *param); +void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, + struct amdgpu_vm *vm); +int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, + struct amdgpu_sync *sync, struct dma_fence *fence, + struct amdgpu_job *job); +int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job); +void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); +int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, + struct amdgpu_vm *vm); +int amdgpu_vm_clear_freed(struct amdgpu_device *adev, + struct amdgpu_vm *vm); +int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct amdgpu_sync *sync); +int amdgpu_vm_bo_update(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + bool clear); +void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, + struct amdgpu_bo *bo); +struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, + struct amdgpu_bo *bo); +struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo); +int amdgpu_vm_bo_map(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + uint64_t addr, uint64_t offset, + uint64_t size, uint32_t flags); +int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + uint64_t addr); +void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c new file mode 100644 index 000000000000..d710226a0fff --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -0,0 +1,222 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ + +#include <drm/drmP.h> +#include "amdgpu.h" + +struct amdgpu_vram_mgr { + struct drm_mm mm; + spinlock_t lock; +}; + +/** + * amdgpu_vram_mgr_init - init VRAM manager and DRM MM + * + * @man: TTM memory type manager + * @p_size: maximum size of VRAM + * + * Allocate and initialize the VRAM manager. + */ +static int amdgpu_vram_mgr_init(struct ttm_mem_type_manager *man, + unsigned long p_size) +{ + struct amdgpu_vram_mgr *mgr; + + mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); + if (!mgr) + return -ENOMEM; + + drm_mm_init(&mgr->mm, 0, p_size); + spin_lock_init(&mgr->lock); + man->priv = mgr; + return 0; +} + +/** + * amdgpu_vram_mgr_fini - free and destroy VRAM manager + * + * @man: TTM memory type manager + * + * Destroy and free the VRAM manager, returns -EBUSY if ranges are still + * allocated inside it. + */ +static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man) +{ + struct amdgpu_vram_mgr *mgr = man->priv; + + spin_lock(&mgr->lock); + if (!drm_mm_clean(&mgr->mm)) { + spin_unlock(&mgr->lock); + return -EBUSY; + } + + drm_mm_takedown(&mgr->mm); + spin_unlock(&mgr->lock); + kfree(mgr); + man->priv = NULL; + return 0; +} + +/** + * amdgpu_vram_mgr_new - allocate new ranges + * + * @man: TTM memory type manager + * @tbo: TTM BO we need this range for + * @place: placement flags and restrictions + * @mem: the resulting mem object + * + * Allocate VRAM for the given BO. + */ +static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man, + struct ttm_buffer_object *tbo, + const struct ttm_place *place, + struct ttm_mem_reg *mem) +{ + struct amdgpu_bo *bo = container_of(tbo, struct amdgpu_bo, tbo); + struct amdgpu_vram_mgr *mgr = man->priv; + struct drm_mm *mm = &mgr->mm; + struct drm_mm_node *nodes; + enum drm_mm_search_flags sflags = DRM_MM_SEARCH_DEFAULT; + enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT; + unsigned long lpfn, num_nodes, pages_per_node, pages_left; + unsigned i; + int r; + + lpfn = place->lpfn; + if (!lpfn) + lpfn = man->size; + + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS || + place->lpfn || amdgpu_vram_page_split == -1) { + pages_per_node = ~0ul; + num_nodes = 1; + } else { + pages_per_node = max((uint32_t)amdgpu_vram_page_split, + mem->page_alignment); + num_nodes = DIV_ROUND_UP(mem->num_pages, pages_per_node); + } + + nodes = kcalloc(num_nodes, sizeof(*nodes), GFP_KERNEL); + if (!nodes) + return -ENOMEM; + + if (place->flags & TTM_PL_FLAG_TOPDOWN) { + sflags = DRM_MM_SEARCH_BELOW; + aflags = DRM_MM_CREATE_TOP; + } + + pages_left = mem->num_pages; + + spin_lock(&mgr->lock); + for (i = 0; i < num_nodes; ++i) { + unsigned long pages = min(pages_left, pages_per_node); + uint32_t alignment = mem->page_alignment; + + if (pages == pages_per_node) + alignment = pages_per_node; + else + sflags |= DRM_MM_SEARCH_BEST; + + r = drm_mm_insert_node_in_range_generic(mm, &nodes[i], pages, + alignment, 0, + place->fpfn, lpfn, + sflags, aflags); + if (unlikely(r)) + goto error; + + pages_left -= pages; + } + spin_unlock(&mgr->lock); + + mem->start = num_nodes == 1 ? nodes[0].start : AMDGPU_BO_INVALID_OFFSET; + mem->mm_node = nodes; + + return 0; + +error: + while (i--) + drm_mm_remove_node(&nodes[i]); + spin_unlock(&mgr->lock); + + kfree(nodes); + return r == -ENOSPC ? 0 : r; +} + +/** + * amdgpu_vram_mgr_del - free ranges + * + * @man: TTM memory type manager + * @tbo: TTM BO we need this range for + * @place: placement flags and restrictions + * @mem: TTM memory object + * + * Free the allocated VRAM again. + */ +static void amdgpu_vram_mgr_del(struct ttm_mem_type_manager *man, + struct ttm_mem_reg *mem) +{ + struct amdgpu_vram_mgr *mgr = man->priv; + struct drm_mm_node *nodes = mem->mm_node; + unsigned pages = mem->num_pages; + + if (!mem->mm_node) + return; + + spin_lock(&mgr->lock); + while (pages) { + pages -= nodes->size; + drm_mm_remove_node(nodes); + ++nodes; + } + spin_unlock(&mgr->lock); + + kfree(mem->mm_node); + mem->mm_node = NULL; +} + +/** + * amdgpu_vram_mgr_debug - dump VRAM table + * + * @man: TTM memory type manager + * @prefix: text prefix + * + * Dump the table content using printk. + */ +static void amdgpu_vram_mgr_debug(struct ttm_mem_type_manager *man, + const char *prefix) +{ + struct amdgpu_vram_mgr *mgr = man->priv; + + spin_lock(&mgr->lock); + drm_mm_debug_table(&mgr->mm, prefix); + spin_unlock(&mgr->lock); +} + +const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func = { + amdgpu_vram_mgr_init, + amdgpu_vram_mgr_fini, + amdgpu_vram_mgr_new, + amdgpu_vram_mgr_del, + amdgpu_vram_mgr_debug +}; diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c index f7d236f95e74..8c9bc75a9c2d 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c @@ -31,6 +31,7 @@ #include "atom.h" #include "atom-bits.h" #include "atombios_encoders.h" +#include "atombios_crtc.h" #include "amdgpu_atombios.h" #include "amdgpu_pll.h" #include "amdgpu_connectors.h" diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 5be788b269e2..bda9e3de191e 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -887,9 +887,6 @@ static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) { struct ci_power_info *pi = ci_get_pi(adev); - if (pi->uvd_power_gated == gate) - return; - pi->uvd_power_gated = gate; ci_update_uvd_dpm(adev, gate); @@ -960,6 +957,12 @@ static void ci_apply_state_adjust_rules(struct amdgpu_device *adev, sclk = ps->performance_levels[0].sclk; } + if (adev->pm.pm_display_cfg.min_core_set_clock > sclk) + sclk = adev->pm.pm_display_cfg.min_core_set_clock; + + if (adev->pm.pm_display_cfg.min_mem_set_clock > mclk) + mclk = adev->pm.pm_display_cfg.min_mem_set_clock; + if (rps->vce_active) { if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; @@ -2201,6 +2204,11 @@ static int ci_upload_firmware(struct amdgpu_device *adev) struct ci_power_info *pi = ci_get_pi(adev); int i, ret; + if (amdgpu_ci_is_smc_running(adev)) { + DRM_INFO("smc is running, no need to load smc firmware\n"); + return 0; + } + for (i = 0; i < adev->usec_timeout; i++) { if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK) break; @@ -4190,8 +4198,10 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) { struct ci_power_info *pi = ci_get_pi(adev); u32 tmp; + int ret = 0; if (!gate) { + /* turn the clocks on when decoding */ if (pi->caps_uvd_dpm || (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) pi->smc_state_table.UvdBootLevel = 0; @@ -4203,9 +4213,14 @@ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK; tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT); WREG32_SMC(ixDPM_TABLE_475, tmp); + ret = ci_enable_uvd_dpm(adev, true); + } else { + ret = ci_enable_uvd_dpm(adev, false); + if (ret) + return ret; } - return ci_enable_uvd_dpm(adev, !gate); + return ret; } static u8 ci_get_vce_boot_level(struct amdgpu_device *adev) @@ -4247,13 +4262,12 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev, ret = ci_enable_vce_dpm(adev, true); } else { + ret = ci_enable_vce_dpm(adev, false); + if (ret) + return ret; /* turn the clocks off when not encoding */ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE); - if (ret) - return ret; - - ret = ci_enable_vce_dpm(adev, false); } } return ret; @@ -5219,6 +5233,7 @@ static void ci_update_current_ps(struct amdgpu_device *adev, pi->current_rps = *rps; pi->current_ps = *new_ps; pi->current_rps.ps_priv = &pi->current_ps; + adev->pm.dpm.current_ps = &pi->current_rps; } static void ci_update_requested_ps(struct amdgpu_device *adev, @@ -5230,6 +5245,7 @@ static void ci_update_requested_ps(struct amdgpu_device *adev, pi->requested_rps = *rps; pi->requested_ps = *new_ps; pi->requested_rps.ps_priv = &pi->requested_ps; + adev->pm.dpm.requested_ps = &pi->requested_rps; } static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev) @@ -5267,8 +5283,6 @@ static int ci_dpm_enable(struct amdgpu_device *adev) struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; int ret; - if (amdgpu_ci_is_smc_running(adev)) - return -EINVAL; if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { ci_enable_voltage_control(adev); ret = ci_construct_voltage_tables(adev); @@ -5689,7 +5703,7 @@ static int ci_parse_power_table(struct amdgpu_device *adev) adev->pm.dpm.num_ps = state_array->ucNumEntries; /* fill in the vce power states */ - for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) { + for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { u32 sclk, mclk; clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; clock_info = (union pplib_clock_info *) @@ -5874,7 +5888,7 @@ static int ci_dpm_init(struct amdgpu_device *adev) pi->pcie_dpm_key_disabled = 0; pi->thermal_sclk_dpm_enabled = 0; - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; @@ -5977,7 +5991,7 @@ static int ci_dpm_init(struct amdgpu_device *adev) tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK; break; default: - DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift); + DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift); break; } WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp); @@ -6069,7 +6083,7 @@ ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, activity_percent = activity_percent > 100 ? 100 : activity_percent; } - seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); + seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); seq_printf(m, "power level avg sclk: %u mclk: %u\n", sclk, mclk); @@ -6094,6 +6108,56 @@ static void ci_dpm_print_power_state(struct amdgpu_device *adev, amdgpu_dpm_print_ps_status(adev, rps); } +static inline bool ci_are_power_levels_equal(const struct ci_pl *ci_cpl1, + const struct ci_pl *ci_cpl2) +{ + return ((ci_cpl1->mclk == ci_cpl2->mclk) && + (ci_cpl1->sclk == ci_cpl2->sclk) && + (ci_cpl1->pcie_gen == ci_cpl2->pcie_gen) && + (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane)); +} + +static int ci_check_state_equal(struct amdgpu_device *adev, + struct amdgpu_ps *cps, + struct amdgpu_ps *rps, + bool *equal) +{ + struct ci_ps *ci_cps; + struct ci_ps *ci_rps; + int i; + + if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) + return -EINVAL; + + ci_cps = ci_get_ps(cps); + ci_rps = ci_get_ps(rps); + + if (ci_cps == NULL) { + *equal = false; + return 0; + } + + if (ci_cps->performance_level_count != ci_rps->performance_level_count) { + + *equal = false; + return 0; + } + + for (i = 0; i < ci_cps->performance_level_count; i++) { + if (!ci_are_power_levels_equal(&(ci_cps->performance_levels[i]), + &(ci_rps->performance_levels[i]))) { + *equal = false; + return 0; + } + } + + /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ + *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); + *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); + + return 0; +} + static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low) { struct ci_power_info *pi = ci_get_pi(adev); @@ -6289,12 +6353,19 @@ static int ci_dpm_suspend(void *handle) if (adev->pm.dpm_enabled) { mutex_lock(&adev->pm.mutex); - /* disable dpm */ - ci_dpm_disable(adev); - /* reset the power state */ - adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; + amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); + amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); + adev->pm.dpm.last_user_state = adev->pm.dpm.user_state; + adev->pm.dpm.last_state = adev->pm.dpm.state; + adev->pm.dpm.user_state = POWER_STATE_TYPE_INTERNAL_BOOT; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_BOOT; mutex_unlock(&adev->pm.mutex); + amdgpu_pm_compute_clocks(adev); + } + return 0; } @@ -6312,6 +6383,8 @@ static int ci_dpm_resume(void *handle) adev->pm.dpm_enabled = false; else adev->pm.dpm_enabled = true; + adev->pm.dpm.user_state = adev->pm.dpm.last_user_state; + adev->pm.dpm.state = adev->pm.dpm.last_state; mutex_unlock(&adev->pm.mutex); if (adev->pm.dpm_enabled) amdgpu_pm_compute_clocks(adev); @@ -6646,6 +6719,8 @@ static const struct amdgpu_dpm_funcs ci_dpm_funcs = { .set_sclk_od = ci_dpm_set_sclk_od, .get_mclk_od = ci_dpm_get_mclk_od, .set_mclk_od = ci_dpm_set_mclk_od, + .check_state_equal = ci_check_state_equal, + .get_vce_clock_state = amdgpu_get_vce_clock_state, }; static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev) @@ -6664,3 +6739,12 @@ static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev) adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs; } + +const struct amdgpu_ip_block_version ci_dpm_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &ci_dpm_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index a845b6a93b79..302df85893ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1189,18 +1189,6 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) return r; } -static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) -{ - u32 tmp = RREG32(mmBIOS_SCRATCH_3); - - if (hung) - tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; - else - tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; - - WREG32(mmBIOS_SCRATCH_3, tmp); -} - /** * cik_asic_reset - soft reset GPU * @@ -1213,11 +1201,12 @@ static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hu static int cik_asic_reset(struct amdgpu_device *adev) { int r; - cik_set_bios_scratch_engine_hung(adev, true); + + amdgpu_atombios_scratch_regs_engine_hung(adev, true); r = cik_gpu_pci_config_reset(adev); - cik_set_bios_scratch_engine_hung(adev, false); + amdgpu_atombios_scratch_regs_engine_hung(adev, false); return r; } @@ -1641,745 +1630,6 @@ static void cik_detect_hw_virtualization(struct amdgpu_device *adev) adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE; } -static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 2, - .rev = 0, - .funcs = &dce_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 2, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version bonaire_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 2, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 2, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 5, - .rev = 0, - .funcs = &dce_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 3, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version hawaii_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 5, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 3, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version kabini_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 3, - .rev = 0, - .funcs = &dce_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 2, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version kabini_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 3, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 2, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version mullins_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 3, - .rev = 0, - .funcs = &dce_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 2, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version mullins_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 3, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 2, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 1, - .rev = 0, - .funcs = &dce_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 1, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &cik_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 8, - .minor = 1, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 7, - .minor = 1, - .rev = 0, - .funcs = &gfx_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &cik_sdma_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 4, - .minor = 2, - .rev = 0, - .funcs = &uvd_v4_2_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vce_v2_0_ip_funcs, - }, -}; - -int cik_set_ip_blocks(struct amdgpu_device *adev) -{ - if (adev->enable_virtual_display) { - switch (adev->asic_type) { - case CHIP_BONAIRE: - adev->ip_blocks = bonaire_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_vd); - break; - case CHIP_HAWAII: - adev->ip_blocks = hawaii_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_vd); - break; - case CHIP_KAVERI: - adev->ip_blocks = kaveri_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks_vd); - break; - case CHIP_KABINI: - adev->ip_blocks = kabini_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks_vd); - break; - case CHIP_MULLINS: - adev->ip_blocks = mullins_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks_vd); - break; - default: - /* FIXME: not supported yet */ - return -EINVAL; - } - } else { - switch (adev->asic_type) { - case CHIP_BONAIRE: - adev->ip_blocks = bonaire_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); - break; - case CHIP_HAWAII: - adev->ip_blocks = hawaii_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); - break; - case CHIP_KAVERI: - adev->ip_blocks = kaveri_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks); - break; - case CHIP_KABINI: - adev->ip_blocks = kabini_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks); - break; - case CHIP_MULLINS: - adev->ip_blocks = mullins_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks); - break; - default: - /* FIXME: not supported yet */ - return -EINVAL; - } - } - - return 0; -} - static const struct amdgpu_asic_funcs cik_asic_funcs = { .read_disabled_bios = &cik_read_disabled_bios, @@ -2612,7 +1862,7 @@ static int cik_common_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs cik_common_ip_funcs = { +static const struct amd_ip_funcs cik_common_ip_funcs = { .name = "cik_common", .early_init = cik_common_early_init, .late_init = NULL, @@ -2628,3 +1878,79 @@ const struct amd_ip_funcs cik_common_ip_funcs = { .set_clockgating_state = cik_common_set_clockgating_state, .set_powergating_state = cik_common_set_powergating_state, }; + +static const struct amdgpu_ip_block_version cik_common_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &cik_common_ip_funcs, +}; + +int cik_set_ip_blocks(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_BONAIRE: + amdgpu_ip_block_add(adev, &cik_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); + amdgpu_ip_block_add(adev, &cik_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v8_2_ip_block); + amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); + amdgpu_ip_block_add(adev, &cik_sdma_ip_block); + amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); + amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); + break; + case CHIP_HAWAII: + amdgpu_ip_block_add(adev, &cik_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); + amdgpu_ip_block_add(adev, &cik_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v8_5_ip_block); + amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block); + amdgpu_ip_block_add(adev, &cik_sdma_ip_block); + amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); + amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); + break; + case CHIP_KAVERI: + amdgpu_ip_block_add(adev, &cik_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); + amdgpu_ip_block_add(adev, &cik_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v8_1_ip_block); + amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block); + amdgpu_ip_block_add(adev, &cik_sdma_ip_block); + amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); + amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); + break; + case CHIP_KABINI: + case CHIP_MULLINS: + amdgpu_ip_block_add(adev, &cik_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); + amdgpu_ip_block_add(adev, &cik_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v8_3_ip_block); + amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); + amdgpu_ip_block_add(adev, &cik_sdma_ip_block); + amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); + amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h index 5ebd2d7a0327..c4989f51ecef 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.h +++ b/drivers/gpu/drm/amd/amdgpu/cik.h @@ -24,8 +24,6 @@ #ifndef __CIK_H__ #define __CIK_H__ -extern const struct amd_ip_funcs cik_common_ip_funcs; - void cik_srbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); int cik_set_ip_blocks(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index be3d6f79a864..319b32cdea84 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -413,7 +413,7 @@ static int cik_ih_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs cik_ih_ip_funcs = { +static const struct amd_ip_funcs cik_ih_ip_funcs = { .name = "cik_ih", .early_init = cik_ih_early_init, .late_init = NULL, @@ -441,3 +441,12 @@ static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev) if (adev->irq.ih_funcs == NULL) adev->irq.ih_funcs = &cik_ih_funcs; } + +const struct amdgpu_ip_block_version cik_ih_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_ih_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.h b/drivers/gpu/drm/amd/amdgpu/cik_ih.h index 6b0f375ec244..1d9ddee2868e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.h @@ -24,6 +24,6 @@ #ifndef __CIK_IH_H__ #define __CIK_IH_H__ -extern const struct amd_ip_funcs cik_ih_ip_funcs; +extern const struct amdgpu_ip_block_version cik_ih_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index cb952acc7133..4c34dbc7a254 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -206,10 +206,10 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) for (i = 0; i < count; i++) if (sdma && sdma->burst_nop && (i == 0)) - amdgpu_ring_write(ring, ring->nop | + amdgpu_ring_write(ring, ring->funcs->nop | SDMA_NOP_COUNT(count - 1)); else - amdgpu_ring_write(ring, ring->nop); + amdgpu_ring_write(ring, ring->funcs->nop); } /** @@ -622,7 +622,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; unsigned index; u32 tmp = 0; u64 gpu_addr; @@ -655,7 +655,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) if (r) goto err1; - r = fence_wait_timeout(f, false, timeout); + r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out\n"); r = -ETIMEDOUT; @@ -675,7 +675,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) err1: amdgpu_ib_free(adev, &ib, NULL); - fence_put(f); + dma_fence_put(f); err0: amdgpu_wb_free(adev, index); return r; @@ -848,22 +848,6 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ } -static unsigned cik_sdma_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 7 + 4; /* cik_sdma_ring_emit_ib */ -} - -static unsigned cik_sdma_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 6 + /* cik_sdma_ring_emit_hdp_flush */ - 3 + /* cik_sdma_ring_emit_hdp_invalidate */ - 6 + /* cik_sdma_ring_emit_pipeline_sync */ - 12 + /* cik_sdma_ring_emit_vm_flush */ - 9 + 9 + 9; /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ -} - static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, bool enable) { @@ -959,11 +943,10 @@ static int cik_sdma_sw_init(void *handle) ring->ring_obj = NULL; sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, - SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, &adev->sdma.trap_irq, (i == 0) ? - AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); if (r) return r; } @@ -1207,7 +1190,7 @@ static int cik_sdma_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs cik_sdma_ip_funcs = { +static const struct amd_ip_funcs cik_sdma_ip_funcs = { .name = "cik_sdma", .early_init = cik_sdma_early_init, .late_init = NULL, @@ -1225,10 +1208,19 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { }; static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), .get_rptr = cik_sdma_ring_get_rptr, .get_wptr = cik_sdma_ring_get_wptr, .set_wptr = cik_sdma_ring_set_wptr, - .parse_cs = NULL, + .emit_frame_size = + 6 + /* cik_sdma_ring_emit_hdp_flush */ + 3 + /* cik_sdma_ring_emit_hdp_invalidate */ + 6 + /* cik_sdma_ring_emit_pipeline_sync */ + 12 + /* cik_sdma_ring_emit_vm_flush */ + 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */ .emit_ib = cik_sdma_ring_emit_ib, .emit_fence = cik_sdma_ring_emit_fence, .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, @@ -1239,8 +1231,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .test_ib = cik_sdma_ring_test_ib, .insert_nop = cik_sdma_ring_insert_nop, .pad_ib = cik_sdma_ring_pad_ib, - .get_emit_ib_size = cik_sdma_ring_get_emit_ib_size, - .get_dma_frame_size = cik_sdma_ring_get_dma_frame_size, }; static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) @@ -1352,3 +1342,12 @@ static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; } } + +const struct amdgpu_ip_block_version cik_sdma_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_sdma_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h index 027727c677b8..a4a8fe01410b 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h @@ -24,6 +24,6 @@ #ifndef __CIK_SDMA_H__ #define __CIK_SDMA_H__ -extern const struct amd_ip_funcs cik_sdma_ip_funcs; +extern const struct amdgpu_ip_block_version cik_sdma_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h index 8659852aea9e..6cbd913fd12e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cikd.h +++ b/drivers/gpu/drm/amd/amdgpu/cikd.h @@ -43,6 +43,14 @@ #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) +/* hpd instance offsets */ +#define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) +#define HPD1_REGISTER_OFFSET (0x180a - 0x1807) +#define HPD2_REGISTER_OFFSET (0x180d - 0x1807) +#define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) +#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) +#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) + #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 3c082e143730..ba2b66be9022 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -438,7 +438,7 @@ static int cz_dpm_init(struct amdgpu_device *adev) pi->caps_td_ramping = true; pi->caps_tcp_ramping = true; } - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; @@ -1250,7 +1250,8 @@ static void cz_update_current_ps(struct amdgpu_device *adev, pi->current_ps = *ps; pi->current_rps = *rps; - pi->current_rps.ps_priv = ps; + pi->current_rps.ps_priv = &pi->current_ps; + adev->pm.dpm.current_ps = &pi->current_rps; } @@ -1262,7 +1263,8 @@ static void cz_update_requested_ps(struct amdgpu_device *adev, pi->requested_ps = *ps; pi->requested_rps = *rps; - pi->requested_rps.ps_priv = ps; + pi->requested_rps.ps_priv = &pi->requested_ps; + adev->pm.dpm.requested_ps = &pi->requested_rps; } @@ -2109,9 +2111,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) if (gate) { if (pi->caps_uvd_pg) { - /* disable clockgating so we can properly shut down the block */ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_CG_STATE_GATE); if (ret) { DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n"); return; @@ -2157,9 +2158,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) return; } - /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); + AMD_CG_STATE_UNGATE); if (ret) { DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n"); return; @@ -2257,6 +2257,18 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) } } +static int cz_check_state_equal(struct amdgpu_device *adev, + struct amdgpu_ps *cps, + struct amdgpu_ps *rps, + bool *equal) +{ + if (equal == NULL) + return -EINVAL; + + *equal = false; + return 0; +} + const struct amd_ip_funcs cz_dpm_ip_funcs = { .name = "cz_dpm", .early_init = cz_dpm_early_init, @@ -2289,6 +2301,7 @@ static const struct amdgpu_dpm_funcs cz_dpm_funcs = { .vblank_too_short = NULL, .powergate_uvd = cz_dpm_powergate_uvd, .powergate_vce = cz_dpm_powergate_vce, + .check_state_equal = cz_check_state_equal, }; static void cz_dpm_set_funcs(struct amdgpu_device *adev) @@ -2296,3 +2309,12 @@ static void cz_dpm_set_funcs(struct amdgpu_device *adev) if (NULL == adev->pm.funcs) adev->pm.funcs = &cz_dpm_funcs; } + +const struct amdgpu_ip_block_version cz_dpm_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &cz_dpm_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 3d23a70b6432..fe7cbb24da7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -394,7 +394,7 @@ static int cz_ih_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs cz_ih_ip_funcs = { +static const struct amd_ip_funcs cz_ih_ip_funcs = { .name = "cz_ih", .early_init = cz_ih_early_init, .late_init = NULL, @@ -423,3 +423,11 @@ static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev) adev->irq.ih_funcs = &cz_ih_funcs; } +const struct amdgpu_ip_block_version cz_ih_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &cz_ih_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.h b/drivers/gpu/drm/amd/amdgpu/cz_ih.h index fc4057a2ecb9..14be7753221b 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.h @@ -24,6 +24,6 @@ #ifndef __CZ_IH_H__ #define __CZ_IH_H__ -extern const struct amd_ip_funcs cz_ih_ip_funcs; +extern const struct amdgpu_ip_block_version cz_ih_ip_block; #endif /* __CZ_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 9260caef74fa..9999dc71b998 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -31,6 +31,7 @@ #include "atombios_encoders.h" #include "amdgpu_pll.h" #include "amdgpu_connectors.h" +#include "dce_v10_0.h" #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" @@ -330,33 +331,12 @@ static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd) { - int idx; bool connected = false; - switch (hpd) { - case AMDGPU_HPD_1: - idx = 0; - break; - case AMDGPU_HPD_2: - idx = 1; - break; - case AMDGPU_HPD_3: - idx = 2; - break; - case AMDGPU_HPD_4: - idx = 3; - break; - case AMDGPU_HPD_5: - idx = 4; - break; - case AMDGPU_HPD_6: - idx = 5; - break; - default: + if (hpd >= adev->mode_info.num_hpd) return connected; - } - if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & + if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) connected = true; @@ -376,37 +356,16 @@ static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, { u32 tmp; bool connected = dce_v10_0_hpd_sense(adev, hpd); - int idx; - switch (hpd) { - case AMDGPU_HPD_1: - idx = 0; - break; - case AMDGPU_HPD_2: - idx = 1; - break; - case AMDGPU_HPD_3: - idx = 2; - break; - case AMDGPU_HPD_4: - idx = 3; - break; - case AMDGPU_HPD_5: - idx = 4; - break; - case AMDGPU_HPD_6: - idx = 5; - break; - default: + if (hpd >= adev->mode_info.num_hpd) return; - } - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); if (connected) tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); else tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); } /** @@ -422,33 +381,12 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) struct drm_device *dev = adev->ddev; struct drm_connector *connector; u32 tmp; - int idx; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - idx = 0; - break; - case AMDGPU_HPD_2: - idx = 1; - break; - case AMDGPU_HPD_3: - idx = 2; - break; - case AMDGPU_HPD_4: - idx = 3; - break; - case AMDGPU_HPD_5: - idx = 4; - break; - case AMDGPU_HPD_6: - idx = 5; - break; - default: + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) continue; - } if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { @@ -457,24 +395,24 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) * https://bugzilla.redhat.com/show_bug.cgi?id=726143 * also avoid interrupt storms during dpms. */ - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); continue; } - tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); - WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); - tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); - WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, @@ -495,37 +433,16 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) struct drm_device *dev = adev->ddev; struct drm_connector *connector; u32 tmp; - int idx; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - idx = 0; - break; - case AMDGPU_HPD_2: - idx = 1; - break; - case AMDGPU_HPD_3: - idx = 2; - break; - case AMDGPU_HPD_4: - idx = 3; - break; - case AMDGPU_HPD_5: - idx = 4; - break; - case AMDGPU_HPD_6: - idx = 5; - break; - default: + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) continue; - } - tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); - WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); @@ -2115,7 +2032,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, u32 tmp, viewport_w, viewport_h; int r; bool bypass_lut = false; - char *format_name; + struct drm_format_name_buf format_name; /* no fb bound */ if (!atomic && !crtc->primary->fb) { @@ -2227,9 +2144,8 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, bypass_lut = true; break; default: - format_name = drm_get_format_name(target_fb->pixel_format); - DRM_ERROR("Unsupported screen format %s\n", format_name); - kfree(format_name); + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->pixel_format, &format_name)); return -EINVAL; } @@ -2577,6 +2493,9 @@ static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, struct amdgpu_device *adev = crtc->dev->dev_private; int xorigin = 0, yorigin = 0; + amdgpu_crtc->cursor_x = x; + amdgpu_crtc->cursor_y = y; + /* avivo cursor are offset into the total surface */ x += crtc->x; y += crtc->y; @@ -2593,11 +2512,6 @@ static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); - WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, - ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); - - amdgpu_crtc->cursor_x = x; - amdgpu_crtc->cursor_y = y; return 0; } @@ -2623,6 +2537,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, int32_t hot_y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; struct drm_gem_object *obj; struct amdgpu_bo *aobj; int ret; @@ -2661,9 +2576,6 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, return ret; } - amdgpu_crtc->cursor_width = width; - amdgpu_crtc->cursor_height = height; - dce_v10_0_lock_cursor(crtc, true); if (hot_x != amdgpu_crtc->cursor_hot_x || @@ -2679,6 +2591,14 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, amdgpu_crtc->cursor_hot_y = hot_y; } + if (width != amdgpu_crtc->cursor_width || + height != amdgpu_crtc->cursor_height) { + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + (width - 1) << 16 | (height - 1)); + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; + } + dce_v10_0_show_cursor(crtc); dce_v10_0_lock_cursor(crtc, false); @@ -2700,6 +2620,7 @@ unpin: static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; if (amdgpu_crtc->cursor_bo) { dce_v10_0_lock_cursor(crtc, true); @@ -2707,6 +2628,10 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, amdgpu_crtc->cursor_y); + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + (amdgpu_crtc->cursor_width - 1) << 16 | + (amdgpu_crtc->cursor_height - 1)); + dce_v10_0_show_cursor(crtc); dce_v10_0_lock_cursor(crtc, false); @@ -3548,7 +3473,7 @@ static int dce_v10_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs dce_v10_0_ip_funcs = { +static const struct amd_ip_funcs dce_v10_0_ip_funcs = { .name = "dce_v10_0", .early_init = dce_v10_0_early_init, .late_init = NULL, @@ -3833,7 +3758,6 @@ static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { .bandwidth_update = &dce_v10_0_bandwidth_update, .vblank_get_counter = &dce_v10_0_vblank_get_counter, .vblank_wait = &dce_v10_0_vblank_wait, - .is_display_hung = &dce_v10_0_is_display_hung, .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, .hpd_sense = &dce_v10_0_hpd_sense, @@ -3879,3 +3803,21 @@ static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) adev->hpd_irq.num_types = AMDGPU_HPD_LAST; adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; } + +const struct amdgpu_ip_block_version dce_v10_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 10, + .minor = 0, + .rev = 0, + .funcs = &dce_v10_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version dce_v10_1_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 10, + .minor = 1, + .rev = 0, + .funcs = &dce_v10_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h index e3dc04d293e4..7a0747789f1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h @@ -24,7 +24,9 @@ #ifndef __DCE_V10_0_H__ #define __DCE_V10_0_H__ -extern const struct amd_ip_funcs dce_v10_0_ip_funcs; + +extern const struct amdgpu_ip_block_version dce_v10_0_ip_block; +extern const struct amdgpu_ip_block_version dce_v10_1_ip_block; void dce_v10_0_disable_dce(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 367739bd1927..b3d62b909f43 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -31,6 +31,7 @@ #include "atombios_encoders.h" #include "amdgpu_pll.h" #include "amdgpu_connectors.h" +#include "dce_v11_0.h" #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" @@ -346,33 +347,12 @@ static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd) { - int idx; bool connected = false; - switch (hpd) { - case AMDGPU_HPD_1: - idx = 0; - break; - case AMDGPU_HPD_2: - idx = 1; - break; - case AMDGPU_HPD_3: - idx = 2; - break; - case AMDGPU_HPD_4: - idx = 3; - break; - case AMDGPU_HPD_5: - idx = 4; - break; - case AMDGPU_HPD_6: - idx = 5; - break; - default: + if (hpd >= adev->mode_info.num_hpd) return connected; - } - if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & + if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) connected = true; @@ -392,37 +372,16 @@ static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, { u32 tmp; bool connected = dce_v11_0_hpd_sense(adev, hpd); - int idx; - switch (hpd) { - case AMDGPU_HPD_1: - idx = 0; - break; - case AMDGPU_HPD_2: - idx = 1; - break; - case AMDGPU_HPD_3: - idx = 2; - break; - case AMDGPU_HPD_4: - idx = 3; - break; - case AMDGPU_HPD_5: - idx = 4; - break; - case AMDGPU_HPD_6: - idx = 5; - break; - default: + if (hpd >= adev->mode_info.num_hpd) return; - } - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); if (connected) tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); else tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); } /** @@ -438,33 +397,12 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) struct drm_device *dev = adev->ddev; struct drm_connector *connector; u32 tmp; - int idx; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - idx = 0; - break; - case AMDGPU_HPD_2: - idx = 1; - break; - case AMDGPU_HPD_3: - idx = 2; - break; - case AMDGPU_HPD_4: - idx = 3; - break; - case AMDGPU_HPD_5: - idx = 4; - break; - case AMDGPU_HPD_6: - idx = 5; - break; - default: + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) continue; - } if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { @@ -473,24 +411,24 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) * https://bugzilla.redhat.com/show_bug.cgi?id=726143 * also avoid interrupt storms during dpms. */ - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); continue; } - tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); - WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); - tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); - WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); @@ -510,37 +448,16 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) struct drm_device *dev = adev->ddev; struct drm_connector *connector; u32 tmp; - int idx; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - idx = 0; - break; - case AMDGPU_HPD_2: - idx = 1; - break; - case AMDGPU_HPD_3: - idx = 2; - break; - case AMDGPU_HPD_4: - idx = 3; - break; - case AMDGPU_HPD_5: - idx = 4; - break; - case AMDGPU_HPD_6: - idx = 5; - break; - default: + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) continue; - } - tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); + tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); - WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); + WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } @@ -2096,7 +2013,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, u32 tmp, viewport_w, viewport_h; int r; bool bypass_lut = false; - char *format_name; + struct drm_format_name_buf format_name; /* no fb bound */ if (!atomic && !crtc->primary->fb) { @@ -2208,9 +2125,8 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, bypass_lut = true; break; default: - format_name = drm_get_format_name(target_fb->pixel_format); - DRM_ERROR("Unsupported screen format %s\n", format_name); - kfree(format_name); + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->pixel_format, &format_name)); return -EINVAL; } @@ -2593,6 +2509,9 @@ static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, struct amdgpu_device *adev = crtc->dev->dev_private; int xorigin = 0, yorigin = 0; + amdgpu_crtc->cursor_x = x; + amdgpu_crtc->cursor_y = y; + /* avivo cursor are offset into the total surface */ x += crtc->x; y += crtc->y; @@ -2609,11 +2528,6 @@ static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); - WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, - ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); - - amdgpu_crtc->cursor_x = x; - amdgpu_crtc->cursor_y = y; return 0; } @@ -2639,6 +2553,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, int32_t hot_y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; struct drm_gem_object *obj; struct amdgpu_bo *aobj; int ret; @@ -2677,9 +2592,6 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, return ret; } - amdgpu_crtc->cursor_width = width; - amdgpu_crtc->cursor_height = height; - dce_v11_0_lock_cursor(crtc, true); if (hot_x != amdgpu_crtc->cursor_hot_x || @@ -2695,6 +2607,14 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, amdgpu_crtc->cursor_hot_y = hot_y; } + if (width != amdgpu_crtc->cursor_width || + height != amdgpu_crtc->cursor_height) { + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + (width - 1) << 16 | (height - 1)); + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; + } + dce_v11_0_show_cursor(crtc); dce_v11_0_lock_cursor(crtc, false); @@ -2716,6 +2636,7 @@ unpin: static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; if (amdgpu_crtc->cursor_bo) { dce_v11_0_lock_cursor(crtc, true); @@ -2723,6 +2644,10 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, amdgpu_crtc->cursor_y); + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + (amdgpu_crtc->cursor_width - 1) << 16 | + (amdgpu_crtc->cursor_height - 1)); + dce_v11_0_show_cursor(crtc); dce_v11_0_lock_cursor(crtc, false); @@ -3605,7 +3530,7 @@ static int dce_v11_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs dce_v11_0_ip_funcs = { +static const struct amd_ip_funcs dce_v11_0_ip_funcs = { .name = "dce_v11_0", .early_init = dce_v11_0_early_init, .late_init = NULL, @@ -3889,7 +3814,6 @@ static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { .bandwidth_update = &dce_v11_0_bandwidth_update, .vblank_get_counter = &dce_v11_0_vblank_get_counter, .vblank_wait = &dce_v11_0_vblank_wait, - .is_display_hung = &dce_v11_0_is_display_hung, .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, .hpd_sense = &dce_v11_0_hpd_sense, @@ -3935,3 +3859,21 @@ static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) adev->hpd_irq.num_types = AMDGPU_HPD_LAST; adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; } + +const struct amdgpu_ip_block_version dce_v11_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 11, + .minor = 0, + .rev = 0, + .funcs = &dce_v11_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version dce_v11_2_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 11, + .minor = 2, + .rev = 0, + .funcs = &dce_v11_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h index 1f58a65ba2ef..0d878ca3acba 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h @@ -24,7 +24,8 @@ #ifndef __DCE_V11_0_H__ #define __DCE_V11_0_H__ -extern const struct amd_ip_funcs dce_v11_0_ip_funcs; +extern const struct amdgpu_ip_block_version dce_v11_0_ip_block; +extern const struct amdgpu_ip_block_version dce_v11_2_ip_block; void dce_v11_0_disable_dce(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 15f9fc0514b2..e564442b6393 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -30,8 +30,19 @@ #include "atombios_encoders.h" #include "amdgpu_pll.h" #include "amdgpu_connectors.h" -#include "si/si_reg.h" -#include "si/sid.h" + +#include "bif/bif_3_0_d.h" +#include "bif/bif_3_0_sh_mask.h" +#include "oss/oss_1_0_d.h" +#include "oss/oss_1_0_sh_mask.h" +#include "gca/gfx_6_0_d.h" +#include "gca/gfx_6_0_sh_mask.h" +#include "gmc/gmc_6_0_d.h" +#include "gmc/gmc_6_0_sh_mask.h" +#include "dce/dce_6_0_d.h" +#include "dce/dce_6_0_sh_mask.h" +#include "gca/gfx_7_2_enum.h" +#include "si_enums.h" static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); @@ -46,6 +57,16 @@ static const u32 crtc_offsets[6] = SI_CRTC5_REGISTER_OFFSET }; +static const u32 hpd_offsets[] = +{ + mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, + mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, +}; + static const uint32_t dig_offsets[] = { SI_CRTC0_REGISTER_OFFSET, SI_CRTC1_REGISTER_OFFSET, @@ -63,46 +84,37 @@ static const struct { uint32_t hpd; } interrupt_status_offsets[6] = { { - .reg = DISP_INTERRUPT_STATUS, + .reg = mmDISP_INTERRUPT_STATUS, .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE2, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE3, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE4, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK }, { - .reg = DISP_INTERRUPT_STATUS_CONTINUE5, + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK } }; -static const uint32_t hpd_int_control_offsets[6] = { - DC_HPD1_INT_CONTROL, - DC_HPD2_INT_CONTROL, - DC_HPD3_INT_CONTROL, - DC_HPD4_INT_CONTROL, - DC_HPD5_INT_CONTROL, - DC_HPD6_INT_CONTROL, -}; - static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, u32 block_offset, u32 reg) { @@ -118,7 +130,7 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc) { - if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) + if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK) return true; else return false; @@ -128,8 +140,8 @@ static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc) { u32 pos1, pos2; - pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); - pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); + pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); if (pos1 != pos2) return true; @@ -151,7 +163,7 @@ static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc) if (crtc >= adev->mode_info.num_crtc) return; - if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) + if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) return; /* depending on when we hit vblank, we may be close to active; if so, @@ -179,7 +191,7 @@ static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) if (crtc >= adev->mode_info.num_crtc) return 0; else - return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); } static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) @@ -219,16 +231,16 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; /* flip at hsync for async, default is vsync */ - WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? - EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? + GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); /* update the scanout addresses */ - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, (u32)crtc_base); /* post the write */ - RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); + RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); } static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, @@ -236,8 +248,8 @@ static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, { if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) return -EINVAL; - *vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + crtc_offsets[crtc]); - *position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); + *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); + *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); return 0; @@ -257,34 +269,11 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, { bool connected = false; - switch (hpd) { - case AMDGPU_HPD_1: - if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case AMDGPU_HPD_2: - if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case AMDGPU_HPD_3: - if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case AMDGPU_HPD_4: - if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case AMDGPU_HPD_5: - if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case AMDGPU_HPD_6: - if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - default: - break; - } + if (hpd >= adev->mode_info.num_hpd) + return connected; + + if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) + connected = true; return connected; } @@ -303,58 +292,15 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, u32 tmp; bool connected = dce_v6_0_hpd_sense(adev, hpd); - switch (hpd) { - case AMDGPU_HPD_1: - tmp = RREG32(DC_HPD1_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD1_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_2: - tmp = RREG32(DC_HPD2_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD2_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_3: - tmp = RREG32(DC_HPD3_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD3_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_4: - tmp = RREG32(DC_HPD4_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD4_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_5: - tmp = RREG32(DC_HPD5_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD5_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_6: - tmp = RREG32(DC_HPD6_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD6_INT_CONTROL, tmp); - break; - default: - break; - } + if (hpd >= adev->mode_info.num_hpd) + return; + + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); + if (connected) + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; + else + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); } /** @@ -369,34 +315,17 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev->ddev; struct drm_connector *connector; - u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | - DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; + u32 tmp; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - WREG32(DC_HPD1_CONTROL, tmp); - break; - case AMDGPU_HPD_2: - WREG32(DC_HPD2_CONTROL, tmp); - break; - case AMDGPU_HPD_3: - WREG32(DC_HPD3_CONTROL, tmp); - break; - case AMDGPU_HPD_4: - WREG32(DC_HPD4_CONTROL, tmp); - break; - case AMDGPU_HPD_5: - WREG32(DC_HPD5_CONTROL, tmp); - break; - case AMDGPU_HPD_6: - WREG32(DC_HPD6_CONTROL, tmp); - break; - default: - break; - } + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) + continue; + + tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { @@ -405,34 +334,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) * https://bugzilla.redhat.com/show_bug.cgi?id=726143 * also avoid interrupt storms during dpms. */ - u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; - - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL; - break; - case AMDGPU_HPD_2: - dc_hpd_int_cntl_reg = DC_HPD2_INT_CONTROL; - break; - case AMDGPU_HPD_3: - dc_hpd_int_cntl_reg = DC_HPD3_INT_CONTROL; - break; - case AMDGPU_HPD_4: - dc_hpd_int_cntl_reg = DC_HPD4_INT_CONTROL; - break; - case AMDGPU_HPD_5: - dc_hpd_int_cntl_reg = DC_HPD5_INT_CONTROL; - break; - case AMDGPU_HPD_6: - dc_hpd_int_cntl_reg = DC_HPD6_INT_CONTROL; - break; - default: - continue; - } - - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); - dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); continue; } @@ -454,46 +358,25 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev->ddev; struct drm_connector *connector; + u32 tmp; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - WREG32(DC_HPD1_CONTROL, 0); - break; - case AMDGPU_HPD_2: - WREG32(DC_HPD2_CONTROL, 0); - break; - case AMDGPU_HPD_3: - WREG32(DC_HPD3_CONTROL, 0); - break; - case AMDGPU_HPD_4: - WREG32(DC_HPD4_CONTROL, 0); - break; - case AMDGPU_HPD_5: - WREG32(DC_HPD5_CONTROL, 0); - break; - case AMDGPU_HPD_6: - WREG32(DC_HPD6_CONTROL, 0); - break; - default: - break; - } + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) + continue; + + tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); + amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } } static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) { - return SI_DC_GPIO_HPD_A; -} - -static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev) -{ - DRM_INFO("xxxx: dce_v6_0_is_display_hung ----no imp!!!!!\n"); - - return true; + return mmDC_GPIO_HPD_A; } static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc) @@ -501,7 +384,7 @@ static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc) if (crtc >= adev->mode_info.num_crtc) return 0; else - return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); } static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, @@ -510,25 +393,25 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, u32 crtc_enabled, tmp, frame_count; int i, j; - save->vga_render_control = RREG32(VGA_RENDER_CONTROL); - save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); + save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); + save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); /* disable VGA render */ - WREG32(VGA_RENDER_CONTROL, 0); + WREG32(mmVGA_RENDER_CONTROL, 0); /* blank the display controllers */ for (i = 0; i < adev->mode_info.num_crtc; i++) { - crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; + crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK; if (crtc_enabled) { save->crtc_enabled[i] = true; - tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); - if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { + if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) { dce_v6_0_vblank_wait(adev, i); - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); - tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; - WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK; + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); } /* wait for the next frame */ frame_count = evergreen_get_vblank_counter(adev, i); @@ -539,11 +422,11 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, } /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); - tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); - tmp &= ~EVERGREEN_CRTC_MASTER_EN; - WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); - WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); save->crtc_enabled[i] = false; /* ***** */ } else { @@ -560,41 +443,40 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev, /* update crtc base addresses */ for (i = 0; i < adev->mode_info.num_crtc; i++) { - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], upper_32_bits(adev->mc.vram_start)); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], upper_32_bits(adev->mc.vram_start)); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], (u32)adev->mc.vram_start); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], (u32)adev->mc.vram_start); } - WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); - WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start); + WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); + WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start); /* unlock regs and wait for update */ for (i = 0; i < adev->mode_info.num_crtc; i++) { if (save->crtc_enabled[i]) { - tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); - if ((tmp & 0x7) != 3) { + tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); + if ((tmp & 0x7) != 0) { tmp &= ~0x7; - tmp |= 0x3; - WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); + WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); } - tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); - if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) { - tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; - WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) { + tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK; + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); } - tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); + tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); if (tmp & 1) { tmp &= ~1; - WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); } for (j = 0; j < adev->usec_timeout; j++) { - tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); - if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0) break; udelay(1); } @@ -602,19 +484,62 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev, } /* Unlock vga access */ - WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); + WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); mdelay(1); - WREG32(VGA_RENDER_CONTROL, save->vga_render_control); + WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); } static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, bool render) { - if (!render) - WREG32(R_000300_VGA_RENDER_CONTROL, - RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); + if (!render) + WREG32(mmVGA_RENDER_CONTROL, + RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); + +} + +static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) +{ + int num_crtc = 0; + + switch (adev->asic_type) { + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + num_crtc = 6; + break; + case CHIP_OLAND: + num_crtc = 2; + break; + default: + num_crtc = 0; + } + return num_crtc; +} + +void dce_v6_0_disable_dce(struct amdgpu_device *adev) +{ + /*Disable VGA render and enabled crtc, if has DCE engine*/ + if (amdgpu_atombios_has_dce_engine_info(adev)) { + u32 tmp; + int crtc_enabled, i; + + dce_v6_0_set_vga_render_state(adev, false); + /*Disable crtc*/ + for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { + crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & + CRTC_CONTROL__CRTC_MASTER_EN_MASK; + if (crtc_enabled) { + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + } + } + } } static void dce_v6_0_program_fmt(struct drm_encoder *encoder) @@ -647,19 +572,23 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder) case 6: if (dither == AMDGPU_FMT_DITHER_ENABLE) /* XXX sort out optimal dither settings */ - tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | - FMT_SPATIAL_DITHER_EN); + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); else - tmp |= FMT_TRUNCATE_EN; + tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; break; case 8: if (dither == AMDGPU_FMT_DITHER_ENABLE) /* XXX sort out optimal dither settings */ - tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | - FMT_RGB_RANDOM_ENABLE | - FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); else - tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); break; case 10: default: @@ -667,7 +596,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder) break; } - WREG32(FMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); } /** @@ -681,7 +610,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder) */ static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) { - u32 tmp = RREG32(MC_SHARED_CHMAP); + u32 tmp = RREG32(mmMC_SHARED_CHMAP); switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { case 0: @@ -1178,28 +1107,28 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, } /* select wm A */ - arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); + arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); tmp = arb_control3; tmp &= ~LATENCY_WATERMARK_MASK(3); tmp |= LATENCY_WATERMARK_MASK(1); - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); - WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset, - (LATENCY_LOW_WATERMARK(latency_watermark_a) | - LATENCY_HIGH_WATERMARK(line_time))); + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, + ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | + (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); /* select wm B */ - tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); + tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); tmp &= ~LATENCY_WATERMARK_MASK(3); tmp |= LATENCY_WATERMARK_MASK(2); - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); - WREG32(DPG_PIPE_LATENCY_CONTROL + amdgpu_crtc->crtc_offset, - (LATENCY_LOW_WATERMARK(latency_watermark_b) | - LATENCY_HIGH_WATERMARK(line_time))); + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, + ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | + (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); /* restore original selection */ - WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); + WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); /* write the priority marks */ - WREG32(PRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); - WREG32(PRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); + WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); + WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); /* save values for DPM */ amdgpu_crtc->line_time = line_time; @@ -1217,7 +1146,7 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, /* * Line Buffer Setup * There are 3 line buffers, each one shared by 2 display controllers. - * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between + * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between * the display controllers. The paritioning is done via one of four * preset allocations specified in bits 21:20: * 0 - half lb @@ -1240,14 +1169,14 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, buffer_alloc = 0; } - WREG32(DC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, + WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, DC_LB_MEMORY_CONFIG(tmp)); - WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, - DMIF_BUFFERS_ALLOCATED(buffer_alloc)); + WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, + (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & - DMIF_BUFFERS_ALLOCATED_COMPLETED) + if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & + PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) break; udelay(1); } @@ -1489,12 +1418,12 @@ static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) static const u32 vga_control_regs[6] = { - AVIVO_D1VGA_CONTROL, - AVIVO_D2VGA_CONTROL, - EVERGREEN_D3VGA_CONTROL, - EVERGREEN_D4VGA_CONTROL, - EVERGREEN_D5VGA_CONTROL, - EVERGREEN_D6VGA_CONTROL, + mmD1VGA_CONTROL, + mmD2VGA_CONTROL, + mmD3VGA_CONTROL, + mmD4VGA_CONTROL, + mmD5VGA_CONTROL, + mmD6VGA_CONTROL, }; static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) @@ -1514,7 +1443,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = dev->dev_private; - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); } static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, @@ -1530,10 +1459,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, struct amdgpu_bo *abo; uint64_t fb_location, tiling_flags; uint32_t fb_format, fb_pitch_pixels, pipe_config; - u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); + u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); u32 viewport_w, viewport_h; int r; bool bypass_lut = false; + struct drm_format_name_buf format_name; /* no fb bound */ if (!atomic && !crtc->primary->fb) { @@ -1573,71 +1503,71 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, switch (target_fb->pixel_format) { case DRM_FORMAT_C8: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | + GRPH_FORMAT(GRPH_FORMAT_INDEXED)); break; case DRM_FORMAT_XRGB4444: case DRM_FORMAT_ARGB4444: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); #endif break; case DRM_FORMAT_XRGB1555: case DRM_FORMAT_ARGB1555: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); #endif break; case DRM_FORMAT_BGRX5551: case DRM_FORMAT_BGRA5551: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | + GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); #endif break; case DRM_FORMAT_RGB565: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB565)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); #endif break; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); #endif break; case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); #endif /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: - fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | - EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | + GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); #ifdef __BIG_ENDIAN - fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); #endif /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; default: DRM_ERROR("Unsupported screen format %s\n", - drm_get_format_name(target_fb->pixel_format)); + drm_get_format_name(target_fb->pixel_format, &format_name)); return -EINVAL; } @@ -1650,75 +1580,75 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); - fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); - fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); - fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); - fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); - fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); - fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); + fb_format |= GRPH_NUM_BANKS(num_banks); + fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); + fb_format |= GRPH_TILE_SPLIT(tile_split); + fb_format |= GRPH_BANK_WIDTH(bankw); + fb_format |= GRPH_BANK_HEIGHT(bankh); + fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { - fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); + fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); } pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config); + fb_format |= GRPH_PIPE_CONFIG(pipe_config); dce_v6_0_vga_enable(crtc, false); /* Make sure surface address is updated at vertical blank rather than * horizontal blank */ - WREG32(EVERGREEN_GRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(fb_location)); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(fb_location)); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); - WREG32(EVERGREEN_GRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); - WREG32(EVERGREEN_GRPH_SWAP_CONTROL + amdgpu_crtc->crtc_offset, fb_swap); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); + WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); /* * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to * retain the full precision throughout the pipeline. */ - WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, - (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), - ~EVERGREEN_LUT_10BIT_BYPASS_EN); + WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, + (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), + ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); if (bypass_lut) DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); - WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_X_START + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_Y_START + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_GRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); - WREG32(EVERGREEN_GRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); + WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); + WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); - WREG32(EVERGREEN_GRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v6_0_grph_enable(crtc, true); - WREG32(EVERGREEN_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, + WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, target_fb->height); x &= ~3; y &= ~1; - WREG32(EVERGREEN_VIEWPORT_START + amdgpu_crtc->crtc_offset, + WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, (x << 16) | y); viewport_w = crtc->mode.hdisplay; viewport_h = (crtc->mode.vdisplay + 1) & ~1; - WREG32(EVERGREEN_VIEWPORT_SIZE + amdgpu_crtc->crtc_offset, + WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, (viewport_w << 16) | viewport_h); /* set pageflip to happen anywhere in vblank interval */ - WREG32(EVERGREEN_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { amdgpu_fb = to_amdgpu_framebuffer(fb); @@ -1745,10 +1675,10 @@ static void dce_v6_0_set_interleave(struct drm_crtc *crtc, struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); if (mode->flags & DRM_MODE_FLAG_INTERLACE) - WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, - EVERGREEN_INTERLEAVE_EN); + WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, + INTERLEAVE_EN); else - WREG32(EVERGREEN_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); } static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) @@ -1761,54 +1691,52 @@ static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); - WREG32(NI_INPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, - (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | - NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); - WREG32(NI_PRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, - NI_GRPH_PRESCALE_BYPASS); - WREG32(NI_PRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, - NI_OVL_PRESCALE_BYPASS); - WREG32(NI_INPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, - (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | - NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); - + WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | + (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); + WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, + PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); + WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, + PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); + WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | + (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); + WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); - WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); - WREG32(EVERGREEN_DC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); - WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); - - WREG32(EVERGREEN_DC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); for (i = 0; i < 256; i++) { - WREG32(EVERGREEN_DC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, + WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, (amdgpu_crtc->lut_r[i] << 20) | (amdgpu_crtc->lut_g[i] << 10) | (amdgpu_crtc->lut_b[i] << 0)); } - WREG32(NI_DEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, - (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | - NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | - NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | - NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); - WREG32(NI_GAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, - (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | - NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); - WREG32(NI_REGAMMA_CONTROL + amdgpu_crtc->crtc_offset, - (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | - NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); - WREG32(NI_OUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, - (NI_OUTPUT_CSC_GRPH_MODE(0) | - NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); + WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | + (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | + ICON_DEGAMMA_MODE(0) | + (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); + WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | + (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); + WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | + (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); + WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, + ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | + (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); /* XXX match this to the depth of the crtc fmt block, move to modeset? */ WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); @@ -1887,12 +1815,12 @@ static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); uint32_t cur_lock; - cur_lock = RREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset); + cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); if (lock) - cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; + cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; else - cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; - WREG32(EVERGREEN_CUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); + cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; + WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); } static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) @@ -1900,9 +1828,9 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = crtc->dev->dev_private; - WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset, - EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | - EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, + (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | + (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); } @@ -1912,15 +1840,15 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = crtc->dev->dev_private; - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(amdgpu_crtc->cursor_addr)); - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, lower_32_bits(amdgpu_crtc->cursor_addr)); - WREG32_IDX(EVERGREEN_CUR_CONTROL + amdgpu_crtc->crtc_offset, - EVERGREEN_CURSOR_EN | - EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | - EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, + CUR_CONTROL__CURSOR_EN_MASK | + (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | + (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); } @@ -1931,7 +1859,8 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, struct amdgpu_device *adev = crtc->dev->dev_private; int xorigin = 0, yorigin = 0; - int w = amdgpu_crtc->cursor_width; + amdgpu_crtc->cursor_x = x; + amdgpu_crtc->cursor_y = y; /* avivo cursor are offset into the total surface */ x += crtc->x; @@ -1947,13 +1876,9 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, y = 0; } - WREG32(EVERGREEN_CUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); - WREG32(EVERGREEN_CUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); - WREG32(EVERGREEN_CUR_SIZE + amdgpu_crtc->crtc_offset, - ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); + WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); + WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); - amdgpu_crtc->cursor_x = x; - amdgpu_crtc->cursor_y = y; return 0; } @@ -1978,6 +1903,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, int32_t hot_y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; struct drm_gem_object *obj; struct amdgpu_bo *aobj; int ret; @@ -2016,12 +1942,11 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, return ret; } - amdgpu_crtc->cursor_width = width; - amdgpu_crtc->cursor_height = height; - dce_v6_0_lock_cursor(crtc, true); - if (hot_x != amdgpu_crtc->cursor_hot_x || + if (width != amdgpu_crtc->cursor_width || + height != amdgpu_crtc->cursor_height || + hot_x != amdgpu_crtc->cursor_hot_x || hot_y != amdgpu_crtc->cursor_hot_y) { int x, y; @@ -2030,10 +1955,20 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, dce_v6_0_cursor_move_locked(crtc, x, y); + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; amdgpu_crtc->cursor_hot_x = hot_x; amdgpu_crtc->cursor_hot_y = hot_y; } + if (width != amdgpu_crtc->cursor_width || + height != amdgpu_crtc->cursor_height) { + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + (width - 1) << 16 | (height - 1)); + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; + } + dce_v6_0_show_cursor(crtc); dce_v6_0_lock_cursor(crtc, false); @@ -2055,6 +1990,7 @@ unpin: static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; if (amdgpu_crtc->cursor_bo) { dce_v6_0_lock_cursor(crtc, true); @@ -2062,6 +1998,10 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, amdgpu_crtc->cursor_y); + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + (amdgpu_crtc->cursor_width - 1) << 16 | + (amdgpu_crtc->cursor_height - 1)); + dce_v6_0_show_cursor(crtc); dce_v6_0_lock_cursor(crtc, false); } @@ -2117,13 +2057,13 @@ static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); amdgpu_irq_update(adev, &adev->crtc_irq, type); amdgpu_irq_update(adev, &adev->pageflip_irq, type); - drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); + drm_crtc_vblank_on(crtc); dce_v6_0_crtc_load_lut(crtc); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); + drm_crtc_vblank_off(crtc); if (amdgpu_crtc->enabled) amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); @@ -2338,21 +2278,20 @@ static int dce_v6_0_early_init(void *handle) dce_v6_0_set_display_funcs(adev); dce_v6_0_set_irq_funcs(adev); + adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); + switch (adev->asic_type) { case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: - adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; case CHIP_OLAND: - adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 2; adev->mode_info.num_dig = 2; break; default: - /* FIXME: not supported yet */ return -EINVAL; } @@ -2556,14 +2495,14 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - interrupt_mask = RREG32(INT_MASK + reg_block); + interrupt_mask = RREG32(mmINT_MASK + reg_block); interrupt_mask &= ~VBLANK_INT_MASK; - WREG32(INT_MASK + reg_block, interrupt_mask); + WREG32(mmINT_MASK + reg_block, interrupt_mask); break; case AMDGPU_IRQ_STATE_ENABLE: - interrupt_mask = RREG32(INT_MASK + reg_block); + interrupt_mask = RREG32(mmINT_MASK + reg_block); interrupt_mask |= VBLANK_INT_MASK; - WREG32(INT_MASK + reg_block, interrupt_mask); + WREG32(mmINT_MASK + reg_block, interrupt_mask); break; default: break; @@ -2582,42 +2521,23 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { - u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; + u32 dc_hpd_int_cntl; - switch (type) { - case AMDGPU_HPD_1: - dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL; - break; - case AMDGPU_HPD_2: - dc_hpd_int_cntl_reg = DC_HPD2_INT_CONTROL; - break; - case AMDGPU_HPD_3: - dc_hpd_int_cntl_reg = DC_HPD3_INT_CONTROL; - break; - case AMDGPU_HPD_4: - dc_hpd_int_cntl_reg = DC_HPD4_INT_CONTROL; - break; - case AMDGPU_HPD_5: - dc_hpd_int_cntl_reg = DC_HPD5_INT_CONTROL; - break; - case AMDGPU_HPD_6: - dc_hpd_int_cntl_reg = DC_HPD6_INT_CONTROL; - break; - default: + if (type >= adev->mode_info.num_hpd) { DRM_DEBUG("invalid hdp %d\n", type); return 0; } switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); - dc_hpd_int_cntl &= ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); + dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); - dc_hpd_int_cntl |= (DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); + dc_hpd_int_cntl |= DC_HPDx_INT_EN; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); break; default: break; @@ -2685,7 +2605,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, switch (entry->src_data) { case 0: /* vblank */ if (disp_int & interrupt_status_offsets[crtc].vblank) - WREG32(VBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); + WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); else DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); @@ -2696,7 +2616,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, break; case 1: /* vline */ if (disp_int & interrupt_status_offsets[crtc].vline) - WREG32(VLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); + WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); else DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); @@ -2722,12 +2642,12 @@ static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, return -EINVAL; } - reg = RREG32(GRPH_INT_CONTROL + crtc_offsets[type]); + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); if (state == AMDGPU_IRQ_STATE_DISABLE) - WREG32(GRPH_INT_CONTROL + crtc_offsets[type], + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); else - WREG32(GRPH_INT_CONTROL + crtc_offsets[type], + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); return 0; @@ -2750,9 +2670,9 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, return -EINVAL; } - if (RREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id]) & + if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) - WREG32(GRPH_INT_STATUS + crtc_offsets[crtc_id], + WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); /* IRQ could occur when in initial stage */ @@ -2790,7 +2710,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t disp_int, mask, int_control, tmp; + uint32_t disp_int, mask, tmp; unsigned hpd; if (entry->src_data >= adev->mode_info.num_hpd) { @@ -2801,12 +2721,11 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, hpd = entry->src_data; disp_int = RREG32(interrupt_status_offsets[hpd].reg); mask = interrupt_status_offsets[hpd].hpd; - int_control = hpd_int_control_offsets[hpd]; if (disp_int & mask) { - tmp = RREG32(int_control); + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; - WREG32(int_control, tmp); + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); schedule_work(&adev->hotplug_work); DRM_INFO("IH: HPD%d\n", hpd + 1); } @@ -2827,7 +2746,7 @@ static int dce_v6_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs dce_v6_0_ip_funcs = { +static const struct amd_ip_funcs dce_v6_0_ip_funcs = { .name = "dce_v6_0", .early_init = dce_v6_0_early_init, .late_init = NULL, @@ -3122,7 +3041,6 @@ static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { .bandwidth_update = &dce_v6_0_bandwidth_update, .vblank_get_counter = &dce_v6_0_vblank_get_counter, .vblank_wait = &dce_v6_0_vblank_wait, - .is_display_hung = &dce_v6_0_is_display_hung, .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, .hpd_sense = &dce_v6_0_hpd_sense, @@ -3168,3 +3086,21 @@ static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) adev->hpd_irq.num_types = AMDGPU_HPD_LAST; adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; } + +const struct amdgpu_ip_block_version dce_v6_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 6, + .minor = 0, + .rev = 0, + .funcs = &dce_v6_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version dce_v6_4_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 6, + .minor = 4, + .rev = 0, + .funcs = &dce_v6_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h index 6a5528105bb6..7b546b596de1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.h @@ -24,6 +24,9 @@ #ifndef __DCE_V6_0_H__ #define __DCE_V6_0_H__ -extern const struct amd_ip_funcs dce_v6_0_ip_funcs; +extern const struct amdgpu_ip_block_version dce_v6_0_ip_block; +extern const struct amdgpu_ip_block_version dce_v6_4_ip_block; + +void dce_v6_0_disable_dce(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 8c4d808db0f1..6ce7fb42dbef 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -31,6 +31,7 @@ #include "atombios_encoders.h" #include "amdgpu_pll.h" #include "amdgpu_connectors.h" +#include "dce_v8_0.h" #include "dce/dce_8_0_d.h" #include "dce/dce_8_0_sh_mask.h" @@ -56,6 +57,16 @@ static const u32 crtc_offsets[6] = CRTC5_REGISTER_OFFSET }; +static const u32 hpd_offsets[] = +{ + HPD0_REGISTER_OFFSET, + HPD1_REGISTER_OFFSET, + HPD2_REGISTER_OFFSET, + HPD3_REGISTER_OFFSET, + HPD4_REGISTER_OFFSET, + HPD5_REGISTER_OFFSET +}; + static const uint32_t dig_offsets[] = { CRTC0_REGISTER_OFFSET, CRTC1_REGISTER_OFFSET, @@ -104,15 +115,6 @@ static const struct { .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK } }; -static const uint32_t hpd_int_control_offsets[6] = { - mmDC_HPD1_INT_CONTROL, - mmDC_HPD2_INT_CONTROL, - mmDC_HPD3_INT_CONTROL, - mmDC_HPD4_INT_CONTROL, - mmDC_HPD5_INT_CONTROL, - mmDC_HPD6_INT_CONTROL, -}; - static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, u32 block_offset, u32 reg) { @@ -278,34 +280,12 @@ static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev, { bool connected = false; - switch (hpd) { - case AMDGPU_HPD_1: - if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) - connected = true; - break; - case AMDGPU_HPD_2: - if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK) - connected = true; - break; - case AMDGPU_HPD_3: - if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK) - connected = true; - break; - case AMDGPU_HPD_4: - if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK) - connected = true; - break; - case AMDGPU_HPD_5: - if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK) - connected = true; - break; - case AMDGPU_HPD_6: - if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK) - connected = true; - break; - default: - break; - } + if (hpd >= adev->mode_info.num_hpd) + return connected; + + if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & + DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) + connected = true; return connected; } @@ -324,58 +304,15 @@ static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev, u32 tmp; bool connected = dce_v8_0_hpd_sense(adev, hpd); - switch (hpd) { - case AMDGPU_HPD_1: - tmp = RREG32(mmDC_HPD1_INT_CONTROL); - if (connected) - tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; - else - tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; - WREG32(mmDC_HPD1_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_2: - tmp = RREG32(mmDC_HPD2_INT_CONTROL); - if (connected) - tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; - else - tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; - WREG32(mmDC_HPD2_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_3: - tmp = RREG32(mmDC_HPD3_INT_CONTROL); - if (connected) - tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; - else - tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; - WREG32(mmDC_HPD3_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_4: - tmp = RREG32(mmDC_HPD4_INT_CONTROL); - if (connected) - tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; - else - tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; - WREG32(mmDC_HPD4_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_5: - tmp = RREG32(mmDC_HPD5_INT_CONTROL); - if (connected) - tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; - else - tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; - WREG32(mmDC_HPD5_INT_CONTROL, tmp); - break; - case AMDGPU_HPD_6: - tmp = RREG32(mmDC_HPD6_INT_CONTROL); - if (connected) - tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; - else - tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; - WREG32(mmDC_HPD6_INT_CONTROL, tmp); - break; - default: - break; - } + if (hpd >= adev->mode_info.num_hpd) + return; + + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); + if (connected) + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; + else + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); } /** @@ -390,35 +327,17 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev->ddev; struct drm_connector *connector; - u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) | - (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) | - DC_HPD1_CONTROL__DC_HPD1_EN_MASK; + u32 tmp; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - WREG32(mmDC_HPD1_CONTROL, tmp); - break; - case AMDGPU_HPD_2: - WREG32(mmDC_HPD2_CONTROL, tmp); - break; - case AMDGPU_HPD_3: - WREG32(mmDC_HPD3_CONTROL, tmp); - break; - case AMDGPU_HPD_4: - WREG32(mmDC_HPD4_CONTROL, tmp); - break; - case AMDGPU_HPD_5: - WREG32(mmDC_HPD5_CONTROL, tmp); - break; - case AMDGPU_HPD_6: - WREG32(mmDC_HPD6_CONTROL, tmp); - break; - default: - break; - } + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) + continue; + + tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { @@ -427,34 +346,9 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) * https://bugzilla.redhat.com/show_bug.cgi?id=726143 * also avoid interrupt storms during dpms. */ - u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; - - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; - break; - case AMDGPU_HPD_2: - dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; - break; - case AMDGPU_HPD_3: - dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; - break; - case AMDGPU_HPD_4: - dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; - break; - case AMDGPU_HPD_5: - dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; - break; - case AMDGPU_HPD_6: - dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; - break; - default: - continue; - } - - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); - dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); continue; } @@ -475,32 +369,18 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev->ddev; struct drm_connector *connector; + u32 tmp; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - switch (amdgpu_connector->hpd.hpd) { - case AMDGPU_HPD_1: - WREG32(mmDC_HPD1_CONTROL, 0); - break; - case AMDGPU_HPD_2: - WREG32(mmDC_HPD2_CONTROL, 0); - break; - case AMDGPU_HPD_3: - WREG32(mmDC_HPD3_CONTROL, 0); - break; - case AMDGPU_HPD_4: - WREG32(mmDC_HPD4_CONTROL, 0); - break; - case AMDGPU_HPD_5: - WREG32(mmDC_HPD5_CONTROL, 0); - break; - case AMDGPU_HPD_6: - WREG32(mmDC_HPD6_CONTROL, 0); - break; - default: - break; - } + if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) + continue; + + tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); + tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; + WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); + amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } } @@ -2030,7 +1910,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, u32 viewport_w, viewport_h; int r; bool bypass_lut = false; - char *format_name; + struct drm_format_name_buf format_name; /* no fb bound */ if (!atomic && !crtc->primary->fb) { @@ -2135,9 +2015,8 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, bypass_lut = true; break; default: - format_name = drm_get_format_name(target_fb->pixel_format); - DRM_ERROR("Unsupported screen format %s\n", format_name); - kfree(format_name); + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->pixel_format, &format_name)); return -EINVAL; } @@ -2465,6 +2344,9 @@ static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, struct amdgpu_device *adev = crtc->dev->dev_private; int xorigin = 0, yorigin = 0; + amdgpu_crtc->cursor_x = x; + amdgpu_crtc->cursor_y = y; + /* avivo cursor are offset into the total surface */ x += crtc->x; y += crtc->y; @@ -2481,11 +2363,6 @@ static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); - WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, - ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); - - amdgpu_crtc->cursor_x = x; - amdgpu_crtc->cursor_y = y; return 0; } @@ -2511,6 +2388,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, int32_t hot_y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; struct drm_gem_object *obj; struct amdgpu_bo *aobj; int ret; @@ -2549,9 +2427,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, return ret; } - amdgpu_crtc->cursor_width = width; - amdgpu_crtc->cursor_height = height; - dce_v8_0_lock_cursor(crtc, true); if (hot_x != amdgpu_crtc->cursor_hot_x || @@ -2563,10 +2438,20 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, dce_v8_0_cursor_move_locked(crtc, x, y); + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; amdgpu_crtc->cursor_hot_x = hot_x; amdgpu_crtc->cursor_hot_y = hot_y; } + if (width != amdgpu_crtc->cursor_width || + height != amdgpu_crtc->cursor_height) { + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + (width - 1) << 16 | (height - 1)); + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; + } + dce_v8_0_show_cursor(crtc); dce_v8_0_lock_cursor(crtc, false); @@ -2588,6 +2473,7 @@ unpin: static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; if (amdgpu_crtc->cursor_bo) { dce_v8_0_lock_cursor(crtc, true); @@ -2595,6 +2481,10 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, amdgpu_crtc->cursor_y); + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + (amdgpu_crtc->cursor_width - 1) << 16 | + (amdgpu_crtc->cursor_height - 1)); + dce_v8_0_show_cursor(crtc); dce_v8_0_lock_cursor(crtc, false); @@ -3198,42 +3088,23 @@ static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { - u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; + u32 dc_hpd_int_cntl; - switch (type) { - case AMDGPU_HPD_1: - dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; - break; - case AMDGPU_HPD_2: - dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; - break; - case AMDGPU_HPD_3: - dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; - break; - case AMDGPU_HPD_4: - dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; - break; - case AMDGPU_HPD_5: - dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; - break; - case AMDGPU_HPD_6: - dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; - break; - default: + if (type >= adev->mode_info.num_hpd) { DRM_DEBUG("invalid hdp %d\n", type); return 0; } switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); + dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; - WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); break; default: break; @@ -3406,7 +3277,7 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t disp_int, mask, int_control, tmp; + uint32_t disp_int, mask, tmp; unsigned hpd; if (entry->src_data >= adev->mode_info.num_hpd) { @@ -3417,12 +3288,11 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, hpd = entry->src_data; disp_int = RREG32(interrupt_status_offsets[hpd].reg); mask = interrupt_status_offsets[hpd].hpd; - int_control = hpd_int_control_offsets[hpd]; if (disp_int & mask) { - tmp = RREG32(int_control); + tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; - WREG32(int_control, tmp); + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); schedule_work(&adev->hotplug_work); DRM_DEBUG("IH: HPD%d\n", hpd + 1); } @@ -3443,7 +3313,7 @@ static int dce_v8_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs dce_v8_0_ip_funcs = { +static const struct amd_ip_funcs dce_v8_0_ip_funcs = { .name = "dce_v8_0", .early_init = dce_v8_0_early_init, .late_init = NULL, @@ -3727,7 +3597,6 @@ static const struct amdgpu_display_funcs dce_v8_0_display_funcs = { .bandwidth_update = &dce_v8_0_bandwidth_update, .vblank_get_counter = &dce_v8_0_vblank_get_counter, .vblank_wait = &dce_v8_0_vblank_wait, - .is_display_hung = &dce_v8_0_is_display_hung, .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, .hpd_sense = &dce_v8_0_hpd_sense, @@ -3773,3 +3642,48 @@ static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) adev->hpd_irq.num_types = AMDGPU_HPD_LAST; adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; } + +const struct amdgpu_ip_block_version dce_v8_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version dce_v8_1_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 1, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version dce_v8_2_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 2, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version dce_v8_3_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 3, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version dce_v8_5_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 5, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h index 7d0770c3a49b..13b802dd946a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h @@ -24,7 +24,11 @@ #ifndef __DCE_V8_0_H__ #define __DCE_V8_0_H__ -extern const struct amd_ip_funcs dce_v8_0_ip_funcs; +extern const struct amdgpu_ip_block_version dce_v8_0_ip_block; +extern const struct amdgpu_ip_block_version dce_v8_1_ip_block; +extern const struct amdgpu_ip_block_version dce_v8_2_ip_block; +extern const struct amdgpu_ip_block_version dce_v8_3_ip_block; +extern const struct amdgpu_ip_block_version dce_v8_5_ip_block; void dce_v8_0_disable_dce(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index c2bd9f045532..e4a5a5ac0ff3 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -27,6 +27,9 @@ #include "atom.h" #include "amdgpu_pll.h" #include "amdgpu_connectors.h" +#ifdef CONFIG_DRM_AMDGPU_SI +#include "dce_v6_0.h" +#endif #ifdef CONFIG_DRM_AMDGPU_CIK #include "dce_v8_0.h" #endif @@ -34,11 +37,13 @@ #include "dce_v11_0.h" #include "dce_virtual.h" +#define DCE_VIRTUAL_VBLANK_PERIOD 16666666 + + static void dce_virtual_set_display_funcs(struct amdgpu_device *adev); static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev); -static int dce_virtual_pageflip_irq(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - struct amdgpu_iv_entry *entry); +static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev, + int index); /** * dce_virtual_vblank_wait - vblank wait asic callback. @@ -90,15 +95,18 @@ static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev) return 0; } -static bool dce_virtual_is_display_hung(struct amdgpu_device *adev) -{ - return false; -} - static void dce_virtual_stop_mc_access(struct amdgpu_device *adev, struct amdgpu_mode_mc_save *save) { switch (adev->asic_type) { +#ifdef CONFIG_DRM_AMDGPU_SI + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + case CHIP_OLAND: + dce_v6_0_disable_dce(adev); + break; +#endif #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_BONAIRE: case CHIP_HAWAII: @@ -119,6 +127,9 @@ static void dce_virtual_stop_mc_access(struct amdgpu_device *adev, dce_v11_0_disable_dce(adev); break; case CHIP_TOPAZ: +#ifdef CONFIG_DRM_AMDGPU_SI + case CHIP_HAINAN: +#endif /* no DCE */ return; default: @@ -195,16 +206,15 @@ static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode) switch (mode) { case DRM_MODE_DPMS_ON: amdgpu_crtc->enabled = true; - /* Make sure VBLANK and PFLIP interrupts are still enabled */ + /* Make sure VBLANK interrupts are still enabled */ type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); amdgpu_irq_update(adev, &adev->crtc_irq, type); - amdgpu_irq_update(adev, &adev->pageflip_irq, type); - drm_vblank_on(dev, amdgpu_crtc->crtc_id); + drm_crtc_vblank_on(crtc); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - drm_vblank_off(dev, amdgpu_crtc->crtc_id); + drm_crtc_vblank_off(crtc); amdgpu_crtc->enabled = false; break; } @@ -264,24 +274,6 @@ static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct drm_encoder *encoder; - - /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - amdgpu_crtc->encoder = encoder; - amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); - break; - } - } - if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { - amdgpu_crtc->encoder = NULL; - amdgpu_crtc->connector = NULL; - return false; - } - return true; } @@ -341,6 +333,7 @@ static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; + amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs); return 0; @@ -350,48 +343,121 @@ static int dce_virtual_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - adev->mode_info.vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; dce_virtual_set_display_funcs(adev); dce_virtual_set_irq_funcs(adev); - adev->mode_info.num_crtc = 1; adev->mode_info.num_hpd = 1; adev->mode_info.num_dig = 1; return 0; } -static bool dce_virtual_get_connector_info(struct amdgpu_device *adev) +static struct drm_encoder * +dce_virtual_encoder(struct drm_connector *connector) { - struct amdgpu_i2c_bus_rec ddc_bus; - struct amdgpu_router router; - struct amdgpu_hpd hpd; + int enc_id = connector->encoder_ids[0]; + struct drm_encoder *encoder; + int i; - /* look up gpio for ddc, hpd */ - ddc_bus.valid = false; - hpd.hpd = AMDGPU_HPD_NONE; - /* needed for aux chan transactions */ - ddc_bus.hpd = hpd.hpd; + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; - memset(&router, 0, sizeof(router)); - router.ddc_valid = false; - router.cd_valid = false; - amdgpu_display_add_connector(adev, - 0, - ATOM_DEVICE_CRT1_SUPPORT, - DRM_MODE_CONNECTOR_VIRTUAL, &ddc_bus, - CONNECTOR_OBJECT_ID_VIRTUAL, - &hpd, - &router); + encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); + if (!encoder) + continue; - amdgpu_display_add_encoder(adev, ENCODER_VIRTUAL_ENUM_VIRTUAL, - ATOM_DEVICE_CRT1_SUPPORT, - 0); + if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) + return encoder; + } - amdgpu_link_encoder_connector(adev->ddev); + /* pick the first one */ + if (enc_id) + return drm_encoder_find(connector->dev, enc_id); + return NULL; +} + +static int dce_virtual_get_modes(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct drm_display_mode *mode = NULL; + unsigned i; + static const struct mode_size { + int w; + int h; + } common_modes[17] = { + { 640, 480}, + { 720, 480}, + { 800, 600}, + { 848, 480}, + {1024, 768}, + {1152, 768}, + {1280, 720}, + {1280, 800}, + {1280, 854}, + {1280, 960}, + {1280, 1024}, + {1440, 900}, + {1400, 1050}, + {1680, 1050}, + {1600, 1200}, + {1920, 1080}, + {1920, 1200} + }; + + for (i = 0; i < 17; i++) { + mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); + drm_mode_probed_add(connector, mode); + } - return true; + return 0; +} + +static int dce_virtual_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + return MODE_OK; } +static int +dce_virtual_dpms(struct drm_connector *connector, int mode) +{ + return 0; +} + +static int +dce_virtual_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t val) +{ + return 0; +} + +static void dce_virtual_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); + kfree(connector); +} + +static void dce_virtual_force(struct drm_connector *connector) +{ + return; +} + +static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = { + .get_modes = dce_virtual_get_modes, + .mode_valid = dce_virtual_mode_valid, + .best_encoder = dce_virtual_encoder, +}; + +static const struct drm_connector_funcs dce_virtual_connector_funcs = { + .dpms = dce_virtual_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = dce_virtual_set_property, + .destroy = dce_virtual_destroy, + .force = dce_virtual_force, +}; + static int dce_virtual_sw_init(void *handle) { int r, i; @@ -420,16 +486,16 @@ static int dce_virtual_sw_init(void *handle) adev->ddev->mode_config.max_width = 16384; adev->ddev->mode_config.max_height = 16384; - /* allocate crtcs */ + /* allocate crtcs, encoders, connectors */ for (i = 0; i < adev->mode_info.num_crtc; i++) { r = dce_virtual_crtc_init(adev, i); if (r) return r; + r = dce_virtual_connector_encoder_init(adev, i); + if (r) + return r; } - dce_virtual_get_connector_info(adev); - amdgpu_print_display_setup(adev->ddev); - drm_kms_helper_poll_init(adev->ddev); adev->mode_info.mode_config_initialized = true; @@ -496,7 +562,7 @@ static int dce_virtual_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs dce_virtual_ip_funcs = { +static const struct amd_ip_funcs dce_virtual_ip_funcs = { .name = "dce_virtual", .early_init = dce_virtual_early_init, .late_init = NULL, @@ -526,8 +592,8 @@ static void dce_virtual_encoder_commit(struct drm_encoder *encoder) static void dce_virtual_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) { return; } @@ -547,10 +613,6 @@ static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { - - /* set the active encoder to connector routing */ - amdgpu_encoder_set_active_device(encoder); - return true; } @@ -576,45 +638,40 @@ static const struct drm_encoder_funcs dce_virtual_encoder_funcs = { .destroy = dce_virtual_encoder_destroy, }; -static void dce_virtual_encoder_add(struct amdgpu_device *adev, - uint32_t encoder_enum, - uint32_t supported_device, - u16 caps) +static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev, + int index) { - struct drm_device *dev = adev->ddev; struct drm_encoder *encoder; - struct amdgpu_encoder *amdgpu_encoder; - - /* see if we already added it */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - amdgpu_encoder = to_amdgpu_encoder(encoder); - if (amdgpu_encoder->encoder_enum == encoder_enum) { - amdgpu_encoder->devices |= supported_device; - return; - } + struct drm_connector *connector; + + /* add a new encoder */ + encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL); + if (!encoder) + return -ENOMEM; + encoder->possible_crtcs = 1 << index; + drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs, + DRM_MODE_ENCODER_VIRTUAL, NULL); + drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs); + connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL); + if (!connector) { + kfree(encoder); + return -ENOMEM; } - /* add a new one */ - amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); - if (!amdgpu_encoder) - return; + /* add a new connector */ + drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs, + DRM_MODE_CONNECTOR_VIRTUAL); + drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs); + connector->display_info.subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = false; + connector->doublescan_allowed = false; + drm_connector_register(connector); - encoder = &amdgpu_encoder->base; - encoder->possible_crtcs = 0x1; - amdgpu_encoder->enc_priv = NULL; - amdgpu_encoder->encoder_enum = encoder_enum; - amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; - amdgpu_encoder->devices = supported_device; - amdgpu_encoder->rmx_type = RMX_OFF; - amdgpu_encoder->underscan_type = UNDERSCAN_OFF; - amdgpu_encoder->is_ext_encoder = false; - amdgpu_encoder->caps = caps; - - drm_encoder_init(dev, encoder, &dce_virtual_encoder_funcs, - DRM_MODE_ENCODER_VIRTUAL, NULL); - drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs); - DRM_INFO("[FM]encoder: %d is VIRTUAL\n", amdgpu_encoder->encoder_id); + /* link them */ + drm_mode_connector_attach_encoder(connector, encoder); + + return 0; } static const struct amdgpu_display_funcs dce_virtual_display_funcs = { @@ -622,7 +679,6 @@ static const struct amdgpu_display_funcs dce_virtual_display_funcs = { .bandwidth_update = &dce_virtual_bandwidth_update, .vblank_get_counter = &dce_virtual_vblank_get_counter, .vblank_wait = &dce_virtual_vblank_wait, - .is_display_hung = &dce_virtual_is_display_hung, .backlight_set_level = NULL, .backlight_get_level = NULL, .hpd_sense = &dce_virtual_hpd_sense, @@ -630,8 +686,8 @@ static const struct amdgpu_display_funcs dce_virtual_display_funcs = { .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg, .page_flip = &dce_virtual_page_flip, .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos, - .add_encoder = &dce_virtual_encoder_add, - .add_connector = &amdgpu_connector_add, + .add_encoder = NULL, + .add_connector = NULL, .stop_mc_access = &dce_virtual_stop_mc_access, .resume_mc_access = &dce_virtual_resume_mc_access, }; @@ -642,107 +698,13 @@ static void dce_virtual_set_display_funcs(struct amdgpu_device *adev) adev->mode_info.funcs = &dce_virtual_display_funcs; } -static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer) -{ - struct amdgpu_mode_info *mode_info = container_of(vblank_timer, struct amdgpu_mode_info ,vblank_timer); - struct amdgpu_device *adev = container_of(mode_info, struct amdgpu_device ,mode_info); - unsigned crtc = 0; - drm_handle_vblank(adev->ddev, crtc); - dce_virtual_pageflip_irq(adev, NULL, NULL); - hrtimer_start(vblank_timer, ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD), HRTIMER_MODE_REL); - return HRTIMER_NORESTART; -} - -static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, - int crtc, - enum amdgpu_interrupt_state state) -{ - if (crtc >= adev->mode_info.num_crtc) { - DRM_DEBUG("invalid crtc %d\n", crtc); - return; - } - - if (state && !adev->mode_info.vsync_timer_enabled) { - DRM_DEBUG("Enable software vsync timer\n"); - hrtimer_init(&adev->mode_info.vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - hrtimer_set_expires(&adev->mode_info.vblank_timer, ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD)); - adev->mode_info.vblank_timer.function = dce_virtual_vblank_timer_handle; - hrtimer_start(&adev->mode_info.vblank_timer, ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD), HRTIMER_MODE_REL); - } else if (!state && adev->mode_info.vsync_timer_enabled) { - DRM_DEBUG("Disable software vsync timer\n"); - hrtimer_cancel(&adev->mode_info.vblank_timer); - } - - adev->mode_info.vsync_timer_enabled = state; - DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state); -} - - -static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - unsigned type, - enum amdgpu_interrupt_state state) -{ - switch (type) { - case AMDGPU_CRTC_IRQ_VBLANK1: - dce_virtual_set_crtc_vblank_interrupt_state(adev, 0, state); - break; - default: - break; - } - return 0; -} - -static void dce_virtual_crtc_vblank_int_ack(struct amdgpu_device *adev, - int crtc) -{ - if (crtc >= adev->mode_info.num_crtc) { - DRM_DEBUG("invalid crtc %d\n", crtc); - return; - } -} - -static int dce_virtual_crtc_irq(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - struct amdgpu_iv_entry *entry) -{ - unsigned crtc = 0; - unsigned irq_type = AMDGPU_CRTC_IRQ_VBLANK1; - - dce_virtual_crtc_vblank_int_ack(adev, crtc); - - if (amdgpu_irq_enabled(adev, source, irq_type)) { - drm_handle_vblank(adev->ddev, crtc); - } - dce_virtual_pageflip_irq(adev, NULL, NULL); - DRM_DEBUG("IH: D%d vblank\n", crtc + 1); - return 0; -} - -static int dce_virtual_set_pageflip_irq_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *src, - unsigned type, - enum amdgpu_interrupt_state state) -{ - if (type >= adev->mode_info.num_crtc) { - DRM_ERROR("invalid pageflip crtc %d\n", type); - return -EINVAL; - } - DRM_DEBUG("[FM]set pageflip irq type %d state %d\n", type, state); - - return 0; -} - -static int dce_virtual_pageflip_irq(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - struct amdgpu_iv_entry *entry) +static int dce_virtual_pageflip(struct amdgpu_device *adev, + unsigned crtc_id) { unsigned long flags; - unsigned crtc_id = 0; struct amdgpu_crtc *amdgpu_crtc; struct amdgpu_flip_work *works; - crtc_id = 0; amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; if (crtc_id >= adev->mode_info.num_crtc) { @@ -781,22 +743,79 @@ static int dce_virtual_pageflip_irq(struct amdgpu_device *adev, return 0; } +static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer) +{ + struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer, + struct amdgpu_crtc, vblank_timer); + struct drm_device *ddev = amdgpu_crtc->base.dev; + struct amdgpu_device *adev = ddev->dev_private; + + drm_handle_vblank(ddev, amdgpu_crtc->crtc_id); + dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id); + hrtimer_start(vblank_timer, ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD), + HRTIMER_MODE_REL); + + return HRTIMER_NORESTART; +} + +static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state) +{ + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) { + DRM_DEBUG("Enable software vsync timer\n"); + hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); + hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer, + ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD)); + adev->mode_info.crtcs[crtc]->vblank_timer.function = + dce_virtual_vblank_timer_handle; + hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer, + ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD), HRTIMER_MODE_REL); + } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) { + DRM_DEBUG("Disable software vsync timer\n"); + hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer); + } + + adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state; + DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state); +} + + +static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + if (type > AMDGPU_CRTC_IRQ_VBLANK6) + return -EINVAL; + + dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state); + + return 0; +} + static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = { .set = dce_virtual_set_crtc_irq_state, - .process = dce_virtual_crtc_irq, -}; - -static const struct amdgpu_irq_src_funcs dce_virtual_pageflip_irq_funcs = { - .set = dce_virtual_set_pageflip_irq_state, - .process = dce_virtual_pageflip_irq, + .process = NULL, }; static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev) { adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs; - - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; - adev->pageflip_irq.funcs = &dce_virtual_pageflip_irq_funcs; } +const struct amdgpu_ip_block_version dce_virtual_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &dce_virtual_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.h b/drivers/gpu/drm/amd/amdgpu/dce_virtual.h index e239243f6ebc..ed422012c8c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.h +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.h @@ -24,8 +24,7 @@ #ifndef __DCE_VIRTUAL_H__ #define __DCE_VIRTUAL_H__ -extern const struct amd_ip_funcs dce_virtual_ip_funcs; -#define DCE_VIRTUAL_VBLANK_PERIOD 16666666 +extern const struct amdgpu_ip_block_version dce_virtual_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 40abb6b81c09..558640aee15a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -26,15 +26,18 @@ #include "amdgpu_gfx.h" #include "amdgpu_ucode.h" #include "si/clearstate_si.h" -#include "si/sid.h" - -#define GFX6_NUM_GFX_RINGS 1 -#define GFX6_NUM_COMPUTE_RINGS 2 -#define STATIC_PER_CU_PG_ENABLE (1 << 3) -#define DYN_PER_CU_PG_ENABLE (1 << 2) -#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 -#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D - +#include "bif/bif_3_0_d.h" +#include "bif/bif_3_0_sh_mask.h" +#include "oss/oss_1_0_d.h" +#include "oss/oss_1_0_sh_mask.h" +#include "gca/gfx_6_0_d.h" +#include "gca/gfx_6_0_sh_mask.h" +#include "gmc/gmc_6_0_d.h" +#include "gmc/gmc_6_0_sh_mask.h" +#include "dce/dce_6_0_d.h" +#include "dce/dce_6_0_sh_mask.h" +#include "gca/gfx_7_2_enum.h" +#include "si_enums.h" static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); @@ -70,6 +73,15 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *bu //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); static void gfx_v6_0_init_pg(struct amdgpu_device *adev); +#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) +#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) +#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) +#define MICRO_TILE_MODE(x) ((x) << 0) +#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) +#define BANK_WIDTH(x) ((x) << 14) +#define BANK_HEIGHT(x) ((x) << 16) +#define MACRO_TILE_ASPECT(x) ((x) << 18) +#define NUM_BANKS(x) ((x) << 20) static const u32 verde_rlc_save_restore_register_list[] = { @@ -400,8 +412,8 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) } if (adev->asic_type == CHIP_VERDE || - adev->asic_type == CHIP_OLAND || - adev->asic_type == CHIP_HAINAN) { + adev->asic_type == CHIP_OLAND || + adev->asic_type == CHIP_HAINAN) { for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { switch (reg_offset) { case 0: @@ -414,7 +426,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 1: + case 1: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -434,7 +446,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 3: + case 3: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -444,7 +456,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 4: + case 4: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -454,7 +466,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 5: + case 5: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -464,7 +476,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 6: + case 6: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -474,7 +486,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 7: + case 7: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -484,7 +496,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 8: + case 8: gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -494,7 +506,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 9: + case 9: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -504,7 +516,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 10: + case 10: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -514,7 +526,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 11: + case 11: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -524,7 +536,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 12: + case 12: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -534,7 +546,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 13: + case 13: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -544,7 +556,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 14: + case 14: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -554,7 +566,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 15: + case 15: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -564,7 +576,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 16: + case 16: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -574,7 +586,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 17: + case 17: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) | @@ -584,7 +596,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 21: + case 21: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -594,7 +606,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 22: + case 22: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -604,7 +616,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); break; - case 23: + case 23: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -614,7 +626,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 24: + case 24: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -624,7 +636,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); break; - case 25: + case 25: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | @@ -639,7 +651,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) break; } adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; - WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden); + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); } } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { @@ -879,7 +891,7 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) break; } adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; - WREG32(GB_TILE_MODE0 + reg_offset, gb_tile_moden); + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); } } else{ @@ -894,19 +906,23 @@ static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 data; if (instance == 0xffffffff) - data = INSTANCE_BROADCAST_WRITES; + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); else - data = INSTANCE_INDEX(instance); + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) - data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; + data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | + GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; else if (se_num == 0xffffffff) - data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); + data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | + (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); else if (sh_num == 0xffffffff) - data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); + data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | + (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); else - data |= SH_INDEX(sh_num) | SE_INDEX(se_num); - WREG32(GRBM_GFX_INDEX, data); + data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | + (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); + WREG32(mmGRBM_GFX_INDEX, data); } static u32 gfx_v6_0_create_bitmask(u32 bit_width) @@ -920,11 +936,11 @@ static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev, { u32 data, mask; - data = RREG32(CC_RB_BACKEND_DISABLE); - data &= BACKEND_DISABLE_MASK; - data |= RREG32(GC_USER_RB_BACKEND_DISABLE); + data = RREG32(mmCC_RB_BACKEND_DISABLE); + data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; + data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); - data >>= BACKEND_DISABLE_SHIFT; + data >>= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; mask = gfx_v6_0_create_bitmask(max_rb_num_per_se / sh_per_se); @@ -936,14 +952,23 @@ static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) switch (adev->asic_type) { case CHIP_TAHITI: case CHIP_PITCAIRN: - *rconf |= RB_XSEL2(2) | RB_XSEL | PKR_MAP(2) | PKR_YSEL(1) | - SE_MAP(2) | SE_XSEL(2) | SE_YSEL(2); + *rconf |= + (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | + (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | + (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); break; case CHIP_VERDE: - *rconf |= RB_XSEL | PKR_MAP(2) | PKR_YSEL(1); + *rconf |= + (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | + (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | + (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); break; case CHIP_OLAND: - *rconf |= RB_YSEL; + *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); break; case CHIP_HAINAN: *rconf |= 0x0; @@ -981,24 +1006,24 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, int idx = (se / 2) * 2; if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { - raster_config_se &= ~SE_MAP_MASK; + raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; if (!se_mask[idx]) { - raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); + raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; } else { - raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); + raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; } } pkr0_mask &= rb_mask; pkr1_mask &= rb_mask; if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { - raster_config_se &= ~PKR_MAP_MASK; + raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; if (!pkr0_mask) { - raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); + raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; } else { - raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); + raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; } } @@ -1009,14 +1034,14 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, rb0_mask &= rb_mask; rb1_mask &= rb_mask; if (!rb0_mask || !rb1_mask) { - raster_config_se &= ~RB_MAP_PKR0_MASK; + raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; if (!rb0_mask) { raster_config_se |= - RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); + RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; } else { raster_config_se |= - RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); + RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; } } @@ -1026,14 +1051,14 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, rb0_mask &= rb_mask; rb1_mask &= rb_mask; if (!rb0_mask || !rb1_mask) { - raster_config_se &= ~RB_MAP_PKR1_MASK; + raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; if (!rb0_mask) { raster_config_se |= - RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); + RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; } else { raster_config_se |= - RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); + RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; } } } @@ -1041,7 +1066,7 @@ static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, /* GRBM_GFX_INDEX has a different offset on SI */ gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); - WREG32(PA_SC_RASTER_CONFIG, raster_config_se); + WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); } /* GRBM_GFX_INDEX has a different offset on SI */ @@ -1063,7 +1088,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, for (j = 0; j < sh_per_se; j++) { gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); data = gfx_v6_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se); - disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); + disabled_rbs |= data << ((i * sh_per_se + j) * 2); } } gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); @@ -1105,7 +1130,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev, if (!adev->gfx.config.backend_enable_mask || adev->gfx.config.num_rbs >= num_rb_pipes) - WREG32(PA_SC_RASTER_CONFIG, data); + WREG32(mmPA_SC_RASTER_CONFIG, data); else gfx_v6_0_write_harvested_raster_configs(adev, data, adev->gfx.config.backend_enable_mask, @@ -1124,11 +1149,11 @@ static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev, u32 cu_per_sh) { u32 data, mask; - data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); - data &= INACTIVE_CUS_MASK; - data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); + data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); + data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; + data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); - data >>= INACTIVE_CUS_SHIFT; + data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; mask = gfx_v6_0_create_bitmask(cu_per_sh); @@ -1148,7 +1173,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, for (i = 0; i < se_num; i++) { for (j = 0; j < sh_per_se; j++) { gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); - data = RREG32(SPI_STATIC_THREAD_MGMT_3); + data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); active_cu = gfx_v6_0_get_cu_enabled(adev, cu_per_sh); mask = 1; @@ -1156,7 +1181,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, mask <<= k; if (active_cu & mask) { data &= ~mask; - WREG32(SPI_STATIC_THREAD_MGMT_3, data); + WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); break; } } @@ -1209,7 +1234,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; break; - case CHIP_VERDE: adev->gfx.config.max_shader_engines = 1; adev->gfx.config.max_tile_pipes = 4; @@ -1266,18 +1290,18 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) break; } - WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); - WREG32(SRBM_INT_CNTL, 1); - WREG32(SRBM_INT_ACK, 1); + WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); + WREG32(mmSRBM_INT_CNTL, 1); + WREG32(mmSRBM_INT_ACK, 1); - WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); + WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); - mc_shared_chmap = RREG32(MC_SHARED_CHMAP); - mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); + mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); + mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; adev->gfx.config.mem_max_burst_length_bytes = 256; - tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; + tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; if (adev->gfx.config.mem_row_size_in_kb > 4) adev->gfx.config.mem_row_size_in_kb = 4; @@ -1285,32 +1309,33 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) adev->gfx.config.num_gpus = 1; adev->gfx.config.multi_gpu_tile_size = 64; - gb_addr_config &= ~ROW_SIZE_MASK; + gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; switch (adev->gfx.config.mem_row_size_in_kb) { case 1: default: - gb_addr_config |= ROW_SIZE(0); + gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; break; case 2: - gb_addr_config |= ROW_SIZE(1); + gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; break; case 4: - gb_addr_config |= ROW_SIZE(2); + gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; break; } adev->gfx.config.gb_addr_config = gb_addr_config; - WREG32(GB_ADDR_CONFIG, gb_addr_config); - WREG32(DMIF_ADDR_CONFIG, gb_addr_config); - WREG32(DMIF_ADDR_CALC, gb_addr_config); - WREG32(HDP_ADDR_CONFIG, gb_addr_config); - WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); - WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); + WREG32(mmGB_ADDR_CONFIG, gb_addr_config); + WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); + WREG32(mmDMIF_ADDR_CALC, gb_addr_config); + WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); + WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); + WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); + #if 0 if (adev->has_uvd) { - WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); - WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); - WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); } #endif gfx_v6_0_tiling_mode_table_init(adev); @@ -1325,45 +1350,48 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) gfx_v6_0_get_cu_info(adev); - WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | - ROQ_IB2_START(0x2b))); - WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); + WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | + (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); + WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | + (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); - sx_debug_1 = RREG32(SX_DEBUG_1); - WREG32(SX_DEBUG_1, sx_debug_1); + sx_debug_1 = RREG32(mmSX_DEBUG_1); + WREG32(mmSX_DEBUG_1, sx_debug_1); - WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); + WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); - WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_frontend) | - SC_BACKEND_PRIM_FIFO_SIZE(adev->gfx.config.sc_prim_fifo_size_backend) | - SC_HIZ_TILE_FIFO_SIZE(adev->gfx.config.sc_hiz_tile_fifo_size) | - SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size))); + WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); - WREG32(VGT_NUM_INSTANCES, 1); - WREG32(CP_PERFMON_CNTL, 0); - WREG32(SQ_CONFIG, 0); - WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | - FORCE_EOV_MAX_REZ_CNT(255))); + WREG32(mmVGT_NUM_INSTANCES, 1); + WREG32(mmCP_PERFMON_CNTL, 0); + WREG32(mmSQ_CONFIG, 0); + WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | + (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); - WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | - AUTO_INVLD_EN(ES_AND_GS_AUTO)); + WREG32(mmVGT_CACHE_INVALIDATION, + (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | + (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); - WREG32(VGT_GS_VERTEX_REUSE, 16); - WREG32(PA_SC_LINE_STIPPLE_STATE, 0); + WREG32(mmVGT_GS_VERTEX_REUSE, 16); + WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); - WREG32(CB_PERFCOUNTER0_SELECT0, 0); - WREG32(CB_PERFCOUNTER0_SELECT1, 0); - WREG32(CB_PERFCOUNTER1_SELECT0, 0); - WREG32(CB_PERFCOUNTER1_SELECT1, 0); - WREG32(CB_PERFCOUNTER2_SELECT0, 0); - WREG32(CB_PERFCOUNTER2_SELECT1, 0); - WREG32(CB_PERFCOUNTER3_SELECT0, 0); - WREG32(CB_PERFCOUNTER3_SELECT1, 0); + WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); + WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); + WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); + WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); + WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); + WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); + WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); + WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); - hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); - WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); + hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); + WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); - WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); + WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | + (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); udelay(50); } @@ -1374,7 +1402,7 @@ static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) int i; adev->gfx.scratch.num_reg = 7; - adev->gfx.scratch.reg_base = SCRATCH_REG0; + adev->gfx.scratch.reg_base = mmSCRATCH_REG0; for (i = 0; i < adev->gfx.scratch.num_reg; i++) { adev->gfx.scratch.free[i] = true; adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; @@ -1430,11 +1458,18 @@ static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL); + amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0x1); } +static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | + EVENT_INDEX(0)); +} + /** * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp * @@ -1448,7 +1483,7 @@ static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, HDP_DEBUG0); + amdgpu_ring_write(ring, mmHDP_DEBUG0); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0x1); } @@ -1460,7 +1495,7 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; /* flush read cache over gart */ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); - amdgpu_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); + amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | @@ -1475,7 +1510,8 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | - DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); + ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | + ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); amdgpu_ring_write(ring, lower_32_bits(seq)); amdgpu_ring_write(ring, upper_32_bits(seq)); } @@ -1522,7 +1558,7 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; uint32_t scratch; uint32_t tmp = 0; long r; @@ -1548,7 +1584,7 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) if (r) goto err2; - r = fence_wait_timeout(f, false, timeout); + r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out\n"); r = -ETIMEDOUT; @@ -1569,7 +1605,7 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) err2: amdgpu_ib_free(adev, &ib, NULL); - fence_put(f); + dma_fence_put(f); err1: amdgpu_gfx_scratch_free(adev, scratch); return r; @@ -1578,11 +1614,13 @@ err1: static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) { int i; - if (enable) - WREG32(CP_ME_CNTL, 0); - else { - WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); - WREG32(SCRATCH_UMSK, 0); + if (enable) { + WREG32(mmCP_ME_CNTL, 0); + } else { + WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | + CP_ME_CNTL__PFP_HALT_MASK | + CP_ME_CNTL__CE_HALT_MASK)); + WREG32(mmSCRATCH_UMSK, 0); for (i = 0; i < adev->gfx.num_gfx_rings; i++) adev->gfx.gfx_ring[i].ready = false; for (i = 0; i < adev->gfx.num_compute_rings; i++) @@ -1616,34 +1654,33 @@ static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) fw_data = (const __le32 *) (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; - WREG32(CP_PFP_UCODE_ADDR, 0); + WREG32(mmCP_PFP_UCODE_ADDR, 0); for (i = 0; i < fw_size; i++) - WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); - WREG32(CP_PFP_UCODE_ADDR, 0); + WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_PFP_UCODE_ADDR, 0); /* CE */ fw_data = (const __le32 *) (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; - WREG32(CP_CE_UCODE_ADDR, 0); + WREG32(mmCP_CE_UCODE_ADDR, 0); for (i = 0; i < fw_size; i++) - WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); - WREG32(CP_CE_UCODE_ADDR, 0); + WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_CE_UCODE_ADDR, 0); /* ME */ fw_data = (const __be32 *) (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; - WREG32(CP_ME_RAM_WADDR, 0); + WREG32(mmCP_ME_RAM_WADDR, 0); for (i = 0; i < fw_size; i++) - WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); - WREG32(CP_ME_RAM_WADDR, 0); + WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_ME_RAM_WADDR, 0); - - WREG32(CP_PFP_UCODE_ADDR, 0); - WREG32(CP_CE_UCODE_ADDR, 0); - WREG32(CP_ME_RAM_WADDR, 0); - WREG32(CP_ME_RAM_RADDR, 0); + WREG32(mmCP_PFP_UCODE_ADDR, 0); + WREG32(mmCP_CE_UCODE_ADDR, 0); + WREG32(mmCP_ME_RAM_WADDR, 0); + WREG32(mmCP_ME_RAM_RADDR, 0); return 0; } @@ -1720,14 +1757,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) int r; u64 rptr_addr; - WREG32(CP_SEM_WAIT_TIMER, 0x0); - WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); + WREG32(mmCP_SEM_WAIT_TIMER, 0x0); + WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); /* Set the write pointer delay */ - WREG32(CP_RB_WPTR_DELAY, 0); + WREG32(mmCP_RB_WPTR_DELAY, 0); - WREG32(CP_DEBUG, 0); - WREG32(SCRATCH_ADDR, 0); + WREG32(mmCP_DEBUG, 0); + WREG32(mmSCRATCH_ADDR, 0); /* ring 0 - compute and gfx */ /* Set ring buffer size */ @@ -1738,24 +1775,24 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; #endif - WREG32(CP_RB0_CNTL, tmp); + WREG32(mmCP_RB0_CNTL, tmp); /* Initialize the ring buffer's read and write pointers */ - WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); + WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(CP_RB0_WPTR, ring->wptr); + WREG32(mmCP_RB0_WPTR, ring->wptr); /* set the wb address whether it's enabled or not */ rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - WREG32(CP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); - WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); + WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); - WREG32(SCRATCH_UMSK, 0); + WREG32(mmSCRATCH_UMSK, 0); mdelay(1); - WREG32(CP_RB0_CNTL, tmp); + WREG32(mmCP_RB0_CNTL, tmp); - WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); + WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); /* start the rings */ gfx_v6_0_cp_gfx_start(adev); @@ -1779,11 +1816,11 @@ static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring == &adev->gfx.gfx_ring[0]) - return RREG32(CP_RB0_WPTR); + return RREG32(mmCP_RB0_WPTR); else if (ring == &adev->gfx.compute_ring[0]) - return RREG32(CP_RB1_WPTR); + return RREG32(mmCP_RB1_WPTR); else if (ring == &adev->gfx.compute_ring[1]) - return RREG32(CP_RB2_WPTR); + return RREG32(mmCP_RB2_WPTR); else BUG(); } @@ -1792,8 +1829,8 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - WREG32(CP_RB0_WPTR, ring->wptr); - (void)RREG32(CP_RB0_WPTR); + WREG32(mmCP_RB0_WPTR, ring->wptr); + (void)RREG32(mmCP_RB0_WPTR); } static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) @@ -1801,11 +1838,11 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; if (ring == &adev->gfx.compute_ring[0]) { - WREG32(CP_RB1_WPTR, ring->wptr); - (void)RREG32(CP_RB1_WPTR); + WREG32(mmCP_RB1_WPTR, ring->wptr); + (void)RREG32(mmCP_RB1_WPTR); } else if (ring == &adev->gfx.compute_ring[1]) { - WREG32(CP_RB2_WPTR, ring->wptr); - (void)RREG32(CP_RB2_WPTR); + WREG32(mmCP_RB2_WPTR, ring->wptr); + (void)RREG32(mmCP_RB2_WPTR); } else { BUG(); } @@ -1817,7 +1854,7 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) struct amdgpu_ring *ring; u32 tmp; u32 rb_bufsz; - int r; + int i, r; u64 rptr_addr; /* ring1 - compute only */ @@ -1829,19 +1866,19 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; #endif - WREG32(CP_RB1_CNTL, tmp); + WREG32(mmCP_RB1_CNTL, tmp); - WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); + WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(CP_RB1_WPTR, ring->wptr); + WREG32(mmCP_RB1_WPTR, ring->wptr); rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); - WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); + WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); mdelay(1); - WREG32(CP_RB1_CNTL, tmp); - WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); + WREG32(mmCP_RB1_CNTL, tmp); + WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); ring = &adev->gfx.compute_ring[1]; rb_bufsz = order_base_2(ring->ring_size / 8); @@ -1849,32 +1886,27 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; #endif - WREG32(CP_RB2_CNTL, tmp); + WREG32(mmCP_RB2_CNTL, tmp); - WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); + WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(CP_RB2_WPTR, ring->wptr); + WREG32(mmCP_RB2_WPTR, ring->wptr); rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - WREG32(CP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); - WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); + WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); mdelay(1); - WREG32(CP_RB2_CNTL, tmp); - WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); + WREG32(mmCP_RB2_CNTL, tmp); + WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); - adev->gfx.compute_ring[0].ready = true; - adev->gfx.compute_ring[1].ready = true; + adev->gfx.compute_ring[0].ready = false; + adev->gfx.compute_ring[1].ready = false; - r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[0]); - if (r) { - adev->gfx.compute_ring[0].ready = false; - return r; - } - - r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[1]); - if (r) { - adev->gfx.compute_ring[1].ready = false; - return r; + for (i = 0; i < 2; i++) { + r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]); + if (r) + return r; + adev->gfx.compute_ring[i].ready = true; } return 0; @@ -1892,24 +1924,26 @@ static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) -{ - u32 tmp = RREG32(CP_INT_CNTL_RING0); +{ + u32 tmp = RREG32(mmCP_INT_CNTL_RING0); u32 mask; int i; if (enable) - tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); + tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | + CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); else - tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); - WREG32(CP_INT_CNTL_RING0, tmp); + tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | + CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); + WREG32(mmCP_INT_CNTL_RING0, tmp); if (!enable) { /* read a gfx register */ - tmp = RREG32(DB_DEPTH_INFO); + tmp = RREG32(mmDB_DEPTH_INFO); mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; for (i = 0; i < adev->usec_timeout; i++) { - if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) + if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) break; udelay(1); } @@ -1940,7 +1974,7 @@ static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; @@ -1966,16 +2000,16 @@ static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); /* write new base address */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | WRITE_DATA_DST_SEL(0))); if (vm_id < 8) { - amdgpu_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); + amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); } else { - amdgpu_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); + amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); } amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, pd_addr >> 12); @@ -1984,7 +2018,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 1 << vm_id); @@ -1992,7 +2026,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ WAIT_REG_MEM_ENGINE(0))); /* me */ - amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 0); /* ref */ amdgpu_ring_write(ring, 0); /* mask */ @@ -2071,7 +2105,6 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) if (src_ptr) { /* save restore block */ if (adev->gfx.rlc.save_restore_obj == NULL) { - r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, @@ -2166,20 +2199,12 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) { - u32 tmp; - - tmp = RREG32(RLC_LB_CNTL); - if (enable) - tmp |= LOAD_BALANCE_ENABLE; - else - tmp &= ~LOAD_BALANCE_ENABLE; - WREG32(RLC_LB_CNTL, tmp); + WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); if (!enable) { gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); - WREG32(SPI_LB_CU_MASK, 0x00ff); + WREG32(mmSPI_LB_CU_MASK, 0x00ff); } - } static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) @@ -2187,13 +2212,13 @@ static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) int i; for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0) + if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) break; udelay(1); } for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0) + if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) break; udelay(1); } @@ -2203,20 +2228,20 @@ static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) { u32 tmp; - tmp = RREG32(RLC_CNTL); + tmp = RREG32(mmRLC_CNTL); if (tmp != rlc) - WREG32(RLC_CNTL, rlc); + WREG32(mmRLC_CNTL, rlc); } static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) { u32 data, orig; - orig = data = RREG32(RLC_CNTL); + orig = data = RREG32(mmRLC_CNTL); - if (data & RLC_ENABLE) { - data &= ~RLC_ENABLE; - WREG32(RLC_CNTL, data); + if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { + data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; + WREG32(mmRLC_CNTL, data); gfx_v6_0_wait_for_rlc_serdes(adev); } @@ -2226,7 +2251,7 @@ static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) { - WREG32(RLC_CNTL, 0); + WREG32(mmRLC_CNTL, 0); gfx_v6_0_enable_gui_idle_interrupt(adev, false); gfx_v6_0_wait_for_rlc_serdes(adev); @@ -2234,7 +2259,7 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) { - WREG32(RLC_CNTL, RLC_ENABLE); + WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); gfx_v6_0_enable_gui_idle_interrupt(adev, true); @@ -2243,13 +2268,9 @@ static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) { - u32 tmp = RREG32(GRBM_SOFT_RESET); - - tmp |= SOFT_RESET_RLC; - WREG32(GRBM_SOFT_RESET, tmp); + WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); udelay(50); - tmp &= ~SOFT_RESET_RLC; - WREG32(GRBM_SOFT_RESET, tmp); + WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); udelay(50); } @@ -2258,11 +2279,12 @@ static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) u32 tmp; /* Enable LBPW only for DDR3 */ - tmp = RREG32(MC_SEQ_MISC0); + tmp = RREG32(mmMC_SEQ_MISC0); if ((tmp & 0xF0000000) == 0xB0000000) return true; return false; } + static void gfx_v6_0_init_cg(struct amdgpu_device *adev) { } @@ -2283,15 +2305,15 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) gfx_v6_0_init_pg(adev); gfx_v6_0_init_cg(adev); - WREG32(RLC_RL_BASE, 0); - WREG32(RLC_RL_SIZE, 0); - WREG32(RLC_LB_CNTL, 0); - WREG32(RLC_LB_CNTR_MAX, 0xffffffff); - WREG32(RLC_LB_CNTR_INIT, 0); - WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); + WREG32(mmRLC_RL_BASE, 0); + WREG32(mmRLC_RL_SIZE, 0); + WREG32(mmRLC_LB_CNTL, 0); + WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); + WREG32(mmRLC_LB_CNTR_INIT, 0); + WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); - WREG32(RLC_MC_CNTL, 0); - WREG32(RLC_UCODE_CNTL, 0); + WREG32(mmRLC_MC_CNTL, 0); + WREG32(mmRLC_UCODE_CNTL, 0); hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; @@ -2301,10 +2323,10 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) amdgpu_ucode_print_rlc_hdr(&hdr->header); for (i = 0; i < fw_size; i++) { - WREG32(RLC_UCODE_ADDR, i); - WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmRLC_UCODE_ADDR, i); + WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); } - WREG32(RLC_UCODE_ADDR, 0); + WREG32(mmRLC_UCODE_ADDR, 0); gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); gfx_v6_0_rlc_start(adev); @@ -2316,38 +2338,38 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) { u32 data, orig, tmp; - orig = data = RREG32(RLC_CGCG_CGLS_CTRL); + orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { gfx_v6_0_enable_gui_idle_interrupt(adev, true); - WREG32(RLC_GCPM_GENERAL_3, 0x00000080); + WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); tmp = gfx_v6_0_halt_rlc(adev); - WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); - WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); - WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); gfx_v6_0_wait_for_rlc_serdes(adev); gfx_v6_0_update_rlc(adev, tmp); - WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); + WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); - data |= CGCG_EN | CGLS_EN; + data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; } else { gfx_v6_0_enable_gui_idle_interrupt(adev, false); - RREG32(CB_CGTT_SCLK_CTRL); - RREG32(CB_CGTT_SCLK_CTRL); - RREG32(CB_CGTT_SCLK_CTRL); - RREG32(CB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); - data &= ~(CGCG_EN | CGLS_EN); + data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); } if (orig != data) - WREG32(RLC_CGCG_CGLS_CTRL, data); + WREG32(mmRLC_CGCG_CGLS_CTRL, data); } @@ -2357,51 +2379,51 @@ static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) u32 data, orig, tmp = 0; if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { - orig = data = RREG32(CGTS_SM_CTRL_REG); + orig = data = RREG32(mmCGTS_SM_CTRL_REG); data = 0x96940200; if (orig != data) - WREG32(CGTS_SM_CTRL_REG, data); + WREG32(mmCGTS_SM_CTRL_REG, data); if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { - orig = data = RREG32(CP_MEM_SLP_CNTL); - data |= CP_MEM_LS_EN; + orig = data = RREG32(mmCP_MEM_SLP_CNTL); + data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; if (orig != data) - WREG32(CP_MEM_SLP_CNTL, data); + WREG32(mmCP_MEM_SLP_CNTL, data); } - orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); + orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); data &= 0xffffffc0; if (orig != data) - WREG32(RLC_CGTT_MGCG_OVERRIDE, data); + WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); tmp = gfx_v6_0_halt_rlc(adev); - WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); - WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); - WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); gfx_v6_0_update_rlc(adev, tmp); } else { - orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); + orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); data |= 0x00000003; if (orig != data) - WREG32(RLC_CGTT_MGCG_OVERRIDE, data); + WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); - data = RREG32(CP_MEM_SLP_CNTL); - if (data & CP_MEM_LS_EN) { - data &= ~CP_MEM_LS_EN; - WREG32(CP_MEM_SLP_CNTL, data); + data = RREG32(mmCP_MEM_SLP_CNTL); + if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { + data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; + WREG32(mmCP_MEM_SLP_CNTL, data); } - orig = data = RREG32(CGTS_SM_CTRL_REG); - data |= LS_OVERRIDE | OVERRIDE; + orig = data = RREG32(mmCGTS_SM_CTRL_REG); + data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; if (orig != data) - WREG32(CGTS_SM_CTRL_REG, data); + WREG32(mmCGTS_SM_CTRL_REG, data); tmp = gfx_v6_0_halt_rlc(adev); - WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); - WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); - WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); + WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); gfx_v6_0_update_rlc(adev, tmp); } @@ -2421,6 +2443,7 @@ static void gfx_v6_0_update_cg(struct amdgpu_device *adev, gfx_v6_0_enable_gui_idle_interrupt(adev, true); } */ + static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, bool enable) { @@ -2435,13 +2458,13 @@ static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) { u32 data, orig; - orig = data = RREG32(RLC_PG_CNTL); + orig = data = RREG32(mmRLC_PG_CNTL); if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) data &= ~0x8000; else data |= 0x8000; if (orig != data) - WREG32(RLC_PG_CNTL, data); + WREG32(mmRLC_PG_CNTL, data); } static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) @@ -2518,26 +2541,13 @@ static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, bool enable) { - - u32 tmp; - if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { - tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10); - WREG32(RLC_TTOP_D, tmp); - - tmp = RREG32(RLC_PG_CNTL); - tmp |= GFX_PG_ENABLE; - WREG32(RLC_PG_CNTL, tmp); - - tmp = RREG32(RLC_AUTO_PG_CTRL); - tmp |= AUTO_PG_EN; - WREG32(RLC_AUTO_PG_CTRL, tmp); + WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); + WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); + WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); } else { - tmp = RREG32(RLC_AUTO_PG_CTRL); - tmp &= ~AUTO_PG_EN; - WREG32(RLC_AUTO_PG_CTRL, tmp); - - tmp = RREG32(DB_RENDER_CONTROL); + WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); + (void)RREG32(mmDB_RENDER_CONTROL); } } @@ -2550,8 +2560,8 @@ static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev, mutex_lock(&adev->grbm_idx_mutex); gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff); - tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); - tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); + tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); + tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); mutex_unlock(&adev->grbm_idx_mutex); @@ -2594,12 +2604,8 @@ static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) } } - WREG32(RLC_PG_AO_CU_MASK, tmp); - - tmp = RREG32(RLC_MAX_PG_CU); - tmp &= ~MAX_PU_CU_MASK; - tmp |= MAX_PU_CU(active_cu_number); - WREG32(RLC_MAX_PG_CU, tmp); + WREG32(mmRLC_PG_AO_CU_MASK, tmp); + WREG32_FIELD(RLC_MAX_PG_CU, MAX_POWERED_UP_CU, active_cu_number); } static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, @@ -2607,13 +2613,13 @@ static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, { u32 data, orig; - orig = data = RREG32(RLC_PG_CNTL); + orig = data = RREG32(mmRLC_PG_CNTL); if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) - data |= STATIC_PER_CU_PG_ENABLE; + data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; else - data &= ~STATIC_PER_CU_PG_ENABLE; + data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; if (orig != data) - WREG32(RLC_PG_CNTL, data); + WREG32(mmRLC_PG_CNTL, data); } static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, @@ -2621,33 +2627,28 @@ static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, { u32 data, orig; - orig = data = RREG32(RLC_PG_CNTL); + orig = data = RREG32(mmRLC_PG_CNTL); if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) - data |= DYN_PER_CU_PG_ENABLE; + data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; else - data &= ~DYN_PER_CU_PG_ENABLE; + data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; if (orig != data) - WREG32(RLC_PG_CNTL, data); + WREG32(mmRLC_PG_CNTL, data); } static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) { u32 tmp; - WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); + WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); + WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); + WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); - tmp = RREG32(RLC_PG_CNTL); - tmp |= GFX_PG_SRC; - WREG32(RLC_PG_CNTL, tmp); - - WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); - - tmp = RREG32(RLC_AUTO_PG_CTRL); - - tmp &= ~GRBM_REG_SGIT_MASK; - tmp |= GRBM_REG_SGIT(0x700); - tmp &= ~PG_AFTER_GRBM_REG_ST_MASK; - WREG32(RLC_AUTO_PG_CTRL, tmp); + tmp = RREG32(mmRLC_AUTO_PG_CTRL); + tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; + tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); + tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; + WREG32(mmRLC_AUTO_PG_CTRL, tmp); } static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) @@ -2703,7 +2704,6 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); - buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); buffer[count++] = cpu_to_le32(0x80000000); buffer[count++] = cpu_to_le32(0x80000000); @@ -2723,7 +2723,7 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, } buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); + buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TAHITI: @@ -2766,16 +2766,16 @@ static void gfx_v6_0_init_pg(struct amdgpu_device *adev) gfx_v6_0_enable_cp_pg(adev, true); gfx_v6_0_enable_gds_pg(adev, true); } else { - WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); - WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); + WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); + WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); } gfx_v6_0_init_ao_cu_mask(adev); gfx_v6_0_update_gfx_pg(adev, true); } else { - WREG32(RLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); - WREG32(RLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); + WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); + WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); } } @@ -2800,50 +2800,86 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) uint64_t clock; mutex_lock(&adev->gfx.gpu_clock_mutex); - WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); - clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | - ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); + WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); + clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | + ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); mutex_unlock(&adev->gfx.gpu_clock_mutex); return clock; } static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) { + if (flags & AMDGPU_HAVE_CTX_SWITCH) + gfx_v6_0_ring_emit_vgt_flush(ring); amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); amdgpu_ring_write(ring, 0x80000000); amdgpu_ring_write(ring, 0); } -static unsigned gfx_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) + +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) { - return - 6; /* gfx_v6_0_ring_emit_ib */ + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); + return RREG32(mmSQ_IND_DATA); } -static unsigned gfx_v6_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring) +static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t thread, + uint32_t regno, uint32_t num, uint32_t *out) { - return - 5 + /* gfx_v6_0_ring_emit_hdp_flush */ - 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ - 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ - 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ - 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ - 3; /* gfx_v6_ring_emit_cntxcntl */ + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (regno << SQ_IND_INDEX__INDEX__SHIFT) | + (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK) | + (SQ_IND_INDEX__AUTO_INCR_MASK)); + while (num--) + *(out++) = RREG32(mmSQ_IND_DATA); } -static unsigned gfx_v6_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring) +static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { - return - 5 + /* gfx_v6_0_ring_emit_hdp_flush */ - 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ - 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ - 17 + /* gfx_v6_0_ring_emit_vm_flush */ - 14 + 14 + 14; /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ + /* type 0 wave data */ + dst[(*no_fields)++] = 0; + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); +} + +static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t start, + uint32_t size, uint32_t *dst) +{ + wave_read_regs( + adev, simd, wave, 0, + start + SQIND_WAVE_SGPRS_OFFSET, size, dst); } static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, .select_se_sh = &gfx_v6_0_select_se_sh, + .read_wave_data = &gfx_v6_0_read_wave_data, + .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, }; static int gfx_v6_0_early_init(void *handle) @@ -2896,9 +2932,7 @@ static int gfx_v6_0_sw_init(void *handle) ring->ring_obj = NULL; sprintf(ring->name, "gfx"); r = amdgpu_ring_init(adev, ring, 1024, - 0x80000000, 0xf, - &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, - AMDGPU_RING_TYPE_GFX); + &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; } @@ -2920,9 +2954,7 @@ static int gfx_v6_0_sw_init(void *handle) sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; r = amdgpu_ring_init(adev, ring, 1024, - 0x80000000, 0xf, - &adev->gfx.eop_irq, irq_type, - AMDGPU_RING_TYPE_COMPUTE); + &adev->gfx.eop_irq, irq_type); if (r) return r; } @@ -2998,7 +3030,7 @@ static bool gfx_v6_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) + if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) return false; else return true; @@ -3029,14 +3061,14 @@ static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); - cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); - cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; default: break; @@ -3051,27 +3083,27 @@ static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, switch (state){ case AMDGPU_IRQ_STATE_DISABLE: if (ring == 0) { - cp_int_cntl = RREG32(CP_INT_CNTL_RING1); - cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING1, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); + cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); break; } else { - cp_int_cntl = RREG32(CP_INT_CNTL_RING2); - cp_int_cntl &= ~CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING2, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); + cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); break; } case AMDGPU_IRQ_STATE_ENABLE: if (ring == 0) { - cp_int_cntl = RREG32(CP_INT_CNTL_RING1); - cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING1, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); + cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); break; } else { - cp_int_cntl = RREG32(CP_INT_CNTL_RING2); - cp_int_cntl |= CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING2, cp_int_cntl); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); + cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); break; } @@ -3092,14 +3124,14 @@ static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; default: break; @@ -3117,14 +3149,14 @@ static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; case AMDGPU_IRQ_STATE_ENABLE: - cp_int_cntl = RREG32(CP_INT_CNTL_RING0); + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; - WREG32(CP_INT_CNTL_RING0, cp_int_cntl); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); break; default: break; @@ -3164,7 +3196,7 @@ static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, break; case 1: case 2: - amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id -1]); + amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); break; default: break; @@ -3237,7 +3269,7 @@ static int gfx_v6_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs gfx_v6_0_ip_funcs = { +static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { .name = "gfx_v6_0", .early_init = gfx_v6_0_early_init, .late_init = NULL, @@ -3255,10 +3287,20 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs = { }; static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { + .type = AMDGPU_RING_TYPE_GFX, + .align_mask = 0xff, + .nop = 0x80000000, .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_gfx, - .parse_cs = NULL, + .emit_frame_size = + 5 + /* gfx_v6_0_ring_emit_hdp_flush */ + 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ + 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ + 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ + 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ + 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ + .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ .emit_ib = gfx_v6_0_ring_emit_ib, .emit_fence = gfx_v6_0_ring_emit_fence, .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, @@ -3269,15 +3311,22 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .test_ib = gfx_v6_0_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, - .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size, - .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_gfx, }; static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { + .type = AMDGPU_RING_TYPE_COMPUTE, + .align_mask = 0xff, + .nop = 0x80000000, .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_compute, - .parse_cs = NULL, + .emit_frame_size = + 5 + /* gfx_v6_0_ring_emit_hdp_flush */ + 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ + 17 + /* gfx_v6_0_ring_emit_vm_flush */ + 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ .emit_ib = gfx_v6_0_ring_emit_ib, .emit_fence = gfx_v6_0_ring_emit_fence, .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, @@ -3287,8 +3336,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { .test_ring = gfx_v6_0_ring_test_ring, .test_ib = gfx_v6_0_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, - .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size, - .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_compute, }; static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) @@ -3360,3 +3407,12 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) cu_info->number = active_cu_number; cu_info->ao_cu_mask = ao_cu_mask; } + +const struct amdgpu_ip_block_version gfx_v6_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 6, + .minor = 0, + .rev = 0, + .funcs = &gfx_v6_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h index b9657e72b248..ced6fc42f688 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h @@ -24,6 +24,6 @@ #ifndef __GFX_V6_0_H__ #define __GFX_V6_0_H__ -extern const struct amd_ip_funcs gfx_v6_0_ip_funcs; +extern const struct amdgpu_ip_block_version gfx_v6_0_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 71116da9e782..c4e14015ec5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2077,9 +2077,9 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask; - int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; + int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; - if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { switch (ring->me) { case 1: ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; @@ -2105,6 +2105,18 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x20); /* poll interval */ } +static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | + EVENT_INDEX(4)); + + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | + EVENT_INDEX(0)); +} + + /** * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp * @@ -2260,6 +2272,7 @@ static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ if (flags & AMDGPU_HAVE_CTX_SWITCH) { + gfx_v7_0_ring_emit_vgt_flush(ring); /* set load_global_config & load_global_uconfig */ dw2 |= 0x8001; /* set load_cs_sh_regs */ @@ -2286,7 +2299,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; uint32_t scratch; uint32_t tmp = 0; long r; @@ -2312,7 +2325,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) if (r) goto err2; - r = fence_wait_timeout(f, false, timeout); + r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out\n"); r = -ETIMEDOUT; @@ -2333,7 +2346,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) err2: amdgpu_ib_free(adev, &ib, NULL); - fence_put(f); + dma_fence_put(f); err1: amdgpu_gfx_scratch_free(adev, scratch); return r; @@ -3222,7 +3235,7 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) */ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; @@ -3262,7 +3275,7 @@ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | @@ -3391,7 +3404,8 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) if (adev->gfx.rlc.save_restore_obj == NULL) { r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->gfx.rlc.save_restore_obj); if (r) { @@ -3435,7 +3449,8 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) if (adev->gfx.rlc.clear_state_obj == NULL) { r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->gfx.rlc.clear_state_obj); if (r) { @@ -3475,7 +3490,8 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) if (adev->gfx.rlc.cp_table_obj == NULL) { r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->gfx.rlc.cp_table_obj); if (r) { @@ -4354,44 +4370,69 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } -static unsigned gfx_v7_0_ring_get_emit_ib_size_gfx(struct amdgpu_ring *ring) +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) { - return - 4; /* gfx_v7_0_ring_emit_ib_gfx */ + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); + return RREG32(mmSQ_IND_DATA); } -static unsigned gfx_v7_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring) +static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t thread, + uint32_t regno, uint32_t num, uint32_t *out) { - return - 20 + /* gfx_v7_0_ring_emit_gds_switch */ - 7 + /* gfx_v7_0_ring_emit_hdp_flush */ - 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ - 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ - 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ - 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ - 3; /* gfx_v7_ring_emit_cntxcntl */ + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (regno << SQ_IND_INDEX__INDEX__SHIFT) | + (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK) | + (SQ_IND_INDEX__AUTO_INCR_MASK)); + while (num--) + *(out++) = RREG32(mmSQ_IND_DATA); } -static unsigned gfx_v7_0_ring_get_emit_ib_size_compute(struct amdgpu_ring *ring) +static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { - return - 4; /* gfx_v7_0_ring_emit_ib_compute */ + /* type 0 wave data */ + dst[(*no_fields)++] = 0; + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); } -static unsigned gfx_v7_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring) +static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t start, + uint32_t size, uint32_t *dst) { - return - 20 + /* gfx_v7_0_ring_emit_gds_switch */ - 7 + /* gfx_v7_0_ring_emit_hdp_flush */ - 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ - 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ - 17 + /* gfx_v7_0_ring_emit_vm_flush */ - 7 + 7 + 7; /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ + wave_read_regs( + adev, simd, wave, 0, + start + SQIND_WAVE_SGPRS_OFFSET, size, dst); } static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, .select_se_sh = &gfx_v7_0_select_se_sh, + .read_wave_data = &gfx_v7_0_read_wave_data, + .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, }; static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { @@ -4643,9 +4684,7 @@ static int gfx_v7_0_sw_init(void *handle) ring->ring_obj = NULL; sprintf(ring->name, "gfx"); r = amdgpu_ring_init(adev, ring, 1024, - PACKET3(PACKET3_NOP, 0x3FFF), 0xf, - &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, - AMDGPU_RING_TYPE_GFX); + &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; } @@ -4670,9 +4709,7 @@ static int gfx_v7_0_sw_init(void *handle) irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; /* type-2 packets are deprecated on MEC, use type-3 instead */ r = amdgpu_ring_init(adev, ring, 1024, - PACKET3(PACKET3_NOP, 0x3FFF), 0xf, - &adev->gfx.eop_irq, irq_type, - AMDGPU_RING_TYPE_COMPUTE); + &adev->gfx.eop_irq, irq_type); if (r) return r; } @@ -5123,7 +5160,7 @@ static int gfx_v7_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs gfx_v7_0_ip_funcs = { +static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { .name = "gfx_v7_0", .early_init = gfx_v7_0_early_init, .late_init = gfx_v7_0_late_init, @@ -5141,10 +5178,21 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { }; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { + .type = AMDGPU_RING_TYPE_GFX, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_gfx, .set_wptr = gfx_v7_0_ring_set_wptr_gfx, - .parse_cs = NULL, + .emit_frame_size = + 20 + /* gfx_v7_0_ring_emit_gds_switch */ + 7 + /* gfx_v7_0_ring_emit_hdp_flush */ + 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ + 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ + 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ + 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ + 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ + .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ .emit_ib = gfx_v7_0_ring_emit_ib_gfx, .emit_fence = gfx_v7_0_ring_emit_fence_gfx, .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, @@ -5157,15 +5205,23 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .insert_nop = amdgpu_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, - .get_emit_ib_size = gfx_v7_0_ring_get_emit_ib_size_gfx, - .get_dma_frame_size = gfx_v7_0_ring_get_dma_frame_size_gfx, }; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { + .type = AMDGPU_RING_TYPE_COMPUTE, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_compute, .set_wptr = gfx_v7_0_ring_set_wptr_compute, - .parse_cs = NULL, + .emit_frame_size = + 20 + /* gfx_v7_0_ring_emit_gds_switch */ + 7 + /* gfx_v7_0_ring_emit_hdp_flush */ + 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ + 17 + /* gfx_v7_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ + .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */ .emit_ib = gfx_v7_0_ring_emit_ib_compute, .emit_fence = gfx_v7_0_ring_emit_fence_compute, .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, @@ -5177,8 +5233,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .test_ib = gfx_v7_0_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, - .get_emit_ib_size = gfx_v7_0_ring_get_emit_ib_size_compute, - .get_dma_frame_size = gfx_v7_0_ring_get_dma_frame_size_compute, }; static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) @@ -5289,3 +5343,39 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) cu_info->number = active_cu_number; cu_info->ao_cu_mask = ao_cu_mask; } + +const struct amdgpu_ip_block_version gfx_v7_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version gfx_v7_1_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 1, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version gfx_v7_2_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 2, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version gfx_v7_3_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 3, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h index 94e3ea147c26..2f5164cc0e53 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h @@ -24,6 +24,9 @@ #ifndef __GFX_V7_0_H__ #define __GFX_V7_0_H__ -extern const struct amd_ip_funcs gfx_v7_0_ip_funcs; +extern const struct amdgpu_ip_block_version gfx_v7_0_ip_block; +extern const struct amdgpu_ip_block_version gfx_v7_1_ip_block; +extern const struct amdgpu_ip_block_version gfx_v7_2_ip_block; +extern const struct amdgpu_ip_block_version gfx_v7_3_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index bb97182dc749..6324f67bdb1f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -25,6 +25,7 @@ #include "amdgpu.h" #include "amdgpu_gfx.h" #include "vi.h" +#include "vi_structs.h" #include "vid.h" #include "amdgpu_ucode.h" #include "amdgpu_atombios.h" @@ -167,6 +168,7 @@ static const u32 golden_settings_tonga_a11[] = mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c, mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, mmTCC_CTRL, 0x00100000, 0xf31fff7f, @@ -797,7 +799,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; uint32_t scratch; uint32_t tmp = 0; long r; @@ -823,7 +825,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) if (r) goto err2; - r = fence_wait_timeout(f, false, timeout); + r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out.\n"); r = -ETIMEDOUT; @@ -843,7 +845,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } err2: amdgpu_ib_free(adev, &ib, NULL); - fence_put(f); + dma_fence_put(f); err1: amdgpu_gfx_scratch_free(adev, scratch); return r; @@ -1057,6 +1059,19 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) adev->firmware.fw_size += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + /* we need account JT in */ + cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); + + if (amdgpu_sriov_vf(adev)) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE]; + info->ucode_id = AMDGPU_UCODE_ID_STORAGE; + info->fw = adev->gfx.mec_fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE); + } + if (adev->gfx.mec2_fw) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; @@ -1126,34 +1141,8 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - switch (adev->asic_type) { - case CHIP_TONGA: - case CHIP_POLARIS10: - buffer[count++] = cpu_to_le32(0x16000012); - buffer[count++] = cpu_to_le32(0x0000002A); - break; - case CHIP_POLARIS11: - buffer[count++] = cpu_to_le32(0x16000012); - buffer[count++] = cpu_to_le32(0x00000000); - break; - case CHIP_FIJI: - buffer[count++] = cpu_to_le32(0x3a00161a); - buffer[count++] = cpu_to_le32(0x0000002e); - break; - case CHIP_TOPAZ: - case CHIP_CARRIZO: - buffer[count++] = cpu_to_le32(0x00000002); - buffer[count++] = cpu_to_le32(0x00000000); - break; - case CHIP_STONEY: - buffer[count++] = cpu_to_le32(0x00000000); - buffer[count++] = cpu_to_le32(0x00000000); - break; - default: - buffer[count++] = cpu_to_le32(0x00000000); - buffer[count++] = cpu_to_le32(0x00000000); - break; - } + buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); + buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); @@ -1272,7 +1261,8 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) if (adev->gfx.rlc.clear_state_obj == NULL) { r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->gfx.rlc.clear_state_obj); if (r) { @@ -1314,7 +1304,8 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) if (adev->gfx.rlc.cp_table_obj == NULL) { r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, &adev->gfx.rlc.cp_table_obj); if (r) { @@ -1382,7 +1373,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) if (adev->gfx.mec.hpd_eop_obj == NULL) { r = amdgpu_bo_create(adev, - adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, + adev->gfx.mec.num_queue * MEC_HPD_SIZE, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, &adev->gfx.mec.hpd_eop_obj); @@ -1411,7 +1402,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) return r; } - memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); + memset(hpd, 0, adev->gfx.mec.num_queue * MEC_HPD_SIZE); amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); @@ -1574,7 +1565,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) { struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; struct amdgpu_ib ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; int r, i; u32 tmp; unsigned total_size, vgpr_offset, sgpr_offset; @@ -1707,7 +1698,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) } /* wait for the GPU to finish processing the IB */ - r = fence_wait(f, false); + r = dma_fence_wait(f, false); if (r) { DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); goto fail; @@ -1728,7 +1719,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) fail: amdgpu_ib_free(adev, &ib, NULL); - fence_put(f); + dma_fence_put(f); return r; } @@ -2044,10 +2035,8 @@ static int gfx_v8_0_sw_init(void *handle) ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; } - r = amdgpu_ring_init(adev, ring, 1024, - PACKET3(PACKET3_NOP, 0x3FFF), 0xf, - &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, - AMDGPU_RING_TYPE_GFX); + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, + AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; } @@ -2071,10 +2060,8 @@ static int gfx_v8_0_sw_init(void *handle) sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; /* type-2 packets are deprecated on MEC, use type-3 instead */ - r = amdgpu_ring_init(adev, ring, 1024, - PACKET3(PACKET3_NOP, 0x3FFF), 0xf, - &adev->gfx.eop_irq, irq_type, - AMDGPU_RING_TYPE_COMPUTE); + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, + irq_type); if (r) return r; } @@ -3678,6 +3665,21 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) num_rb_pipes); } + /* cache the values for userspace */ + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); + adev->gfx.config.rb_config[i][j].rb_backend_disable = + RREG32(mmCC_RB_BACKEND_DISABLE); + adev->gfx.config.rb_config[i][j].user_rb_backend_disable = + RREG32(mmGC_USER_RB_BACKEND_DISABLE); + adev->gfx.config.rb_config[i][j].raster_config = + RREG32(mmPA_SC_RASTER_CONFIG); + adev->gfx.config.rb_config[i][j].raster_config_1 = + RREG32(mmPA_SC_RASTER_CONFIG_1); + } + } + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); mutex_unlock(&adev->grbm_idx_mutex); } @@ -3904,7 +3906,7 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) int list_size; unsigned int *register_list_format = kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); - if (register_list_format == NULL) + if (!register_list_format) return -ENOMEM; memcpy(register_list_format, adev->gfx.rlc.register_list_format, adev->gfx.rlc.reg_list_format_size_bytes); @@ -4330,7 +4332,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) struct amdgpu_ring *ring; u32 tmp; u32 rb_bufsz; - u64 rb_addr, rptr_addr; + u64 rb_addr, rptr_addr, wptr_gpu_addr; int r; /* Set the write pointer delay */ @@ -4361,6 +4363,9 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); + WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); mdelay(1); WREG32(mmCP_RB0_CNTL, tmp); @@ -4466,267 +4471,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) return 0; } -struct vi_mqd { - uint32_t header; /* ordinal0 */ - uint32_t compute_dispatch_initiator; /* ordinal1 */ - uint32_t compute_dim_x; /* ordinal2 */ - uint32_t compute_dim_y; /* ordinal3 */ - uint32_t compute_dim_z; /* ordinal4 */ - uint32_t compute_start_x; /* ordinal5 */ - uint32_t compute_start_y; /* ordinal6 */ - uint32_t compute_start_z; /* ordinal7 */ - uint32_t compute_num_thread_x; /* ordinal8 */ - uint32_t compute_num_thread_y; /* ordinal9 */ - uint32_t compute_num_thread_z; /* ordinal10 */ - uint32_t compute_pipelinestat_enable; /* ordinal11 */ - uint32_t compute_perfcount_enable; /* ordinal12 */ - uint32_t compute_pgm_lo; /* ordinal13 */ - uint32_t compute_pgm_hi; /* ordinal14 */ - uint32_t compute_tba_lo; /* ordinal15 */ - uint32_t compute_tba_hi; /* ordinal16 */ - uint32_t compute_tma_lo; /* ordinal17 */ - uint32_t compute_tma_hi; /* ordinal18 */ - uint32_t compute_pgm_rsrc1; /* ordinal19 */ - uint32_t compute_pgm_rsrc2; /* ordinal20 */ - uint32_t compute_vmid; /* ordinal21 */ - uint32_t compute_resource_limits; /* ordinal22 */ - uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */ - uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */ - uint32_t compute_tmpring_size; /* ordinal25 */ - uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */ - uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */ - uint32_t compute_restart_x; /* ordinal28 */ - uint32_t compute_restart_y; /* ordinal29 */ - uint32_t compute_restart_z; /* ordinal30 */ - uint32_t compute_thread_trace_enable; /* ordinal31 */ - uint32_t compute_misc_reserved; /* ordinal32 */ - uint32_t compute_dispatch_id; /* ordinal33 */ - uint32_t compute_threadgroup_id; /* ordinal34 */ - uint32_t compute_relaunch; /* ordinal35 */ - uint32_t compute_wave_restore_addr_lo; /* ordinal36 */ - uint32_t compute_wave_restore_addr_hi; /* ordinal37 */ - uint32_t compute_wave_restore_control; /* ordinal38 */ - uint32_t reserved9; /* ordinal39 */ - uint32_t reserved10; /* ordinal40 */ - uint32_t reserved11; /* ordinal41 */ - uint32_t reserved12; /* ordinal42 */ - uint32_t reserved13; /* ordinal43 */ - uint32_t reserved14; /* ordinal44 */ - uint32_t reserved15; /* ordinal45 */ - uint32_t reserved16; /* ordinal46 */ - uint32_t reserved17; /* ordinal47 */ - uint32_t reserved18; /* ordinal48 */ - uint32_t reserved19; /* ordinal49 */ - uint32_t reserved20; /* ordinal50 */ - uint32_t reserved21; /* ordinal51 */ - uint32_t reserved22; /* ordinal52 */ - uint32_t reserved23; /* ordinal53 */ - uint32_t reserved24; /* ordinal54 */ - uint32_t reserved25; /* ordinal55 */ - uint32_t reserved26; /* ordinal56 */ - uint32_t reserved27; /* ordinal57 */ - uint32_t reserved28; /* ordinal58 */ - uint32_t reserved29; /* ordinal59 */ - uint32_t reserved30; /* ordinal60 */ - uint32_t reserved31; /* ordinal61 */ - uint32_t reserved32; /* ordinal62 */ - uint32_t reserved33; /* ordinal63 */ - uint32_t reserved34; /* ordinal64 */ - uint32_t compute_user_data_0; /* ordinal65 */ - uint32_t compute_user_data_1; /* ordinal66 */ - uint32_t compute_user_data_2; /* ordinal67 */ - uint32_t compute_user_data_3; /* ordinal68 */ - uint32_t compute_user_data_4; /* ordinal69 */ - uint32_t compute_user_data_5; /* ordinal70 */ - uint32_t compute_user_data_6; /* ordinal71 */ - uint32_t compute_user_data_7; /* ordinal72 */ - uint32_t compute_user_data_8; /* ordinal73 */ - uint32_t compute_user_data_9; /* ordinal74 */ - uint32_t compute_user_data_10; /* ordinal75 */ - uint32_t compute_user_data_11; /* ordinal76 */ - uint32_t compute_user_data_12; /* ordinal77 */ - uint32_t compute_user_data_13; /* ordinal78 */ - uint32_t compute_user_data_14; /* ordinal79 */ - uint32_t compute_user_data_15; /* ordinal80 */ - uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */ - uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */ - uint32_t reserved35; /* ordinal83 */ - uint32_t reserved36; /* ordinal84 */ - uint32_t reserved37; /* ordinal85 */ - uint32_t cp_mqd_query_time_lo; /* ordinal86 */ - uint32_t cp_mqd_query_time_hi; /* ordinal87 */ - uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */ - uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */ - uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */ - uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */ - uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */ - uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */ - uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */ - uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */ - uint32_t reserved38; /* ordinal96 */ - uint32_t reserved39; /* ordinal97 */ - uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */ - uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */ - uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */ - uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */ - uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */ - uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */ - uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */ - uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */ - uint32_t reserved40; /* ordinal106 */ - uint32_t reserved41; /* ordinal107 */ - uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */ - uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */ - uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */ - uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */ - uint32_t reserved42; /* ordinal112 */ - uint32_t reserved43; /* ordinal113 */ - uint32_t cp_pq_exe_status_lo; /* ordinal114 */ - uint32_t cp_pq_exe_status_hi; /* ordinal115 */ - uint32_t cp_packet_id_lo; /* ordinal116 */ - uint32_t cp_packet_id_hi; /* ordinal117 */ - uint32_t cp_packet_exe_status_lo; /* ordinal118 */ - uint32_t cp_packet_exe_status_hi; /* ordinal119 */ - uint32_t gds_save_base_addr_lo; /* ordinal120 */ - uint32_t gds_save_base_addr_hi; /* ordinal121 */ - uint32_t gds_save_mask_lo; /* ordinal122 */ - uint32_t gds_save_mask_hi; /* ordinal123 */ - uint32_t ctx_save_base_addr_lo; /* ordinal124 */ - uint32_t ctx_save_base_addr_hi; /* ordinal125 */ - uint32_t reserved44; /* ordinal126 */ - uint32_t reserved45; /* ordinal127 */ - uint32_t cp_mqd_base_addr_lo; /* ordinal128 */ - uint32_t cp_mqd_base_addr_hi; /* ordinal129 */ - uint32_t cp_hqd_active; /* ordinal130 */ - uint32_t cp_hqd_vmid; /* ordinal131 */ - uint32_t cp_hqd_persistent_state; /* ordinal132 */ - uint32_t cp_hqd_pipe_priority; /* ordinal133 */ - uint32_t cp_hqd_queue_priority; /* ordinal134 */ - uint32_t cp_hqd_quantum; /* ordinal135 */ - uint32_t cp_hqd_pq_base_lo; /* ordinal136 */ - uint32_t cp_hqd_pq_base_hi; /* ordinal137 */ - uint32_t cp_hqd_pq_rptr; /* ordinal138 */ - uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */ - uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */ - uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */ - uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */ - uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */ - uint32_t cp_hqd_pq_wptr; /* ordinal144 */ - uint32_t cp_hqd_pq_control; /* ordinal145 */ - uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */ - uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */ - uint32_t cp_hqd_ib_rptr; /* ordinal148 */ - uint32_t cp_hqd_ib_control; /* ordinal149 */ - uint32_t cp_hqd_iq_timer; /* ordinal150 */ - uint32_t cp_hqd_iq_rptr; /* ordinal151 */ - uint32_t cp_hqd_dequeue_request; /* ordinal152 */ - uint32_t cp_hqd_dma_offload; /* ordinal153 */ - uint32_t cp_hqd_sema_cmd; /* ordinal154 */ - uint32_t cp_hqd_msg_type; /* ordinal155 */ - uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */ - uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */ - uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */ - uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */ - uint32_t cp_hqd_hq_status0; /* ordinal160 */ - uint32_t cp_hqd_hq_control0; /* ordinal161 */ - uint32_t cp_mqd_control; /* ordinal162 */ - uint32_t cp_hqd_hq_status1; /* ordinal163 */ - uint32_t cp_hqd_hq_control1; /* ordinal164 */ - uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */ - uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */ - uint32_t cp_hqd_eop_control; /* ordinal167 */ - uint32_t cp_hqd_eop_rptr; /* ordinal168 */ - uint32_t cp_hqd_eop_wptr; /* ordinal169 */ - uint32_t cp_hqd_eop_done_events; /* ordinal170 */ - uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */ - uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */ - uint32_t cp_hqd_ctx_save_control; /* ordinal173 */ - uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */ - uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */ - uint32_t cp_hqd_wg_state_offset; /* ordinal176 */ - uint32_t cp_hqd_ctx_save_size; /* ordinal177 */ - uint32_t cp_hqd_gds_resource_state; /* ordinal178 */ - uint32_t cp_hqd_error; /* ordinal179 */ - uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */ - uint32_t cp_hqd_eop_dones; /* ordinal181 */ - uint32_t reserved46; /* ordinal182 */ - uint32_t reserved47; /* ordinal183 */ - uint32_t reserved48; /* ordinal184 */ - uint32_t reserved49; /* ordinal185 */ - uint32_t reserved50; /* ordinal186 */ - uint32_t reserved51; /* ordinal187 */ - uint32_t reserved52; /* ordinal188 */ - uint32_t reserved53; /* ordinal189 */ - uint32_t reserved54; /* ordinal190 */ - uint32_t reserved55; /* ordinal191 */ - uint32_t iqtimer_pkt_header; /* ordinal192 */ - uint32_t iqtimer_pkt_dw0; /* ordinal193 */ - uint32_t iqtimer_pkt_dw1; /* ordinal194 */ - uint32_t iqtimer_pkt_dw2; /* ordinal195 */ - uint32_t iqtimer_pkt_dw3; /* ordinal196 */ - uint32_t iqtimer_pkt_dw4; /* ordinal197 */ - uint32_t iqtimer_pkt_dw5; /* ordinal198 */ - uint32_t iqtimer_pkt_dw6; /* ordinal199 */ - uint32_t iqtimer_pkt_dw7; /* ordinal200 */ - uint32_t iqtimer_pkt_dw8; /* ordinal201 */ - uint32_t iqtimer_pkt_dw9; /* ordinal202 */ - uint32_t iqtimer_pkt_dw10; /* ordinal203 */ - uint32_t iqtimer_pkt_dw11; /* ordinal204 */ - uint32_t iqtimer_pkt_dw12; /* ordinal205 */ - uint32_t iqtimer_pkt_dw13; /* ordinal206 */ - uint32_t iqtimer_pkt_dw14; /* ordinal207 */ - uint32_t iqtimer_pkt_dw15; /* ordinal208 */ - uint32_t iqtimer_pkt_dw16; /* ordinal209 */ - uint32_t iqtimer_pkt_dw17; /* ordinal210 */ - uint32_t iqtimer_pkt_dw18; /* ordinal211 */ - uint32_t iqtimer_pkt_dw19; /* ordinal212 */ - uint32_t iqtimer_pkt_dw20; /* ordinal213 */ - uint32_t iqtimer_pkt_dw21; /* ordinal214 */ - uint32_t iqtimer_pkt_dw22; /* ordinal215 */ - uint32_t iqtimer_pkt_dw23; /* ordinal216 */ - uint32_t iqtimer_pkt_dw24; /* ordinal217 */ - uint32_t iqtimer_pkt_dw25; /* ordinal218 */ - uint32_t iqtimer_pkt_dw26; /* ordinal219 */ - uint32_t iqtimer_pkt_dw27; /* ordinal220 */ - uint32_t iqtimer_pkt_dw28; /* ordinal221 */ - uint32_t iqtimer_pkt_dw29; /* ordinal222 */ - uint32_t iqtimer_pkt_dw30; /* ordinal223 */ - uint32_t iqtimer_pkt_dw31; /* ordinal224 */ - uint32_t reserved56; /* ordinal225 */ - uint32_t reserved57; /* ordinal226 */ - uint32_t reserved58; /* ordinal227 */ - uint32_t set_resources_header; /* ordinal228 */ - uint32_t set_resources_dw1; /* ordinal229 */ - uint32_t set_resources_dw2; /* ordinal230 */ - uint32_t set_resources_dw3; /* ordinal231 */ - uint32_t set_resources_dw4; /* ordinal232 */ - uint32_t set_resources_dw5; /* ordinal233 */ - uint32_t set_resources_dw6; /* ordinal234 */ - uint32_t set_resources_dw7; /* ordinal235 */ - uint32_t reserved59; /* ordinal236 */ - uint32_t reserved60; /* ordinal237 */ - uint32_t reserved61; /* ordinal238 */ - uint32_t reserved62; /* ordinal239 */ - uint32_t reserved63; /* ordinal240 */ - uint32_t reserved64; /* ordinal241 */ - uint32_t reserved65; /* ordinal242 */ - uint32_t reserved66; /* ordinal243 */ - uint32_t reserved67; /* ordinal244 */ - uint32_t reserved68; /* ordinal245 */ - uint32_t reserved69; /* ordinal246 */ - uint32_t reserved70; /* ordinal247 */ - uint32_t reserved71; /* ordinal248 */ - uint32_t reserved72; /* ordinal249 */ - uint32_t reserved73; /* ordinal250 */ - uint32_t reserved74; /* ordinal251 */ - uint32_t reserved75; /* ordinal252 */ - uint32_t reserved76; /* ordinal253 */ - uint32_t reserved77; /* ordinal254 */ - uint32_t reserved78; /* ordinal255 */ - - uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */ -}; - static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) { int i, r; @@ -4760,34 +4504,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) u32 *buf; struct vi_mqd *mqd; - /* init the pipes */ - mutex_lock(&adev->srbm_mutex); - for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { - int me = (i < 4) ? 1 : 2; - int pipe = (i < 4) ? i : (i - 4); - - eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); - eop_gpu_addr >>= 8; - - vi_srbm_select(adev, me, pipe, 0, 0); - - /* write the EOP addr */ - WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr); - WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); - - /* set the VMID assigned */ - WREG32(mmCP_HQD_VMID, 0); - - /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ - tmp = RREG32(mmCP_HQD_EOP_CONTROL); - tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, - (order_base_2(MEC_HPD_SIZE / 4) - 1)); - WREG32(mmCP_HQD_EOP_CONTROL, tmp); - } - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - - /* init the queues. Just two for now. */ + /* init the queues. */ for (i = 0; i < adev->gfx.num_compute_rings; i++) { struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; @@ -4839,6 +4556,22 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) ring->pipe, ring->queue, 0); + eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); + eop_gpu_addr >>= 8; + + /* write the EOP addr */ + WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr); + WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); + + /* set the VMID assigned */ + WREG32(mmCP_HQD_VMID, 0); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = RREG32(mmCP_HQD_EOP_CONTROL); + tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, + (order_base_2(MEC_HPD_SIZE / 4) - 1)); + WREG32(mmCP_HQD_EOP_CONTROL, tmp); + /* disable wptr polling */ tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); @@ -4922,9 +4655,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); - mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; - WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr); + WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo); WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, mqd->cp_hqd_pq_wptr_poll_addr_hi); @@ -5095,6 +4828,10 @@ static int gfx_v8_0_hw_fini(void *handle) amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + if (amdgpu_sriov_vf(adev)) { + pr_debug("For SRIOV client, shouldn't do anything.\n"); + return 0; + } gfx_v8_0_cp_enable(adev, false); gfx_v8_0_rlc_stop(adev); gfx_v8_0_cp_compute_fini(adev); @@ -5437,9 +5174,70 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } +static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) +{ + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK)); + return RREG32(mmSQ_IND_DATA); +} + +static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t thread, + uint32_t regno, uint32_t num, uint32_t *out) +{ + WREG32(mmSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | + (regno << SQ_IND_INDEX__INDEX__SHIFT) | + (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | + (SQ_IND_INDEX__FORCE_READ_MASK) | + (SQ_IND_INDEX__AUTO_INCR_MASK)); + while (num--) + *(out++) = RREG32(mmSQ_IND_DATA); +} + +static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) +{ + /* type 0 wave data */ + dst[(*no_fields)++] = 0; + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); +} + +static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t start, + uint32_t size, uint32_t *dst) +{ + wave_read_regs( + adev, simd, wave, 0, + start + SQIND_WAVE_SGPRS_OFFSET, size, dst); +} + + static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, .select_se_sh = &gfx_v8_0_select_se_sh, + .read_wave_data = &gfx_v8_0_read_wave_data, + .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs, }; static int gfx_v8_0_early_init(void *handle) @@ -5891,29 +5689,24 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev adev->gfx.rlc.funcs->enter_safe_mode(adev); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { - /* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/ - * Cmp_busy/GFX_Idle interrupts - */ - gfx_v8_0_enable_gui_idle_interrupt(adev, true); - temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK; if (temp1 != data1) WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); - /* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ + /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ gfx_v8_0_wait_for_rlc_serdes(adev); - /* 3 - clear cgcg override */ + /* 2 - clear cgcg override */ gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD); /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ gfx_v8_0_wait_for_rlc_serdes(adev); - /* 4 - write cmd to set CGLS */ + /* 3 - write cmd to set CGLS */ gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD); - /* 5 - enable cgcg */ + /* 4 - enable cgcg */ data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { @@ -5931,6 +5724,11 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev if (temp != data) WREG32(mmRLC_CGCG_CGLS_CTRL, data); + + /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/ + * Cmp_busy/GFX_Idle interrupts + */ + gfx_v8_0_enable_gui_idle_interrupt(adev, true); } else { /* disable cntx_empty_int_enable & GFX Idle interrupt */ gfx_v8_0_enable_gui_idle_interrupt(adev, false); @@ -6119,7 +5917,7 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask, reg_mem_engine; - if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { switch (ring->me) { case 1: ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; @@ -6147,6 +5945,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x20); /* poll interval */ } +static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | + EVENT_INDEX(4)); + + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | + EVENT_INDEX(0)); +} + + static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) { amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); @@ -6221,7 +6031,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; @@ -6239,11 +6049,7 @@ static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); - - /* GFX8 emits 128 dw nop to prevent DE do vm_flush before CE finish CEIB */ - if (usepfp) - amdgpu_ring_insert_nop(ring, 128); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | @@ -6336,6 +6142,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ if (flags & AMDGPU_HAVE_CTX_SWITCH) { + gfx_v8_0_ring_emit_vgt_flush(ring); /* set load_global_config & load_global_uconfig */ dw2 |= 0x8001; /* set load_cs_sh_regs */ @@ -6359,42 +6166,6 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) amdgpu_ring_write(ring, 0); } -static unsigned gfx_v8_0_ring_get_emit_ib_size_gfx(struct amdgpu_ring *ring) -{ - return - 4; /* gfx_v8_0_ring_emit_ib_gfx */ -} - -static unsigned gfx_v8_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring) -{ - return - 20 + /* gfx_v8_0_ring_emit_gds_switch */ - 7 + /* gfx_v8_0_ring_emit_hdp_flush */ - 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ - 6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, vm fence */ - 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ - 256 + 19 + /* gfx_v8_0_ring_emit_vm_flush */ - 2 + /* gfx_v8_ring_emit_sb */ - 3; /* gfx_v8_ring_emit_cntxcntl */ -} - -static unsigned gfx_v8_0_ring_get_emit_ib_size_compute(struct amdgpu_ring *ring) -{ - return - 4; /* gfx_v8_0_ring_emit_ib_compute */ -} - -static unsigned gfx_v8_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring) -{ - return - 20 + /* gfx_v8_0_ring_emit_gds_switch */ - 7 + /* gfx_v8_0_ring_emit_hdp_flush */ - 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ - 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ - 17 + /* gfx_v8_0_ring_emit_vm_flush */ - 7 + 7 + 7; /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ -} - static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, enum amdgpu_interrupt_state state) { @@ -6540,7 +6311,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, return 0; } -const struct amd_ip_funcs gfx_v8_0_ip_funcs = { +static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { .name = "gfx_v8_0", .early_init = gfx_v8_0_early_init, .late_init = gfx_v8_0_late_init, @@ -6561,10 +6332,22 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = { }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { + .type = AMDGPU_RING_TYPE_GFX, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_gfx, .set_wptr = gfx_v8_0_ring_set_wptr_gfx, - .parse_cs = NULL, + .emit_frame_size = + 20 + /* gfx_v8_0_ring_emit_gds_switch */ + 7 + /* gfx_v8_0_ring_emit_hdp_flush */ + 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ + 6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, vm fence */ + 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ + 128 + 19 + /* gfx_v8_0_ring_emit_vm_flush */ + 2 + /* gfx_v8_ring_emit_sb */ + 3 + 4, /* gfx_v8_ring_emit_cntxcntl including vgt flush */ + .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ .emit_ib = gfx_v8_0_ring_emit_ib_gfx, .emit_fence = gfx_v8_0_ring_emit_fence_gfx, .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, @@ -6578,15 +6361,23 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .pad_ib = amdgpu_ring_generic_pad_ib, .emit_switch_buffer = gfx_v8_ring_emit_sb, .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl, - .get_emit_ib_size = gfx_v8_0_ring_get_emit_ib_size_gfx, - .get_dma_frame_size = gfx_v8_0_ring_get_dma_frame_size_gfx, }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { + .type = AMDGPU_RING_TYPE_COMPUTE, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_compute, .set_wptr = gfx_v8_0_ring_set_wptr_compute, - .parse_cs = NULL, + .emit_frame_size = + 20 + /* gfx_v8_0_ring_emit_gds_switch */ + 7 + /* gfx_v8_0_ring_emit_hdp_flush */ + 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ + 17 + /* gfx_v8_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ + .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */ .emit_ib = gfx_v8_0_ring_emit_ib_compute, .emit_fence = gfx_v8_0_ring_emit_fence_compute, .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, @@ -6598,8 +6389,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .test_ib = gfx_v8_0_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, - .get_emit_ib_size = gfx_v8_0_ring_get_emit_ib_size_compute, - .get_dma_frame_size = gfx_v8_0_ring_get_dma_frame_size_compute, }; static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) @@ -6752,3 +6541,21 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) cu_info->number = active_cu_number; cu_info->ao_cu_mask = ao_cu_mask; } + +const struct amdgpu_ip_block_version gfx_v8_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gfx_v8_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version gfx_v8_1_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 8, + .minor = 1, + .rev = 0, + .funcs = &gfx_v8_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h index ebed1f829297..788cc3ab584b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h @@ -24,6 +24,7 @@ #ifndef __GFX_V8_0_H__ #define __GFX_V8_0_H__ -extern const struct amd_ip_funcs gfx_v8_0_ip_funcs; +extern const struct amdgpu_ip_block_version gfx_v8_0_ip_block; +extern const struct amdgpu_ip_block_version gfx_v8_1_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index b13c8aaec078..45a573e63d4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -1,4 +1,3 @@ - /* * Copyright 2014 Advanced Micro Devices, Inc. * @@ -26,7 +25,16 @@ #include "amdgpu.h" #include "gmc_v6_0.h" #include "amdgpu_ucode.h" -#include "si/sid.h" + +#include "bif/bif_3_0_d.h" +#include "bif/bif_3_0_sh_mask.h" +#include "oss/oss_1_0_d.h" +#include "oss/oss_1_0_sh_mask.h" +#include "gmc/gmc_6_0_d.h" +#include "gmc/gmc_6_0_sh_mask.h" +#include "dce/dce_6_0_d.h" +#include "dce/dce_6_0_sh_mask.h" +#include "si_enums.h" static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); @@ -37,6 +45,16 @@ MODULE_FIRMWARE("radeon/pitcairn_mc.bin"); MODULE_FIRMWARE("radeon/verde_mc.bin"); MODULE_FIRMWARE("radeon/oland_mc.bin"); +#define MC_SEQ_MISC0__MT__MASK 0xf0000000 +#define MC_SEQ_MISC0__MT__GDDR1 0x10000000 +#define MC_SEQ_MISC0__MT__DDR2 0x20000000 +#define MC_SEQ_MISC0__MT__GDDR3 0x30000000 +#define MC_SEQ_MISC0__MT__GDDR4 0x40000000 +#define MC_SEQ_MISC0__MT__GDDR5 0x50000000 +#define MC_SEQ_MISC0__MT__HBM 0x60000000 +#define MC_SEQ_MISC0__MT__DDR3 0xB0000000 + + static const u32 crtc_offsets[6] = { SI_CRTC0_REGISTER_OFFSET, @@ -57,14 +75,14 @@ static void gmc_v6_0_mc_stop(struct amdgpu_device *adev, gmc_v6_0_wait_for_idle((void *)adev); - blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); - if (REG_GET_FIELD(blackout, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE) != 1) { + blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { /* Block CPU access */ - WREG32(BIF_FB_EN, 0); + WREG32(mmBIF_FB_EN, 0); /* blackout the MC */ blackout = REG_SET_FIELD(blackout, - mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0); - WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); + MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); } /* wait for the MC to settle */ udelay(100); @@ -77,13 +95,13 @@ static void gmc_v6_0_mc_resume(struct amdgpu_device *adev, u32 tmp; /* unblackout the MC */ - tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); - tmp = REG_SET_FIELD(tmp, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0); - WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); + tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); /* allow CPU access */ - tmp = REG_SET_FIELD(0, mmBIF_FB_EN, xxFB_READ_EN, 1); - tmp = REG_SET_FIELD(tmp, mmBIF_FB_EN, xxFB_WRITE_EN, 1); - WREG32(BIF_FB_EN, tmp); + tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); + tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); + WREG32(mmBIF_FB_EN, tmp); if (adev->mode_info.num_crtc) amdgpu_display_resume_mc_access(adev, save); @@ -158,37 +176,37 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) new_fw_data = (const __le32 *) (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); - running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; + running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; if (running == 0) { /* reset the engine and set to writable */ - WREG32(MC_SEQ_SUP_CNTL, 0x00000008); - WREG32(MC_SEQ_SUP_CNTL, 0x00000010); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); /* load mc io regs */ for (i = 0; i < regs_size; i++) { - WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); - WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); + WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); + WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); } /* load the MC ucode */ for (i = 0; i < ucode_size; i++) { - WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); + WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); } /* put the engine back into the active state */ - WREG32(MC_SEQ_SUP_CNTL, 0x00000008); - WREG32(MC_SEQ_SUP_CNTL, 0x00000004); - WREG32(MC_SEQ_SUP_CNTL, 0x00000001); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); /* wait for training to complete */ for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) + if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) break; udelay(1); } for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) + if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) break; udelay(1); } @@ -225,7 +243,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev) WREG32((0xb08 + j), 0x00000000); WREG32((0xb09 + j), 0x00000000); } - WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); + WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); gmc_v6_0_mc_stop(adev, &save); @@ -233,24 +251,24 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev) dev_warn(adev->dev, "Wait for MC idle timedout !\n"); } - WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); + WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK); /* Update configuration */ - WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, + WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->mc.vram_start >> 12); - WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, + WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->mc.vram_end >> 12); - WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, + WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, adev->vram_scratch.gpu_addr >> 12); tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); - WREG32(MC_VM_FB_LOCATION, tmp); + WREG32(mmMC_VM_FB_LOCATION, tmp); /* XXX double check these! */ - WREG32(HDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); - WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); - WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); - WREG32(MC_VM_AGP_BASE, 0); - WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); - WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); + WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); + WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); + WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); + WREG32(mmMC_VM_AGP_BASE, 0); + WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); if (gmc_v6_0_wait_for_idle((void *)adev)) { dev_warn(adev->dev, "Wait for MC idle timedout !\n"); @@ -265,16 +283,16 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) u32 tmp; int chansize, numchan; - tmp = RREG32(MC_ARB_RAMCFG); - if (tmp & CHANSIZE_OVERRIDE) { + tmp = RREG32(mmMC_ARB_RAMCFG); + if (tmp & (1 << 11)) { chansize = 16; - } else if (tmp & CHANSIZE_MASK) { + } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { chansize = 64; } else { chansize = 32; } - tmp = RREG32(MC_SHARED_CHMAP); - switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { + tmp = RREG32(mmMC_SHARED_CHMAP); + switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { case 0: default: numchan = 1; @@ -309,15 +327,15 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) adev->mc.aper_base = pci_resource_start(adev->pdev, 0); adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ - adev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; - adev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; + adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.visible_vram_size = adev->mc.aper_size; /* unless the user had overridden it, set the gart * size equal to the 1024 or vram, whichever is larger. */ if (amdgpu_gart_size == -1) - adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev); + adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); else adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; @@ -329,9 +347,9 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) { - WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); + WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); - WREG32(VM_INVALIDATE_REQUEST, 1 << vmid); + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); } static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, @@ -355,20 +373,20 @@ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, { u32 tmp; - tmp = RREG32(VM_CONTEXT1_CNTL); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT, value); - tmp = REG_SET_FIELD(tmp, mmVM_CONTEXT1_CNTL, - xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); - WREG32(VM_CONTEXT1_CNTL, tmp); + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + WREG32(mmVM_CONTEXT1_CNTL, tmp); } static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) @@ -383,33 +401,39 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) if (r) return r; /* Setup TLB control */ - WREG32(MC_VM_MX_L1_TLB_CNTL, + WREG32(mmMC_VM_MX_L1_TLB_CNTL, (0xA << 7) | - ENABLE_L1_TLB | - ENABLE_L1_FRAGMENT_PROCESSING | - SYSTEM_ACCESS_MODE_NOT_IN_SYS | - ENABLE_ADVANCED_DRIVER_MODEL | - SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); + MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | + MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | + MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | + MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | + (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); /* Setup L2 cache */ - WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | - ENABLE_L2_FRAGMENT_PROCESSING | - ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | - ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | - EFFECTIVE_L2_QUEUE_SIZE(7) | - CONTEXT1_IDENTITY_ACCESS_MODE(1)); - WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); - WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | - BANK_SELECT(4) | - L2_CACHE_BIGK_FRAGMENT_SIZE(4)); + WREG32(mmVM_L2_CNTL, + VM_L2_CNTL__ENABLE_L2_CACHE_MASK | + VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | + VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | + VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | + (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | + (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); + WREG32(mmVM_L2_CNTL2, + VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | + VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); + WREG32(mmVM_L2_CNTL3, + VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | + (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) | + (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); /* setup context0 */ - WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); - WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); - WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); - WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); + WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, (u32)(adev->dummy_page.addr >> 12)); - WREG32(VM_CONTEXT0_CNTL2, 0); - WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); + WREG32(mmVM_CONTEXT0_CNTL2, 0); + WREG32(mmVM_CONTEXT0_CNTL, + VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | + (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | + VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); WREG32(0x575, 0); WREG32(0x576, 0); @@ -417,39 +441,41 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) /* empty context1-15 */ /* set vm size, must be a multiple of 4 */ - WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); - WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); + WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); + WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); /* Assign the pt base to something valid for now; the pts used for * the VMs are determined by the application and setup and assigned * on the fly in the vm part of radeon_gart.c */ for (i = 1; i < 16; i++) { if (i < 8) - WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, adev->gart.table_addr >> 12); else - WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, + WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, adev->gart.table_addr >> 12); } /* enable context1-15 */ - WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, + WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, (u32)(adev->dummy_page.addr >> 12)); - WREG32(VM_CONTEXT1_CNTL2, 4); - WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | - PAGE_TABLE_BLOCK_SIZE(amdgpu_vm_block_size - 9) | - RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | - DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | - DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | - PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | - PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | - VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | - VALID_PROTECTION_FAULT_ENABLE_DEFAULT | - READ_PROTECTION_FAULT_ENABLE_INTERRUPT | - READ_PROTECTION_FAULT_ENABLE_DEFAULT | - WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | - WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); + WREG32(mmVM_CONTEXT1_CNTL2, 4); + WREG32(mmVM_CONTEXT1_CNTL, + VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | + (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | + ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) | + VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); gmc_v6_0_gart_flush_gpu_tlb(adev, 0); dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", @@ -488,19 +514,22 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) }*/ /* Disable all tables */ - WREG32(VM_CONTEXT0_CNTL, 0); - WREG32(VM_CONTEXT1_CNTL, 0); + WREG32(mmVM_CONTEXT0_CNTL, 0); + WREG32(mmVM_CONTEXT1_CNTL, 0); /* Setup TLB control */ - WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | - SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); + WREG32(mmMC_VM_MX_L1_TLB_CNTL, + MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | + (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); /* Setup L2 cache */ - WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | - ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | - EFFECTIVE_L2_QUEUE_SIZE(7) | - CONTEXT1_IDENTITY_ACCESS_MODE(1)); - WREG32(VM_L2_CNTL2, 0); - WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | - L2_CACHE_BIGK_FRAGMENT_SIZE(0)); + WREG32(mmVM_L2_CNTL, + VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | + VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | + (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | + (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); + WREG32(mmVM_L2_CNTL2, 0); + WREG32(mmVM_L2_CNTL3, + VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | + (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); amdgpu_gart_table_vram_unpin(adev); } @@ -523,7 +552,7 @@ static int gmc_v6_0_vm_init(struct amdgpu_device *adev) /* base offset of vram pages */ if (adev->flags & AMD_IS_APU) { - u64 tmp = RREG32(MC_VM_FB_OFFSET); + u64 tmp = RREG32(mmMC_VM_FB_OFFSET); tmp <<= 22; adev->vm_manager.vram_base_offset = tmp; } else @@ -540,19 +569,19 @@ static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, u32 addr, u32 mc_client) { u32 mc_id; - u32 vmid = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, xxVMID); - u32 protections = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, - xxPROTECTIONS); + u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); + u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + PROTECTIONS); char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; - mc_id = REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, - xxMEMORY_CLIENT_ID); + mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + MEMORY_CLIENT_ID); dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", protections, vmid, addr, - REG_GET_FIELD(status, mmVM_CONTEXT1_PROTECTION_FAULT_STATUS, - xxMEMORY_CLIENT_RW) ? + REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + MEMORY_CLIENT_RW) ? "write" : "read", block, mc_client, mc_id); } @@ -655,7 +684,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, { u32 orig, data; - orig = data = RREG32(HDP_HOST_PATH_CNTL); + orig = data = RREG32(mmHDP_HOST_PATH_CNTL); if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); @@ -663,7 +692,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); if (orig != data) - WREG32(HDP_HOST_PATH_CNTL, data); + WREG32(mmHDP_HOST_PATH_CNTL, data); } static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, @@ -671,7 +700,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, { u32 orig, data; - orig = data = RREG32(HDP_MEM_POWER_LS); + orig = data = RREG32(mmHDP_MEM_POWER_LS); if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); @@ -679,7 +708,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); if (orig != data) - WREG32(HDP_MEM_POWER_LS, data); + WREG32(mmHDP_MEM_POWER_LS, data); } */ @@ -713,7 +742,7 @@ static int gmc_v6_0_early_init(void *handle) if (adev->flags & AMD_IS_APU) { adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; } else { - u32 tmp = RREG32(MC_SEQ_MISC0); + u32 tmp = RREG32(mmMC_SEQ_MISC0); tmp &= MC_SEQ_MISC0__MT__MASK; adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); } @@ -766,11 +795,6 @@ static int gmc_v6_0_sw_init(void *handle) return r; } - r = amdgpu_ttm_global_init(adev); - if (r) { - return r; - } - r = gmc_v6_0_mc_init(adev); if (r) return r; @@ -879,7 +903,7 @@ static int gmc_v6_0_resume(void *handle) static bool gmc_v6_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - u32 tmp = RREG32(SRBM_STATUS); + u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) @@ -895,7 +919,7 @@ static int gmc_v6_0_wait_for_idle(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32(SRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | + tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | @@ -913,17 +937,17 @@ static int gmc_v6_0_soft_reset(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_mode_mc_save save; u32 srbm_soft_reset = 0; - u32 tmp = RREG32(SRBM_STATUS); + u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__VMC_BUSY_MASK) srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, - mmSRBM_SOFT_RESET, xxSOFT_RESET_VMC, 1); + SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { if (!(adev->flags & AMD_IS_APU)) srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, - mmSRBM_SOFT_RESET, xxSOFT_RESET_MC, 1); + SRBM_SOFT_RESET, SOFT_RESET_MC, 1); } if (srbm_soft_reset) { @@ -933,17 +957,17 @@ static int gmc_v6_0_soft_reset(void *handle) } - tmp = RREG32(SRBM_SOFT_RESET); + tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); - WREG32(SRBM_SOFT_RESET, tmp); - tmp = RREG32(SRBM_SOFT_RESET); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); udelay(50); tmp &= ~srbm_soft_reset; - WREG32(SRBM_SOFT_RESET, tmp); - tmp = RREG32(SRBM_SOFT_RESET); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); udelay(50); @@ -969,20 +993,20 @@ static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - tmp = RREG32(VM_CONTEXT0_CNTL); + tmp = RREG32(mmVM_CONTEXT0_CNTL); tmp &= ~bits; - WREG32(VM_CONTEXT0_CNTL, tmp); - tmp = RREG32(VM_CONTEXT1_CNTL); + WREG32(mmVM_CONTEXT0_CNTL, tmp); + tmp = RREG32(mmVM_CONTEXT1_CNTL); tmp &= ~bits; - WREG32(VM_CONTEXT1_CNTL, tmp); + WREG32(mmVM_CONTEXT1_CNTL, tmp); break; case AMDGPU_IRQ_STATE_ENABLE: - tmp = RREG32(VM_CONTEXT0_CNTL); + tmp = RREG32(mmVM_CONTEXT0_CNTL); tmp |= bits; - WREG32(VM_CONTEXT0_CNTL, tmp); - tmp = RREG32(VM_CONTEXT1_CNTL); + WREG32(mmVM_CONTEXT0_CNTL, tmp); + tmp = RREG32(mmVM_CONTEXT1_CNTL); tmp |= bits; - WREG32(VM_CONTEXT1_CNTL, tmp); + WREG32(mmVM_CONTEXT1_CNTL, tmp); break; default: break; @@ -997,9 +1021,9 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, { u32 addr, status; - addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); - status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); - WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); + addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); + status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); + WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); if (!addr && !status) return 0; @@ -1007,13 +1031,15 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v6_0_set_fault_enable_default(adev, false); - dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", - addr); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", - status); - gmc_v6_0_vm_decode_fault(adev, status, addr, 0); + if (printk_ratelimit()) { + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + addr); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + status); + gmc_v6_0_vm_decode_fault(adev, status, addr, 0); + } return 0; } @@ -1030,7 +1056,7 @@ static int gmc_v6_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs gmc_v6_0_ip_funcs = { +static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { .name = "gmc_v6_0", .early_init = gmc_v6_0_early_init, .late_init = gmc_v6_0_late_init, @@ -1069,3 +1095,11 @@ static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs; } +const struct amdgpu_ip_block_version gmc_v6_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 6, + .minor = 0, + .rev = 0, + .funcs = &gmc_v6_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h index 42c4fc676cd4..ed2f64dec47a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h @@ -24,6 +24,6 @@ #ifndef __GMC_V6_0_H__ #define __GMC_V6_0_H__ -extern const struct amd_ip_funcs gmc_v6_0_ip_funcs; +extern const struct amdgpu_ip_block_version gmc_v6_0_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index aa0c4b964621..273b16fb9459 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -385,7 +385,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) * size equal to the 1024 or vram, whichever is larger. */ if (amdgpu_gart_size == -1) - adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev); + adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); else adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; @@ -711,7 +711,7 @@ static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, MEMORY_CLIENT_ID); - printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", + dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", protections, vmid, addr, REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, MEMORY_CLIENT_RW) ? @@ -945,11 +945,6 @@ static int gmc_v7_0_sw_init(void *handle) return r; } - r = amdgpu_ttm_global_init(adev); - if (r) { - return r; - } - r = gmc_v7_0_mc_init(adev); if (r) return r; @@ -1198,13 +1193,15 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v7_0_set_fault_enable_default(adev, false); - dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", - addr); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", - status); - gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); + if (printk_ratelimit()) { + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + addr); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + status); + gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); + } return 0; } @@ -1235,7 +1232,7 @@ static int gmc_v7_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs gmc_v7_0_ip_funcs = { +static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { .name = "gmc_v7_0", .early_init = gmc_v7_0_early_init, .late_init = gmc_v7_0_late_init, @@ -1273,3 +1270,21 @@ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) adev->mc.vm_fault.num_types = 1; adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs; } + +const struct amdgpu_ip_block_version gmc_v7_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version gmc_v7_4_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 4, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h index 0b386b5d2f7a..ebce2966c1c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h @@ -24,6 +24,7 @@ #ifndef __GMC_V7_0_H__ #define __GMC_V7_0_H__ -extern const struct amd_ip_funcs gmc_v7_0_ip_funcs; +extern const struct amdgpu_ip_block_version gmc_v7_0_ip_block; +extern const struct amdgpu_ip_block_version gmc_v7_4_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index a16b2201d52c..0daac3a5be79 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -472,7 +472,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) * size equal to the 1024 or vram, whichever is larger. */ if (amdgpu_gart_size == -1) - adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev); + adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); else adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; @@ -837,7 +837,7 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, MEMORY_CLIENT_ID); - printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", + dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", protections, vmid, addr, REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, MEMORY_CLIENT_RW) ? @@ -952,11 +952,6 @@ static int gmc_v8_0_sw_init(void *handle) return r; } - r = amdgpu_ttm_global_init(adev); - if (r) { - return r; - } - r = gmc_v8_0_mc_init(adev); if (r) return r; @@ -1242,13 +1237,15 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v8_0_set_fault_enable_default(adev, false); - dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", - entry->src_id, entry->src_data); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", - addr); - dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", - status); - gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); + if (printk_ratelimit()) { + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + addr); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + status); + gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); + } return 0; } @@ -1437,7 +1434,7 @@ static int gmc_v8_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs gmc_v8_0_ip_funcs = { +static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { .name = "gmc_v8_0", .early_init = gmc_v8_0_early_init, .late_init = gmc_v8_0_late_init, @@ -1478,3 +1475,30 @@ static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) adev->mc.vm_fault.num_types = 1; adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; } + +const struct amdgpu_ip_block_version gmc_v8_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gmc_v8_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version gmc_v8_1_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 8, + .minor = 1, + .rev = 0, + .funcs = &gmc_v8_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version gmc_v8_5_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 8, + .minor = 5, + .rev = 0, + .funcs = &gmc_v8_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h index fc5001a8119d..19b8a8aed204 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h @@ -24,6 +24,8 @@ #ifndef __GMC_V8_0_H__ #define __GMC_V8_0_H__ -extern const struct amd_ip_funcs gmc_v8_0_ip_funcs; +extern const struct amdgpu_ip_block_version gmc_v8_0_ip_block; +extern const struct amdgpu_ip_block_version gmc_v8_1_ip_block; +extern const struct amdgpu_ip_block_version gmc_v8_5_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 3b8906ce3511..ac21bb7bc0f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -392,7 +392,7 @@ static int iceland_ih_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs iceland_ih_ip_funcs = { +static const struct amd_ip_funcs iceland_ih_ip_funcs = { .name = "iceland_ih", .early_init = iceland_ih_early_init, .late_init = NULL, @@ -421,3 +421,11 @@ static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev) adev->irq.ih_funcs = &iceland_ih_funcs; } +const struct amdgpu_ip_block_version iceland_ih_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 4, + .rev = 0, + .funcs = &iceland_ih_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h index 57558cddfbcb..3235f4277548 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h @@ -24,6 +24,6 @@ #ifndef __ICELAND_IH_H__ #define __ICELAND_IH_H__ -extern const struct amd_ip_funcs iceland_ih_ip_funcs; +extern const struct amdgpu_ip_block_version iceland_ih_ip_block; #endif /* __ICELAND_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index 71d2856222fa..5a1bc358bcb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -2796,7 +2796,7 @@ static int kv_parse_power_table(struct amdgpu_device *adev) adev->pm.dpm.num_ps = state_array->ucNumEntries; /* fill in the vce power states */ - for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) { + for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { u32 sclk; clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; clock_info = (union pplib_clock_info *) @@ -2845,7 +2845,7 @@ static int kv_dpm_init(struct amdgpu_device *adev) pi->caps_tcp_ramping = true; } - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK) pi->caps_sclk_ds = true; else pi->caps_sclk_ds = false; @@ -3245,6 +3245,18 @@ static int kv_dpm_set_powergating_state(void *handle, return 0; } +static int kv_check_state_equal(struct amdgpu_device *adev, + struct amdgpu_ps *cps, + struct amdgpu_ps *rps, + bool *equal) +{ + if (equal == NULL) + return -EINVAL; + + *equal = false; + return 0; +} + const struct amd_ip_funcs kv_dpm_ip_funcs = { .name = "kv_dpm", .early_init = kv_dpm_early_init, @@ -3275,6 +3287,8 @@ static const struct amdgpu_dpm_funcs kv_dpm_funcs = { .force_performance_level = &kv_dpm_force_performance_level, .powergate_uvd = &kv_dpm_powergate_uvd, .enable_bapm = &kv_dpm_enable_bapm, + .get_vce_clock_state = amdgpu_get_vce_clock_state, + .check_state_equal = kv_check_state_equal, }; static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev) @@ -3293,3 +3307,12 @@ static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev) adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; } + +const struct amdgpu_ip_block_version kv_dpm_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &kv_dpm_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 565dab3c7218..fbe74a33899c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -232,10 +232,10 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) for (i = 0; i < count; i++) if (sdma && sdma->burst_nop && (i == 0)) - amdgpu_ring_write(ring, ring->nop | + amdgpu_ring_write(ring, ring->funcs->nop | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); else - amdgpu_ring_write(ring, ring->nop); + amdgpu_ring_write(ring, ring->funcs->nop); } /** @@ -668,7 +668,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; unsigned index; u32 tmp = 0; u64 gpu_addr; @@ -705,7 +705,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) if (r) goto err1; - r = fence_wait_timeout(f, false, timeout); + r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out\n"); r = -ETIMEDOUT; @@ -725,7 +725,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) err1: amdgpu_ib_free(adev, &ib, NULL); - fence_put(f); + dma_fence_put(f); err0: amdgpu_wb_free(adev, index); return r; @@ -775,11 +775,11 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, unsigned ndw = count * 2; ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | - SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); ib->ptr[ib->length_dw++] = pe; ib->ptr[ib->length_dw++] = upper_32_bits(pe); ib->ptr[ib->length_dw++] = ndw; - for (; ndw > 0; ndw -= 2, --count, pe += 8) { + for (; ndw > 0; ndw -= 2) { ib->ptr[ib->length_dw++] = lower_32_bits(value); ib->ptr[ib->length_dw++] = upper_32_bits(value); value += incr; @@ -902,22 +902,6 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ } -static unsigned sdma_v2_4_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 7 + 6; /* sdma_v2_4_ring_emit_ib */ -} - -static unsigned sdma_v2_4_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 6 + /* sdma_v2_4_ring_emit_hdp_flush */ - 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */ - 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ - 12 + /* sdma_v2_4_ring_emit_vm_flush */ - 10 + 10 + 10; /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ -} - static int sdma_v2_4_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -965,11 +949,10 @@ static int sdma_v2_4_sw_init(void *handle) ring->use_doorbell = false; sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, - SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, &adev->sdma.trap_irq, (i == 0) ? - AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); if (r) return r; } @@ -1204,7 +1187,7 @@ static int sdma_v2_4_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs sdma_v2_4_ip_funcs = { +static const struct amd_ip_funcs sdma_v2_4_ip_funcs = { .name = "sdma_v2_4", .early_init = sdma_v2_4_early_init, .late_init = NULL, @@ -1222,10 +1205,19 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { }; static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), .get_rptr = sdma_v2_4_ring_get_rptr, .get_wptr = sdma_v2_4_ring_get_wptr, .set_wptr = sdma_v2_4_ring_set_wptr, - .parse_cs = NULL, + .emit_frame_size = + 6 + /* sdma_v2_4_ring_emit_hdp_flush */ + 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */ + 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ + 12 + /* sdma_v2_4_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */ .emit_ib = sdma_v2_4_ring_emit_ib, .emit_fence = sdma_v2_4_ring_emit_fence, .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, @@ -1236,8 +1228,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .test_ib = sdma_v2_4_ring_test_ib, .insert_nop = sdma_v2_4_ring_insert_nop, .pad_ib = sdma_v2_4_ring_pad_ib, - .get_emit_ib_size = sdma_v2_4_ring_get_emit_ib_size, - .get_dma_frame_size = sdma_v2_4_ring_get_dma_frame_size, }; static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) @@ -1350,3 +1340,12 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; } } + +const struct amdgpu_ip_block_version sdma_v2_4_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 4, + .rev = 0, + .funcs = &sdma_v2_4_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h index 07349f5ee10f..28b433729216 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h @@ -24,6 +24,6 @@ #ifndef __SDMA_V2_4_H__ #define __SDMA_V2_4_H__ -extern const struct amd_ip_funcs sdma_v2_4_ip_funcs; +extern const struct amdgpu_ip_block_version sdma_v2_4_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index a9d10941fb53..1170a64a3184 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -392,10 +392,10 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) for (i = 0; i < count; i++) if (sdma && sdma->burst_nop && (i == 0)) - amdgpu_ring_write(ring, ring->nop | + amdgpu_ring_write(ring, ring->funcs->nop | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); else - amdgpu_ring_write(ring, ring->nop); + amdgpu_ring_write(ring, ring->funcs->nop); } /** @@ -871,7 +871,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; unsigned index; u32 tmp = 0; u64 gpu_addr; @@ -908,7 +908,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) if (r) goto err1; - r = fence_wait_timeout(f, false, timeout); + r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out\n"); r = -ETIMEDOUT; @@ -927,7 +927,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } err1: amdgpu_ib_free(adev, &ib, NULL); - fence_put(f); + dma_fence_put(f); err0: amdgpu_wb_free(adev, index); return r; @@ -977,11 +977,11 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, unsigned ndw = count * 2; ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | - SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); ib->ptr[ib->length_dw++] = lower_32_bits(pe); ib->ptr[ib->length_dw++] = upper_32_bits(pe); ib->ptr[ib->length_dw++] = ndw; - for (; ndw > 0; ndw -= 2, --count, pe += 8) { + for (; ndw > 0; ndw -= 2) { ib->ptr[ib->length_dw++] = lower_32_bits(value); ib->ptr[ib->length_dw++] = upper_32_bits(value); value += incr; @@ -1104,22 +1104,6 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ } -static unsigned sdma_v3_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 7 + 6; /* sdma_v3_0_ring_emit_ib */ -} - -static unsigned sdma_v3_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 6 + /* sdma_v3_0_ring_emit_hdp_flush */ - 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */ - 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ - 12 + /* sdma_v3_0_ring_emit_vm_flush */ - 10 + 10 + 10; /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ -} - static int sdma_v3_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1177,11 +1161,10 @@ static int sdma_v3_0_sw_init(void *handle) sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, - SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, &adev->sdma.trap_irq, (i == 0) ? - AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); if (r) return r; } @@ -1544,7 +1527,7 @@ static int sdma_v3_0_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs sdma_v3_0_ip_funcs = { +static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { .name = "sdma_v3_0", .early_init = sdma_v3_0_early_init, .late_init = NULL, @@ -1565,10 +1548,19 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { }; static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), .get_rptr = sdma_v3_0_ring_get_rptr, .get_wptr = sdma_v3_0_ring_get_wptr, .set_wptr = sdma_v3_0_ring_set_wptr, - .parse_cs = NULL, + .emit_frame_size = + 6 + /* sdma_v3_0_ring_emit_hdp_flush */ + 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */ + 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ + 12 + /* sdma_v3_0_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ .emit_ib = sdma_v3_0_ring_emit_ib, .emit_fence = sdma_v3_0_ring_emit_fence, .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, @@ -1579,8 +1571,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .test_ib = sdma_v3_0_ring_test_ib, .insert_nop = sdma_v3_0_ring_insert_nop, .pad_ib = sdma_v3_0_ring_pad_ib, - .get_emit_ib_size = sdma_v3_0_ring_get_emit_ib_size, - .get_dma_frame_size = sdma_v3_0_ring_get_dma_frame_size, }; static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) @@ -1693,3 +1683,21 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; } } + +const struct amdgpu_ip_block_version sdma_v3_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &sdma_v3_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version sdma_v3_1_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 3, + .minor = 1, + .rev = 0, + .funcs = &sdma_v3_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h index 0cb9698a3054..7aa223d35f1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h @@ -24,6 +24,7 @@ #ifndef __SDMA_V3_0_H__ #define __SDMA_V3_0_H__ -extern const struct amd_ip_funcs sdma_v3_0_ip_funcs; +extern const struct amdgpu_ip_block_version sdma_v3_0_ip_block; +extern const struct amdgpu_ip_block_version sdma_v3_1_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index dc9511c5ecb8..3ed8ad8725b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -39,6 +39,7 @@ #include "si_dma.h" #include "dce_v6_0.h" #include "si.h" +#include "dce_virtual.h" static const u32 tahiti_golden_registers[] = { @@ -905,7 +906,7 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); } -u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) +static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) { unsigned long flags; u32 r; @@ -918,7 +919,7 @@ u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) return r; } -void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; @@ -1811,7 +1812,7 @@ static int si_common_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs si_common_ip_funcs = { +static const struct amd_ip_funcs si_common_ip_funcs = { .name = "si_common", .early_init = si_common_early_init, .late_init = NULL, @@ -1828,119 +1829,13 @@ const struct amd_ip_funcs si_common_ip_funcs = { .set_powergating_state = si_common_set_powergating_state, }; -static const struct amdgpu_ip_block_version verde_ip_blocks[] = +static const struct amdgpu_ip_block_version si_common_ip_block = { - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &si_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &gmc_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &si_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &dce_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &gfx_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &si_dma_ip_funcs, - }, -/* { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 3, - .minor = 1, - .rev = 0, - .funcs = &si_null_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &si_null_ip_funcs, - }, - */ -}; - - -static const struct amdgpu_ip_block_version hainan_ip_blocks[] = -{ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &si_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &gmc_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &si_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &gfx_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &si_dma_ip_funcs, - }, + .type = AMD_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &si_common_ip_funcs, }; int si_set_ip_blocks(struct amdgpu_device *adev) @@ -1949,13 +1844,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev) case CHIP_VERDE: case CHIP_TAHITI: case CHIP_PITCAIRN: + amdgpu_ip_block_add(adev, &si_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); + amdgpu_ip_block_add(adev, &si_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v6_0_ip_block); + amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); + amdgpu_ip_block_add(adev, &si_dma_ip_block); + /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ + /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ + break; case CHIP_OLAND: - adev->ip_blocks = verde_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks); + amdgpu_ip_block_add(adev, &si_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); + amdgpu_ip_block_add(adev, &si_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v6_4_ip_block); + amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); + amdgpu_ip_block_add(adev, &si_dma_ip_block); + /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ + /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ break; case CHIP_HAINAN: - adev->ip_blocks = hainan_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks); + amdgpu_ip_block_add(adev, &si_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); + amdgpu_ip_block_add(adev, &si_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); + amdgpu_ip_block_add(adev, &si_dma_ip_block); break; default: BUG(); diff --git a/drivers/gpu/drm/amd/amdgpu/si.h b/drivers/gpu/drm/amd/amdgpu/si.h index 959d7b63e0e5..589225080c24 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.h +++ b/drivers/gpu/drm/amd/amdgpu/si.h @@ -24,8 +24,6 @@ #ifndef __SI_H__ #define __SI_H__ -extern const struct amd_ip_funcs si_common_ip_funcs; - void si_srbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); int si_set_ip_blocks(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index de358193a8f9..3dd552ae0b59 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -274,7 +274,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) { struct amdgpu_device *adev = ring->adev; struct amdgpu_ib ib; - struct fence *f = NULL; + struct dma_fence *f = NULL; unsigned index; u32 tmp = 0; u64 gpu_addr; @@ -305,7 +305,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) if (r) goto err1; - r = fence_wait_timeout(f, false, timeout); + r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { DRM_ERROR("amdgpu: IB test timed out\n"); r = -ETIMEDOUT; @@ -325,7 +325,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) err1: amdgpu_ib_free(adev, &ib, NULL); - fence_put(f); + dma_fence_put(f); err0: amdgpu_wb_free(adev, index); return r; @@ -495,22 +495,6 @@ static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ } -static unsigned si_dma_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 7 + 3; /* si_dma_ring_emit_ib */ -} - -static unsigned si_dma_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 3 + /* si_dma_ring_emit_hdp_flush */ - 3 + /* si_dma_ring_emit_hdp_invalidate */ - 6 + /* si_dma_ring_emit_pipeline_sync */ - 12 + /* si_dma_ring_emit_vm_flush */ - 9 + 9 + 9; /* si_dma_ring_emit_fence x3 for user fence, vm fence */ -} - static int si_dma_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -547,11 +531,10 @@ static int si_dma_sw_init(void *handle) ring->use_doorbell = false; sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), 0xf, &adev->sdma.trap_irq, (i == 0) ? - AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); if (r) return r; } @@ -762,7 +745,7 @@ static int si_dma_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs si_dma_ip_funcs = { +static const struct amd_ip_funcs si_dma_ip_funcs = { .name = "si_dma", .early_init = si_dma_early_init, .late_init = NULL, @@ -780,10 +763,19 @@ const struct amd_ip_funcs si_dma_ip_funcs = { }; static const struct amdgpu_ring_funcs si_dma_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), .get_rptr = si_dma_ring_get_rptr, .get_wptr = si_dma_ring_get_wptr, .set_wptr = si_dma_ring_set_wptr, - .parse_cs = NULL, + .emit_frame_size = + 3 + /* si_dma_ring_emit_hdp_flush */ + 3 + /* si_dma_ring_emit_hdp_invalidate */ + 6 + /* si_dma_ring_emit_pipeline_sync */ + 12 + /* si_dma_ring_emit_vm_flush */ + 9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 3, /* si_dma_ring_emit_ib */ .emit_ib = si_dma_ring_emit_ib, .emit_fence = si_dma_ring_emit_fence, .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, @@ -794,8 +786,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { .test_ib = si_dma_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .pad_ib = si_dma_ring_pad_ib, - .get_emit_ib_size = si_dma_ring_get_emit_ib_size, - .get_dma_frame_size = si_dma_ring_get_dma_frame_size, }; static void si_dma_set_ring_funcs(struct amdgpu_device *adev) @@ -913,3 +903,12 @@ static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev) adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; } } + +const struct amdgpu_ip_block_version si_dma_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &si_dma_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.h b/drivers/gpu/drm/amd/amdgpu/si_dma.h index 3a3e0c78a54b..5ac1b8452fb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.h +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.h @@ -24,6 +24,6 @@ #ifndef __SI_DMA_H__ #define __SI_DMA_H__ -extern const struct amd_ip_funcs si_dma_ip_funcs; +extern const struct amdgpu_ip_block_version si_dma_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index d6f85b1a0b93..6c65a1a2de79 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c @@ -3171,6 +3171,7 @@ static void ni_update_current_ps(struct amdgpu_device *adev, eg_pi->current_rps = *rps; ni_pi->current_ps = *new_ps; eg_pi->current_rps.ps_priv = &ni_pi->current_ps; + adev->pm.dpm.current_ps = &eg_pi->current_rps; } static void ni_update_requested_ps(struct amdgpu_device *adev, @@ -3183,6 +3184,7 @@ static void ni_update_requested_ps(struct amdgpu_device *adev, eg_pi->requested_rps = *rps; ni_pi->requested_ps = *new_ps; eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; + adev->pm.dpm.requested_ps = &eg_pi->requested_rps; } static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, @@ -3504,6 +3506,7 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, (adev->pdev->revision == 0x80) || (adev->pdev->revision == 0x81) || (adev->pdev->revision == 0x83) || + (adev->pdev->revision == 0x87) || (adev->pdev->device == 0x6604) || (adev->pdev->device == 0x6605)) { max_sclk = 75000; @@ -7347,7 +7350,7 @@ static int si_parse_power_table(struct amdgpu_device *adev) adev->pm.dpm.num_ps = state_array->ucNumEntries; /* fill in the vce power states */ - for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) { + for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { u32 sclk, mclk; clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; clock_info = (union pplib_clock_info *) @@ -7713,6 +7716,7 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev) (adev->pdev->revision == 0x80) || (adev->pdev->revision == 0x81) || (adev->pdev->revision == 0x83) || + (adev->pdev->revision == 0x87) || (adev->pdev->device == 0x6604) || (adev->pdev->device == 0x6605)) chip_name = "oland_k"; @@ -7986,6 +7990,57 @@ static int si_dpm_early_init(void *handle) return 0; } +static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, + const struct rv7xx_pl *si_cpl2) +{ + return ((si_cpl1->mclk == si_cpl2->mclk) && + (si_cpl1->sclk == si_cpl2->sclk) && + (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && + (si_cpl1->vddc == si_cpl2->vddc) && + (si_cpl1->vddci == si_cpl2->vddci)); +} + +static int si_check_state_equal(struct amdgpu_device *adev, + struct amdgpu_ps *cps, + struct amdgpu_ps *rps, + bool *equal) +{ + struct si_ps *si_cps; + struct si_ps *si_rps; + int i; + + if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) + return -EINVAL; + + si_cps = si_get_ps(cps); + si_rps = si_get_ps(rps); + + if (si_cps == NULL) { + printk("si_cps is NULL\n"); + *equal = false; + return 0; + } + + if (si_cps->performance_level_count != si_rps->performance_level_count) { + *equal = false; + return 0; + } + + for (i = 0; i < si_cps->performance_level_count; i++) { + if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), + &(si_rps->performance_levels[i]))) { + *equal = false; + return 0; + } + } + + /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ + *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); + *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); + + return 0; +} + const struct amd_ip_funcs si_dpm_ip_funcs = { .name = "si_dpm", @@ -8020,6 +8075,8 @@ static const struct amdgpu_dpm_funcs si_dpm_funcs = { .get_fan_control_mode = &si_dpm_get_fan_control_mode, .set_fan_speed_percent = &si_dpm_set_fan_speed_percent, .get_fan_speed_percent = &si_dpm_get_fan_speed_percent, + .check_state_equal = &si_check_state_equal, + .get_vce_clock_state = amdgpu_get_vce_clock_state, }; static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev) @@ -8039,3 +8096,11 @@ static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; } +const struct amdgpu_ip_block_version si_dpm_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 6, + .minor = 0, + .rev = 0, + .funcs = &si_dpm_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h new file mode 100644 index 000000000000..fde2086246fa --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h @@ -0,0 +1,272 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef SI_ENUMS_H +#define SI_ENUMS_H + +#define VBLANK_INT_MASK (1 << 0) +#define DC_HPDx_INT_EN (1 << 16) +#define VBLANK_ACK (1 << 4) +#define VLINE_ACK (1 << 4) + +#define CURSOR_WIDTH 64 +#define CURSOR_HEIGHT 64 + +#define VGA_VSTATUS_CNTL 0xFFFCFFFF +#define PRIORITY_MARK_MASK 0x7fff +#define PRIORITY_OFF (1 << 16) +#define PRIORITY_ALWAYS_ON (1 << 20) +#define INTERLEAVE_EN (1 << 0) + +#define LATENCY_WATERMARK_MASK(x) ((x) << 16) +#define DC_LB_MEMORY_CONFIG(x) ((x) << 20) +#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) + +#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) +#define GRPH_ENDIAN_NONE 0 +#define GRPH_ENDIAN_8IN16 1 +#define GRPH_ENDIAN_8IN32 2 +#define GRPH_ENDIAN_8IN64 3 + +#define GRPH_DEPTH(x) (((x) & 0x3) << 0) +#define GRPH_DEPTH_8BPP 0 +#define GRPH_DEPTH_16BPP 1 +#define GRPH_DEPTH_32BPP 2 + +#define GRPH_FORMAT(x) (((x) & 0x7) << 8) +#define GRPH_FORMAT_INDEXED 0 +#define GRPH_FORMAT_ARGB1555 0 +#define GRPH_FORMAT_ARGB565 1 +#define GRPH_FORMAT_ARGB4444 2 +#define GRPH_FORMAT_AI88 3 +#define GRPH_FORMAT_MONO16 4 +#define GRPH_FORMAT_BGRA5551 5 +#define GRPH_FORMAT_ARGB8888 0 +#define GRPH_FORMAT_ARGB2101010 1 +#define GRPH_FORMAT_32BPP_DIG 2 +#define GRPH_FORMAT_8B_ARGB2101010 3 +#define GRPH_FORMAT_BGRA1010102 4 +#define GRPH_FORMAT_8B_BGRA1010102 5 +#define GRPH_FORMAT_RGB111110 6 +#define GRPH_FORMAT_BGR101111 7 + +#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) +#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) +#define GRPH_ARRAY_LINEAR_GENERAL 0 +#define GRPH_ARRAY_LINEAR_ALIGNED 1 +#define GRPH_ARRAY_1D_TILED_THIN1 2 +#define GRPH_ARRAY_2D_TILED_THIN1 4 +#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) +#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) +#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) +#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) +#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) +#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) + +#define CURSOR_EN (1 << 0) +#define CURSOR_MODE(x) (((x) & 0x3) << 8) +#define CURSOR_MONO 0 +#define CURSOR_24_1 1 +#define CURSOR_24_8_PRE_MULT 2 +#define CURSOR_24_8_UNPRE_MULT 3 +#define CURSOR_2X_MAGNIFY (1 << 16) +#define CURSOR_FORCE_MC_ON (1 << 20) +#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) +#define CURSOR_URGENT_ALWAYS 0 +#define CURSOR_URGENT_1_8 1 +#define CURSOR_URGENT_1_4 2 +#define CURSOR_URGENT_3_8 3 +#define CURSOR_URGENT_1_2 4 +#define CURSOR_UPDATE_PENDING (1 << 0) +#define CURSOR_UPDATE_TAKEN (1 << 1) +#define CURSOR_UPDATE_LOCK (1 << 16) +#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) + +#define AMDGPU_NUM_OF_VMIDS 8 +#define SI_CRTC0_REGISTER_OFFSET 0 +#define SI_CRTC1_REGISTER_OFFSET 0x300 +#define SI_CRTC2_REGISTER_OFFSET 0x2600 +#define SI_CRTC3_REGISTER_OFFSET 0x2900 +#define SI_CRTC4_REGISTER_OFFSET 0x2c00 +#define SI_CRTC5_REGISTER_OFFSET 0x2f00 + +#define DMA0_REGISTER_OFFSET 0x000 +#define DMA1_REGISTER_OFFSET 0x200 +#define ES_AND_GS_AUTO 3 +#define RADEON_PACKET_TYPE3 3 +#define CE_PARTITION_BASE 3 +#define BUF_SWAP_32BIT (2 << 16) + +#define GFX_POWER_STATUS (1 << 1) +#define GFX_CLOCK_STATUS (1 << 2) +#define GFX_LS_STATUS (1 << 3) +#define RLC_BUSY_STATUS (1 << 0) + +#define RLC_PUD(x) ((x) << 0) +#define RLC_PUD_MASK (0xff << 0) +#define RLC_PDD(x) ((x) << 8) +#define RLC_PDD_MASK (0xff << 8) +#define RLC_TTPD(x) ((x) << 16) +#define RLC_TTPD_MASK (0xff << 16) +#define RLC_MSD(x) ((x) << 24) +#define RLC_MSD_MASK (0xff << 24) +#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) +#define WRITE_DATA_DST_SEL(x) ((x) << 8) +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + +#define GFX6_NUM_GFX_RINGS 1 +#define GFX6_NUM_COMPUTE_RINGS 2 +#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 +#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D + +#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 +#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 +#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 + +#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) +#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) +#define PACKET3_NOP 0x10 +#define PACKET3_SET_BASE 0x11 +#define PACKET3_BASE_INDEX(x) ((x) << 0) +#define PACKET3_CLEAR_STATE 0x12 +#define PACKET3_INDEX_BUFFER_SIZE 0x13 +#define PACKET3_DISPATCH_DIRECT 0x15 +#define PACKET3_DISPATCH_INDIRECT 0x16 +#define PACKET3_ALLOC_GDS 0x1B +#define PACKET3_WRITE_GDS_RAM 0x1C +#define PACKET3_ATOMIC_GDS 0x1D +#define PACKET3_ATOMIC 0x1E +#define PACKET3_OCCLUSION_QUERY 0x1F +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_DRAW_INDIRECT 0x24 +#define PACKET3_DRAW_INDEX_INDIRECT 0x25 +#define PACKET3_INDEX_BASE 0x26 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_INDEX_TYPE 0x2A +#define PACKET3_DRAW_INDIRECT_MULTI 0x2C +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_DRAW_INDEX_IMMD 0x2E +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 +#define PACKET3_INDIRECT_BUFFER_CONST 0x31 +#define PACKET3_INDIRECT_BUFFER 0x3F +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 +#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 +#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 +#define PACKET3_WRITE_DATA 0x37 +#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 +#define PACKET3_MEM_SEMAPHORE 0x39 +#define PACKET3_MPEG_INDEX 0x3A +#define PACKET3_COPY_DW 0x3B +#define PACKET3_WAIT_REG_MEM 0x3C +#define PACKET3_MEM_WRITE 0x3D +#define PACKET3_COPY_DATA 0x40 +#define PACKET3_CP_DMA 0x41 +# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) +# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) +# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) +# define PACKET3_CP_DMA_CP_SYNC (1 << 31) +# define PACKET3_CP_DMA_DIS_WC (1 << 21) +# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) +# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) +# define PACKET3_CP_DMA_CMD_SAS (1 << 26) +# define PACKET3_CP_DMA_CMD_DAS (1 << 27) +# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) +# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) +# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) +#define PACKET3_PFP_SYNC_ME 0x42 +#define PACKET3_SURFACE_SYNC 0x43 +# define PACKET3_DEST_BASE_0_ENA (1 << 0) +# define PACKET3_DEST_BASE_1_ENA (1 << 1) +# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) +# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) +# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) +# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) +# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) +# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) +# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) +# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) +# define PACKET3_DB_DEST_BASE_ENA (1 << 14) +# define PACKET3_DEST_BASE_2_ENA (1 << 19) +# define PACKET3_DEST_BASE_3_ENA (1 << 21) +# define PACKET3_TCL1_ACTION_ENA (1 << 22) +# define PACKET3_TC_ACTION_ENA (1 << 23) +# define PACKET3_CB_ACTION_ENA (1 << 25) +# define PACKET3_DB_ACTION_ENA (1 << 26) +# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) +# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) +#define PACKET3_ME_INITIALIZE 0x44 +#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define PACKET3_EVENT_WRITE_EOP 0x47 +#define PACKET3_EVENT_WRITE_EOS 0x48 +#define PACKET3_PREAMBLE_CNTL 0x4A +# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) +# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) +#define PACKET3_ONE_REG_WRITE 0x57 +#define PACKET3_LOAD_CONFIG_REG 0x5F +#define PACKET3_LOAD_CONTEXT_REG 0x60 +#define PACKET3_LOAD_SH_REG 0x61 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_START 0x00002000 +#define PACKET3_SET_CONFIG_REG_END 0x00002c00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_START 0x000a000 +#define PACKET3_SET_CONTEXT_REG_END 0x000a400 +#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 +#define PACKET3_SET_RESOURCE_INDIRECT 0x74 +#define PACKET3_SET_SH_REG 0x76 +#define PACKET3_SET_SH_REG_START 0x00002c00 +#define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG_OFFSET 0x77 +#define PACKET3_ME_WRITE 0x7A +#define PACKET3_SCRATCH_RAM_WRITE 0x7D +#define PACKET3_SCRATCH_RAM_READ 0x7E +#define PACKET3_CE_WRITE 0x7F +#define PACKET3_LOAD_CONST_RAM 0x80 +#define PACKET3_WRITE_CONST_RAM 0x81 +#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 +#define PACKET3_DUMP_CONST_RAM 0x83 +#define PACKET3_INCREMENT_CE_COUNTER 0x84 +#define PACKET3_INCREMENT_DE_COUNTER 0x85 +#define PACKET3_WAIT_ON_CE_COUNTER 0x86 +#define PACKET3_WAIT_ON_DE_COUNTER 0x87 +#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 +#define PACKET3_SET_CE_DE_COUNTERS 0x89 +#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A +#define PACKET3_SWITCH_BUFFER 0x8B +#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) +#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) +#define PACKET3_SEM_SEL_WAIT (0x7 << 29) + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 8fae3d4a2360..db0f36846661 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -268,7 +268,7 @@ static int si_ih_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs si_ih_ip_funcs = { +static const struct amd_ip_funcs si_ih_ip_funcs = { .name = "si_ih", .early_init = si_ih_early_init, .late_init = NULL, @@ -297,3 +297,11 @@ static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev) adev->irq.ih_funcs = &si_ih_funcs; } +const struct amdgpu_ip_block_version si_ih_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &si_ih_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.h b/drivers/gpu/drm/amd/amdgpu/si_ih.h index f3e3a954369c..42e64a53e24f 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.h @@ -24,6 +24,6 @@ #ifndef __SI_IH_H__ #define __SI_IH_H__ -extern const struct amd_ip_funcs si_ih_ip_funcs; +extern const struct amdgpu_ip_block_version si_ih_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index b4ea229bb449..52b71ee58793 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -455,7 +455,7 @@ static int tonga_ih_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs tonga_ih_ip_funcs = { +static const struct amd_ip_funcs tonga_ih_ip_funcs = { .name = "tonga_ih", .early_init = tonga_ih_early_init, .late_init = NULL, @@ -487,3 +487,11 @@ static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev) adev->irq.ih_funcs = &tonga_ih_funcs; } +const struct amdgpu_ip_block_version tonga_ih_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &tonga_ih_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h index 7392d70fa4a7..499027eee5c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h @@ -24,6 +24,6 @@ #ifndef __TONGA_IH_H__ #define __TONGA_IH_H__ -extern const struct amd_ip_funcs tonga_ih_ip_funcs; +extern const struct amdgpu_ip_block_version tonga_ih_ip_block; -#endif /* __CZ_IH_H__ */ +#endif /* __TONGA_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index f6c941550b8f..96444e4d862a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -36,13 +36,17 @@ #include "bif/bif_4_1_d.h" +#include "smu/smu_7_0_1_d.h" +#include "smu/smu_7_0_1_sh_mask.h" + static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); static void uvd_v4_2_init_cg(struct amdgpu_device *adev); static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v4_2_start(struct amdgpu_device *adev); static void uvd_v4_2_stop(struct amdgpu_device *adev); - +static int uvd_v4_2_set_clockgating_state(void *handle, + enum amd_clockgating_state state); /** * uvd_v4_2_ring_get_rptr - get read pointer * @@ -116,8 +120,7 @@ static int uvd_v4_2_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); return r; } @@ -152,9 +155,9 @@ static int uvd_v4_2_hw_init(void *handle) uint32_t tmp; int r; - /* raise clocks while booting up the VCPU */ - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - + uvd_v4_2_init_cg(adev); + uvd_v4_2_set_clockgating_state(adev, AMD_CG_STATE_GATE); + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); r = uvd_v4_2_start(adev); if (r) goto done; @@ -194,8 +197,6 @@ static int uvd_v4_2_hw_init(void *handle) amdgpu_ring_commit(ring); done: - /* lower clocks again */ - amdgpu_asic_set_uvd_clocks(adev, 0, 0); if (!r) DRM_INFO("UVD initialized successfully.\n"); @@ -272,9 +273,6 @@ static int uvd_v4_2_start(struct amdgpu_device *adev) uvd_v4_2_mc_resume(adev); - /* disable clock gating */ - WREG32(mmUVD_CGC_GATE, 0); - /* disable interupt */ WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); @@ -526,20 +524,6 @@ static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, ib->length_dw); } -static unsigned uvd_v4_2_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 4; /* uvd_v4_2_ring_emit_ib */ -} - -static unsigned uvd_v4_2_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 2 + /* uvd_v4_2_ring_emit_hdp_flush */ - 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ - 14; /* uvd_v4_2_ring_emit_fence x1 no user fence */ -} - /** * uvd_v4_2_mc_resume - memory controller programming * @@ -580,8 +564,6 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); - - uvd_v4_2_init_cg(adev); } static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, @@ -591,7 +573,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); - data = 0xfff; + data |= 0xfff; WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); orig = data = RREG32(mmUVD_CGC_CTRL); @@ -615,6 +597,8 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, { u32 tmp, tmp2; + WREG32_FIELD(UVD_CGC_GATE, REGS, 0); + tmp = RREG32(mmUVD_CGC_CTRL); tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | @@ -738,7 +722,7 @@ static int uvd_v4_2_set_powergating_state(void *handle, } } -const struct amd_ip_funcs uvd_v4_2_ip_funcs = { +static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { .name = "uvd_v4_2", .early_init = uvd_v4_2_early_init, .late_init = NULL, @@ -756,10 +740,18 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { }; static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { + .type = AMDGPU_RING_TYPE_UVD, + .align_mask = 0xf, + .nop = PACKET0(mmUVD_NO_OP, 0), .get_rptr = uvd_v4_2_ring_get_rptr, .get_wptr = uvd_v4_2_ring_get_wptr, .set_wptr = uvd_v4_2_ring_set_wptr, .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = + 2 + /* uvd_v4_2_ring_emit_hdp_flush */ + 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ + 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ + .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ .emit_ib = uvd_v4_2_ring_emit_ib, .emit_fence = uvd_v4_2_ring_emit_fence, .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, @@ -770,8 +762,6 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, - .get_emit_ib_size = uvd_v4_2_ring_get_emit_ib_size, - .get_dma_frame_size = uvd_v4_2_ring_get_dma_frame_size, }; static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) @@ -789,3 +779,12 @@ static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) adev->uvd.irq.num_types = 1; adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; } + +const struct amdgpu_ip_block_version uvd_v4_2_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 4, + .minor = 2, + .rev = 0, + .funcs = &uvd_v4_2_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h index 0a615dd50840..8a0444bb8b95 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h @@ -24,6 +24,6 @@ #ifndef __UVD_V4_2_H__ #define __UVD_V4_2_H__ -extern const struct amd_ip_funcs uvd_v4_2_ip_funcs; +extern const struct amdgpu_ip_block_version uvd_v4_2_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 400c16fe579e..a79e283590fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -33,12 +33,17 @@ #include "oss/oss_2_0_sh_mask.h" #include "bif/bif_5_0_d.h" #include "vi.h" +#include "smu/smu_7_1_2_d.h" +#include "smu/smu_7_1_2_sh_mask.h" static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v5_0_start(struct amdgpu_device *adev); static void uvd_v5_0_stop(struct amdgpu_device *adev); - +static int uvd_v5_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state); +static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, + bool enable); /** * uvd_v5_0_ring_get_rptr - get read pointer * @@ -112,8 +117,7 @@ static int uvd_v5_0_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); return r; } @@ -148,9 +152,6 @@ static int uvd_v5_0_hw_init(void *handle) uint32_t tmp; int r; - /* raise clocks while booting up the VCPU */ - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - r = uvd_v5_0_start(adev); if (r) goto done; @@ -188,11 +189,7 @@ static int uvd_v5_0_hw_init(void *handle) amdgpu_ring_write(ring, 3); amdgpu_ring_commit(ring); - done: - /* lower clocks again */ - amdgpu_asic_set_uvd_clocks(adev, 0, 0); - if (!r) DRM_INFO("UVD initialized successfully.\n"); @@ -225,6 +222,7 @@ static int uvd_v5_0_suspend(void *handle) r = uvd_v5_0_hw_fini(adev); if (r) return r; + uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); r = amdgpu_uvd_suspend(adev); if (r) @@ -312,8 +310,9 @@ static int uvd_v5_0_start(struct amdgpu_device *adev) uvd_v5_0_mc_resume(adev); - /* disable clock gating */ - WREG32(mmUVD_CGC_GATE, 0); + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); + uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); + uvd_v5_0_enable_mgcg(adev, true); /* disable interupt */ WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); @@ -577,20 +576,6 @@ static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, ib->length_dw); } -static unsigned uvd_v5_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 6; /* uvd_v5_0_ring_emit_ib */ -} - -static unsigned uvd_v5_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 2 + /* uvd_v5_0_ring_emit_hdp_flush */ - 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ - 14; /* uvd_v5_0_ring_emit_fence x1 no user fence */ -} - static bool uvd_v5_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -641,16 +626,12 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) +static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) { - uint32_t data, data1, data2, suvd_flags; + uint32_t data1, data3, suvd_flags; - data = RREG32(mmUVD_CGC_CTRL); data1 = RREG32(mmUVD_SUVD_CGC_GATE); - data2 = RREG32(mmUVD_SUVD_CGC_CTRL); - - data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | - UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + data3 = RREG32(mmUVD_CGC_GATE); suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | UVD_SUVD_CGC_GATE__SIT_MASK | @@ -658,6 +639,51 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_GATE__SCM_MASK | UVD_SUVD_CGC_GATE__SDB_MASK; + if (enable) { + data3 |= (UVD_CGC_GATE__SYS_MASK | + UVD_CGC_GATE__UDEC_MASK | + UVD_CGC_GATE__MPEG2_MASK | + UVD_CGC_GATE__RBC_MASK | + UVD_CGC_GATE__LMI_MC_MASK | + UVD_CGC_GATE__IDCT_MASK | + UVD_CGC_GATE__MPRD_MASK | + UVD_CGC_GATE__MPC_MASK | + UVD_CGC_GATE__LBSI_MASK | + UVD_CGC_GATE__LRBBM_MASK | + UVD_CGC_GATE__UDEC_RE_MASK | + UVD_CGC_GATE__UDEC_CM_MASK | + UVD_CGC_GATE__UDEC_IT_MASK | + UVD_CGC_GATE__UDEC_DB_MASK | + UVD_CGC_GATE__UDEC_MP_MASK | + UVD_CGC_GATE__WCB_MASK | + UVD_CGC_GATE__JPEG_MASK | + UVD_CGC_GATE__SCPU_MASK); + /* only in pg enabled, we can gate clock to vcpu*/ + if (adev->pg_flags & AMD_PG_SUPPORT_UVD) + data3 |= UVD_CGC_GATE__VCPU_MASK; + data3 &= ~UVD_CGC_GATE__REGS_MASK; + data1 |= suvd_flags; + } else { + data3 = 0; + data1 = 0; + } + + WREG32(mmUVD_SUVD_CGC_GATE, data1); + WREG32(mmUVD_CGC_GATE, data3); +} + +static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data2; + + data = RREG32(mmUVD_CGC_CTRL); + data2 = RREG32(mmUVD_SUVD_CGC_CTRL); + + + data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | + UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); @@ -688,11 +714,8 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); - data1 |= suvd_flags; WREG32(mmUVD_CGC_CTRL, data); - WREG32(mmUVD_CGC_GATE, 0); - WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32(mmUVD_SUVD_CGC_CTRL, data2); } @@ -737,6 +760,32 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) } #endif +static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data |= 0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } else { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data &= ~0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } +} + static int uvd_v5_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { @@ -752,17 +801,18 @@ static int uvd_v5_0_set_clockgating_state(void *handle, curstate = state; if (enable) { - /* disable HW gating and enable Sw gating */ - uvd_v5_0_set_sw_clock_gating(adev); - } else { /* wait for STATUS to clear */ if (uvd_v5_0_wait_for_idle(handle)) return -EBUSY; + uvd_v5_0_enable_clock_gating(adev, true); /* enable HW gates because UVD is idle */ /* uvd_v5_0_set_hw_clock_gating(adev); */ + } else { + uvd_v5_0_enable_clock_gating(adev, false); } + uvd_v5_0_set_sw_clock_gating(adev); return 0; } @@ -789,7 +839,7 @@ static int uvd_v5_0_set_powergating_state(void *handle, } } -const struct amd_ip_funcs uvd_v5_0_ip_funcs = { +static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { .name = "uvd_v5_0", .early_init = uvd_v5_0_early_init, .late_init = NULL, @@ -807,10 +857,18 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { }; static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_UVD, + .align_mask = 0xf, + .nop = PACKET0(mmUVD_NO_OP, 0), .get_rptr = uvd_v5_0_ring_get_rptr, .get_wptr = uvd_v5_0_ring_get_wptr, .set_wptr = uvd_v5_0_ring_set_wptr, .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = + 2 + /* uvd_v5_0_ring_emit_hdp_flush */ + 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ + 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ + .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ .emit_ib = uvd_v5_0_ring_emit_ib, .emit_fence = uvd_v5_0_ring_emit_fence, .emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush, @@ -821,8 +879,6 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, - .get_emit_ib_size = uvd_v5_0_ring_get_emit_ib_size, - .get_dma_frame_size = uvd_v5_0_ring_get_dma_frame_size, }; static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) @@ -840,3 +896,12 @@ static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) adev->uvd.irq.num_types = 1; adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; } + +const struct amdgpu_ip_block_version uvd_v5_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 5, + .minor = 0, + .rev = 0, + .funcs = &uvd_v5_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h index e3b3c49fa5de..2eaaea793ac5 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h @@ -24,6 +24,6 @@ #ifndef __UVD_V5_0_H__ #define __UVD_V5_0_H__ -extern const struct amd_ip_funcs uvd_v5_0_ip_funcs; +extern const struct amdgpu_ip_block_version uvd_v5_0_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index ab3df6d75656..ba0bbf7138dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -42,6 +42,10 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v6_0_start(struct amdgpu_device *adev); static void uvd_v6_0_stop(struct amdgpu_device *adev); static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); +static int uvd_v6_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state); +static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, + bool enable); /** * uvd_v6_0_ring_get_rptr - get read pointer @@ -116,8 +120,7 @@ static int uvd_v6_0_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); return r; } @@ -394,11 +397,11 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) lmi_swap_cntl = 0; mp_swap_cntl = 0; + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); + uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); + uvd_v6_0_enable_mgcg(adev, true); uvd_v6_0_mc_resume(adev); - /* disable clock gating */ - WREG32_FIELD(UVD_CGC_CTRL, DYN_CLOCK_MODE, 0); - /* disable interupt */ WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); @@ -725,31 +728,6 @@ static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0xE); } -static unsigned uvd_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 8; /* uvd_v6_0_ring_emit_ib */ -} - -static unsigned uvd_v6_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 2 + /* uvd_v6_0_ring_emit_hdp_flush */ - 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ - 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ - 14; /* uvd_v6_0_ring_emit_fence x1 no user fence */ -} - -static unsigned uvd_v6_0_ring_get_dma_frame_size_vm(struct amdgpu_ring *ring) -{ - return - 2 + /* uvd_v6_0_ring_emit_hdp_flush */ - 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ - 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ - 20 + /* uvd_v6_0_ring_emit_vm_flush */ - 14 + 14; /* uvd_v6_0_ring_emit_fence x2 vm fence */ -} - static bool uvd_v6_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -862,22 +840,72 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, return 0; } +static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) +{ + uint32_t data1, data3; + + data1 = RREG32(mmUVD_SUVD_CGC_GATE); + data3 = RREG32(mmUVD_CGC_GATE); + + data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | + UVD_SUVD_CGC_GATE__SIT_MASK | + UVD_SUVD_CGC_GATE__SMP_MASK | + UVD_SUVD_CGC_GATE__SCM_MASK | + UVD_SUVD_CGC_GATE__SDB_MASK | + UVD_SUVD_CGC_GATE__SRE_H264_MASK | + UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | + UVD_SUVD_CGC_GATE__SIT_H264_MASK | + UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | + UVD_SUVD_CGC_GATE__SCM_H264_MASK | + UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | + UVD_SUVD_CGC_GATE__SDB_H264_MASK | + UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; + + if (enable) { + data3 |= (UVD_CGC_GATE__SYS_MASK | + UVD_CGC_GATE__UDEC_MASK | + UVD_CGC_GATE__MPEG2_MASK | + UVD_CGC_GATE__RBC_MASK | + UVD_CGC_GATE__LMI_MC_MASK | + UVD_CGC_GATE__LMI_UMC_MASK | + UVD_CGC_GATE__IDCT_MASK | + UVD_CGC_GATE__MPRD_MASK | + UVD_CGC_GATE__MPC_MASK | + UVD_CGC_GATE__LBSI_MASK | + UVD_CGC_GATE__LRBBM_MASK | + UVD_CGC_GATE__UDEC_RE_MASK | + UVD_CGC_GATE__UDEC_CM_MASK | + UVD_CGC_GATE__UDEC_IT_MASK | + UVD_CGC_GATE__UDEC_DB_MASK | + UVD_CGC_GATE__UDEC_MP_MASK | + UVD_CGC_GATE__WCB_MASK | + UVD_CGC_GATE__JPEG_MASK | + UVD_CGC_GATE__SCPU_MASK | + UVD_CGC_GATE__JPEG2_MASK); + /* only in pg enabled, we can gate clock to vcpu*/ + if (adev->pg_flags & AMD_PG_SUPPORT_UVD) + data3 |= UVD_CGC_GATE__VCPU_MASK; + + data3 &= ~UVD_CGC_GATE__REGS_MASK; + } else { + data3 = 0; + } + + WREG32(mmUVD_SUVD_CGC_GATE, data1); + WREG32(mmUVD_CGC_GATE, data3); +} + static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) { - uint32_t data, data1, data2, suvd_flags; + uint32_t data, data2; data = RREG32(mmUVD_CGC_CTRL); - data1 = RREG32(mmUVD_SUVD_CGC_GATE); data2 = RREG32(mmUVD_SUVD_CGC_CTRL); + data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); - suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | - UVD_SUVD_CGC_GATE__SIT_MASK | - UVD_SUVD_CGC_GATE__SMP_MASK | - UVD_SUVD_CGC_GATE__SCM_MASK | - UVD_SUVD_CGC_GATE__SDB_MASK; data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | @@ -910,11 +938,8 @@ static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); - data1 |= suvd_flags; WREG32(mmUVD_CGC_CTRL, data); - WREG32(mmUVD_CGC_GATE, 0); - WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32(mmUVD_SUVD_CGC_CTRL, data2); } @@ -961,44 +986,53 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) } #endif -static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable) +static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, + bool enable) { - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); + u32 orig, data; - if (enable) - tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); - else - tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data |= 0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); + orig = data = RREG32(mmUVD_CGC_CTRL); + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } else { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data &= ~0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } } static int uvd_v6_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - if (adev->asic_type == CHIP_FIJI || - adev->asic_type == CHIP_POLARIS10) - uvd_v6_set_bypass_mode(adev, state == AMD_CG_STATE_GATE ? true : false); + bool enable = (state == AMD_CG_STATE_GATE) ? true : false; if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; - if (state == AMD_CG_STATE_GATE) { - /* disable HW gating and enable Sw gating */ - uvd_v6_0_set_sw_clock_gating(adev); - } else { + if (enable) { /* wait for STATUS to clear */ if (uvd_v6_0_wait_for_idle(handle)) return -EBUSY; - + uvd_v6_0_enable_clock_gating(adev, true); /* enable HW gates because UVD is idle */ /* uvd_v6_0_set_hw_clock_gating(adev); */ + } else { + /* disable HW gating and enable Sw gating */ + uvd_v6_0_enable_clock_gating(adev, false); } - + uvd_v6_0_set_sw_clock_gating(adev); return 0; } @@ -1027,7 +1061,7 @@ static int uvd_v6_0_set_powergating_state(void *handle, } } -const struct amd_ip_funcs uvd_v6_0_ip_funcs = { +static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { .name = "uvd_v6_0", .early_init = uvd_v6_0_early_init, .late_init = NULL, @@ -1048,10 +1082,19 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = { }; static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { + .type = AMDGPU_RING_TYPE_UVD, + .align_mask = 0xf, + .nop = PACKET0(mmUVD_NO_OP, 0), .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = + 2 + /* uvd_v6_0_ring_emit_hdp_flush */ + 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ + 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ + 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */ + .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ .emit_ib = uvd_v6_0_ring_emit_ib, .emit_fence = uvd_v6_0_ring_emit_fence, .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, @@ -1062,15 +1105,22 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, - .get_emit_ib_size = uvd_v6_0_ring_get_emit_ib_size, - .get_dma_frame_size = uvd_v6_0_ring_get_dma_frame_size, }; static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_UVD, + .align_mask = 0xf, + .nop = PACKET0(mmUVD_NO_OP, 0), .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, - .parse_cs = NULL, + .emit_frame_size = + 2 + /* uvd_v6_0_ring_emit_hdp_flush */ + 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ + 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ + 20 + /* uvd_v6_0_ring_emit_vm_flush */ + 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */ + .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ .emit_ib = uvd_v6_0_ring_emit_ib, .emit_fence = uvd_v6_0_ring_emit_fence, .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, @@ -1083,8 +1133,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, - .get_emit_ib_size = uvd_v6_0_ring_get_emit_ib_size, - .get_dma_frame_size = uvd_v6_0_ring_get_dma_frame_size_vm, }; static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) @@ -1108,3 +1156,30 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) adev->uvd.irq.num_types = 1; adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs; } + +const struct amdgpu_ip_block_version uvd_v6_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 6, + .minor = 0, + .rev = 0, + .funcs = &uvd_v6_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version uvd_v6_2_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 6, + .minor = 2, + .rev = 0, + .funcs = &uvd_v6_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version uvd_v6_3_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 6, + .minor = 3, + .rev = 0, + .funcs = &uvd_v6_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h index 6b92a2352986..d3d48c6428cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h @@ -24,6 +24,8 @@ #ifndef __UVD_V6_0_H__ #define __UVD_V6_0_H__ -extern const struct amd_ip_funcs uvd_v6_0_ip_funcs; +extern const struct amdgpu_ip_block_version uvd_v6_0_ip_block; +extern const struct amdgpu_ip_block_version uvd_v6_2_ip_block; +extern const struct amdgpu_ip_block_version uvd_v6_3_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 76e64ad04a53..38ed903dd6f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -224,8 +224,8 @@ static int vce_v2_0_sw_init(void *handle) for (i = 0; i < adev->vce.num_rings; i++) { ring = &adev->vce.ring[i]; sprintf(ring->name, "vce%d", i); - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, - &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); + r = amdgpu_ring_init(adev, ring, 512, + &adev->vce.irq, 0); if (r) return r; } @@ -592,7 +592,7 @@ static int vce_v2_0_set_powergating_state(void *handle, return vce_v2_0_start(adev); } -const struct amd_ip_funcs vce_v2_0_ip_funcs = { +static const struct amd_ip_funcs vce_v2_0_ip_funcs = { .name = "vce_v2_0", .early_init = vce_v2_0_early_init, .late_init = NULL, @@ -610,10 +610,15 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { }; static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_VCE, + .align_mask = 0xf, + .nop = VCE_CMD_NO_OP, .get_rptr = vce_v2_0_ring_get_rptr, .get_wptr = vce_v2_0_ring_get_wptr, .set_wptr = vce_v2_0_ring_set_wptr, .parse_cs = amdgpu_vce_ring_parse_cs, + .emit_frame_size = 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */ + .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */ .emit_ib = amdgpu_vce_ring_emit_ib, .emit_fence = amdgpu_vce_ring_emit_fence, .test_ring = amdgpu_vce_ring_test_ring, @@ -622,8 +627,6 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_vce_ring_begin_use, .end_use = amdgpu_vce_ring_end_use, - .get_emit_ib_size = amdgpu_vce_ring_get_emit_ib_size, - .get_dma_frame_size = amdgpu_vce_ring_get_dma_frame_size, }; static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev) @@ -644,3 +647,12 @@ static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev) adev->vce.irq.num_types = 1; adev->vce.irq.funcs = &vce_v2_0_irq_funcs; }; + +const struct amdgpu_ip_block_version vce_v2_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vce_v2_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h index 0d2ae8a01acd..4d15167654a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h @@ -24,6 +24,6 @@ #ifndef __VCE_V2_0_H__ #define __VCE_V2_0_H__ -extern const struct amd_ip_funcs vce_v2_0_ip_funcs; +extern const struct amdgpu_ip_block_version vce_v2_0_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 6feed726e299..6b3293a1c7b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -134,7 +134,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev, accessible but the firmware will throttle the clocks on the fly as necessary. */ - if (gated) { + if (!gated) { data = RREG32(mmVCE_CLOCK_GATING_B); data |= 0x1ff; data &= ~0xef0000; @@ -395,8 +395,7 @@ static int vce_v3_0_sw_init(void *handle) for (i = 0; i < adev->vce.num_rings; i++) { ring = &adev->vce.ring[i]; sprintf(ring->name, "vce%d", i); - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, - &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); if (r) return r; } @@ -814,28 +813,7 @@ static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, seq); } -static unsigned vce_v3_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 5; /* vce_v3_0_ring_emit_ib */ -} - -static unsigned vce_v3_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 4 + /* vce_v3_0_emit_pipeline_sync */ - 6; /* amdgpu_vce_ring_emit_fence x1 no user fence */ -} - -static unsigned vce_v3_0_ring_get_dma_frame_size_vm(struct amdgpu_ring *ring) -{ - return - 6 + /* vce_v3_0_emit_vm_flush */ - 4 + /* vce_v3_0_emit_pipeline_sync */ - 6 + 6; /* amdgpu_vce_ring_emit_fence x2 vm fence */ -} - -const struct amd_ip_funcs vce_v3_0_ip_funcs = { +static const struct amd_ip_funcs vce_v3_0_ip_funcs = { .name = "vce_v3_0", .early_init = vce_v3_0_early_init, .late_init = NULL, @@ -856,10 +834,17 @@ const struct amd_ip_funcs vce_v3_0_ip_funcs = { }; static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { + .type = AMDGPU_RING_TYPE_VCE, + .align_mask = 0xf, + .nop = VCE_CMD_NO_OP, .get_rptr = vce_v3_0_ring_get_rptr, .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, .parse_cs = amdgpu_vce_ring_parse_cs, + .emit_frame_size = + 4 + /* vce_v3_0_emit_pipeline_sync */ + 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */ + .emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */ .emit_ib = amdgpu_vce_ring_emit_ib, .emit_fence = amdgpu_vce_ring_emit_fence, .test_ring = amdgpu_vce_ring_test_ring, @@ -868,15 +853,21 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_vce_ring_begin_use, .end_use = amdgpu_vce_ring_end_use, - .get_emit_ib_size = vce_v3_0_ring_get_emit_ib_size, - .get_dma_frame_size = vce_v3_0_ring_get_dma_frame_size, }; static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCE, + .align_mask = 0xf, + .nop = VCE_CMD_NO_OP, .get_rptr = vce_v3_0_ring_get_rptr, .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, - .parse_cs = NULL, + .parse_cs = amdgpu_vce_ring_parse_cs_vm, + .emit_frame_size = + 6 + /* vce_v3_0_emit_vm_flush */ + 4 + /* vce_v3_0_emit_pipeline_sync */ + 6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */ + .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */ .emit_ib = vce_v3_0_ring_emit_ib, .emit_vm_flush = vce_v3_0_emit_vm_flush, .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync, @@ -887,8 +878,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_vce_ring_begin_use, .end_use = amdgpu_vce_ring_end_use, - .get_emit_ib_size = vce_v3_0_ring_get_emit_ib_size, - .get_dma_frame_size = vce_v3_0_ring_get_dma_frame_size_vm, }; static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) @@ -916,3 +905,30 @@ static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev) adev->vce.irq.num_types = 1; adev->vce.irq.funcs = &vce_v3_0_irq_funcs; }; + +const struct amdgpu_ip_block_version vce_v3_0_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &vce_v3_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version vce_v3_1_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 3, + .minor = 1, + .rev = 0, + .funcs = &vce_v3_0_ip_funcs, +}; + +const struct amdgpu_ip_block_version vce_v3_4_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 3, + .minor = 4, + .rev = 0, + .funcs = &vce_v3_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h index b45af65da81f..08b908c7de0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h @@ -24,6 +24,8 @@ #ifndef __VCE_V3_0_H__ #define __VCE_V3_0_H__ -extern const struct amd_ip_funcs vce_v3_0_ip_funcs; +extern const struct amdgpu_ip_block_version vce_v3_0_ip_block; +extern const struct amdgpu_ip_block_version vce_v3_1_ip_block; +extern const struct amdgpu_ip_block_version vce_v3_4_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 7c13090df7c0..9f771f4ffcb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -80,7 +80,9 @@ #include "dce_virtual.h" MODULE_FIRMWARE("amdgpu/topaz_smc.bin"); +MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin"); MODULE_FIRMWARE("amdgpu/tonga_smc.bin"); +MODULE_FIRMWARE("amdgpu/tonga_k_smc.bin"); MODULE_FIRMWARE("amdgpu/fiji_smc.bin"); MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin"); @@ -121,8 +123,8 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) u32 r; spin_lock_irqsave(&adev->smc_idx_lock, flags); - WREG32(mmSMC_IND_INDEX_0, (reg)); - r = RREG32(mmSMC_IND_DATA_0); + WREG32(mmSMC_IND_INDEX_11, (reg)); + r = RREG32(mmSMC_IND_DATA_11); spin_unlock_irqrestore(&adev->smc_idx_lock, flags); return r; } @@ -132,8 +134,8 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) unsigned long flags; spin_lock_irqsave(&adev->smc_idx_lock, flags); - WREG32(mmSMC_IND_INDEX_0, (reg)); - WREG32(mmSMC_IND_DATA_0, (v)); + WREG32(mmSMC_IND_INDEX_11, (reg)); + WREG32(mmSMC_IND_DATA_11, (v)); spin_unlock_irqrestore(&adev->smc_idx_lock, flags); } @@ -437,12 +439,12 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, /* take the smc lock since we are using the smc index */ spin_lock_irqsave(&adev->smc_idx_lock, flags); /* set rom index to 0 */ - WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); - WREG32(mmSMC_IND_DATA_0, 0); + WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); + WREG32(mmSMC_IND_DATA_11, 0); /* set index to data for continous read */ - WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); + WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); for (i = 0; i < length_dw; i++) - dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); + dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); spin_unlock_irqrestore(&adev->smc_idx_lock, flags); return true; @@ -556,21 +558,100 @@ static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {mmPA_SC_RASTER_CONFIG_1, false, true}, }; -static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, - u32 sh_num, u32 reg_offset) -{ - uint32_t val; +static uint32_t vi_get_register_value(struct amdgpu_device *adev, + bool indexed, u32 se_num, + u32 sh_num, u32 reg_offset) +{ + if (indexed) { + uint32_t val; + unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; + unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; + + switch (reg_offset) { + case mmCC_RB_BACKEND_DISABLE: + return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; + case mmGC_USER_RB_BACKEND_DISABLE: + return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; + case mmPA_SC_RASTER_CONFIG: + return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; + case mmPA_SC_RASTER_CONFIG_1: + return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; + } - mutex_lock(&adev->grbm_idx_mutex); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); + mutex_lock(&adev->grbm_idx_mutex); + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); - val = RREG32(reg_offset); + val = RREG32(reg_offset); - if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); - mutex_unlock(&adev->grbm_idx_mutex); - return val; + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + return val; + } else { + unsigned idx; + + switch (reg_offset) { + case mmGB_ADDR_CONFIG: + return adev->gfx.config.gb_addr_config; + case mmMC_ARB_RAMCFG: + return adev->gfx.config.mc_arb_ramcfg; + case mmGB_TILE_MODE0: + case mmGB_TILE_MODE1: + case mmGB_TILE_MODE2: + case mmGB_TILE_MODE3: + case mmGB_TILE_MODE4: + case mmGB_TILE_MODE5: + case mmGB_TILE_MODE6: + case mmGB_TILE_MODE7: + case mmGB_TILE_MODE8: + case mmGB_TILE_MODE9: + case mmGB_TILE_MODE10: + case mmGB_TILE_MODE11: + case mmGB_TILE_MODE12: + case mmGB_TILE_MODE13: + case mmGB_TILE_MODE14: + case mmGB_TILE_MODE15: + case mmGB_TILE_MODE16: + case mmGB_TILE_MODE17: + case mmGB_TILE_MODE18: + case mmGB_TILE_MODE19: + case mmGB_TILE_MODE20: + case mmGB_TILE_MODE21: + case mmGB_TILE_MODE22: + case mmGB_TILE_MODE23: + case mmGB_TILE_MODE24: + case mmGB_TILE_MODE25: + case mmGB_TILE_MODE26: + case mmGB_TILE_MODE27: + case mmGB_TILE_MODE28: + case mmGB_TILE_MODE29: + case mmGB_TILE_MODE30: + case mmGB_TILE_MODE31: + idx = (reg_offset - mmGB_TILE_MODE0); + return adev->gfx.config.tile_mode_array[idx]; + case mmGB_MACROTILE_MODE0: + case mmGB_MACROTILE_MODE1: + case mmGB_MACROTILE_MODE2: + case mmGB_MACROTILE_MODE3: + case mmGB_MACROTILE_MODE4: + case mmGB_MACROTILE_MODE5: + case mmGB_MACROTILE_MODE6: + case mmGB_MACROTILE_MODE7: + case mmGB_MACROTILE_MODE8: + case mmGB_MACROTILE_MODE9: + case mmGB_MACROTILE_MODE10: + case mmGB_MACROTILE_MODE11: + case mmGB_MACROTILE_MODE12: + case mmGB_MACROTILE_MODE13: + case mmGB_MACROTILE_MODE14: + case mmGB_MACROTILE_MODE15: + idx = (reg_offset - mmGB_MACROTILE_MODE0); + return adev->gfx.config.macrotile_mode_array[idx]; + default: + return RREG32(reg_offset); + } + } } static int vi_read_register(struct amdgpu_device *adev, u32 se_num, @@ -605,10 +686,9 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, if (reg_offset != asic_register_entry->reg_offset) continue; if (!asic_register_entry->untouched) - *value = asic_register_entry->grbm_indexed ? - vi_read_indexed_register(adev, se_num, - sh_num, reg_offset) : - RREG32(reg_offset); + *value = vi_get_register_value(adev, + asic_register_entry->grbm_indexed, + se_num, sh_num, reg_offset); return 0; } } @@ -618,10 +698,9 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, continue; if (!vi_allowed_read_registers[i].untouched) - *value = vi_allowed_read_registers[i].grbm_indexed ? - vi_read_indexed_register(adev, se_num, - sh_num, reg_offset) : - RREG32(reg_offset); + *value = vi_get_register_value(adev, + vi_allowed_read_registers[i].grbm_indexed, + se_num, sh_num, reg_offset); return 0; } return -EINVAL; @@ -652,18 +731,6 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) return -EINVAL; } -static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) -{ - u32 tmp = RREG32(mmBIOS_SCRATCH_3); - - if (hung) - tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; - else - tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; - - WREG32(mmBIOS_SCRATCH_3, tmp); -} - /** * vi_asic_reset - soft reset GPU * @@ -677,11 +744,11 @@ static int vi_asic_reset(struct amdgpu_device *adev) { int r; - vi_set_bios_scratch_engine_hung(adev, true); + amdgpu_atombios_scratch_regs_engine_hung(adev, true); r = vi_gpu_pci_config_reset(adev); - vi_set_bios_scratch_engine_hung(adev, false); + amdgpu_atombios_scratch_regs_engine_hung(adev, false); return r; } @@ -781,734 +848,6 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, WREG32(mmBIF_DOORBELL_APER_EN, tmp); } -/* topaz has no DCE, UVD, VCE */ -static const struct amdgpu_ip_block_version topaz_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 4, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 4, - .rev = 0, - .funcs = &iceland_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 1, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 4, - .rev = 0, - .funcs = &sdma_v2_4_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version topaz_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 7, - .minor = 4, - .rev = 0, - .funcs = &gmc_v7_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 2, - .minor = 4, - .rev = 0, - .funcs = &iceland_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 1, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 1, - .minor = 0, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 2, - .minor = 4, - .rev = 0, - .funcs = &sdma_v2_4_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version tonga_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gmc_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &tonga_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 1, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 10, - .minor = 0, - .rev = 0, - .funcs = &dce_v10_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &sdma_v3_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 5, - .minor = 0, - .rev = 0, - .funcs = &uvd_v5_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &vce_v3_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version tonga_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gmc_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &tonga_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 1, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 10, - .minor = 0, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &sdma_v3_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 5, - .minor = 0, - .rev = 0, - .funcs = &uvd_v5_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &vce_v3_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version fiji_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 8, - .minor = 5, - .rev = 0, - .funcs = &gmc_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &tonga_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 1, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 10, - .minor = 1, - .rev = 0, - .funcs = &dce_v10_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &sdma_v3_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &uvd_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &vce_v3_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version fiji_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 8, - .minor = 5, - .rev = 0, - .funcs = &gmc_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &tonga_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 1, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 10, - .minor = 1, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &sdma_v3_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &uvd_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &vce_v3_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 8, - .minor = 1, - .rev = 0, - .funcs = &gmc_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 3, - .minor = 1, - .rev = 0, - .funcs = &tonga_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 2, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 11, - .minor = 2, - .rev = 0, - .funcs = &dce_v11_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 3, - .minor = 1, - .rev = 0, - .funcs = &sdma_v3_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 6, - .minor = 3, - .rev = 0, - .funcs = &uvd_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 3, - .minor = 4, - .rev = 0, - .funcs = &vce_v3_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version polaris11_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 8, - .minor = 1, - .rev = 0, - .funcs = &gmc_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 3, - .minor = 1, - .rev = 0, - .funcs = &tonga_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 7, - .minor = 2, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 11, - .minor = 2, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 3, - .minor = 1, - .rev = 0, - .funcs = &sdma_v3_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 6, - .minor = 3, - .rev = 0, - .funcs = &uvd_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 3, - .minor = 4, - .rev = 0, - .funcs = &vce_v3_0_ip_funcs, - }, -}; - -static const struct amdgpu_ip_block_version cz_ip_blocks[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gmc_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &cz_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 11, - .minor = 0, - .rev = 0, - .funcs = &dce_v11_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &sdma_v3_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &uvd_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &vce_v3_0_ip_funcs, - }, -#if defined(CONFIG_DRM_AMD_ACP) - { - .type = AMD_IP_BLOCK_TYPE_ACP, - .major = 2, - .minor = 2, - .rev = 0, - .funcs = &acp_ip_funcs, - }, -#endif -}; - -static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] = -{ - /* ORDER MATTERS! */ - { - .type = AMD_IP_BLOCK_TYPE_COMMON, - .major = 2, - .minor = 0, - .rev = 0, - .funcs = &vi_common_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GMC, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gmc_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_IH, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &cz_ih_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SMC, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &amdgpu_pp_ip_funcs - }, - { - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 11, - .minor = 0, - .rev = 0, - .funcs = &dce_virtual_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_GFX, - .major = 8, - .minor = 0, - .rev = 0, - .funcs = &gfx_v8_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_SDMA, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &sdma_v3_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_UVD, - .major = 6, - .minor = 0, - .rev = 0, - .funcs = &uvd_v6_0_ip_funcs, - }, - { - .type = AMD_IP_BLOCK_TYPE_VCE, - .major = 3, - .minor = 0, - .rev = 0, - .funcs = &vce_v3_0_ip_funcs, - }, -#if defined(CONFIG_DRM_AMD_ACP) - { - .type = AMD_IP_BLOCK_TYPE_ACP, - .major = 2, - .minor = 2, - .rev = 0, - .funcs = &acp_ip_funcs, - }, -#endif -}; - -int vi_set_ip_blocks(struct amdgpu_device *adev) -{ - if (adev->enable_virtual_display) { - switch (adev->asic_type) { - case CHIP_TOPAZ: - adev->ip_blocks = topaz_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks_vd); - break; - case CHIP_FIJI: - adev->ip_blocks = fiji_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd); - break; - case CHIP_TONGA: - adev->ip_blocks = tonga_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd); - break; - case CHIP_POLARIS11: - case CHIP_POLARIS10: - adev->ip_blocks = polaris11_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd); - break; - - case CHIP_CARRIZO: - case CHIP_STONEY: - adev->ip_blocks = cz_ip_blocks_vd; - adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd); - break; - default: - /* FIXME: not supported yet */ - return -EINVAL; - } - } else { - switch (adev->asic_type) { - case CHIP_TOPAZ: - adev->ip_blocks = topaz_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks); - break; - case CHIP_FIJI: - adev->ip_blocks = fiji_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks); - break; - case CHIP_TONGA: - adev->ip_blocks = tonga_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); - break; - case CHIP_POLARIS11: - case CHIP_POLARIS10: - adev->ip_blocks = polaris11_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks); - break; - case CHIP_CARRIZO: - case CHIP_STONEY: - adev->ip_blocks = cz_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks); - break; - default: - /* FIXME: not supported yet */ - return -EINVAL; - } - } - - return 0; -} - #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 @@ -1587,22 +926,25 @@ static int vi_common_early_init(void *handle) AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_ROM_MGCG | AMD_CG_SUPPORT_MC_MGCG | - AMD_CG_SUPPORT_MC_LS; + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_UVD_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x3c; break; case CHIP_TONGA: adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; - adev->pg_flags = 0; + adev->pg_flags = AMD_PG_SUPPORT_UVD; adev->external_rev_id = adev->rev_id + 0x14; break; case CHIP_POLARIS11: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | + AMD_CG_SUPPORT_VCE_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x5A; break; case CHIP_POLARIS10: - adev->cg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | + AMD_CG_SUPPORT_VCE_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x50; break; @@ -1908,7 +1250,7 @@ static int vi_common_set_powergating_state(void *handle, return 0; } -const struct amd_ip_funcs vi_common_ip_funcs = { +static const struct amd_ip_funcs vi_common_ip_funcs = { .name = "vi_common", .early_init = vi_common_early_init, .late_init = NULL, @@ -1925,3 +1267,110 @@ const struct amd_ip_funcs vi_common_ip_funcs = { .set_powergating_state = vi_common_set_powergating_state, }; +static const struct amdgpu_ip_block_version vi_common_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &vi_common_ip_funcs, +}; + +int vi_set_ip_blocks(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_TOPAZ: + /* topaz has no DCE, UVD, VCE */ + amdgpu_ip_block_add(adev, &vi_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block); + amdgpu_ip_block_add(adev, &iceland_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block); + break; + case CHIP_FIJI: + amdgpu_ip_block_add(adev, &vi_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block); + amdgpu_ip_block_add(adev, &tonga_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v10_1_ip_block); + amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); + amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); + amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); + break; + case CHIP_TONGA: + amdgpu_ip_block_add(adev, &vi_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); + amdgpu_ip_block_add(adev, &tonga_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v10_0_ip_block); + amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); + amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block); + amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); + break; + case CHIP_POLARIS11: + case CHIP_POLARIS10: + amdgpu_ip_block_add(adev, &vi_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block); + amdgpu_ip_block_add(adev, &tonga_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v11_2_ip_block); + amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block); + amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block); + amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); + break; + case CHIP_CARRIZO: + amdgpu_ip_block_add(adev, &vi_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); + amdgpu_ip_block_add(adev, &cz_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); + amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); + amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); + amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); + amdgpu_ip_block_add(adev, &vce_v3_1_ip_block); +#if defined(CONFIG_DRM_AMD_ACP) + amdgpu_ip_block_add(adev, &acp_ip_block); +#endif + break; + case CHIP_STONEY: + amdgpu_ip_block_add(adev, &vi_common_ip_block); + amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); + amdgpu_ip_block_add(adev, &cz_ih_ip_block); + amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) + amdgpu_ip_block_add(adev, &dce_virtual_ip_block); + else + amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); + amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block); + amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); + amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block); + amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); +#if defined(CONFIG_DRM_AMD_ACP) + amdgpu_ip_block_add(adev, &acp_ip_block); +#endif + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h index 502094042462..575d7aed5d32 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.h +++ b/drivers/gpu/drm/amd/amdgpu/vi.h @@ -24,8 +24,6 @@ #ifndef __VI_H__ #define __VI_H__ -extern const struct amd_ip_funcs vi_common_ip_funcs; - void vi_srbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); int vi_set_ip_blocks(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index bec8125bceb0..d1986276dbbd 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -84,6 +84,29 @@ enum amd_powergating_state { AMD_PG_STATE_UNGATE, }; +struct amd_vce_state { + /* vce clocks */ + u32 evclk; + u32 ecclk; + /* gpu clocks */ + u32 sclk; + u32 mclk; + u8 clk_idx; + u8 pstate; +}; + + +#define AMD_MAX_VCE_LEVELS 6 + +enum amd_vce_level { + AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ + AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ + AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ + AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ + AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ + AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ +}; + /* CG flags */ #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h new file mode 100644 index 000000000000..7138fbf7256a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h @@ -0,0 +1,661 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_3_0_D_H +#define BIF_3_0_D_H + +#define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C +#define ixPB0_DFT_JIT_INJ_REG0 0x13000 +#define ixPB0_DFT_JIT_INJ_REG1 0x13004 +#define ixPB0_DFT_JIT_INJ_REG2 0x13008 +#define ixPB0_GLB_CTRL_REG0 0x10004 +#define ixPB0_GLB_CTRL_REG1 0x10008 +#define ixPB0_GLB_CTRL_REG2 0x1000C +#define ixPB0_GLB_CTRL_REG3 0x10010 +#define ixPB0_GLB_CTRL_REG4 0x10014 +#define ixPB0_GLB_CTRL_REG5 0x10018 +#define ixPB0_GLB_OVRD_REG0 0x10030 +#define ixPB0_GLB_OVRD_REG1 0x10034 +#define ixPB0_GLB_OVRD_REG2 0x10038 +#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C +#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020 +#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024 +#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028 +#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C +#define ixPB0_HW_DEBUG 0x12004 +#define ixPB0_PIF_CNTL 0x0010 +#define ixPB0_PIF_CNTL2 0x0014 +#define ixPB0_PIF_HW_DEBUG 0x0002 +#define ixPB0_PIF_PAIRING 0x0011 +#define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020 +#define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032 +#define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021 +#define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033 +#define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034 +#define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035 +#define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036 +#define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037 +#define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022 +#define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023 +#define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024 +#define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025 +#define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026 +#define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027 +#define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030 +#define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031 +#define ixPB0_PIF_PWRDOWN_0 0x0012 +#define ixPB0_PIF_PWRDOWN_1 0x0013 +#define ixPB0_PIF_PWRDOWN_2 0x0017 +#define ixPB0_PIF_PWRDOWN_3 0x0018 +#define ixPB0_PIF_SC_CTL 0x0016 +#define ixPB0_PIF_SCRATCH 0x0001 +#define ixPB0_PIF_SEQ_STATUS_0 0x0028 +#define ixPB0_PIF_SEQ_STATUS_10 0x003A +#define ixPB0_PIF_SEQ_STATUS_1 0x0029 +#define ixPB0_PIF_SEQ_STATUS_11 0x003B +#define ixPB0_PIF_SEQ_STATUS_12 0x003C +#define ixPB0_PIF_SEQ_STATUS_13 0x003D +#define ixPB0_PIF_SEQ_STATUS_14 0x003E +#define ixPB0_PIF_SEQ_STATUS_15 0x003F +#define ixPB0_PIF_SEQ_STATUS_2 0x002A +#define ixPB0_PIF_SEQ_STATUS_3 0x002B +#define ixPB0_PIF_SEQ_STATUS_4 0x002C +#define ixPB0_PIF_SEQ_STATUS_5 0x002D +#define ixPB0_PIF_SEQ_STATUS_6 0x002E +#define ixPB0_PIF_SEQ_STATUS_7 0x002F +#define ixPB0_PIF_SEQ_STATUS_8 0x0038 +#define ixPB0_PIF_SEQ_STATUS_9 0x0039 +#define ixPB0_PIF_TXPHYSTATUS 0x0015 +#define ixPB0_PLL_LC0_CTRL_REG0 0x14480 +#define ixPB0_PLL_LC0_OVRD_REG0 0x14490 +#define ixPB0_PLL_LC0_OVRD_REG1 0x14494 +#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 +#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 +#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 +#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C +#define ixPB0_PLL_RO0_CTRL_REG0 0x14440 +#define ixPB0_PLL_RO0_OVRD_REG0 0x14450 +#define ixPB0_PLL_RO0_OVRD_REG1 0x14454 +#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 +#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 +#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 +#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C +#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000 +#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010 +#define ixPB0_RX_GLB_CTRL_REG0 0x16000 +#define ixPB0_RX_GLB_CTRL_REG1 0x16004 +#define ixPB0_RX_GLB_CTRL_REG2 0x16008 +#define ixPB0_RX_GLB_CTRL_REG3 0x1600C +#define ixPB0_RX_GLB_CTRL_REG4 0x16010 +#define ixPB0_RX_GLB_CTRL_REG5 0x16014 +#define ixPB0_RX_GLB_CTRL_REG6 0x16018 +#define ixPB0_RX_GLB_CTRL_REG7 0x1601C +#define ixPB0_RX_GLB_CTRL_REG8 0x16020 +#define ixPB0_RX_GLB_OVRD_REG0 0x16030 +#define ixPB0_RX_GLB_OVRD_REG1 0x16034 +#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 +#define ixPB0_RX_LANE0_CTRL_REG0 0x16440 +#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 +#define ixPB0_RX_LANE10_CTRL_REG0 0x17500 +#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 +#define ixPB0_RX_LANE11_CTRL_REG0 0x17600 +#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 +#define ixPB0_RX_LANE12_CTRL_REG0 0x17840 +#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 +#define ixPB0_RX_LANE13_CTRL_REG0 0x17880 +#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 +#define ixPB0_RX_LANE14_CTRL_REG0 0x17900 +#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 +#define ixPB0_RX_LANE15_CTRL_REG0 0x17A00 +#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 +#define ixPB0_RX_LANE1_CTRL_REG0 0x16480 +#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 +#define ixPB0_RX_LANE2_CTRL_REG0 0x16500 +#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 +#define ixPB0_RX_LANE3_CTRL_REG0 0x16600 +#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 +#define ixPB0_RX_LANE4_CTRL_REG0 0x16800 +#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 +#define ixPB0_RX_LANE5_CTRL_REG0 0x16880 +#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 +#define ixPB0_RX_LANE6_CTRL_REG0 0x16900 +#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 +#define ixPB0_RX_LANE7_CTRL_REG0 0x16A00 +#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 +#define ixPB0_RX_LANE8_CTRL_REG0 0x17440 +#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 +#define ixPB0_RX_LANE9_CTRL_REG0 0x17480 +#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 +#define ixPB0_STRAP_GLB_REG0 0x12020 +#define ixPB0_STRAP_PLL_REG0 0x12030 +#define ixPB0_STRAP_RX_REG0 0x12028 +#define ixPB0_STRAP_RX_REG1 0x1202C +#define ixPB0_STRAP_TX_REG0 0x12024 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 +#define ixPB0_TX_GLB_CTRL_REG0 0x18000 +#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004 +#define ixPB0_TX_GLB_OVRD_REG0 0x18030 +#define ixPB0_TX_GLB_OVRD_REG1 0x18034 +#define ixPB0_TX_GLB_OVRD_REG2 0x18038 +#define ixPB0_TX_GLB_OVRD_REG3 0x1803C +#define ixPB0_TX_GLB_OVRD_REG4 0x18040 +#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 +#define ixPB0_TX_LANE0_CTRL_REG0 0x18440 +#define ixPB0_TX_LANE0_OVRD_REG0 0x18444 +#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 +#define ixPB0_TX_LANE10_CTRL_REG0 0x19500 +#define ixPB0_TX_LANE10_OVRD_REG0 0x19504 +#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 +#define ixPB0_TX_LANE11_CTRL_REG0 0x19600 +#define ixPB0_TX_LANE11_OVRD_REG0 0x19604 +#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 +#define ixPB0_TX_LANE12_CTRL_REG0 0x19840 +#define ixPB0_TX_LANE12_OVRD_REG0 0x19844 +#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 +#define ixPB0_TX_LANE13_CTRL_REG0 0x19880 +#define ixPB0_TX_LANE13_OVRD_REG0 0x19884 +#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 +#define ixPB0_TX_LANE14_CTRL_REG0 0x19900 +#define ixPB0_TX_LANE14_OVRD_REG0 0x19904 +#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 +#define ixPB0_TX_LANE15_CTRL_REG0 0x19A00 +#define ixPB0_TX_LANE15_OVRD_REG0 0x19A04 +#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 +#define ixPB0_TX_LANE1_CTRL_REG0 0x18480 +#define ixPB0_TX_LANE1_OVRD_REG0 0x18484 +#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 +#define ixPB0_TX_LANE2_CTRL_REG0 0x18500 +#define ixPB0_TX_LANE2_OVRD_REG0 0x18504 +#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 +#define ixPB0_TX_LANE3_CTRL_REG0 0x18600 +#define ixPB0_TX_LANE3_OVRD_REG0 0x18604 +#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 +#define ixPB0_TX_LANE4_CTRL_REG0 0x18840 +#define ixPB0_TX_LANE4_OVRD_REG0 0x18844 +#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 +#define ixPB0_TX_LANE5_CTRL_REG0 0x18880 +#define ixPB0_TX_LANE5_OVRD_REG0 0x18884 +#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 +#define ixPB0_TX_LANE6_CTRL_REG0 0x18900 +#define ixPB0_TX_LANE6_OVRD_REG0 0x18904 +#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 +#define ixPB0_TX_LANE7_CTRL_REG0 0x18A00 +#define ixPB0_TX_LANE7_OVRD_REG0 0x18A04 +#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 +#define ixPB0_TX_LANE8_CTRL_REG0 0x19440 +#define ixPB0_TX_LANE8_OVRD_REG0 0x19444 +#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 +#define ixPB0_TX_LANE9_CTRL_REG0 0x19480 +#define ixPB0_TX_LANE9_OVRD_REG0 0x19484 +#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 +#define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C +#define ixPB1_DFT_JIT_INJ_REG0 0x13000 +#define ixPB1_DFT_JIT_INJ_REG1 0x13004 +#define ixPB1_DFT_JIT_INJ_REG2 0x13008 +#define ixPB1_GLB_CTRL_REG0 0x10004 +#define ixPB1_GLB_CTRL_REG1 0x10008 +#define ixPB1_GLB_CTRL_REG2 0x1000C +#define ixPB1_GLB_CTRL_REG3 0x10010 +#define ixPB1_GLB_CTRL_REG4 0x10014 +#define ixPB1_GLB_CTRL_REG5 0x10018 +#define ixPB1_GLB_OVRD_REG0 0x10030 +#define ixPB1_GLB_OVRD_REG1 0x10034 +#define ixPB1_GLB_OVRD_REG2 0x10038 +#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x1001C +#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x10020 +#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x10024 +#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x10028 +#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x1002C +#define ixPB1_HW_DEBUG 0x12004 +#define ixPB1_PIF_CNTL 0x0010 +#define ixPB1_PIF_CNTL2 0x0014 +#define ixPB1_PIF_HW_DEBUG 0x0002 +#define ixPB1_PIF_PAIRING 0x0011 +#define ixPB1_PIF_PDNB_OVERRIDE_0 0x0020 +#define ixPB1_PIF_PDNB_OVERRIDE_10 0x0032 +#define ixPB1_PIF_PDNB_OVERRIDE_1 0x0021 +#define ixPB1_PIF_PDNB_OVERRIDE_11 0x0033 +#define ixPB1_PIF_PDNB_OVERRIDE_12 0x0034 +#define ixPB1_PIF_PDNB_OVERRIDE_13 0x0035 +#define ixPB1_PIF_PDNB_OVERRIDE_14 0x0036 +#define ixPB1_PIF_PDNB_OVERRIDE_15 0x0037 +#define ixPB1_PIF_PDNB_OVERRIDE_2 0x0022 +#define ixPB1_PIF_PDNB_OVERRIDE_3 0x0023 +#define ixPB1_PIF_PDNB_OVERRIDE_4 0x0024 +#define ixPB1_PIF_PDNB_OVERRIDE_5 0x0025 +#define ixPB1_PIF_PDNB_OVERRIDE_6 0x0026 +#define ixPB1_PIF_PDNB_OVERRIDE_7 0x0027 +#define ixPB1_PIF_PDNB_OVERRIDE_8 0x0030 +#define ixPB1_PIF_PDNB_OVERRIDE_9 0x0031 +#define ixPB1_PIF_PWRDOWN_0 0x0012 +#define ixPB1_PIF_PWRDOWN_1 0x0013 +#define ixPB1_PIF_PWRDOWN_2 0x0017 +#define ixPB1_PIF_PWRDOWN_3 0x0018 +#define ixPB1_PIF_SC_CTL 0x0016 +#define ixPB1_PIF_SCRATCH 0x0001 +#define ixPB1_PIF_SEQ_STATUS_0 0x0028 +#define ixPB1_PIF_SEQ_STATUS_10 0x003A +#define ixPB1_PIF_SEQ_STATUS_1 0x0029 +#define ixPB1_PIF_SEQ_STATUS_11 0x003B +#define ixPB1_PIF_SEQ_STATUS_12 0x003C +#define ixPB1_PIF_SEQ_STATUS_13 0x003D +#define ixPB1_PIF_SEQ_STATUS_14 0x003E +#define ixPB1_PIF_SEQ_STATUS_15 0x003F +#define ixPB1_PIF_SEQ_STATUS_2 0x002A +#define ixPB1_PIF_SEQ_STATUS_3 0x002B +#define ixPB1_PIF_SEQ_STATUS_4 0x002C +#define ixPB1_PIF_SEQ_STATUS_5 0x002D +#define ixPB1_PIF_SEQ_STATUS_6 0x002E +#define ixPB1_PIF_SEQ_STATUS_7 0x002F +#define ixPB1_PIF_SEQ_STATUS_8 0x0038 +#define ixPB1_PIF_SEQ_STATUS_9 0x0039 +#define ixPB1_PIF_TXPHYSTATUS 0x0015 +#define ixPB1_PLL_LC0_CTRL_REG0 0x14480 +#define ixPB1_PLL_LC0_OVRD_REG0 0x14490 +#define ixPB1_PLL_LC0_OVRD_REG1 0x14494 +#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 +#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 +#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 +#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C +#define ixPB1_PLL_RO0_CTRL_REG0 0x14440 +#define ixPB1_PLL_RO0_OVRD_REG0 0x14450 +#define ixPB1_PLL_RO0_OVRD_REG1 0x14454 +#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 +#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 +#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 +#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C +#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x14000 +#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x14010 +#define ixPB1_RX_GLB_CTRL_REG0 0x16000 +#define ixPB1_RX_GLB_CTRL_REG1 0x16004 +#define ixPB1_RX_GLB_CTRL_REG2 0x16008 +#define ixPB1_RX_GLB_CTRL_REG3 0x1600C +#define ixPB1_RX_GLB_CTRL_REG4 0x16010 +#define ixPB1_RX_GLB_CTRL_REG5 0x16014 +#define ixPB1_RX_GLB_CTRL_REG6 0x16018 +#define ixPB1_RX_GLB_CTRL_REG7 0x1601C +#define ixPB1_RX_GLB_CTRL_REG8 0x16020 +#define ixPB1_RX_GLB_OVRD_REG0 0x16030 +#define ixPB1_RX_GLB_OVRD_REG1 0x16034 +#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 +#define ixPB1_RX_LANE0_CTRL_REG0 0x16440 +#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 +#define ixPB1_RX_LANE10_CTRL_REG0 0x17500 +#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 +#define ixPB1_RX_LANE11_CTRL_REG0 0x17600 +#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 +#define ixPB1_RX_LANE12_CTRL_REG0 0x17840 +#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 +#define ixPB1_RX_LANE13_CTRL_REG0 0x17880 +#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 +#define ixPB1_RX_LANE14_CTRL_REG0 0x17900 +#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 +#define ixPB1_RX_LANE15_CTRL_REG0 0x17A00 +#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 +#define ixPB1_RX_LANE1_CTRL_REG0 0x16480 +#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 +#define ixPB1_RX_LANE2_CTRL_REG0 0x16500 +#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 +#define ixPB1_RX_LANE3_CTRL_REG0 0x16600 +#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 +#define ixPB1_RX_LANE4_CTRL_REG0 0x16800 +#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 +#define ixPB1_RX_LANE5_CTRL_REG0 0x16880 +#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 +#define ixPB1_RX_LANE6_CTRL_REG0 0x16900 +#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 +#define ixPB1_RX_LANE7_CTRL_REG0 0x16A00 +#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 +#define ixPB1_RX_LANE8_CTRL_REG0 0x17440 +#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 +#define ixPB1_RX_LANE9_CTRL_REG0 0x17480 +#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 +#define ixPB1_STRAP_GLB_REG0 0x12020 +#define ixPB1_STRAP_PLL_REG0 0x12030 +#define ixPB1_STRAP_RX_REG0 0x12028 +#define ixPB1_STRAP_RX_REG1 0x1202C +#define ixPB1_STRAP_TX_REG0 0x12024 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 +#define ixPB1_TX_GLB_CTRL_REG0 0x18000 +#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x18004 +#define ixPB1_TX_GLB_OVRD_REG0 0x18030 +#define ixPB1_TX_GLB_OVRD_REG1 0x18034 +#define ixPB1_TX_GLB_OVRD_REG2 0x18038 +#define ixPB1_TX_GLB_OVRD_REG3 0x1803C +#define ixPB1_TX_GLB_OVRD_REG4 0x18040 +#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 +#define ixPB1_TX_LANE0_CTRL_REG0 0x18440 +#define ixPB1_TX_LANE0_OVRD_REG0 0x18444 +#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 +#define ixPB1_TX_LANE10_CTRL_REG0 0x19500 +#define ixPB1_TX_LANE10_OVRD_REG0 0x19504 +#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 +#define ixPB1_TX_LANE11_CTRL_REG0 0x19600 +#define ixPB1_TX_LANE11_OVRD_REG0 0x19604 +#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 +#define ixPB1_TX_LANE12_CTRL_REG0 0x19840 +#define ixPB1_TX_LANE12_OVRD_REG0 0x19844 +#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 +#define ixPB1_TX_LANE13_CTRL_REG0 0x19880 +#define ixPB1_TX_LANE13_OVRD_REG0 0x19884 +#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 +#define ixPB1_TX_LANE14_CTRL_REG0 0x19900 +#define ixPB1_TX_LANE14_OVRD_REG0 0x19904 +#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 +#define ixPB1_TX_LANE15_CTRL_REG0 0x19A00 +#define ixPB1_TX_LANE15_OVRD_REG0 0x19A04 +#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 +#define ixPB1_TX_LANE1_CTRL_REG0 0x18480 +#define ixPB1_TX_LANE1_OVRD_REG0 0x18484 +#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 +#define ixPB1_TX_LANE2_CTRL_REG0 0x18500 +#define ixPB1_TX_LANE2_OVRD_REG0 0x18504 +#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 +#define ixPB1_TX_LANE3_CTRL_REG0 0x18600 +#define ixPB1_TX_LANE3_OVRD_REG0 0x18604 +#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 +#define ixPB1_TX_LANE4_CTRL_REG0 0x18840 +#define ixPB1_TX_LANE4_OVRD_REG0 0x18844 +#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 +#define ixPB1_TX_LANE5_CTRL_REG0 0x18880 +#define ixPB1_TX_LANE5_OVRD_REG0 0x18884 +#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 +#define ixPB1_TX_LANE6_CTRL_REG0 0x18900 +#define ixPB1_TX_LANE6_OVRD_REG0 0x18904 +#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 +#define ixPB1_TX_LANE7_CTRL_REG0 0x18A00 +#define ixPB1_TX_LANE7_OVRD_REG0 0x18A04 +#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 +#define ixPB1_TX_LANE8_CTRL_REG0 0x19440 +#define ixPB1_TX_LANE8_OVRD_REG0 0x19444 +#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 +#define ixPB1_TX_LANE9_CTRL_REG0 0x19480 +#define ixPB1_TX_LANE9_OVRD_REG0 0x19484 +#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 +#define ixPCIE_BUS_CNTL 0x0021 +#define ixPCIE_CFG_CNTL 0x003C +#define ixPCIE_CI_CNTL 0x0020 +#define ixPCIE_CNTL 0x0010 +#define ixPCIE_CNTL2 0x001C +#define ixPCIE_CONFIG_CNTL 0x0011 +#define ixPCIE_DEBUG_CNTL 0x0012 +#define ixPCIE_ERR_CNTL 0x006A +#define ixPCIE_F0_DPA_CAP 0x00E0 +#define ixPCIE_F0_DPA_CNTL 0x00E5 +#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x00E4 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x00E7 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x00E8 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x00E9 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x00EA +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x00EB +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x00EC +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x00ED +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x00EE +#define ixPCIE_FC_CPL 0x0062 +#define ixPCIE_FC_NP 0x0061 +#define ixPCIE_FC_P 0x0060 +#define ixPCIE_HW_DEBUG 0x0002 +#define ixPCIE_I2C_REG_ADDR_EXPAND 0x003A +#define ixPCIE_I2C_REG_DATA 0x003B +#define ixPCIE_INT_CNTL 0x001A +#define ixPCIE_INT_STATUS 0x001B +#define ixPCIE_LC_BEST_EQ_SETTINGS 0x00B9 +#define ixPCIE_LC_BW_CHANGE_CNTL 0x00B2 +#define ixPCIE_LC_CDR_CNTL 0x00B3 +#define ixPCIE_LC_CNTL 0x00A0 +#define ixPCIE_LC_CNTL2 0x00B1 +#define ixPCIE_LC_CNTL3 0x00B5 +#define ixPCIE_LC_CNTL4 0x00B6 +#define ixPCIE_LC_CNTL5 0x00B7 +#define ixPCIE_LC_FORCE_COEFF 0x00B8 +#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x00BA +#define ixPCIE_LC_LANE_CNTL 0x00B4 +#define ixPCIE_LC_LINK_WIDTH_CNTL 0x00A2 +#define ixPCIE_LC_N_FTS_CNTL 0x00A3 +#define ixPCIE_LC_SPEED_CNTL 0x00A4 +#define ixPCIE_LC_STATE0 0x00A5 +#define ixPCIE_LC_STATE10 0x0026 +#define ixPCIE_LC_STATE1 0x00A6 +#define ixPCIE_LC_STATE11 0x0027 +#define ixPCIE_LC_STATE2 0x00A7 +#define ixPCIE_LC_STATE3 0x00A8 +#define ixPCIE_LC_STATE4 0x00A9 +#define ixPCIE_LC_STATE5 0x00AA +#define ixPCIE_LC_STATE6 0x0022 +#define ixPCIE_LC_STATE7 0x0023 +#define ixPCIE_LC_STATE8 0x0024 +#define ixPCIE_LC_STATE9 0x0025 +#define ixPCIE_LC_STATUS1 0x0028 +#define ixPCIE_LC_STATUS2 0x0029 +#define ixPCIE_LC_TRAINING_CNTL 0x00A1 +#define ixPCIE_P_BUF_STATUS 0x0041 +#define ixPCIE_P_CNTL 0x0040 +#define ixPCIE_P_DECODER_STATUS 0x0042 +#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x0093 +#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x0094 +#define ixPCIE_PERF_CNTL_MST_C_CLK 0x0087 +#define ixPCIE_PERF_CNTL_MST_R_CLK 0x0084 +#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x0090 +#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x008A +#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x008D +#define ixPCIE_PERF_CNTL_TXCLK 0x0081 +#define ixPCIE_PERF_CNTL_TXCLK2 0x0095 +#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x0088 +#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x0085 +#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x0091 +#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x008B +#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x008E +#define ixPCIE_PERF_COUNT0_TXCLK 0x0082 +#define ixPCIE_PERF_COUNT0_TXCLK2 0x0096 +#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x0089 +#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x0086 +#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x0092 +#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x008C +#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x008F +#define ixPCIE_PERF_COUNT1_TXCLK 0x0083 +#define ixPCIE_PERF_COUNT1_TXCLK2 0x0097 +#define ixPCIE_PERF_COUNT_CNTL 0x0080 +#define ixPCIEP_HW_DEBUG 0x0002 +#define ixPCIE_P_MISC_STATUS 0x0043 +#define ixPCIEP_PORT_CNTL 0x0010 +#define ixPCIE_P_PORT_LANE_STATUS 0x0050 +#define ixPCIE_PRBS_CLR 0x00C8 +#define ixPCIE_PRBS_ERRCNT_0 0x00D0 +#define ixPCIE_PRBS_ERRCNT_10 0x00DA +#define ixPCIE_PRBS_ERRCNT_1 0x00D1 +#define ixPCIE_PRBS_ERRCNT_11 0x00DB +#define ixPCIE_PRBS_ERRCNT_12 0x00DC +#define ixPCIE_PRBS_ERRCNT_13 0x00DD +#define ixPCIE_PRBS_ERRCNT_14 0x00DE +#define ixPCIE_PRBS_ERRCNT_15 0x00DF +#define ixPCIE_PRBS_ERRCNT_2 0x00D2 +#define ixPCIE_PRBS_ERRCNT_3 0x00D3 +#define ixPCIE_PRBS_ERRCNT_4 0x00D4 +#define ixPCIE_PRBS_ERRCNT_5 0x00D5 +#define ixPCIE_PRBS_ERRCNT_6 0x00D6 +#define ixPCIE_PRBS_ERRCNT_7 0x00D7 +#define ixPCIE_PRBS_ERRCNT_8 0x00D8 +#define ixPCIE_PRBS_ERRCNT_9 0x00D9 +#define ixPCIE_PRBS_FREERUN 0x00CB +#define ixPCIE_PRBS_HI_BITCNT 0x00CF +#define ixPCIE_PRBS_LO_BITCNT 0x00CE +#define ixPCIE_PRBS_MISC 0x00CC +#define ixPCIE_PRBS_STATUS1 0x00C9 +#define ixPCIE_PRBS_STATUS2 0x00CA +#define ixPCIE_PRBS_USER_PATTERN 0x00CD +#define ixPCIE_P_RCV_L0S_FTS_DET 0x0050 +#define ixPCIEP_RESERVED 0x0000 +#define ixPCIEP_SCRATCH 0x0001 +#define ixPCIEP_STRAP_LC 0x00C0 +#define ixPCIEP_STRAP_MISC 0x00C1 +#define ixPCIE_RESERVED 0x0000 +#define ixPCIE_RX_CNTL 0x0070 +#define ixPCIE_RX_CNTL2 0x001D +#define ixPCIE_RX_CNTL3 0x0074 +#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x0082 +#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x0081 +#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x0080 +#define ixPCIE_RX_EXPECTED_SEQNUM 0x0071 +#define ixPCIE_RX_LAST_TLP0 0x0031 +#define ixPCIE_RX_LAST_TLP1 0x0032 +#define ixPCIE_RX_LAST_TLP2 0x0033 +#define ixPCIE_RX_LAST_TLP3 0x0034 +#define ixPCIE_RX_NUM_NAK 0x000E +#define ixPCIE_RX_NUM_NAK_GENERATED 0x000F +#define ixPCIE_RX_VENDOR_SPECIFIC 0x0072 +#define ixPCIE_SCRATCH 0x0001 +#define ixPCIE_STRAP_F0 0x00B0 +#define ixPCIE_STRAP_F1 0x00B1 +#define ixPCIE_STRAP_F2 0x00B2 +#define ixPCIE_STRAP_F3 0x00B3 +#define ixPCIE_STRAP_F4 0x00B4 +#define ixPCIE_STRAP_F5 0x00B5 +#define ixPCIE_STRAP_F6 0x00B6 +#define ixPCIE_STRAP_F7 0x00B7 +#define ixPCIE_STRAP_I2C_BD 0x00C4 +#define ixPCIE_STRAP_MISC 0x00C0 +#define ixPCIE_STRAP_MISC2 0x00C1 +#define ixPCIE_STRAP_PI 0x00C2 +#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x0026 +#define ixPCIE_TX_CNTL 0x0020 +#define ixPCIE_TX_CREDITS_ADVT_CPL 0x0032 +#define ixPCIE_TX_CREDITS_ADVT_NP 0x0031 +#define ixPCIE_TX_CREDITS_ADVT_P 0x0030 +#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x0037 +#define ixPCIE_TX_CREDITS_INIT_CPL 0x0035 +#define ixPCIE_TX_CREDITS_INIT_NP 0x0034 +#define ixPCIE_TX_CREDITS_INIT_P 0x0033 +#define ixPCIE_TX_CREDITS_STATUS 0x0036 +#define ixPCIE_TX_LAST_TLP0 0x0035 +#define ixPCIE_TX_LAST_TLP1 0x0036 +#define ixPCIE_TX_LAST_TLP2 0x0037 +#define ixPCIE_TX_LAST_TLP3 0x0038 +#define ixPCIE_TX_REPLAY 0x0025 +#define ixPCIE_TX_REQUESTER_ID 0x0021 +#define ixPCIE_TX_REQUEST_NUM_CNTL 0x0023 +#define ixPCIE_TX_SEQ 0x0024 +#define ixPCIE_TX_VENDOR_SPECIFIC 0x0022 +#define ixPCIE_WPR_CNTL 0x0030 +#define mmBACO_CNTL 0x14E5 +#define mmBF_ANA_ISO_CNTL 0x14C7 +#define mmBIF_BACO_DEBUG 0x14DF +#define mmBIF_BACO_DEBUG_LATCH 0x14DC +#define mmBIF_BACO_MSIC 0x14DE +#define mmBIF_BUSNUM_CNTL1 0x1525 +#define mmBIF_BUSNUM_CNTL2 0x152B +#define mmBIF_BUSNUM_LIST0 0x1526 +#define mmBIF_BUSNUM_LIST1 0x1527 +#define mmBIF_BUSY_DELAY_CNTR 0x1529 +#define mmBIF_CLK_PDWN_DELAY_TIMER 0x151F +#define mmBIF_DEBUG_CNTL 0x151C +#define mmBIF_DEBUG_MUX 0x151D +#define mmBIF_DEBUG_OUT 0x151E +#define mmBIF_DEVFUNCNUM_LIST0 0x14E8 +#define mmBIF_DEVFUNCNUM_LIST1 0x14E7 +#define mmBIF_FB_EN 0x1524 +#define mmBIF_FEATURES_CONTROL_MISC 0x14C2 +#define mmBIF_PERFCOUNTER0_RESULT 0x152D +#define mmBIF_PERFCOUNTER1_RESULT 0x152E +#define mmBIF_PERFMON_CNTL 0x152C +#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x152F +#define mmBIF_RESET_EN 0x1511 +#define mmBIF_SCRATCH0 0x150E +#define mmBIF_SCRATCH1 0x150F +#define mmBIF_SSA_DISP_LOWER 0x14D2 +#define mmBIF_SSA_DISP_UPPER 0x14D3 +#define mmBIF_SSA_GFX0_LOWER 0x14CA +#define mmBIF_SSA_GFX0_UPPER 0x14CB +#define mmBIF_SSA_GFX1_LOWER 0x14CC +#define mmBIF_SSA_GFX1_UPPER 0x14CD +#define mmBIF_SSA_GFX2_LOWER 0x14CE +#define mmBIF_SSA_GFX2_UPPER 0x14CF +#define mmBIF_SSA_GFX3_LOWER 0x14D0 +#define mmBIF_SSA_GFX3_UPPER 0x14D1 +#define mmBIF_SSA_MC_LOWER 0x14D4 +#define mmBIF_SSA_MC_UPPER 0x14D5 +#define mmBIF_SSA_PWR_STATUS 0x14C8 +#define mmBIF_XDMA_HI 0x14C1 +#define mmBIF_XDMA_LO 0x14C0 +#define mmBIOS_SCRATCH_0 0x05C9 +#define mmBIOS_SCRATCH_10 0x05D3 +#define mmBIOS_SCRATCH_1 0x05CA +#define mmBIOS_SCRATCH_11 0x05D4 +#define mmBIOS_SCRATCH_12 0x05D5 +#define mmBIOS_SCRATCH_13 0x05D6 +#define mmBIOS_SCRATCH_14 0x05D7 +#define mmBIOS_SCRATCH_15 0x05D8 +#define mmBIOS_SCRATCH_2 0x05CB +#define mmBIOS_SCRATCH_3 0x05CC +#define mmBIOS_SCRATCH_4 0x05CD +#define mmBIOS_SCRATCH_5 0x05CE +#define mmBIOS_SCRATCH_6 0x05CF +#define mmBIOS_SCRATCH_7 0x05D0 +#define mmBIOS_SCRATCH_8 0x05D1 +#define mmBIOS_SCRATCH_9 0x05D2 +#define mmBUS_CNTL 0x1508 +#define mmCAPTURE_HOST_BUSNUM 0x153C +#define mmCLKREQB_PAD_CNTL 0x1521 +#define mmCONFIG_APER_SIZE 0x150C +#define mmCONFIG_CNTL 0x1509 +#define mmCONFIG_F0_BASE 0x150B +#define mmCONFIG_MEMSIZE 0x150A +#define mmCONFIG_REG_APER_SIZE 0x150D +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 +#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 +#define mmHOST_BUSNUM 0x153D +#define mmHW_DEBUG 0x1515 +#define mmIMPCTL_RESET 0x14F5 +#define mmINTERRUPT_CNTL 0x151A +#define mmINTERRUPT_CNTL2 0x151B +#define mmMASTER_CREDIT_CNTL 0x1516 +#define mmMM_CFGREGS_CNTL 0x1513 +#define mmMM_DATA 0x0001 +#define mmMM_INDEX 0x0000 +#define mmMM_INDEX_HI 0x0006 +#define mmNEW_REFCLKB_TIMER 0x14EA +#define mmNEW_REFCLKB_TIMER_1 0x14E9 +#define mmPCIE_DATA 0x000D +#define mmPCIE_INDEX 0x000C +#define mmPEER0_FB_OFFSET_HI 0x14F3 +#define mmPEER0_FB_OFFSET_LO 0x14F2 +#define mmPEER1_FB_OFFSET_HI 0x14F1 +#define mmPEER1_FB_OFFSET_LO 0x14F0 +#define mmPEER2_FB_OFFSET_HI 0x14EF +#define mmPEER2_FB_OFFSET_LO 0x14EE +#define mmPEER3_FB_OFFSET_HI 0x14ED +#define mmPEER3_FB_OFFSET_LO 0x14EC +#define mmPEER_REG_RANGE0 0x153E +#define mmPEER_REG_RANGE1 0x153F +#define mmSLAVE_HANG_ERROR 0x153B +#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 +#define mmSLAVE_REQ_CREDIT_CNTL 0x1517 +#define mmSMBCLK_PAD_CNTL 0x1523 +#define mmSMBDAT_PAD_CNTL 0x1522 +#define mmSMBUS_BACO_DUMMY 0x14C6 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h new file mode 100644 index 000000000000..e94445acf3c6 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h @@ -0,0 +1,8127 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_3_0_SH_MASK_H +#define BIF_3_0_SH_MASK_H + +#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L +#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 +#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L +#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 +#define BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BACO_CNTL__BACO_EN__SHIFT 0x00000000 +#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L +#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 +#define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L +#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 +#define BACO_CNTL__BACO_MODE_MASK 0x00000040L +#define BACO_CNTL__BACO_MODE__SHIFT 0x00000006 +#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x00000003 +#define BACO_CNTL__BACO_RESET_EN_MASK 0x00000010L +#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x00000004 +#define BACO_CNTL__PWRGOOD_BF_MASK 0x00000200L +#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x00000009 +#define BACO_CNTL__PWRGOOD_DVO_MASK 0x00001000L +#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0x0000000c +#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x00000400L +#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0x0000000a +#define BACO_CNTL__PWRGOOD_MEM_MASK 0x00000800L +#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0x0000000b +#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000100L +#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x00000008 +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x00000001L +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x00000000 +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x00000002L +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x00000001 +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x00000001L +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x00000000 +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x00000001L +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x00000000 +#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x00000001L +#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x00000000 +#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0x000000ffL +#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x00000000 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x00000008 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000ffL +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x00000000 +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x00000011 +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x00000010 +#define BIF_BUSNUM_LIST0__ID0_MASK 0x000000ffL +#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x00000000 +#define BIF_BUSNUM_LIST0__ID1_MASK 0x0000ff00L +#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x00000008 +#define BIF_BUSNUM_LIST0__ID2_MASK 0x00ff0000L +#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x00000010 +#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000L +#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x00000018 +#define BIF_BUSNUM_LIST1__ID4_MASK 0x000000ffL +#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x00000000 +#define BIF_BUSNUM_LIST1__ID5_MASK 0x0000ff00L +#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x00000008 +#define BIF_BUSNUM_LIST1__ID6_MASK 0x00ff0000L +#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x00000010 +#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000L +#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x00000018 +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003fL +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x00000000 +#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x000003ffL +#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x00000000 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x00000010L +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x00000004 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x00000020L +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x00000005 +#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x00000001L +#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x00000000 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x00001f00L +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x00000008 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x001f0000L +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x00000010 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x01000000L +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x00000018 +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x00000002L +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x00000001 +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x00000004L +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x00000002 +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x00000008L +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x00000003 +#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x00000080L +#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x00000007 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000L +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x0000001e +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x00000040L +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x00000006 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x0000003fL +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x00000000 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x00003f00L +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x00000008 +#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x0001ffffL +#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x00000000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000ffL +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x00000000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000ff00L +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x00000008 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00ff0000L +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x00000010 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000L +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x00000018 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000ffL +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x00000000 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000ff00L +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x00000008 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00ff0000L +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x00000010 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000L +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x00000018 +#define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_FB_EN__FB_READ_EN__SHIFT 0x00000000 +#define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x00000001 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x00000003 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x00000002 +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x00000100L +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x00000008 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x00000000 +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x00000080L +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x00000007 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x00000005 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x00000006 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x00000001 +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x00000004 +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000 +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000 +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x00000001L +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x00000000 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x00000002L +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x00000001 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x00000004L +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x00000002 +#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x00001f00L +#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000008 +#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x0003e000L +#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000d +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x00000007L +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x00000000 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x00000038L +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x00000003 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x000003c0L +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x00000006 +#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x00400000L +#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x00000016 +#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x00000040L +#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x00000006 +#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x0003f000L +#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0x0000000c +#define BIF_RESET_EN__COR_RESET_EN_MASK 0x00000008L +#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x00000003 +#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0x000c0000L +#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x00000012 +#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x00000080L +#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x00000007 +#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x00800000L +#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x00000017 +#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0x0c000000L +#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x0000001a +#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x01000000L +#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x00000018 +#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000L +#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x0000001c +#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x02000000L +#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x00000019 +#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000L +#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x0000001e +#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x00000200L +#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x00000009 +#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x00000400L +#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0x0000000a +#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x00000800L +#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0x0000000b +#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x00000004L +#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x00000002 +#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x00100000L +#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x00000014 +#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x00200000L +#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x00000015 +#define BIF_RESET_EN__REG_RESET_EN_MASK 0x00000010L +#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x00000004 +#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x00000100L +#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x00000008 +#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x00000002L +#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x00000001 +#define BIF_RESET_EN__STY_RESET_EN_MASK 0x00000020L +#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x00000005 +#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffffL +#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x00000000 +#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffffL +#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x00000000 +#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK 0x0003fffcL +#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x00000002 +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK 0x0003fffcL +#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x00000002 +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK 0x0003fffcL +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x00000002 +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK 0x0003fffcL +#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x00000002 +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK 0x0003fffcL +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x00000002 +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK 0x0003fffcL +#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x00000002 +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK 0x0003fffcL +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x00000002 +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK 0x0003fffcL +#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x00000002 +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK 0x0003fffcL +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x00000002 +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK 0x0003fffcL +#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x00000002 +#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK 0x20000000L +#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x0000001d +#define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK 0x0003fffcL +#define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x00000002 +#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK 0x40000000L +#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT 0x0000001e +#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK 0x80000000L +#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT 0x0000001f +#define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK 0x0003fffcL +#define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x00000002 +#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x00000002L +#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT 0x00000001 +#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK 0x00000001L +#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT 0x00000000 +#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK 0x00000004L +#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x00000002 +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffffL +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x00000000 +#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x0000001f +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffffL +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x00000000 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffffL +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x00000000 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffffL +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x00000000 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffffL +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x00000000 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffffL +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x00000000 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffffL +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x00000000 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffffL +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x00000000 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffffL +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x00000000 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffffL +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x00000000 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffffL +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x00000000 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffffL +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x00000000 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffffL +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x00000000 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffffL +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x00000000 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffffL +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x00000000 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffffL +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x00000000 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffffL +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x00000000 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffffL +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x00000000 +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x00000100L +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x00000008 +#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x00000002L +#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x00000001 +#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x00000001L +#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x00000000 +#define BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x00000004 +#define BUS_CNTL__PMI_INT_DIS_MASK 0x00000020L +#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000005 +#define BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x00000002 +#define BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x00000003 +#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x00000012 +#define BUS_CNTL__SET_AZ_TC_MASK 0x00001c00L +#define BUS_CNTL__SET_AZ_TC__SHIFT 0x0000000a +#define BUS_CNTL__SET_MC_TC_MASK 0x0000e000L +#define BUS_CNTL__SET_MC_TC__SHIFT 0x0000000d +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x00000007 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x00000006 +#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x00000011 +#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x00000010 +#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x00000000 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x00000000 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0x0000000c +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x00000002 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0x0000000b +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x00000001 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x00000009 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x00000005 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x00000006 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x00000007 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x00000008 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x00000003 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0x0000000a +#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffffL +#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x00000000 +#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x00000000 +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x00000002 +#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x00000003 +#define CONFIG_CNTL__VGA_DIS_MASK 0x00000002L +#define CONFIG_CNTL__VGA_DIS__SHIFT 0x00000001 +#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffffL +#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x00000000 +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffffL +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x00000000 +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000fffffL +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x00000000 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x00000000 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x00000000 +#define HOST_BUSNUM__HOST_ID_MASK 0x0000ffffL +#define HOST_BUSNUM__HOST_ID__SHIFT 0x00000000 +#define HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L +#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 +#define HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L +#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 +#define HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L +#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 +#define HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L +#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 +#define HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L +#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 +#define HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L +#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 +#define HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L +#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 +#define HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L +#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 +#define HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L +#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 +#define HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L +#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 +#define HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L +#define HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a +#define HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L +#define HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b +#define HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L +#define HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c +#define HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L +#define HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d +#define HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L +#define HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e +#define HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L +#define HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f +#define HW_DEBUG__HW_16_DEBUG_MASK 0x00010000L +#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x00000010 +#define HW_DEBUG__HW_17_DEBUG_MASK 0x00020000L +#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x00000011 +#define HW_DEBUG__HW_18_DEBUG_MASK 0x00040000L +#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x00000012 +#define HW_DEBUG__HW_19_DEBUG_MASK 0x00080000L +#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x00000013 +#define HW_DEBUG__HW_20_DEBUG_MASK 0x00100000L +#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x00000014 +#define HW_DEBUG__HW_21_DEBUG_MASK 0x00200000L +#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x00000015 +#define HW_DEBUG__HW_22_DEBUG_MASK 0x00400000L +#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x00000016 +#define HW_DEBUG__HW_23_DEBUG_MASK 0x00800000L +#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x00000017 +#define HW_DEBUG__HW_24_DEBUG_MASK 0x01000000L +#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x00000018 +#define HW_DEBUG__HW_25_DEBUG_MASK 0x02000000L +#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x00000019 +#define HW_DEBUG__HW_26_DEBUG_MASK 0x04000000L +#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x0000001a +#define HW_DEBUG__HW_27_DEBUG_MASK 0x08000000L +#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x0000001b +#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000L +#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x0000001c +#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000L +#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x0000001d +#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000L +#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x0000001e +#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000L +#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x0000001f +#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x00000001L +#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x00000000 +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffffL +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x00000000 +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x00001e00L +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x00000009 +#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x00000008 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x00000001 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x00000000 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000f0L +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x00000004 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x00000003 +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x00006000L +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0x0000000d +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x003f0000L +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x00000010 +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x0000003fL +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x00000000 +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x00000000 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x00000008L +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x00000003 +#define MM_DATA__MM_DATA_MASK 0xffffffffL +#define MM_DATA__MM_DATA__SHIFT 0x00000000 +#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffffL +#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x00000000 +#define MM_INDEX__MM_APER_MASK 0x80000000L +#define MM_INDEX__MM_APER__SHIFT 0x0000001f +#define MM_INDEX__MM_OFFSET_MASK 0x7fffffffL +#define MM_INDEX__MM_OFFSET__SHIFT 0x00000000 +#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x000003ffL +#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x00000000 +#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x00000400L +#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0x0000000a +#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x00200000L +#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x00000015 +#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x00000001L +#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x00000000 +#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x001ffffeL +#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x00000001 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x00000001L +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x00000000 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x0000003eL +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x00000001 +#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0x00000f00L +#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x00000008 +#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x00800000L +#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x00000017 +#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x00400000L +#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x00000016 +#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x0000001fL +#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x00000000 +#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000L +#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x00000018 +#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x00010000L +#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x00000010 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x00000100L +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x00000008 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0x000000ffL +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x00000000 +#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0x0000ffffL +#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0x0000ffffL +#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x00030000L +#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x00000010 +#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x00700000L +#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x00000014 +#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x00800000L +#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x00000017 +#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x01000000L +#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x00000018 +#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x02000000L +#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x00000019 +#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x04000000L +#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x0000001a +#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000L +#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x0000001e +#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000L +#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x0000001f +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x00000001L +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x0000007eL +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x00000001 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x00000080L +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x00000007 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x00003f00L +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x00000008 +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x00004000L +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0x0000000e +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x003f8000L +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0x0000000f +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x00400000L +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x00000016 +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000L +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x00000017 +#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000L +#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x0000001e +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x00000001L +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0x000000feL +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x00000001 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x00000100L +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x00000008 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0x0000fe00L +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x00000009 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x00010000L +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x00000010 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0x00fe0000L +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x00000011 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x01000000L +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x00000018 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000L +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x00000019 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x00000060L +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x00000005 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x00000007 +#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L +#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x00000009 +#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x0001c000L +#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0x0000000e +#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x00001000L +#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0x0000000c +#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x00000800L +#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0x0000000b +#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x001c0000L +#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x00000012 +#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000L +#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x0000001f +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x00400000L +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x00000016 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x07800000L +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x00000017 +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x08000000L +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x0000001b +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000L +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x0000001c +#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x00200000L +#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x00000015 +#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x0000001fL +#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x03c00000L +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x00000016 +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0x0000ffffL +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x00000000 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x00040000L +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x00000012 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x00030000L +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x00000010 +#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x04000000L +#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000001a +#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000L +#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x0000001c +#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x08000000L +#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x0000001b +#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0x000000ffL +#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x00000000 +#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0x0000ffffL +#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x00000000 +#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000L +#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x00000010 +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x00008000L +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0x0000000f +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000L +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x00000010 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x00000004L +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x00000002 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x00000008L +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x00000003 +#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x00000001L +#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000 +#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x00000002L +#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x00000001 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x00000001L +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x00000002L +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x00000010L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x00000004 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x00100000L +#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0x000f0000L +#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0x00000f00L +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x00000008 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0x0000f000L +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x00001000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x00002000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0x0000000d +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x00004000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0x0000000e +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x00008000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0x0000000f +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0x000c0000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x00000012 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0x00c00000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x00000016 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0x0c000000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x0000001a +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x03000000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x00000018 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000L +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x0000001c +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x00001000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x00002000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0x0000000d +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x00004000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0x0000000e +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x00008000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0x0000000f +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0x000c0000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x00000012 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x00000016 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0x0c000000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x0000001a +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x0000001e +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x00030000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x03000000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x00000018 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000L +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x0000001c +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x00004000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0x0000000e +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x00008000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0x0000000f +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x00001000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x00002000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0x0000000d +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0x0c000000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x0000001a +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x0000001e +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0x000c0000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x00000012 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0x00c00000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x00000016 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x03000000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x0000001c +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x00030000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x00300000L +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x00001000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0x0000000c +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x00002000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0x0000000d +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x00004000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0x0000000e +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x00008000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0x0000000f +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0x000c0000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x00000012 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0x00c00000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x00000016 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0x0c000000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x0000001a +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x0000001e +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x00000004L +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x00000002 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x00000002L +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x00000001 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x00000001L +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x00000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x00030000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x00000010 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x00300000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x00000014 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x03000000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x00000018 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000L +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x0000001c +#define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK 0x00000001L +#define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT 0x00000000 +#define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x00000002L +#define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT 0x00000001 +#define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK 0x00000004L +#define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x00000002 +#define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK 0x00000008L +#define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT 0x00000003 +#define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK 0x00000010L +#define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT 0x00000004 +#define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK 0x00000020L +#define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT 0x00000005 +#define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK 0x00000040L +#define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT 0x00000006 +#define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK 0x00000080L +#define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT 0x00000007 +#define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK 0x00000100L +#define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT 0x00000008 +#define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK 0x00000200L +#define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT 0x00000009 +#define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK 0x00000400L +#define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT 0x0000000a +#define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK 0x00000800L +#define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT 0x0000000b +#define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK 0x00001000L +#define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT 0x0000000c +#define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK 0x00002000L +#define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT 0x0000000d +#define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK 0x00004000L +#define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT 0x0000000e +#define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK 0x00008000L +#define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT 0x0000000f +#define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK 0x00010000L +#define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT 0x00000010 +#define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK 0x00020000L +#define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT 0x00000011 +#define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK 0x00040000L +#define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT 0x00000012 +#define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK 0x00080000L +#define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT 0x00000013 +#define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK 0x00100000L +#define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT 0x00000014 +#define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK 0x00200000L +#define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT 0x00000015 +#define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK 0x00400000L +#define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT 0x00000016 +#define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK 0x00800000L +#define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT 0x00000017 +#define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK 0x01000000L +#define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT 0x00000018 +#define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK 0x02000000L +#define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x00000019 +#define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK 0x04000000L +#define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT 0x0000001a +#define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK 0x08000000L +#define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT 0x0000001b +#define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK 0x10000000L +#define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT 0x0000001c +#define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK 0x20000000L +#define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x0000001d +#define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK 0x40000000L +#define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT 0x0000001e +#define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK 0x80000000L +#define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT 0x0000001f +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x00000080L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x00000007 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x00000100L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x00000008 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x00040000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x00000012 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x00080000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x00000013 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x00100000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x00000014 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x00200000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x00000015 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x00400000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x00000016 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x00800000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x00000017 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x00000200L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x00000009 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x00000400L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x0000000a +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x00000800L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x0000000b +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x00001000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x0000000c +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x00002000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x0000000d +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x00004000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x0000000e +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x00008000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x0000000f +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x00010000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x00000010 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x00020000L +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x00000011 +#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x00000006L +#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x00000001 +#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x07000000L +#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x00000018 +#define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x00000002L +#define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x00000001 +#define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x00000020L +#define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x00000005 +#define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x00000200L +#define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x00000009 +#define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x00002000L +#define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0x0000000d +#define PB0_PIF_CNTL__DIVINIT_MODE_MASK 0x00000100L +#define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT 0x00000008 +#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x00700000L +#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x00000014 +#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x00000010L +#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x00000004 +#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x00800000L +#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x00000017 +#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000L +#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x0000001c +#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000L +#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x0000001d +#define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK 0x000e0000L +#define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x00000011 +#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L +#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x00000003 +#define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x00000004L +#define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x00000002 +#define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L +#define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0x0000000a +#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x00000040L +#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x00000006 +#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x00000080L +#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x00000007 +#define PB0_PIF_CNTL__RXEN_GATER_MASK 0x0f000000L +#define PB0_PIF_CNTL__RXEN_GATER__SHIFT 0x00000018 +#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x00000800L +#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0x0000000b +#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x00000001L +#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x00000000 +#define PB0_PIF_CNTL__TXGND_TIME_MASK 0x00010000L +#define PB0_PIF_CNTL__TXGND_TIME__SHIFT 0x00000010 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK 0x00000001L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT 0x00000000 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x00000002L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT 0x00000001 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK 0x00000004L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x00000002 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK 0x00000008L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT 0x00000003 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK 0x00000010L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT 0x00000004 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK 0x00000020L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT 0x00000005 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK 0x00000040L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT 0x00000006 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK 0x00000080L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT 0x00000007 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK 0x00000100L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT 0x00000008 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK 0x00000200L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT 0x00000009 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK 0x00000400L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT 0x0000000a +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK 0x00000800L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT 0x0000000b +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK 0x00001000L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT 0x0000000c +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK 0x00002000L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT 0x0000000d +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK 0x00004000L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT 0x0000000e +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK 0x00008000L +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT 0x0000000f +#define PB0_PIF_PAIRING__MULTI_PIF_MASK 0x02000000L +#define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x00000019 +#define PB0_PIF_PAIRING__X16_LANE_15_0_MASK 0x00100000L +#define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x00000014 +#define PB0_PIF_PAIRING__X2_LANE_1_0_MASK 0x00000001L +#define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x00000000 +#define PB0_PIF_PAIRING__X2_LANE_11_10_MASK 0x00000020L +#define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x00000005 +#define PB0_PIF_PAIRING__X2_LANE_13_12_MASK 0x00000040L +#define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x00000006 +#define PB0_PIF_PAIRING__X2_LANE_15_14_MASK 0x00000080L +#define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x00000007 +#define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x00000002L +#define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x00000001 +#define PB0_PIF_PAIRING__X2_LANE_5_4_MASK 0x00000004L +#define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x00000002 +#define PB0_PIF_PAIRING__X2_LANE_7_6_MASK 0x00000008L +#define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x00000003 +#define PB0_PIF_PAIRING__X2_LANE_9_8_MASK 0x00000010L +#define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x00000004 +#define PB0_PIF_PAIRING__X4_LANE_11_8_MASK 0x00000400L +#define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT 0x0000000a +#define PB0_PIF_PAIRING__X4_LANE_15_12_MASK 0x00000800L +#define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT 0x0000000b +#define PB0_PIF_PAIRING__X4_LANE_3_0_MASK 0x00000100L +#define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x00000008 +#define PB0_PIF_PAIRING__X4_LANE_7_4_MASK 0x00000200L +#define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x00000009 +#define PB0_PIF_PAIRING__X8_LANE_15_8_MASK 0x00020000L +#define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x00000011 +#define PB0_PIF_PAIRING__X8_LANE_7_0_MASK 0x00010000L +#define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x00000010 +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000b +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x00000100L +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x00000008 +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x00000200L +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x00000009 +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x00000010L +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000004 +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0x000000e0L +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000005 +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x00004000L +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0x0000000e +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x00038000L +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000f +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x00000001L +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000000 +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0x0000000eL +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000001 +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x00000400L +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0x0000000a +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x00003800L +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000b +#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x00000008L +#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x00000003 +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x00001c00L +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0x0000000a +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x00000380L +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x00000007 +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000L +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x0000001c +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000L +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x0000001d +#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x07000000L +#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x00000018 +#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x00000070L +#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x00000004 +#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x00010000L +#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x00000010 +#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x00000007L +#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x00000000 +#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x00000008L +#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x00000003 +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x00001c00L +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0x0000000a +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x00000380L +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x00000007 +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000L +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x0000001c +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000L +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x0000001d +#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x07000000L +#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x00000018 +#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x00000070L +#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x00000004 +#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x00010000L +#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x00000010 +#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x00000007L +#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x00000000 +#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x00000008L +#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x00000003 +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x00001c00L +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0x0000000a +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x00000380L +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x00000007 +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000L +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x0000001c +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000L +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x0000001d +#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x07000000L +#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x00000018 +#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x00000070L +#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x00000004 +#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x00010000L +#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x00000010 +#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x00000007L +#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x00000000 +#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x00000008L +#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x00000003 +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x00001c00L +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0x0000000a +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x00000380L +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x00000007 +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000L +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x0000001c +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000L +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x0000001d +#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x07000000L +#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x00000018 +#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x00000070L +#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x00000004 +#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x00010000L +#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x00000010 +#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x00000007L +#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x00000000 +#define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK 0x00000001L +#define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x00000000 +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x00000005 +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x00000010L +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x00000004 +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x00000008L +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x00000003 +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x00000004L +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x00000002 +#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x00010000L +#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x00000010 +#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x04000000L +#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x0000001a +#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x08000000L +#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x0000001b +#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000L +#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x0000001c +#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000L +#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x0000001d +#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000L +#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x0000001e +#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000L +#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x0000001f +#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x00020000L +#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x00000011 +#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x00040000L +#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x00000012 +#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x00080000L +#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x00000013 +#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x00100000L +#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x00000014 +#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x00200000L +#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x00000015 +#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x00400000L +#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x00000016 +#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x00800000L +#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x00000017 +#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x01000000L +#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x00000018 +#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x02000000L +#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x00000019 +#define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x00000100L +#define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x00000008 +#define PB0_PIF_SC_CTL__SC_PHASE_2_MASK 0x00000200L +#define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x00000009 +#define PB0_PIF_SC_CTL__SC_PHASE_3_MASK 0x00000400L +#define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT 0x0000000a +#define PB0_PIF_SC_CTL__SC_PHASE_4_MASK 0x00000800L +#define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT 0x0000000b +#define PB0_PIF_SC_CTL__SC_PHASE_5_MASK 0x00001000L +#define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT 0x0000000c +#define PB0_PIF_SC_CTL__SC_PHASE_6_MASK 0x00002000L +#define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT 0x0000000d +#define PB0_PIF_SC_CTL__SC_PHASE_7_MASK 0x00004000L +#define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT 0x0000000e +#define PB0_PIF_SC_CTL__SC_PHASE_8_MASK 0x00008000L +#define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT 0x0000000f +#define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x00000002L +#define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x00000001 +#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x00000040L +#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x00000006 +#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffffL +#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x00000006 +#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x00000001L +#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x00000000 +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x00000020L +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x00000005 +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x00000010L +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x00000004 +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x00000008L +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x00000003 +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x00000004L +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x00000002 +#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x00000700L +#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x00000008 +#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x00000002L +#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x00000001 +#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x00000040L +#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x00000006 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x00000001L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x00000000 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x00000400L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0x0000000a +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x00000800L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0x0000000b +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x00001000L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0x0000000c +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x00002000L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0x0000000d +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x00004000L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0x0000000e +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x00008000L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0x0000000f +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x00000002L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x00000001 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x00000004L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x00000002 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x00000008L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x00000003 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x00000010L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x00000004 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x00000020L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x00000005 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x00000040L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x00000006 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x00000080L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x00000007 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x00000100L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x00000008 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x00000200L +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x00000009 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x00000003L +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x00000000 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x00000004L +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x00000002 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x00000008L +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x00000003 +#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x00000010L +#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x00000004 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x00000008L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000003 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x00000007L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x00000080L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x00000007 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000070L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000004 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x00000200L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x00000009 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x00000100L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x00000008 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x00040000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x00000012 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x0003fc00L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0x0000000a +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x0000001c +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0x0ff80000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x00000013 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x0000001f +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000L +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x0000001d +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x00000008L +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000003 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x00000007L +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x00040000L +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x00000012 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x0003c000L +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0x0000000e +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000020L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x00000005 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000010L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000004 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00000080L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x00000007 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000040L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x00000006 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x00000200L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x00000009 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x00000100L +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x00000008 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x00000300L +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x00000070L +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x00000300L +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x00000070L +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x00000300L +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x00000070L +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x00000300L +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x00000070L +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x00000003L +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x00000000 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x00000004L +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x00000002 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x000007f0L +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x00000004 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x00000008L +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x00000003 +#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x00000800L +#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0x0000000b +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x00000100L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000008 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0x000000ffL +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x00001000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0x0000000c +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000e00L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000009 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x00004000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0x0000000e +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x00002000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0x0000000d +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x0000001c +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0x0fff8000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0x0000000f +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x0000001f +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000L +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x0000001e +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x00400000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000016 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x00380000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000013 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x00000020L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x00000005 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x0000001fL +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x00000100L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x00000008 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0x000000c0L +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x00000006 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000400L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x0000000a +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000200L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000009 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00001000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x0000000c +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000800L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x0000000b +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x00004000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0x0000000e +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x00002000L +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0x0000000d +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x00000300L +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x00000070L +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x00000300L +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x00000070L +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x00000300L +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x00000070L +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x00000300L +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x00000008 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x00000070L +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x00000004 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000200L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000009 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000400L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000a +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000800L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000b +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00100000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000014 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00200000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000015 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00001000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x0000000c +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00002000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000d +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00004000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000e +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00400000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000016 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00800000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000017 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x00000100L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000008 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000002L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000001 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000004L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x00000002 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000008L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x00000003 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00010000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000010 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00020000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000011 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00000010L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x00000004 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00000020L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x00000005 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00000040L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x00000006 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00040000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000012 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00080000L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000013 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x00000080L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000007 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x00000001L +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x000003ffL +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0x000ffc00L +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0x0000000a +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000L +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000L +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x0000001e +#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000L +#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x0000001e +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0x0000000fL +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0x000000f0L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x00000004 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0x00000f00L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x00000008 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0x0000f000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0x000f0000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x00000010 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x01000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x02000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x00000019 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x04000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x0000001a +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x08000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x0000001b +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000L +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x0000001d +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0x0000f000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0x000f0000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x00000010 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x03000000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0x0c000000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x0000001a +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000L +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000L +#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x0000001e +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x00000001L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x00000002L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x00000001 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x00000004L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x00000002 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0x0f000000L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000L +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x00000007L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x00000038L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x00000003 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x000001c0L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x00000006 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0x0f000000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0x00000e00L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x00000009 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x00007000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x00038000L +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0x0000000f +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x0000001fL +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x000003e0L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x00000005 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x00007c00L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0x0000000a +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x00008000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0x0000000f +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x00010000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x00000010 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x00020000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x00000011 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x00040000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x00000012 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x00080000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x00000013 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x00100000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x08000000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x0000001b +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000L +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x0000001d +#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000L +#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x0000001e +#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x08000000L +#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001b +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0x0000000fL +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0x000000f0L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x00000004 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0x00000f00L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x00000008 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0x0000f000L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0x000f0000L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x00000010 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0x00f00000L +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x00000014 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x01000000L +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x04000000L +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001a +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x001c0000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x00000012 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0x00e00000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x00000015 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x07000000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x00000018 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x08000000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x0000001b +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x0000001c +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x0000001d +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0x0000000fL +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x00000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0x000000f0L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x00000004 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0x00000f00L +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x00000008 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x00001000L +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x0000000c +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x00002000L +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0x0000000d +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x00020000L +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000011 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x0000001f +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x0000001e +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x00000002L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x00000001 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x00000001L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x00000000 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x00000008L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x00000003 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x00000004L +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x00000002 +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000L +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x0000001d +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000L +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x0000001c +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000100L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000008 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x000000c0L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000006 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x00000400L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0x0000000a +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x00000200L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x00000009 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00001000L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000c +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000800L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x0000000b +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x00004000L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0x0000000e +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x00002000L +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0x0000000d +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x00010000L +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x00000010 +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x00008000L +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0x0000000f +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x00040000L +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x00000012 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x00020000L +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x00000011 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x00100000L +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x00000014 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x00080000L +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x00000013 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x00400000L +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x00000016 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x00200000L +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x00000015 +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x01000000L +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x00000018 +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x00800000L +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x00000017 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x00000002L +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x00000001 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x00000001L +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x00000000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x00000010L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x00000004 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x00000080L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x00000007 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x00000020L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x00000005 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x00000040L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x00000006 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x00001000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0x0000000c +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x00008000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0x0000000f +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x00002000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0x0000000d +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x00004000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0x0000000e +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x00010000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x00000010 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x00080000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x00000013 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x00020000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x00000011 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x00040000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x00000012 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x00100000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x00000014 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x00800000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x00000017 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x00200000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x00000015 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x00400000L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x00000016 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x00000100L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x00000008 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x00000800L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0x0000000b +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x00000200L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x00000009 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x00000400L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0x0000000a +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0x000000ffL +#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x00000000 +#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x00002000L +#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0x0000000d +#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0x00000c00L +#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0x0000000a +#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x00001000L +#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0x0000000c +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x00000008L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x00000003 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x00000080L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x00000007 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x00000100L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x00000008 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x00000200L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x00000009 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x00000070L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x00000004 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x00000007L +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x00000000 +#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0x000000ffL +#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x00000000 +#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x00002000L +#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0x0000000d +#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0x00000c00L +#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0x0000000a +#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x00001000L +#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0x0000000c +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x00000008L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x00000003 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x00000080L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x00000007 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x00000100L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x00000008 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x00000200L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x00000009 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x00000070L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x00000004 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x00000007L +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x00000000 +#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0x000000ffL +#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x00000000 +#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x00002000L +#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0x0000000d +#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0x00000c00L +#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0x0000000a +#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x00001000L +#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0x0000000c +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x00000008L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x00000003 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x00000080L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x00000007 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x00000100L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x00000008 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x00000200L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x00000009 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x00000070L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x00000004 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x00000007L +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x00000000 +#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0x000000ffL +#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x00000000 +#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x00002000L +#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0x0000000d +#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0x00000c00L +#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0x0000000a +#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x00001000L +#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0x0000000c +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x00000008L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x00000003 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x00000080L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x00000007 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x00000100L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x00000008 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x00000200L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x00000009 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x00000070L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x00000004 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x00000007L +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x00000000 +#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0x000000ffL +#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x00000000 +#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x00002000L +#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0x0000000d +#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0x00000c00L +#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0x0000000a +#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x00001000L +#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0x0000000c +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x00000008L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x00000003 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x00000080L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x00000007 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x00000100L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x00000008 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x00000200L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x00000009 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x00000070L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x00000004 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x00000007L +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x00000000 +#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0x000000ffL +#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x00000000 +#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x00002000L +#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0x0000000d +#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0x00000c00L +#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0x0000000a +#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x00001000L +#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0x0000000c +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x00000008L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x00000003 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x00000080L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x00000007 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x00000100L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x00000008 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x00000200L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x00000009 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x00000070L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x00000004 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x00000007L +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x00000000 +#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0x000000ffL +#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x00000000 +#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x00002000L +#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0x0000000d +#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0x00000c00L +#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0x0000000a +#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x00001000L +#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0x0000000c +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x00000008L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x00000003 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x00000080L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x00000007 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x00000100L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x00000008 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x00000200L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x00000009 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x00000070L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x00000004 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x00000007L +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x00000000 +#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0x000000ffL +#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x00000000 +#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x00002000L +#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0x0000000d +#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0x00000c00L +#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0x0000000a +#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x00001000L +#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0x0000000c +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x00000008L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x00000003 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x00000080L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x00000007 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x00000100L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x00000008 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x00000200L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x00000009 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x00000070L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x00000004 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x00000007L +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x00000000 +#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0x000000ffL +#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x00000000 +#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x00002000L +#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0x0000000d +#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0x00000c00L +#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0x0000000a +#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x00001000L +#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0x0000000c +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x00000008L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x00000003 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x00000080L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x00000007 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x00000100L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x00000008 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x00000200L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x00000009 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x00000070L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x00000004 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x00000007L +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x00000000 +#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0x000000ffL +#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x00000000 +#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x00002000L +#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0x0000000d +#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0x00000c00L +#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0x0000000a +#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x00001000L +#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0x0000000c +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x00000008L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x00000003 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x00000080L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x00000007 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x00000100L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x00000008 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x00000200L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x00000009 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x00000070L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x00000004 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x00000007L +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x00000000 +#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0x000000ffL +#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x00000000 +#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x00002000L +#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0x0000000d +#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0x00000c00L +#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0x0000000a +#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x00001000L +#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0x0000000c +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x00000008L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x00000003 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x00000080L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x00000007 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x00000100L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x00000008 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x00000200L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x00000009 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x00000070L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x00000004 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x00000007L +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x00000000 +#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0x000000ffL +#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x00000000 +#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x00002000L +#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0x0000000d +#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0x00000c00L +#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0x0000000a +#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x00001000L +#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0x0000000c +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x00000008L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x00000003 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x00000080L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x00000007 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x00000100L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x00000008 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x00000200L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x00000009 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x00000070L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x00000004 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x00000007L +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x00000000 +#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0x000000ffL +#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x00000000 +#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x00002000L +#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0x0000000d +#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0x00000c00L +#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0x0000000a +#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x00001000L +#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0x0000000c +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x00000008L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x00000003 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x00000080L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x00000007 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x00000100L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x00000008 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x00000200L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x00000009 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x00000070L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x00000004 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x00000007L +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x00000000 +#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0x000000ffL +#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x00000000 +#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x00002000L +#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0x0000000d +#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0x00000c00L +#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0x0000000a +#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x00001000L +#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0x0000000c +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x00000008L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x00000003 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x00000080L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x00000007 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x00000100L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x00000008 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x00000200L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x00000009 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x00000070L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x00000004 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x00000007L +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x00000000 +#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0x000000ffL +#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x00000000 +#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x00002000L +#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0x0000000d +#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0x00000c00L +#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0x0000000a +#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x00001000L +#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0x0000000c +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x00000008L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x00000003 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x00000080L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x00000007 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x00000100L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x00000008 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x00000200L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x00000009 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x00000070L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x00000004 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x00000007L +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x00000000 +#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0x000000ffL +#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x00000000 +#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x00002000L +#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0x0000000d +#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0x00000c00L +#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0x0000000a +#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x00001000L +#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0x0000000c +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x00000008L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x00000003 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x00000080L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x00000007 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x00000100L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x00000008 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x00000200L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x00000009 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x00000070L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x00000004 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x00000007L +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x00000000 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x00008000L +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000000f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x00000001L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x00000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x00000400L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0x0000000a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x00000800L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0x0000000b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x00001000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0x0000000c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x00002000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0x0000000d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x00004000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0x0000000e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x00008000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0x0000000f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x00010000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x00000010 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x00020000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x00000011 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x00040000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x00000012 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x00080000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x00000013 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x00000002L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x00000001 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x00100000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x00000014 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x00200000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x00000015 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x00400000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x00000016 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x00800000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x00000017 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x01000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x00000018 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x02000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x00000019 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x04000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x0000001a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x08000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x0000001b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x0000001c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x0000001d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x00000004L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x00000002 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x0000001e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x0000001f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x00000008L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x00000003 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x00000010L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x00000004 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x00000020L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x00000005 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x00000040L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x00000006 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x00000080L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x00000007 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x00000100L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x00000008 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x00000200L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x00000009 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x00000001L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x00000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x00000002L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x00000001 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x00000004L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x00000002 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x00000008L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x00000003 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x00000010L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x00000004 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x00000020L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x00000005 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x00000040L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x00000006 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x00000080L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x00000007 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x00000100L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x00000008 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x00000200L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x00000009 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x00000400L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0x0000000a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x00000800L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0x0000000b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x00001000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0x0000000c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x00002000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0x0000000d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x00004000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0x0000000e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x00008000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0x0000000f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x00010000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x00000010 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x00020000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x00000011 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x00040000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x00000012 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x00080000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x00000013 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x00100000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x00000014 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x00200000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x00000015 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x00400000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x00000016 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x00800000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x00000017 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x01000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x00000018 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x02000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x00000019 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x04000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x0000001a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x08000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x0000001b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x0000001c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x0000001d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x0000001e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x0000001f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x00000001L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x00000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x00000002L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x00000001 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x00000004L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x00000002 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x00000008L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x00000003 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x00000010L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x00000004 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x00000020L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x00000005 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x00000040L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x00000006 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x00000080L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x00000007 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x00000100L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x00000008 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x00000200L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x00000009 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x00000400L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0x0000000a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x00000800L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0x0000000b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x00001000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0x0000000c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x00002000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0x0000000d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x00004000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0x0000000e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x00008000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0x0000000f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x00010000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x00000010 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x00020000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x00000011 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x00040000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x00000012 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x00080000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x00000013 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x00100000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x00000014 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x00200000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x00000015 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x00400000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x00000016 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x00800000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x00000017 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x01000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x00000018 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x02000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x00000019 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x04000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x0000001a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x08000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x0000001b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x0000001c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x0000001d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x0000001e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x0000001f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x00000010L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x00000004 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x00000020L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x00000005 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x00000040L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x00000006 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x00000080L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x00000007 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x00000100L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x00000008 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x00000200L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x00000009 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x00000400L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0x0000000a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x00000800L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0x0000000b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x00001000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0x0000000c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x00002000L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0x0000000d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x00000001L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x00000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x00000002L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x00000001 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x00000004L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x00000002 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x00000008L +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x00000003 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x00000700L +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x00000008 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x00003800L +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0x0000000b +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x0001c000L +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0x0000000e +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x00400000L +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x00000016 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x00200000L +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x00000015 +#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x00080000L +#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x00000013 +#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x00800000L +#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x00000017 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x00000007L +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x00000038L +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x00000003 +#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x01000000L +#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x00000018 +#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x00100000L +#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x00000014 +#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x00060000L +#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x00000011 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x0000001e +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x00000001L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x00000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x00000400L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0x0000000a +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x00000800L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0x0000000b +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x00001000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0x0000000c +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x00002000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0x0000000d +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x00004000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0x0000000e +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x00008000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0x0000000f +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x00000002L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x00000001 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x00000004L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x00000002 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x00000008L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x00000003 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x00000010L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x00000004 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x00000020L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x00000005 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x00000040L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x00000006 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x00000080L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x00000007 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x00000100L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x00000008 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x00000200L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x00000009 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x00010000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x00000010 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x00200000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x00000015 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x00400000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x00000016 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x00800000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x00000017 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x00020000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x00000011 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x00040000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x00000012 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x00080000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x00000013 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x00100000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x00000014 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x01000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x00000018 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x08000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x0000001b +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x02000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x00000019 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x04000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x0000001a +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x0000001c +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000L +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x0000001d +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000008L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000003 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x00000007L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0x000000f0L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x00000100L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x00000008 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00001e00L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000009 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x00002000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0x0000000d +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x0007c000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0x0000000e +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x00080000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x00000013 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x01f00000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000014 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x02000000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x00000019 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x0000001a +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000L +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x0000001e +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0x0000000fL +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x00000010L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x00000020L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x00000005 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x00000040L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x00000006 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00000080L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000007 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x00000100L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x00000008 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00000400L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000a +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000200L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x00000009 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x00001000L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0x0000000c +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x00000800L +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0x0000000b +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x00004000L +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0x0000000e +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x00002000L +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0x0000000d +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x02000000L +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x00000019 +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x01ff8000L +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0x0000000f +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x08000000L +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x0000001b +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x04000000L +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x0000001a +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000L +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x0000001d +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000L +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x0000001c +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000L +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x0000001f +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000L +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x0000001e +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0x0000f000L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0x0000000c +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000f0000L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000010 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x01f00000L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x00000014 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000019 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x00000800L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0x0000000b +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x00000400L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0x0000000a +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x00000008L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x00000003 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x00000004L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x00000002 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x00000020L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x00000005 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x00000010L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x00000080L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x00000007 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x00000040L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x00000006 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x00000200L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x00000009 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x00000100L +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x00000008 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x00000002L +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x00000001 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x00000001L +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x00003c00L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0x0000000a +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0003c000L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0000000e +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x007c0000L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x00000012 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0f800000L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000017 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0x0000000fL +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x0000001c +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000000f0L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x00000100L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x00000008 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x00000200L +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000009 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0000000fL +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000000 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x00000010L +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x00000004 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x00000020L +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000005 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x00000100L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x00000008 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x00000800L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0x0000000b +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x00000200L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x00000009 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x00000400L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0x0000000a +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x00001000L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0x0000000c +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x00008000L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0x0000000f +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x00002000L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0x0000000d +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x00004000L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0x0000000e +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x00000010L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x00000004 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x00000080L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x00000007 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x00000020L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x00000005 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x00000040L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x00000006 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x00000001L +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x00000000 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x00000002L +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x00000001 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x00000004L +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x00000002 +#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x00000008L +#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x00000003 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x00000002L +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x00000001 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x00000001L +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x00000000 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x00000008L +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x00000003 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x00000004L +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x00000002 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x00000020L +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x00000005 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x00000010L +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x00000004 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x00000080L +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x00000007 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x00000040L +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x00000006 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0x0000fc00L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0x0000000a +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x00000300L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x00000008 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x00000080L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x00000007 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x00000008L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x00000003 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x00000070L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x00000004 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x00000007L +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x00000000 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x00000001L +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x00000000 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x00000002L +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x00000001 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x00000004L +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x00000002 +#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x00000008L +#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x00000003 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x00000002L +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x00000001 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x00000001L +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x00000000 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x00000008L +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x00000003 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x00000004L +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x00000002 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x00000020L +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x00000005 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x00000010L +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x00000004 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x00000080L +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x00000007 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x00000040L +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x00000006 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0x0000fc00L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0x0000000a +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x00000300L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x00000008 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x00000080L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x00000007 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x00000008L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x00000003 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x00000070L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x00000004 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x00000007L +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x00000000 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x00000001L +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x00000000 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x00000002L +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x00000001 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x00000004L +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x00000002 +#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x00000008L +#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x00000003 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x00000002L +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x00000001 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x00000001L +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x00000000 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x00000008L +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x00000003 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x00000004L +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x00000002 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x00000020L +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x00000005 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x00000010L +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x00000004 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x00000080L +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x00000007 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x00000040L +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x00000006 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0x0000fc00L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0x0000000a +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x00000300L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x00000008 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x00000080L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x00000007 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x00000008L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x00000003 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x00000070L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x00000004 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x00000007L +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x00000000 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x00000001L +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x00000000 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x00000002L +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x00000001 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x00000004L +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x00000002 +#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x00000008L +#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x00000003 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x00000002L +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x00000001 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x00000001L +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x00000000 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x00000008L +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x00000003 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x00000004L +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x00000002 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x00000020L +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x00000005 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x00000010L +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x00000004 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x00000080L +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x00000007 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x00000040L +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x00000006 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0x0000fc00L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0x0000000a +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x00000300L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x00000008 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x00000080L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x00000007 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x00000008L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x00000003 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x00000070L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x00000004 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x00000007L +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x00000000 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x00000001L +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x00000000 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x00000002L +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x00000001 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x00000004L +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x00000002 +#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x00000008L +#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x00000003 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x00000002L +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x00000001 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x00000001L +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x00000000 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x00000008L +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x00000003 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x00000004L +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x00000002 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x00000020L +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x00000005 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x00000010L +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x00000004 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x00000080L +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x00000007 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x00000040L +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x00000006 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0x0000fc00L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0x0000000a +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x00000300L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x00000008 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x00000080L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x00000007 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x00000008L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x00000003 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x00000070L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x00000004 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x00000007L +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x00000000 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x00000001L +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x00000000 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x00000002L +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x00000001 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x00000004L +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x00000002 +#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x00000008L +#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x00000003 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x00000002L +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x00000001 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x00000001L +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x00000000 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x00000008L +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x00000003 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x00000004L +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x00000002 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x00000020L +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x00000005 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x00000010L +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x00000004 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x00000080L +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x00000007 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x00000040L +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x00000006 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0x0000fc00L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0x0000000a +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x00000300L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x00000008 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x00000080L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x00000007 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x00000008L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x00000003 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x00000070L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x00000004 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x00000007L +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x00000000 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x00000001L +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x00000000 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x00000002L +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x00000001 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x00000004L +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x00000002 +#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x00000008L +#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x00000003 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x00000002L +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x00000001 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x00000001L +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x00000000 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x00000008L +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x00000003 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x00000004L +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x00000002 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x00000020L +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x00000005 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x00000010L +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x00000004 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x00000080L +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x00000007 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x00000040L +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x00000006 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0x0000fc00L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0x0000000a +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x00000300L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x00000008 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x00000080L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x00000007 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x00000008L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x00000003 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x00000070L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x00000004 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x00000007L +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x00000000 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x00000001L +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x00000000 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x00000002L +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x00000001 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x00000004L +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x00000002 +#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x00000008L +#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x00000003 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x00000002L +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x00000001 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x00000001L +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x00000000 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x00000008L +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x00000003 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x00000004L +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x00000002 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x00000020L +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x00000005 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x00000010L +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x00000004 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x00000080L +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x00000007 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x00000040L +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x00000006 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0x0000fc00L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0x0000000a +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x00000300L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x00000008 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x00000080L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x00000007 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x00000008L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x00000003 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x00000070L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x00000004 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x00000007L +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x00000000 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x00000001L +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x00000000 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x00000002L +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x00000001 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x00000004L +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x00000002 +#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x00000008L +#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x00000003 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x00000002L +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x00000001 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x00000001L +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x00000000 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x00000008L +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x00000003 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x00000004L +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x00000002 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x00000020L +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x00000005 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x00000010L +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x00000004 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x00000080L +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x00000007 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x00000040L +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x00000006 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0x0000fc00L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0x0000000a +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x00000300L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x00000008 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x00000080L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x00000007 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x00000008L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x00000003 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x00000070L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x00000004 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x00000007L +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x00000000 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x00000001L +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x00000000 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x00000002L +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x00000001 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x00000004L +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x00000002 +#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x00000008L +#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x00000003 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x00000002L +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x00000001 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x00000001L +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x00000000 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x00000008L +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x00000003 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x00000004L +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x00000002 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x00000020L +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x00000005 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x00000010L +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x00000004 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x00000080L +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x00000007 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x00000040L +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x00000006 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0x0000fc00L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0x0000000a +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x00000300L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x00000008 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x00000080L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x00000007 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x00000008L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x00000003 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x00000070L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x00000004 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x00000007L +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x00000000 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x00000001L +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x00000000 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x00000002L +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x00000001 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x00000004L +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x00000002 +#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x00000008L +#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x00000003 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x00000002L +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x00000001 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x00000001L +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x00000000 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x00000008L +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x00000003 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x00000004L +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x00000002 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x00000020L +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x00000005 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x00000010L +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x00000004 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x00000080L +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x00000007 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x00000040L +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x00000006 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0x0000fc00L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0x0000000a +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x00000300L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x00000008 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x00000080L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x00000007 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x00000008L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x00000003 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x00000070L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x00000004 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x00000007L +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x00000000 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x00000001L +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x00000000 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x00000002L +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x00000001 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x00000004L +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x00000002 +#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x00000008L +#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x00000003 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x00000002L +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x00000001 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x00000001L +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x00000000 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x00000008L +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x00000003 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x00000004L +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x00000002 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x00000020L +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x00000005 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x00000010L +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x00000004 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x00000080L +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x00000007 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x00000040L +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x00000006 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0x0000fc00L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0x0000000a +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x00000300L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x00000008 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x00000080L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x00000007 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x00000008L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x00000003 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x00000070L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x00000004 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x00000007L +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x00000000 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x00000001L +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x00000000 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x00000002L +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x00000001 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x00000004L +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x00000002 +#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x00000008L +#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x00000003 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x00000002L +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x00000001 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x00000001L +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x00000000 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x00000008L +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x00000003 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x00000004L +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x00000002 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x00000020L +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x00000005 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x00000010L +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x00000004 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x00000080L +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x00000007 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x00000040L +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x00000006 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0x0000fc00L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0x0000000a +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x00000300L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x00000008 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x00000080L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x00000007 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x00000008L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x00000003 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x00000070L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x00000004 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x00000007L +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x00000000 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x00000001L +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x00000000 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x00000002L +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x00000001 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x00000004L +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x00000002 +#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x00000008L +#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x00000003 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x00000002L +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x00000001 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x00000001L +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x00000000 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x00000008L +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x00000003 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x00000004L +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x00000002 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x00000020L +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x00000005 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x00000010L +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x00000004 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x00000080L +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x00000007 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x00000040L +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x00000006 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0x0000fc00L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0x0000000a +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x00000300L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x00000008 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x00000080L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x00000007 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x00000008L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x00000003 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x00000070L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x00000004 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x00000007L +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x00000000 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x00000001L +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x00000000 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x00000002L +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x00000001 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x00000004L +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x00000002 +#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x00000008L +#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x00000003 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x00000002L +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x00000001 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x00000001L +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x00000000 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x00000008L +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x00000003 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x00000004L +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x00000002 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x00000020L +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x00000005 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x00000010L +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x00000004 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x00000080L +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x00000007 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x00000040L +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x00000006 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0x0000fc00L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0x0000000a +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x00000300L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x00000008 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x00000080L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x00000007 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x00000008L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x00000003 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x00000070L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x00000004 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x00000007L +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x00000000 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x00000001L +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x00000000 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x00000002L +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x00000001 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x00000004L +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x00000002 +#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x00000008L +#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x00000003 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x00000002L +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x00000001 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x00000001L +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x00000000 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x00000008L +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x00000003 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x00000004L +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x00000002 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x00000020L +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x00000005 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x00000010L +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x00000004 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x00000080L +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x00000007 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x00000040L +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x00000006 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0x0000fc00L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0x0000000a +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x00000300L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x00000008 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x00000080L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x00000007 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x00000008L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x00000003 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x00000070L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x00000004 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x00000007L +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x00000000 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x00000001L +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x00000000 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x0000003eL +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x00000001 +#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0x00000f00L +#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x00000008 +#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x00800000L +#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x00000017 +#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x00400000L +#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x00000016 +#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x0000001fL +#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x00000000 +#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000L +#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x00000018 +#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x00010000L +#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x00000010 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x00000100L +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x00000008 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0x000000ffL +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x00000000 +#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0x0000ffffL +#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0x0000ffffL +#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x00030000L +#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x00000010 +#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x00700000L +#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x00000014 +#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x00800000L +#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x00000017 +#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x01000000L +#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x00000018 +#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x02000000L +#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x00000019 +#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x04000000L +#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x0000001a +#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000L +#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x0000001e +#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000L +#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x0000001f +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x00000001L +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x0000007eL +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x00000001 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x00000080L +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x00000007 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x00003f00L +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x00000008 +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x00004000L +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0x0000000e +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x003f8000L +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0x0000000f +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x00400000L +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x00000016 +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000L +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x00000017 +#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000L +#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x0000001e +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x00000001L +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0x000000feL +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x00000001 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x00000100L +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x00000008 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0x0000fe00L +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x00000009 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x00010000L +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x00000010 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0x00fe0000L +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x00000011 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x01000000L +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x00000018 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000L +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x00000019 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x00000060L +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x00000005 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x00000007 +#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L +#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x00000009 +#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x0001c000L +#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0x0000000e +#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x00001000L +#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0x0000000c +#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x00000800L +#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0x0000000b +#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x001c0000L +#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x00000012 +#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000L +#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x0000001f +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x00400000L +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x00000016 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x07800000L +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x00000017 +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x08000000L +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x0000001b +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000L +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x0000001c +#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x00200000L +#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x00000015 +#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x0000001fL +#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x03c00000L +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x00000016 +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0x0000ffffL +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x00000000 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x00040000L +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x00000012 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x00030000L +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x00000010 +#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x04000000L +#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000001a +#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000L +#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x0000001c +#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x08000000L +#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x0000001b +#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0x000000ffL +#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x00000000 +#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0x0000ffffL +#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x00000000 +#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000L +#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x00000010 +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x00008000L +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0x0000000f +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000L +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x00000010 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x00000004L +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x00000002 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x00000008L +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x00000003 +#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x00000001L +#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000 +#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x00000002L +#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x00000001 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x00000001L +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x00000002L +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x00000010L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x00000004 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x00100000L +#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0x000f0000L +#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0x00000f00L +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x00000008 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0x0000f000L +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x00001000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x00002000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0x0000000d +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x00004000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0x0000000e +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x00008000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0x0000000f +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0x000c0000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x00000012 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0x00c00000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x00000016 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0x0c000000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x0000001a +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x03000000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x00000018 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000L +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x0000001c +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x00001000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x00002000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0x0000000d +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x00004000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0x0000000e +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x00008000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0x0000000f +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0x000c0000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x00000012 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x00000016 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0x0c000000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x0000001a +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x0000001e +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x00030000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x03000000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x00000018 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000L +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x0000001c +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x00004000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0x0000000e +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x00008000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0x0000000f +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x00001000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x00002000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0x0000000d +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0x0c000000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x0000001a +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x0000001e +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0x000c0000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x00000012 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0x00c00000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x00000016 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x03000000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x0000001c +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x00030000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x00300000L +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x00001000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0x0000000c +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x00002000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0x0000000d +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x00004000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0x0000000e +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x00008000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0x0000000f +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0x000c0000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x00000012 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0x00c00000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x00000016 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0x0c000000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x0000001a +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x0000001e +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x00000004L +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x00000002 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x00000002L +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x00000001 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x00000001L +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x00000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x00030000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x00000010 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x00300000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x00000014 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x03000000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x00000018 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000L +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x0000001c +#define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK 0x00000001L +#define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT 0x00000000 +#define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x00000002L +#define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT 0x00000001 +#define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK 0x00000004L +#define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x00000002 +#define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK 0x00000008L +#define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT 0x00000003 +#define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK 0x00000010L +#define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT 0x00000004 +#define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK 0x00000020L +#define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT 0x00000005 +#define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK 0x00000040L +#define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT 0x00000006 +#define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK 0x00000080L +#define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT 0x00000007 +#define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK 0x00000100L +#define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT 0x00000008 +#define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK 0x00000200L +#define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT 0x00000009 +#define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK 0x00000400L +#define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT 0x0000000a +#define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK 0x00000800L +#define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT 0x0000000b +#define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK 0x00001000L +#define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT 0x0000000c +#define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK 0x00002000L +#define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT 0x0000000d +#define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK 0x00004000L +#define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT 0x0000000e +#define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK 0x00008000L +#define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT 0x0000000f +#define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK 0x00010000L +#define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT 0x00000010 +#define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK 0x00020000L +#define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT 0x00000011 +#define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK 0x00040000L +#define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT 0x00000012 +#define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK 0x00080000L +#define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT 0x00000013 +#define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK 0x00100000L +#define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT 0x00000014 +#define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK 0x00200000L +#define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT 0x00000015 +#define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK 0x00400000L +#define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT 0x00000016 +#define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK 0x00800000L +#define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT 0x00000017 +#define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK 0x01000000L +#define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT 0x00000018 +#define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK 0x02000000L +#define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x00000019 +#define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK 0x04000000L +#define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT 0x0000001a +#define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK 0x08000000L +#define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT 0x0000001b +#define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK 0x10000000L +#define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT 0x0000001c +#define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK 0x20000000L +#define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT 0x0000001d +#define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK 0x40000000L +#define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT 0x0000001e +#define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK 0x80000000L +#define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT 0x0000001f +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x00000080L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x00000007 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x00000100L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x00000008 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x00040000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x00000012 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x00080000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x00000013 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x00100000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x00000014 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x00200000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x00000015 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x00400000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x00000016 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x00800000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x00000017 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x00000200L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x00000009 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x00000400L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x0000000a +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x00000800L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x0000000b +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x00001000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x0000000c +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x00002000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x0000000d +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x00004000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x0000000e +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x00008000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x0000000f +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x00010000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x00000010 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x00020000L +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x00000011 +#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x00000006L +#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x00000001 +#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x07000000L +#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x00000018 +#define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x00000002L +#define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x00000001 +#define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x00000020L +#define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x00000005 +#define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x00000200L +#define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x00000009 +#define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x00002000L +#define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0x0000000d +#define PB1_PIF_CNTL__DIVINIT_MODE_MASK 0x00000100L +#define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT 0x00000008 +#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x00700000L +#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x00000014 +#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x00000010L +#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x00000004 +#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x00800000L +#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x00000017 +#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000L +#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x0000001c +#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000L +#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x0000001d +#define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK 0x000e0000L +#define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x00000011 +#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L +#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x00000003 +#define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x00000004L +#define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x00000002 +#define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L +#define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0x0000000a +#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x00000040L +#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x00000006 +#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x00000080L +#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x00000007 +#define PB1_PIF_CNTL__RXEN_GATER_MASK 0x0f000000L +#define PB1_PIF_CNTL__RXEN_GATER__SHIFT 0x00000018 +#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x00000800L +#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0x0000000b +#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x00000001L +#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x00000000 +#define PB1_PIF_CNTL__TXGND_TIME_MASK 0x00010000L +#define PB1_PIF_CNTL__TXGND_TIME__SHIFT 0x00000010 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK 0x00000001L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT 0x00000000 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x00000002L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT 0x00000001 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK 0x00000004L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x00000002 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK 0x00000008L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT 0x00000003 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK 0x00000010L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT 0x00000004 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK 0x00000020L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT 0x00000005 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK 0x00000040L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT 0x00000006 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK 0x00000080L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT 0x00000007 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK 0x00000100L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT 0x00000008 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK 0x00000200L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT 0x00000009 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK 0x00000400L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT 0x0000000a +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK 0x00000800L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT 0x0000000b +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK 0x00001000L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT 0x0000000c +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK 0x00002000L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT 0x0000000d +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK 0x00004000L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT 0x0000000e +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK 0x00008000L +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT 0x0000000f +#define PB1_PIF_PAIRING__MULTI_PIF_MASK 0x02000000L +#define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x00000019 +#define PB1_PIF_PAIRING__X16_LANE_15_0_MASK 0x00100000L +#define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x00000014 +#define PB1_PIF_PAIRING__X2_LANE_1_0_MASK 0x00000001L +#define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x00000000 +#define PB1_PIF_PAIRING__X2_LANE_11_10_MASK 0x00000020L +#define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x00000005 +#define PB1_PIF_PAIRING__X2_LANE_13_12_MASK 0x00000040L +#define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x00000006 +#define PB1_PIF_PAIRING__X2_LANE_15_14_MASK 0x00000080L +#define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x00000007 +#define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x00000002L +#define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x00000001 +#define PB1_PIF_PAIRING__X2_LANE_5_4_MASK 0x00000004L +#define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x00000002 +#define PB1_PIF_PAIRING__X2_LANE_7_6_MASK 0x00000008L +#define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x00000003 +#define PB1_PIF_PAIRING__X2_LANE_9_8_MASK 0x00000010L +#define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x00000004 +#define PB1_PIF_PAIRING__X4_LANE_11_8_MASK 0x00000400L +#define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT 0x0000000a +#define PB1_PIF_PAIRING__X4_LANE_15_12_MASK 0x00000800L +#define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT 0x0000000b +#define PB1_PIF_PAIRING__X4_LANE_3_0_MASK 0x00000100L +#define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x00000008 +#define PB1_PIF_PAIRING__X4_LANE_7_4_MASK 0x00000200L +#define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x00000009 +#define PB1_PIF_PAIRING__X8_LANE_15_8_MASK 0x00020000L +#define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x00000011 +#define PB1_PIF_PAIRING__X8_LANE_7_0_MASK 0x00010000L +#define PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x00000010 +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000b +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x00000100L +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x00000008 +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x00000200L +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x00000009 +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x00000010L +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000004 +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0x000000e0L +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000005 +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x00004000L +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0x0000000e +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x00038000L +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000f +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x00000001L +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000000 +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0x0000000eL +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000001 +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x00000400L +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0x0000000a +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x00003800L +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000b +#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x00000008L +#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x00000003 +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x00001c00L +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0x0000000a +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x00000380L +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x00000007 +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000L +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x0000001c +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000L +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x0000001d +#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x07000000L +#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x00000018 +#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x00000070L +#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x00000004 +#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x00010000L +#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x00000010 +#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x00000007L +#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x00000000 +#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x00000008L +#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x00000003 +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x00001c00L +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0x0000000a +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x00000380L +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x00000007 +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000L +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x0000001c +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000L +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x0000001d +#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x07000000L +#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x00000018 +#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x00000070L +#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x00000004 +#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x00010000L +#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x00000010 +#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x00000007L +#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x00000000 +#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x00000008L +#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x00000003 +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x00001c00L +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0x0000000a +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x00000380L +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x00000007 +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000L +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x0000001c +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000L +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x0000001d +#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x07000000L +#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x00000018 +#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x00000070L +#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x00000004 +#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x00010000L +#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x00000010 +#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x00000007L +#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x00000000 +#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x00000008L +#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x00000003 +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x00001c00L +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0x0000000a +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x00000380L +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x00000007 +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000L +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x0000001c +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000L +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x0000001d +#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x07000000L +#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x00000018 +#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x00000070L +#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x00000004 +#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x00010000L +#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x00000010 +#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x00000007L +#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x00000000 +#define PB1_PIF_SC_CTL__SC_CALIBRATION_MASK 0x00000001L +#define PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x00000000 +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x00000005 +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x00000010L +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x00000004 +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x00000008L +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x00000003 +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x00000004L +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x00000002 +#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x00010000L +#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x00000010 +#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x04000000L +#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x0000001a +#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x08000000L +#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x0000001b +#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000L +#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x0000001c +#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000L +#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x0000001d +#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000L +#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x0000001e +#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000L +#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x0000001f +#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x00020000L +#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x00000011 +#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x00040000L +#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x00000012 +#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x00080000L +#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x00000013 +#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x00100000L +#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x00000014 +#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x00200000L +#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x00000015 +#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x00400000L +#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x00000016 +#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x00800000L +#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x00000017 +#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x01000000L +#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x00000018 +#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x02000000L +#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x00000019 +#define PB1_PIF_SC_CTL__SC_PHASE_1_MASK 0x00000100L +#define PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x00000008 +#define PB1_PIF_SC_CTL__SC_PHASE_2_MASK 0x00000200L +#define PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x00000009 +#define PB1_PIF_SC_CTL__SC_PHASE_3_MASK 0x00000400L +#define PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT 0x0000000a +#define PB1_PIF_SC_CTL__SC_PHASE_4_MASK 0x00000800L +#define PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT 0x0000000b +#define PB1_PIF_SC_CTL__SC_PHASE_5_MASK 0x00001000L +#define PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT 0x0000000c +#define PB1_PIF_SC_CTL__SC_PHASE_6_MASK 0x00002000L +#define PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT 0x0000000d +#define PB1_PIF_SC_CTL__SC_PHASE_7_MASK 0x00004000L +#define PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT 0x0000000e +#define PB1_PIF_SC_CTL__SC_PHASE_8_MASK 0x00008000L +#define PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT 0x0000000f +#define PB1_PIF_SC_CTL__SC_RXDETECT_MASK 0x00000002L +#define PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x00000001 +#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x00000040L +#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x00000006 +#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffffL +#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x00000006 +#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x00000001L +#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x00000000 +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x00000020L +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x00000005 +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x00000010L +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x00000004 +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x00000008L +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x00000003 +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x00000004L +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x00000002 +#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x00000700L +#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x00000008 +#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x00000002L +#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x00000001 +#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x00000040L +#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x00000006 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x00000001L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x00000000 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x00000400L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0x0000000a +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x00000800L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0x0000000b +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x00001000L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0x0000000c +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x00002000L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0x0000000d +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x00004000L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0x0000000e +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x00008000L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0x0000000f +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x00000002L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x00000001 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x00000004L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x00000002 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x00000008L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x00000003 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x00000010L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x00000004 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x00000020L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x00000005 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x00000040L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x00000006 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x00000080L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x00000007 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x00000100L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x00000008 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x00000200L +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x00000009 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x00000003L +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x00000000 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x00000004L +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x00000002 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x00000008L +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x00000003 +#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x00000010L +#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x00000004 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x00000008L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000003 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x00000007L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x00000080L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x00000007 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000070L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000004 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x00000200L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x00000009 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x00000100L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x00000008 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x00040000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x00000012 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x0003fc00L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0x0000000a +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x0000001c +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0x0ff80000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x00000013 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x0000001f +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000L +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x0000001d +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x00000008L +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000003 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x00000007L +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x00040000L +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x00000012 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x0003c000L +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0x0000000e +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000020L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x00000005 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000010L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000004 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00000080L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x00000007 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000040L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x00000006 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x00000200L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x00000009 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x00000100L +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x00000008 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x00000300L +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x00000070L +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x00000300L +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x00000070L +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x00000300L +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x00000070L +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x00000300L +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x00000070L +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x00000003L +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x00000000 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x00000004L +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x00000002 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x000007f0L +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x00000004 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x00000008L +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x00000003 +#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x00000800L +#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0x0000000b +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x00000100L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000008 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0x000000ffL +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x00001000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0x0000000c +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000e00L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000009 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x00004000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0x0000000e +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x00002000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0x0000000d +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x0000001c +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0x0fff8000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0x0000000f +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x0000001f +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000L +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x0000001e +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x00400000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000016 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x00380000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000013 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x00000020L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x00000005 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x0000001fL +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x00000100L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x00000008 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0x000000c0L +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x00000006 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000400L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x0000000a +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000200L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000009 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00001000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x0000000c +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000800L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x0000000b +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x00004000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0x0000000e +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x00002000L +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0x0000000d +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x00000300L +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x00000070L +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x00000300L +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x00000070L +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x00000300L +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x00000070L +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x00000300L +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x00000008 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x00000070L +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x00000004 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000200L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000009 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000400L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000a +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000800L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000b +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00100000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000014 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00200000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000015 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00001000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x0000000c +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00002000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000d +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00004000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000e +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00400000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000016 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00800000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000017 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x00000100L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000008 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000002L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000001 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000004L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x00000002 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000008L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x00000003 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00010000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000010 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00020000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000011 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00000010L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x00000004 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00000020L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x00000005 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00000040L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x00000006 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00040000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000012 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00080000L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000013 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x00000080L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000007 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x00000001L +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x000003ffL +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0x000ffc00L +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0x0000000a +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000L +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000L +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x0000001e +#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000L +#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x0000001e +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0x0000000fL +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0x000000f0L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x00000004 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0x00000f00L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x00000008 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0x0000f000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0x000f0000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x00000010 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x01000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x02000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x00000019 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x04000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x0000001a +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x08000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x0000001b +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000L +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x0000001d +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0x0000f000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0x000f0000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x00000010 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x03000000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0x0c000000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x0000001a +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000L +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000L +#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x0000001e +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x00000001L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x00000002L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x00000001 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x00000004L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x00000002 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0x0f000000L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000L +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x00000007L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x00000038L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x00000003 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x000001c0L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x00000006 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0x0f000000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0x00000e00L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x00000009 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x00007000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x00038000L +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0x0000000f +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x0000001fL +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x000003e0L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x00000005 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x00007c00L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0x0000000a +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x00008000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0x0000000f +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x00010000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x00000010 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x00020000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x00000011 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x00040000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x00000012 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x00080000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x00000013 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x00100000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x08000000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x0000001b +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000L +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x0000001d +#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000L +#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x0000001e +#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x08000000L +#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001b +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0x0000000fL +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0x000000f0L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x00000004 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0x00000f00L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x00000008 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0x0000f000L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0x000f0000L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x00000010 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0x00f00000L +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x00000014 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x01000000L +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x04000000L +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001a +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x001c0000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x00000012 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0x00e00000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x00000015 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x07000000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x00000018 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x08000000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x0000001b +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x0000001c +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x0000001d +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0x0000000fL +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x00000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0x000000f0L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x00000004 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0x00000f00L +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x00000008 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x00001000L +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x0000000c +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x00002000L +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0x0000000d +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x00020000L +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000011 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x0000001f +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x0000001e +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x00000002L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x00000001 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x00000001L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x00000000 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x00000008L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x00000003 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x00000004L +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x00000002 +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000L +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x0000001d +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000L +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x0000001c +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000100L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000008 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x000000c0L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000006 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x00000400L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0x0000000a +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x00000200L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x00000009 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00001000L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000c +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000800L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x0000000b +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x00004000L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0x0000000e +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x00002000L +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0x0000000d +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x00010000L +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x00000010 +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x00008000L +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0x0000000f +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x00040000L +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x00000012 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x00020000L +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x00000011 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x00100000L +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x00000014 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x00080000L +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x00000013 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x00400000L +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x00000016 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x00200000L +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x00000015 +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x01000000L +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x00000018 +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x00800000L +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x00000017 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x00000002L +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x00000001 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x00000001L +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x00000000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x00000010L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x00000004 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x00000080L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x00000007 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x00000020L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x00000005 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x00000040L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x00000006 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x00001000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0x0000000c +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x00008000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0x0000000f +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x00002000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0x0000000d +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x00004000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0x0000000e +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x00010000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x00000010 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x00080000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x00000013 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x00020000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x00000011 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x00040000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x00000012 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x00100000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x00000014 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x00800000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x00000017 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x00200000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x00000015 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x00400000L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x00000016 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x00000100L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x00000008 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x00000800L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0x0000000b +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x00000200L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x00000009 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x00000400L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0x0000000a +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0x000000ffL +#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x00000000 +#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x00002000L +#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0x0000000d +#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0x00000c00L +#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0x0000000a +#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x00001000L +#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0x0000000c +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x00000008L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x00000003 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x00000080L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x00000007 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x00000100L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x00000008 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x00000200L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x00000009 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x00000070L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x00000004 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x00000007L +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x00000000 +#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0x000000ffL +#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x00000000 +#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x00002000L +#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0x0000000d +#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0x00000c00L +#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0x0000000a +#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x00001000L +#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0x0000000c +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x00000008L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x00000003 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x00000080L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x00000007 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x00000100L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x00000008 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x00000200L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x00000009 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x00000070L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x00000004 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x00000007L +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x00000000 +#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0x000000ffL +#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x00000000 +#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x00002000L +#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0x0000000d +#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0x00000c00L +#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0x0000000a +#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x00001000L +#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0x0000000c +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x00000008L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x00000003 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x00000080L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x00000007 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x00000100L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x00000008 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x00000200L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x00000009 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x00000070L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x00000004 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x00000007L +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x00000000 +#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0x000000ffL +#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x00000000 +#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x00002000L +#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0x0000000d +#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0x00000c00L +#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0x0000000a +#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x00001000L +#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0x0000000c +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x00000008L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x00000003 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x00000080L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x00000007 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x00000100L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x00000008 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x00000200L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x00000009 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x00000070L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x00000004 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x00000007L +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x00000000 +#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0x000000ffL +#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x00000000 +#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x00002000L +#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0x0000000d +#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0x00000c00L +#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0x0000000a +#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x00001000L +#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0x0000000c +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x00000008L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x00000003 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x00000080L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x00000007 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x00000100L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x00000008 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x00000200L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x00000009 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x00000070L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x00000004 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x00000007L +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x00000000 +#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0x000000ffL +#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x00000000 +#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x00002000L +#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0x0000000d +#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0x00000c00L +#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0x0000000a +#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x00001000L +#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0x0000000c +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x00000008L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x00000003 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x00000080L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x00000007 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x00000100L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x00000008 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x00000200L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x00000009 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x00000070L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x00000004 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x00000007L +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x00000000 +#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0x000000ffL +#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x00000000 +#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x00002000L +#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0x0000000d +#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0x00000c00L +#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0x0000000a +#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x00001000L +#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0x0000000c +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x00000008L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x00000003 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x00000080L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x00000007 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x00000100L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x00000008 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x00000200L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x00000009 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x00000070L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x00000004 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x00000007L +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x00000000 +#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0x000000ffL +#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x00000000 +#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x00002000L +#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0x0000000d +#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0x00000c00L +#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0x0000000a +#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x00001000L +#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0x0000000c +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x00000008L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x00000003 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x00000080L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x00000007 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x00000100L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x00000008 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x00000200L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x00000009 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x00000070L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x00000004 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x00000007L +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x00000000 +#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0x000000ffL +#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x00000000 +#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x00002000L +#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0x0000000d +#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0x00000c00L +#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0x0000000a +#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x00001000L +#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0x0000000c +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x00000008L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x00000003 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x00000080L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x00000007 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x00000100L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x00000008 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x00000200L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x00000009 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x00000070L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x00000004 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x00000007L +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x00000000 +#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0x000000ffL +#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x00000000 +#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x00002000L +#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0x0000000d +#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0x00000c00L +#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0x0000000a +#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x00001000L +#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0x0000000c +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x00000008L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x00000003 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x00000080L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x00000007 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x00000100L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x00000008 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x00000200L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x00000009 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x00000070L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x00000004 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x00000007L +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x00000000 +#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0x000000ffL +#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x00000000 +#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x00002000L +#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0x0000000d +#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0x00000c00L +#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0x0000000a +#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x00001000L +#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0x0000000c +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x00000008L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x00000003 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x00000080L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x00000007 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x00000100L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x00000008 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x00000200L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x00000009 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x00000070L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x00000004 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x00000007L +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x00000000 +#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0x000000ffL +#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x00000000 +#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x00002000L +#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0x0000000d +#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0x00000c00L +#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0x0000000a +#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x00001000L +#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0x0000000c +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x00000008L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x00000003 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x00000080L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x00000007 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x00000100L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x00000008 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x00000200L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x00000009 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x00000070L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x00000004 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x00000007L +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x00000000 +#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0x000000ffL +#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x00000000 +#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x00002000L +#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0x0000000d +#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0x00000c00L +#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0x0000000a +#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x00001000L +#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0x0000000c +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x00000008L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x00000003 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x00000080L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x00000007 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x00000100L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x00000008 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x00000200L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x00000009 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x00000070L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x00000004 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x00000007L +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x00000000 +#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0x000000ffL +#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x00000000 +#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x00002000L +#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0x0000000d +#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0x00000c00L +#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0x0000000a +#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x00001000L +#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0x0000000c +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x00000008L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x00000003 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x00000080L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x00000007 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x00000100L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x00000008 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x00000200L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x00000009 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x00000070L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x00000004 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x00000007L +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x00000000 +#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0x000000ffL +#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x00000000 +#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x00002000L +#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0x0000000d +#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0x00000c00L +#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0x0000000a +#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x00001000L +#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0x0000000c +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x00000008L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x00000003 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x00000080L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x00000007 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x00000100L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x00000008 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x00000200L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x00000009 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x00000070L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x00000004 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x00000007L +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x00000000 +#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0x000000ffL +#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x00000000 +#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x00002000L +#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0x0000000d +#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0x00000c00L +#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0x0000000a +#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x00001000L +#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0x0000000c +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x00000008L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x00000003 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x00000080L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x00000007 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x00000100L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x00000008 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x00000200L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x00000009 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x00000070L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x00000004 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x00000007L +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x00000000 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x00008000L +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000000f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x00000001L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x00000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x00000400L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0x0000000a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x00000800L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0x0000000b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x00001000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0x0000000c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x00002000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0x0000000d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x00004000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0x0000000e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x00008000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0x0000000f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x00010000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x00000010 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x00020000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x00000011 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x00040000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x00000012 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x00080000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x00000013 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x00000002L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x00000001 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x00100000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x00000014 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x00200000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x00000015 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x00400000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x00000016 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x00800000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x00000017 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x01000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x00000018 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x02000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x00000019 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x04000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x0000001a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x08000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x0000001b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x0000001c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x0000001d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x00000004L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x00000002 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x0000001e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x0000001f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x00000008L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x00000003 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x00000010L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x00000004 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x00000020L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x00000005 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x00000040L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x00000006 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x00000080L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x00000007 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x00000100L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x00000008 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x00000200L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x00000009 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x00000001L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x00000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x00000002L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x00000001 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x00000004L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x00000002 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x00000008L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x00000003 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x00000010L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x00000004 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x00000020L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x00000005 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x00000040L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x00000006 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x00000080L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x00000007 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x00000100L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x00000008 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x00000200L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x00000009 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x00000400L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0x0000000a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x00000800L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0x0000000b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x00001000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0x0000000c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x00002000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0x0000000d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x00004000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0x0000000e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x00008000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0x0000000f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x00010000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x00000010 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x00020000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x00000011 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x00040000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x00000012 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x00080000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x00000013 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x00100000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x00000014 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x00200000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x00000015 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x00400000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x00000016 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x00800000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x00000017 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x01000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x00000018 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x02000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x00000019 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x04000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x0000001a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x08000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x0000001b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x0000001c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x0000001d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x0000001e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x0000001f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x00000001L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x00000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x00000002L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x00000001 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x00000004L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x00000002 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x00000008L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x00000003 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x00000010L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x00000004 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x00000020L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x00000005 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x00000040L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x00000006 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x00000080L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x00000007 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x00000100L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x00000008 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x00000200L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x00000009 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x00000400L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0x0000000a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x00000800L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0x0000000b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x00001000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0x0000000c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x00002000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0x0000000d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x00004000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0x0000000e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x00008000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0x0000000f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x00010000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x00000010 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x00020000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x00000011 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x00040000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x00000012 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x00080000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x00000013 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x00100000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x00000014 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x00200000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x00000015 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x00400000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x00000016 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x00800000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x00000017 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x01000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x00000018 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x02000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x00000019 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x04000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x0000001a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x08000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x0000001b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x0000001c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x0000001d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x0000001e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x0000001f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x00000010L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x00000004 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x00000020L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x00000005 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x00000040L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x00000006 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x00000080L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x00000007 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x00000100L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x00000008 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x00000200L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x00000009 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x00000400L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0x0000000a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x00000800L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0x0000000b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x00001000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0x0000000c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x00002000L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0x0000000d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x00000001L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x00000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x00000002L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x00000001 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x00000004L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x00000002 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x00000008L +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x00000003 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x00000700L +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x00000008 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x00003800L +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0x0000000b +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x0001c000L +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0x0000000e +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x00400000L +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x00000016 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x00200000L +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x00000015 +#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x00080000L +#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x00000013 +#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x00800000L +#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x00000017 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x00000007L +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x00000038L +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x00000003 +#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x01000000L +#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x00000018 +#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x00100000L +#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x00000014 +#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x00060000L +#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x00000011 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x0000001e +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x00000001L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x00000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x00000400L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0x0000000a +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x00000800L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0x0000000b +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x00001000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0x0000000c +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x00002000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0x0000000d +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x00004000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0x0000000e +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x00008000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0x0000000f +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x00000002L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x00000001 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x00000004L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x00000002 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x00000008L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x00000003 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x00000010L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x00000004 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x00000020L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x00000005 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x00000040L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x00000006 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x00000080L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x00000007 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x00000100L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x00000008 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x00000200L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x00000009 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x00010000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x00000010 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x00200000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x00000015 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x00400000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x00000016 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x00800000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x00000017 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x00020000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x00000011 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x00040000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x00000012 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x00080000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x00000013 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x00100000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x00000014 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x01000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x00000018 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x08000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x0000001b +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x02000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x00000019 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x04000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x0000001a +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x0000001c +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000L +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x0000001d +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000008L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000003 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x00000007L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0x000000f0L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x00000100L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x00000008 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00001e00L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000009 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x00002000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0x0000000d +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x0007c000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0x0000000e +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x00080000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x00000013 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x01f00000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000014 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x02000000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x00000019 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x0000001a +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000L +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x0000001e +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0x0000000fL +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x00000010L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x00000020L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x00000005 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x00000040L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x00000006 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00000080L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000007 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x00000100L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x00000008 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00000400L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000a +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000200L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x00000009 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x00001000L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0x0000000c +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x00000800L +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0x0000000b +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x00004000L +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0x0000000e +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x00002000L +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0x0000000d +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x02000000L +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x00000019 +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x01ff8000L +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0x0000000f +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x08000000L +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x0000001b +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x04000000L +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x0000001a +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000L +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x0000001d +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000L +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x0000001c +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000L +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x0000001f +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000L +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x0000001e +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0x0000f000L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0x0000000c +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000f0000L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000010 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x01f00000L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x00000014 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000019 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x00000800L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0x0000000b +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x00000400L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0x0000000a +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x00000008L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x00000003 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x00000004L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x00000002 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x00000020L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x00000005 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x00000010L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x00000080L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x00000007 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x00000040L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x00000006 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x00000200L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x00000009 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x00000100L +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x00000008 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x00000002L +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x00000001 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x00000001L +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x00003c00L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0x0000000a +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0003c000L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0000000e +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x007c0000L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x00000012 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0f800000L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000017 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0x0000000fL +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x0000001c +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000000f0L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x00000100L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x00000008 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x00000200L +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000009 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0000000fL +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000000 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x00000010L +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x00000004 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x00000020L +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000005 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x00000100L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x00000008 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x00000800L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0x0000000b +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x00000200L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x00000009 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x00000400L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0x0000000a +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x00001000L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0x0000000c +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x00008000L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0x0000000f +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x00002000L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0x0000000d +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x00004000L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0x0000000e +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x00000010L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x00000004 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x00000080L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x00000007 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x00000020L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x00000005 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x00000040L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x00000006 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x00000001L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x00000008L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x00000002L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x00000004L +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x00000001L +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x00000000 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x00000002L +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x00000001 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x00000004L +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x00000002 +#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x00000008L +#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x00000003 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x00000002L +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x00000001 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x00000001L +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x00000000 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x00000008L +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x00000003 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x00000004L +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x00000002 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x00000020L +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x00000005 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x00000010L +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x00000004 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x00000080L +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x00000007 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x00000040L +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x00000006 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0x0000fc00L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0x0000000a +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x00000300L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x00000008 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x00000080L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x00000007 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x00000008L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x00000003 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x00000070L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x00000004 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x00000007L +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x00000000 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x00000001L +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x00000000 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x00000002L +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x00000001 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x00000004L +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x00000002 +#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x00000008L +#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x00000003 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x00000002L +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x00000001 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x00000001L +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x00000000 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x00000008L +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x00000003 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x00000004L +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x00000002 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x00000020L +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x00000005 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x00000010L +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x00000004 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x00000080L +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x00000007 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x00000040L +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x00000006 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0x0000fc00L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0x0000000a +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x00000300L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x00000008 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x00000080L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x00000007 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x00000008L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x00000003 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x00000070L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x00000004 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x00000007L +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x00000000 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x00000001L +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x00000000 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x00000002L +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x00000001 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x00000004L +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x00000002 +#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x00000008L +#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x00000003 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x00000002L +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x00000001 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x00000001L +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x00000000 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x00000008L +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x00000003 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x00000004L +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x00000002 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x00000020L +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x00000005 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x00000010L +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x00000004 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x00000080L +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x00000007 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x00000040L +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x00000006 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0x0000fc00L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0x0000000a +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x00000300L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x00000008 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x00000080L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x00000007 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x00000008L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x00000003 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x00000070L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x00000004 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x00000007L +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x00000000 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x00000001L +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x00000000 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x00000002L +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x00000001 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x00000004L +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x00000002 +#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x00000008L +#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x00000003 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x00000002L +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x00000001 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x00000001L +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x00000000 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x00000008L +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x00000003 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x00000004L +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x00000002 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x00000020L +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x00000005 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x00000010L +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x00000004 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x00000080L +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x00000007 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x00000040L +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x00000006 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0x0000fc00L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0x0000000a +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x00000300L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x00000008 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x00000080L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x00000007 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x00000008L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x00000003 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x00000070L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x00000004 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x00000007L +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x00000000 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x00000001L +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x00000000 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x00000002L +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x00000001 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x00000004L +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x00000002 +#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x00000008L +#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x00000003 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x00000002L +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x00000001 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x00000001L +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x00000000 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x00000008L +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x00000003 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x00000004L +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x00000002 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x00000020L +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x00000005 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x00000010L +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x00000004 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x00000080L +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x00000007 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x00000040L +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x00000006 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0x0000fc00L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0x0000000a +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x00000300L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x00000008 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x00000080L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x00000007 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x00000008L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x00000003 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x00000070L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x00000004 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x00000007L +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x00000000 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x00000001L +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x00000000 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x00000002L +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x00000001 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x00000004L +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x00000002 +#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x00000008L +#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x00000003 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x00000002L +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x00000001 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x00000001L +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x00000000 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x00000008L +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x00000003 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x00000004L +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x00000002 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x00000020L +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x00000005 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x00000010L +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x00000004 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x00000080L +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x00000007 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x00000040L +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x00000006 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0x0000fc00L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0x0000000a +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x00000300L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x00000008 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x00000080L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x00000007 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x00000008L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x00000003 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x00000070L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x00000004 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x00000007L +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x00000000 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x00000001L +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x00000000 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x00000002L +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x00000001 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x00000004L +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x00000002 +#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x00000008L +#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x00000003 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x00000002L +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x00000001 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x00000001L +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x00000000 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x00000008L +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x00000003 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x00000004L +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x00000002 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x00000020L +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x00000005 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x00000010L +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x00000004 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x00000080L +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x00000007 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x00000040L +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x00000006 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0x0000fc00L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0x0000000a +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x00000300L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x00000008 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x00000080L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x00000007 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x00000008L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x00000003 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x00000070L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x00000004 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x00000007L +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x00000000 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x00000001L +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x00000000 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x00000002L +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x00000001 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x00000004L +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x00000002 +#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x00000008L +#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x00000003 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x00000002L +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x00000001 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x00000001L +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x00000000 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x00000008L +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x00000003 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x00000004L +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x00000002 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x00000020L +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x00000005 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x00000010L +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x00000004 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x00000080L +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x00000007 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x00000040L +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x00000006 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0x0000fc00L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0x0000000a +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x00000300L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x00000008 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x00000080L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x00000007 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x00000008L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x00000003 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x00000070L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x00000004 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x00000007L +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x00000000 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x00000001L +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x00000000 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x00000002L +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x00000001 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x00000004L +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x00000002 +#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x00000008L +#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x00000003 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x00000002L +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x00000001 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x00000001L +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x00000000 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x00000008L +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x00000003 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x00000004L +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x00000002 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x00000020L +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x00000005 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x00000010L +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x00000004 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x00000080L +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x00000007 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x00000040L +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x00000006 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0x0000fc00L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0x0000000a +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x00000300L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x00000008 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x00000080L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x00000007 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x00000008L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x00000003 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x00000070L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x00000004 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x00000007L +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x00000000 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x00000001L +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x00000000 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x00000002L +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x00000001 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x00000004L +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x00000002 +#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x00000008L +#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x00000003 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x00000002L +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x00000001 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x00000001L +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x00000000 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x00000008L +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x00000003 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x00000004L +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x00000002 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x00000020L +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x00000005 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x00000010L +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x00000004 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x00000080L +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x00000007 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x00000040L +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x00000006 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0x0000fc00L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0x0000000a +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x00000300L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x00000008 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x00000080L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x00000007 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x00000008L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x00000003 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x00000070L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x00000004 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x00000007L +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x00000000 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x00000001L +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x00000000 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x00000002L +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x00000001 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x00000004L +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x00000002 +#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x00000008L +#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x00000003 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x00000002L +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x00000001 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x00000001L +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x00000000 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x00000008L +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x00000003 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x00000004L +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x00000002 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x00000020L +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x00000005 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x00000010L +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x00000004 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x00000080L +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x00000007 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x00000040L +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x00000006 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0x0000fc00L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0x0000000a +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x00000300L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x00000008 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x00000080L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x00000007 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x00000008L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x00000003 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x00000070L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x00000004 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x00000007L +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x00000000 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x00000001L +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x00000000 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x00000002L +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x00000001 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x00000004L +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x00000002 +#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x00000008L +#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x00000003 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x00000002L +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x00000001 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x00000001L +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x00000000 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x00000008L +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x00000003 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x00000004L +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x00000002 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x00000020L +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x00000005 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x00000010L +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x00000004 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x00000080L +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x00000007 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x00000040L +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x00000006 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0x0000fc00L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0x0000000a +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x00000300L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x00000008 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x00000080L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x00000007 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x00000008L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x00000003 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x00000070L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x00000004 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x00000007L +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x00000000 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x00000001L +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x00000000 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x00000002L +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x00000001 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x00000004L +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x00000002 +#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x00000008L +#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x00000003 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x00000002L +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x00000001 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x00000001L +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x00000000 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x00000008L +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x00000003 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x00000004L +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x00000002 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x00000020L +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x00000005 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x00000010L +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x00000004 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x00000080L +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x00000007 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x00000040L +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x00000006 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0x0000fc00L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0x0000000a +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x00000300L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x00000008 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x00000080L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x00000007 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x00000008L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x00000003 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x00000070L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x00000004 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x00000007L +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x00000000 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x00000001L +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x00000000 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x00000002L +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x00000001 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x00000004L +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x00000002 +#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x00000008L +#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x00000003 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x00000002L +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x00000001 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x00000001L +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x00000000 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x00000008L +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x00000003 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x00000004L +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x00000002 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x00000020L +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x00000005 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x00000010L +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x00000004 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x00000080L +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x00000007 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x00000040L +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x00000006 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0x0000fc00L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0x0000000a +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x00000300L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x00000008 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x00000080L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x00000007 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x00000008L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x00000003 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x00000070L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x00000004 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x00000007L +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x00000000 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x00000001L +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x00000000 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x00000002L +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x00000001 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x00000004L +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x00000002 +#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x00000008L +#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x00000003 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x00000002L +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x00000001 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x00000001L +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x00000000 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x00000008L +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x00000003 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x00000004L +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x00000002 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x00000020L +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x00000005 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x00000010L +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x00000004 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x00000080L +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x00000007 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x00000040L +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x00000006 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0x0000fc00L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0x0000000a +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x00000300L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x00000008 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x00000080L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x00000007 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x00000008L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x00000003 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x00000070L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x00000004 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x00000007L +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x00000000 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x00000001L +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x00000000 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x00000002L +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x00000001 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x00000004L +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x00000002 +#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x00000008L +#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x00000003 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x00000002L +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x00000001 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x00000001L +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x00000000 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x00000008L +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x00000003 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x00000004L +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x00000002 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x00000020L +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x00000005 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x00000010L +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x00000004 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x00000080L +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x00000007 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x00000040L +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x00000006 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0x0000fc00L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0x0000000a +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x00000300L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x00000008 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x00000080L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x00000007 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x00000008L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x00000003 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x00000070L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x00000004 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x00000007L +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x00000000 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x00000007 +#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L +#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000006 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000001L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x00000000 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x00000002 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000002L +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x00000001 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x00000004 +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x00002000L +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0x0000000d +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x00000009 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x00000003 +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x00000002 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0x0000000a +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0x0000000b +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0x0000000c +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x00000008 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000c0L +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x00000006 +#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L +#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x00000012 +#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L +#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x00000016 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L +#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x00000013 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L +#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x00000017 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000L +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x00000018 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x00000011 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x00000015 +#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L +#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x00000010 +#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L +#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x00000014 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007c0L +#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x00000006 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x00000000 +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003eL +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x00000001 +#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x00000000 +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000eL +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x00000001 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x00000009 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x00000008 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x00000017 +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x0000001f +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0x0000000f +#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x00100000L +#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x00000014 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x00000013 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x00000011 +#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L +#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x00000010 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x00000012 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x00000015 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x00000016 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001c00L +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0x0000000a +#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000L +#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x00000018 +#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x00000007 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x02000000L +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x00000019 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x00000010 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x00000014 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x00000018 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000e0000L +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x00000011 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00e00000L +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x00000015 +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000fL +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x00000000 +#define PCIE_DATA__PCIE_DATA_MASK 0xffffffffL +#define PCIE_DATA__PCIE_DATA__SHIFT 0x00000000 +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000L +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x00000010 +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0x000000ffL +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x00000000 +#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x00000100L +#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x00000008 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x0000000b +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x00001000L +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x0000000c +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x00002000L +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x0000000d +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x00000008 +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0x0000000f +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0x0000000e +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x00000010 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x00000000 +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x00000007 +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x00000005 +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x00000001 +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x00000006 +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x00000004 +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0x0000000c +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x00000008 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00ff0000L +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x00000010 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000L +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x00000018 +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x0000001fL +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x00000000 +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000ffL +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0x000000ffL +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x00000000 +#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0x000000ffL +#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x00000000 +#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0000ff00L +#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x00000008 +#define PCIE_FC_NP__NPD_CREDITS_MASK 0x000000ffL +#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x00000000 +#define PCIE_FC_NP__NPH_CREDITS_MASK 0x0000ff00L +#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x00000008 +#define PCIE_FC_P__PD_CREDITS_MASK 0x000000ffL +#define PCIE_FC_P__PD_CREDITS__SHIFT 0x00000000 +#define PCIE_FC_P__PH_CREDITS_MASK 0x0000ff00L +#define PCIE_FC_P__PH_CREDITS__SHIFT 0x00000008 +#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L +#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 +#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L +#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 +#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L +#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 +#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L +#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 +#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L +#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 +#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L +#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 +#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L +#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 +#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L +#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 +#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L +#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 +#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L +#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 +#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L +#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a +#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L +#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b +#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L +#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c +#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L +#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d +#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L +#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e +#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L +#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001ffffL +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x00000000 +#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffffL +#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x00000000 +#define PCIE_INDEX__PCIE_INDEX_MASK 0x000000ffL +#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x00000000 +#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x00000000 +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x00000002 +#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x00000080L +#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x00000007 +#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x00000004 +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x00000001 +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x00000006 +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x00000100L +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x00000008 +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x00000003 +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x00000000 +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x00000002 +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x00000080L +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x00000007 +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x00000004 +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x00000001 +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x00000006 +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x00000100L +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x00000008 +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x00000003 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000fc00L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0x0000000a +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x00000016 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003f0000L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x00000010 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003f0L +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x00000004 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000fL +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x00000000 +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x00000000 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x00000005 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x00000001 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0x0000000a +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x00000006 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x00000009 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x00000008 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x00000003 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x00000004 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x00000007 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x00000002 +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x00000018 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000fffL +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x00000000 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00fff000L +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0x0000000c +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x00000011 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x00000012 +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x00000016 +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x00000014 +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x00080000L +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x00000013 +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x00000010 +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x0000001a +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000c000L +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0x0000000e +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x0000001f +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0x0000000c +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0x0000000b +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x0000001b +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0x0000000a +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x00000007 +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x00000008 +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x0000001c +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x00000019 +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x00000015 +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x00000006 +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x0000001d +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003fL +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x00000000 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x00000017 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0x0000000d +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x00000009 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x00000012 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x00000013 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x00000008 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000c0L +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x00000006 +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x00000010 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x00000009 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x00000004 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x00000017 +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x00003000L +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0x0000000c +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0x0000c000L +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0x0000000e +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x0000000a +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x00000015 +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x0000001e +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x00000018 +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x00000011 +#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000L +#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x0000001f +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x00000003 +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0x0000000b +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x00000005 +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x00400000L +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x00000016 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x00000001 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x00000000 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000L +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x0000001a +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x00000019 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x00000010L +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x00010000L +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x00000010 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x00000004 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0x0000000a +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x00000300L +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x00000008 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x00000018 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x00000006 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x00020000L +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x00000011 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x003c0000L +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x00000012 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x00000007 +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x00800000L +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x00000017 +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0x0000000e +#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x00000020L +#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x00000005 +#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L +#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0x0000000d +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x00000000 +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x00008000L +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0x0000000f +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x00000016 +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x00000800L +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0x0000000b +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x00001000L +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0x0000000c +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000L +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x0000001a +#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x0000003fL +#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x00000000 +#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0x00000fc0L +#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x00000006 +#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x0003f000L +#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0x0000000c +#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0x00fc0000L +#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x00000012 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000f0L +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x00000004 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x00000018 +#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L +#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x00000019 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x0000001b +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x0000001c +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x00000001 +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x0000001e +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x0000001d +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x00000014 +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x0000001f +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x00000011 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000f00L +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x00000008 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x00000017 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000f000L +#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0x0000000c +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000c0000L +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x00000012 +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x00000010 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x00000002 +#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L +#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x00000003 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x00000015 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x00000016 +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x00080000L +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x00000013 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x00000001L +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x00000000 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x00001f80L +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x00000007 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x0007e000L +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0x0000000d +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x0000007eL +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x00000001 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x00000001L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x00000000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x00001f80L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x00000007 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x0007e000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0x0000000d +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x0000007eL +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x00000001 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x01f80000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x00000013 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000L +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x00000019 +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000ffffL +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x00000000 +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000L +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x00000010 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x00000010 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x00000013 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x00000015 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x00000012 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x00000017 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x00000011 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x00000004 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x00000000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x00000007 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x00000008 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0x0000000a +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x00000009 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0x0000000b +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0x0000000f +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0x0000000e +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x00000014 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0x0000000d +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0x0000000c +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000L +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x00000018 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x00000009 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00ff0000L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x00000010 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000ffL +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x00000008 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x00000000 +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00020000L +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x00000011 +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x00400000L +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x00000016 +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x04000000L +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x0000001a +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00010000L +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x00000010 +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x00006000L +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x0000000d +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x03000000L +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x00000018 +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000L +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x0000001f +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000L +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x0000001e +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00008000L +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x0000000f +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000100L +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x00000008 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000040L +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x00000006 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000080L +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x00000007 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000020L +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x00000005 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x00000000 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x00000001 +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000200L +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x00000009 +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000L +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x0000001c +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000L +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x0000001d +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x08000000L +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x0000001b +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00040000L +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x00000012 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00100000L +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x00000014 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00080000L +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x00000013 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00200000L +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x00000015 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00001000L +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x0000000c +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00000c00L +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x0000000a +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x00800000L +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x00000017 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000004L +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x00000002 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000018L +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x00000003 +#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003fL +#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x00000000 +#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003f00L +#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x00000008 +#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003f0000L +#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x00000010 +#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000L +#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x00000018 +#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003fL +#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x00000000 +#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003f00L +#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x00000008 +#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003f0000L +#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x00000010 +#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000L +#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x00000018 +#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003fL +#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x00000000 +#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003f00L +#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x00000008 +#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003f0000L +#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x00000010 +#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000L +#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x00000018 +#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003fL +#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x00000000 +#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003f00L +#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x00000008 +#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003f0000L +#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x00000010 +#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000L +#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x00000018 +#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003f0000L +#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x00000010 +#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000L +#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x00000018 +#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003fL +#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x00000000 +#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003f00L +#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x00000008 +#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003fL +#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x00000000 +#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003f00L +#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x00000008 +#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003f0000L +#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x00000010 +#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000L +#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x00000018 +#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003fL +#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x00000000 +#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003f00L +#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x00000008 +#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003f0000L +#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x00000010 +#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000L +#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x00000018 +#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003fL +#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x00000000 +#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003f00L +#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x00000008 +#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003f0000L +#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x00000010 +#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000L +#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x00000018 +#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003fL +#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x00000000 +#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003f00L +#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x00000008 +#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003f0000L +#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x00000010 +#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000L +#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x00000018 +#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003fL +#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x00000000 +#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003f00L +#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x00000008 +#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003f0000L +#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x00000010 +#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000L +#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x00000018 +#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003fL +#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x00000000 +#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003f00L +#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x00000008 +#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003f0000L +#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x00000010 +#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000L +#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x00000018 +#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003fL +#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x00000000 +#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003f00L +#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x00000008 +#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003f0000L +#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x00000010 +#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000L +#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x00000018 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000e0L +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x00000005 +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001cL +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x00000002 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x00000000 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x00000001 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000ffffL +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x00000000 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000L +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x00000010 +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x0000001c +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00c00000L +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x00000016 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x00000011 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x00000004 +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0x0000000d +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x00000018 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x00000019 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0x0000000b +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000L +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x0000001e +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x00000010 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x00000013 +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0x0000000c +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x00000006 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x00000007 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x00000014 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x00000005 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x00000008 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x0000001a +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x0000001b +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x00000015 +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000fL +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x00000000 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x00000012 +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x0000001d +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000ffffL +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x00000000 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000L +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x00000010 +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0x0000000d +#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L +#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0x0000000c +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x00000008L +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x00000003 +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000c000L +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0x0000000e +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x00000004 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x00000006 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x00000007 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x00000005 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x00000008 +#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L +#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x00000000 +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x00000004L +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x00000002 +#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L +#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x00000001 +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000ffffL +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0x00000f00L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0x000000f0L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x00000004 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0x00f00000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x00000014 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0x0000f000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0x0000000c +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0x000f0000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x0f000000L +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0x0000000fL +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0x00000f00L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0x000000f0L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x00000004 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0x00f00000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x00000014 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0x0000f000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0x0000000c +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0x000f0000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0f000000L +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0x0000000fL +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0x00ff0000L +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x00000010 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000L +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x00000018 +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0x000000ffL +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x00000000 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0x0000ff00L +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x00000008 +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffffL +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffffL +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x00000000 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x00000000 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x00000002 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x00000001 +#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L +#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 +#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L +#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 +#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L +#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 +#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L +#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 +#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L +#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 +#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L +#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 +#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L +#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 +#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L +#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 +#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L +#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 +#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L +#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 +#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L +#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a +#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L +#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b +#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L +#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c +#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L +#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d +#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L +#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e +#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L +#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000ffL +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x00000000 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000L +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x00000010 +#define PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffffL +#define PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x00000000 +#define PCIE_PORT_INDEX__PCIE_INDEX_MASK 0x000000ffL +#define PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x00000000 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x00007f00L +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x00000008 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x00000001 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x00000002 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L +#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x00000003 +#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L +#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x00000005 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L +#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x00000004 +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x00000040L +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x00000006 +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x00000000 +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007eL +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x00000001 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x00000000 +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0x000f0000L +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x00000010 +#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000ffffL +#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x00000000 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffffL +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x00000000 +#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000ffffL +#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x00000000 +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000ffL +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x00000000 +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffffL +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x00000000 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000010L +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x00000004 +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000L +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x00000010 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x00000060L +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x00000005 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000c000L +#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0x0000000e +#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L +#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x00000000 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00000f80L +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x00000007 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x00000006L +#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x00000001 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000008L +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x00000003 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000ffffL +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x00000000 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000L +#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x00000010 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000ffffL +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x00000000 +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffffL +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x00000000 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000ff00L +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x00000008 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000ffL +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x00000000 +#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffffL +#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x00000000 +#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffffL +#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x00000000 +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x0000000f +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0x0000000b +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0x0000000c +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0x0000000d +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x00000000 +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x00000010 +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000cL +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x00000002 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x00000004 +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0x0000000e +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000c0L +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x00000006 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x00000008 +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x00000001 +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x00000002 +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x00000003 +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x00000000 +#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffffL +#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x00000000 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x00000003 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x00000000 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x00000005 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x00000004 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x00000001 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x00000002 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x00000004 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x00000003 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x00000002 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x00000000 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x00000001 +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0x0000000f +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0x0000000e +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0x0000000c +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x00000001 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x00000004 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0x0000000a +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x00000005 +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x00000017 +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x00000003 +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x00000006 +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x00000018 +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x00000000 +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0x0000000b +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x00000007 +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x00000008 +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x00000016 +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x00000002 +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x00000019 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x00000015 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x00000009 +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0x0000000d +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x00000014 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x00000013 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x00000010 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000fffL +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x00000000 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00ff0000L +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x00000010 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000fffL +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x00000000 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00ff0000L +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x00000010 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000fffL +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x00000000 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00ff0000L +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x00000010 +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000fffL +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x00000000 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffffL +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x00000000 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffffL +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x00000000 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffffL +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x00000000 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffffL +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x00000000 +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffffL +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x00000000 +#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffffL +#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x00000000 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00ffffffL +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x00000000 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x00000018 +#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffffL +#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x00000000 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x00000040L +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x00000006 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x00000020L +#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x00000005 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x00000400L +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0x0000000a +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x00000080L +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x00000007 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x00000200L +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x00000009 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x00000010L +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x00000004 +#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x00000000 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x00000004L +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x00000002 +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x00000800L +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0x0000000b +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x00001000L +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0x0000000c +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x00000100L +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x00000008 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x00000008L +#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x00000003 +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x00000040L +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x00000006 +#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x00000020L +#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x00000005 +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x00000400L +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0x0000000a +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x00000080L +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x00000007 +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x00000200L +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x00000009 +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x00000010L +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x00000004 +#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x00000001L +#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x00000000 +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001 +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x00000004L +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x00000002 +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x00000800L +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0x0000000b +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x00001000L +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0x0000000c +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x00000100L +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x00000008 +#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x00000008L +#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x00000003 +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x00000040L +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x00000006 +#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x00000020L +#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x00000005 +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x00000400L +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0x0000000a +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x00000080L +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x00000007 +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x00000200L +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x00000009 +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x00000010L +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x00000004 +#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x00000001L +#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x00000000 +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x00000001 +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x00000004L +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x00000002 +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x00000800L +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0x0000000b +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x00001000L +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0x0000000c +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x00000100L +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x00000008 +#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x00000008L +#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x00000003 +#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F3__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F4__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F5__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F6__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffffL +#define PCIE_STRAP_F7__RESERVED__SHIFT 0x00000000 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x00000080L +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x00000007 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x0000007fL +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x00000000 +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x00000002L +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x00000001 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x00000008L +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x00000003 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x00000002 +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x00000018 +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x02000000L +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x00000019 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x04000000L +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x0000001a +#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000L +#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x0000001e +#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0x0000000fL +#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x00000000 +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x00001f00L +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x00000008 +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x0000001d +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x00002000L +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x0000000d +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x00008000L +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x0000000f +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x00004000L +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0x0000000e +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000L +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x0000001c +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x00000001L +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x00000000 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000L +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x0000001d +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000L +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x0000001c +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000fffL +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0x0000000c +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x00000000 +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x00000016 +#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L +#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x00000014 +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x00000017 +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0x0000000f +#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L +#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x00000015 +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0x0000000e +#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0x0000000c +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000c00L +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0x0000000a +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x00000008 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x00000018 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x00000004 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x00000014 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000fffL +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00ff0000L +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x00000014 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x00000015 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x00000012 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x00000013 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x00000010 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x00000011 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x00000004 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x00000005 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x00000002 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x00000003 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x00000000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x00000001 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffffL +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x00000000 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffffL +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x00000000 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffffL +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x00000000 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffffL +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x00000000 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L +#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x00000000 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000L +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0x0000000f +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x00000010 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000ff00L +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x00000008 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000f8L +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x00000003 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x00000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x0000001f +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000L +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x00000018 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x0000001e +#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0fff0000L +#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x00000010 +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000fffL +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x00000000 +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00ffffffL +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x00000000 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x00000003 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x00000000 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x00000002 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x00000001 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x00000006 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x00000004 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x00000005 +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000fffffL +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x00000000 +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x0000001f +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000fffffL +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x00000000 +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000fffffL +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x00000000 +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x0000001f +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000fffffL +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x00000000 +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000fffffL +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x00000000 +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x0000001f +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000fffffL +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x00000000 +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000fffffL +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x00000000 +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x0000001f +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000fffffL +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x00000000 +#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000L +#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x00000010 +#define PEER_REG_RANGE0__START_ADDR_MASK 0x0000ffffL +#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x00000000 +#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000L +#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x00000010 +#define PEER_REG_RANGE1__START_ADDR_MASK 0x0000ffffL +#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x00000000 +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x00000010L +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x00000004 +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x00000020L +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x00000005 +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x00000002L +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x00000001 +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x00000008L +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x00000003 +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x00000001L +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x00000000 +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x00000004L +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x00000002 +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0x0000000eL +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x00000001 +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x00100000L +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x00000014 +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x00007c00L +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0x0000000a +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x00008000L +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0x0000000f +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x0000001fL +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x00000000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x000001e0L +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x00000005 +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000L +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x00000019 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x00000001L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x00000000 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x00001000L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0x0000000c +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x00000004L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x00000002 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x00000800L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0x0000000b +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x00000002L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x00000001 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x00000200L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x00000009 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x00000020L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x00000005 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x00000040L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x00000006 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x00000080L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x00000007 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x00000100L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x00000008 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x00000018L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x00000003 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x00000400L +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0x0000000a +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x00000001L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x00000000 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x00001000L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0x0000000c +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x00000004L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x00000002 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x00000800L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0x0000000b +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x00000002L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x00000001 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x00000200L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x00000009 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x00000020L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x00000005 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x00000040L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x00000006 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x00000080L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x00000007 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x00000100L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x00000008 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x00000018L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x00000003 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x00000400L +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0x0000000a +#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffffL +#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h index 09a7df17570d..09a7df17570d 100755..100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h index 1ddc4183a1c9..1ddc4183a1c9 100755..100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h new file mode 100644 index 000000000000..ae798f768853 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h @@ -0,0 +1,4457 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_6_0_D_H +#define DCE_6_0_D_H + +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000A +#define ixATTR0B 0x000B +#define ixATTR0C 0x000C +#define ixATTR0D 0x000D +#define ixATTR0E 0x000E +#define ixATTR0F 0x000F +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR10 0x000B +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR11 0x000C +#define ixAUDIO_DESCRIPTOR12 0x000D +#define ixAUDIO_DESCRIPTOR13 0x000E +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000A +#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002A +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002B +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002C +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002D +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002E +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002F +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003A +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003B +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003C +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003D +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003E +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003F +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005A +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005B +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005C +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005D +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005E +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005F +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270D +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270E +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273E +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2F09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2F0B +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2F0A +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17FF +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1F05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1F0F +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1F0B +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1F04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1F0A +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377B +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377A +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371C +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371D +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371E +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371F +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3F09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3F0C +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3F0E +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0F02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0F04 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0F00 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378A +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378B +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378C +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378D +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378E +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378F +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZALIA_STREAM_DEBUG 0x0005 +#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000A +#define ixCRT0B 0x000B +#define ixCRT0C 0x000C +#define ixCRT0D 0x000D +#define ixCRT0E 0x000E +#define ixCRT0F 0x000F +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001E +#define ixCRT1F 0x001F +#define ixCRT22 0x0022 +#define ixDCIO_DEBUG10 0x0010 +#define ixDCIO_DEBUG1 0x0001 +#define ixDCIO_DEBUG11 0x0011 +#define ixDCIO_DEBUG12 0x0012 +#define ixDCIO_DEBUG13 0x0013 +#define ixDCIO_DEBUG2 0x0002 +#define ixDCIO_DEBUG3 0x0003 +#define ixDCIO_DEBUG4 0x0004 +#define ixDCIO_DEBUG5 0x0005 +#define ixDCIO_DEBUG6 0x0006 +#define ixDCIO_DEBUG7 0x0007 +#define ixDCIO_DEBUG8 0x0008 +#define ixDCIO_DEBUG9 0x0009 +#define ixDCIO_DEBUGA 0x000A +#define ixDCIO_DEBUGB 0x000B +#define ixDCIO_DEBUGC 0x000C +#define ixDCIO_DEBUGD 0x000D +#define ixDCIO_DEBUGE 0x000E +#define ixDCIO_DEBUGF 0x000F +#define ixDCIO_DEBUG_ID 0x0000 +#define ixDMIF_DEBUG02_CORE0 0x0002 +#define ixDMIF_DEBUG02_CORE1 0x000A +#define ixDP_AUX1_DEBUG_A 0x0010 +#define ixDP_AUX1_DEBUG_B 0x0011 +#define ixDP_AUX1_DEBUG_C 0x0012 +#define ixDP_AUX1_DEBUG_D 0x0013 +#define ixDP_AUX1_DEBUG_E 0x0014 +#define ixDP_AUX1_DEBUG_F 0x0015 +#define ixDP_AUX1_DEBUG_G 0x0016 +#define ixDP_AUX1_DEBUG_H 0x0017 +#define ixDP_AUX1_DEBUG_I 0x0018 +#define ixDP_AUX2_DEBUG_A 0x0020 +#define ixDP_AUX2_DEBUG_B 0x0021 +#define ixDP_AUX2_DEBUG_C 0x0022 +#define ixDP_AUX2_DEBUG_D 0x0023 +#define ixDP_AUX2_DEBUG_E 0x0024 +#define ixDP_AUX2_DEBUG_F 0x0025 +#define ixDP_AUX2_DEBUG_G 0x0026 +#define ixDP_AUX2_DEBUG_H 0x0027 +#define ixDP_AUX2_DEBUG_I 0x0028 +#define ixDP_AUX3_DEBUG_A 0x0030 +#define ixDP_AUX3_DEBUG_B 0x0031 +#define ixDP_AUX3_DEBUG_C 0x0032 +#define ixDP_AUX3_DEBUG_D 0x0033 +#define ixDP_AUX3_DEBUG_E 0x0034 +#define ixDP_AUX3_DEBUG_F 0x0035 +#define ixDP_AUX3_DEBUG_G 0x0036 +#define ixDP_AUX3_DEBUG_H 0x0037 +#define ixDP_AUX3_DEBUG_I 0x0038 +#define ixDP_AUX4_DEBUG_A 0x0040 +#define ixDP_AUX4_DEBUG_B 0x0041 +#define ixDP_AUX4_DEBUG_C 0x0042 +#define ixDP_AUX4_DEBUG_D 0x0043 +#define ixDP_AUX4_DEBUG_E 0x0044 +#define ixDP_AUX4_DEBUG_F 0x0045 +#define ixDP_AUX4_DEBUG_G 0x0046 +#define ixDP_AUX4_DEBUG_H 0x0047 +#define ixDP_AUX4_DEBUG_I 0x0048 +#define ixDP_AUX5_DEBUG_A 0x0070 +#define ixDP_AUX5_DEBUG_B 0x0071 +#define ixDP_AUX5_DEBUG_C 0x0072 +#define ixDP_AUX5_DEBUG_D 0x0073 +#define ixDP_AUX5_DEBUG_E 0x0074 +#define ixDP_AUX5_DEBUG_F 0x0075 +#define ixDP_AUX5_DEBUG_G 0x0076 +#define ixDP_AUX5_DEBUG_H 0x0077 +#define ixDP_AUX5_DEBUG_I 0x0078 +#define ixDP_AUX6_DEBUG_A 0x0080 +#define ixDP_AUX6_DEBUG_B 0x0081 +#define ixDP_AUX6_DEBUG_C 0x0082 +#define ixDP_AUX6_DEBUG_D 0x0083 +#define ixDP_AUX6_DEBUG_E 0x0084 +#define ixDP_AUX6_DEBUG_F 0x0085 +#define ixDP_AUX6_DEBUG_G 0x0086 +#define ixDP_AUX6_DEBUG_H 0x0087 +#define ixDP_AUX6_DEBUG_I 0x0088 +#define ixFMT_DEBUG0 0x0001 +#define ixFMT_DEBUG1 0x0002 +#define ixFMT_DEBUG2 0x0003 +#define ixFMT_DEBUG_ID 0x0000 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 +#define ixIDDCCIF02_DBG_DCCIF_C 0x0009 +#define ixIDDCCIF04_DBG_DCCIF_E 0x000B +#define ixIDDCCIF05_DBG_DCCIF_F 0x000C +#define ixMVP_DEBUG_12 0x000C +#define ixMVP_DEBUG_13 0x000D +#define ixMVP_DEBUG_14 0x000E +#define ixMVP_DEBUG_15 0x000F +#define ixMVP_DEBUG_16 0x0010 +#define ixMVP_DEBUG_17 0x0011 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION10 0x000F +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000A +#define ixSINK_DESCRIPTION6 0x000B +#define ixSINK_DESCRIPTION7 0x000C +#define ixSINK_DESCRIPTION8 0x000D +#define ixSINK_DESCRIPTION9 0x000E +#define ixVGADCC_DBG_DCCIF_C 0x007E +#define mmABM_TEST_DEBUG_DATA 0x169F +#define mmABM_TEST_DEBUG_INDEX 0x169E +#define mmAFMT_60958_0 0x1C41 +#define mmAFMT_60958_1 0x1C42 +#define mmAFMT_60958_2 0x1C48 +#define mmAFMT_AUDIO_CRC_CONTROL 0x1C43 +#define mmAFMT_AUDIO_CRC_RESULT 0x1C49 +#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1C52 +#define mmAFMT_AUDIO_INFO0 0x1C3F +#define mmAFMT_AUDIO_INFO1 0x1C40 +#define mmAFMT_AUDIO_PACKET_CONTROL 0x1C4B +#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1C17 +#define mmAFMT_AUDIO_SRC_CONTROL 0x1C4F +#define mmAFMT_AVI_INFO0 0x1C21 +#define mmAFMT_AVI_INFO1 0x1C22 +#define mmAFMT_AVI_INFO2 0x1C23 +#define mmAFMT_AVI_INFO3 0x1C24 +#define mmAFMT_GENERIC_0 0x1C28 +#define mmAFMT_GENERIC_1 0x1C29 +#define mmAFMT_GENERIC_2 0x1C2A +#define mmAFMT_GENERIC_3 0x1C2B +#define mmAFMT_GENERIC_4 0x1C2C +#define mmAFMT_GENERIC_5 0x1C2D +#define mmAFMT_GENERIC_6 0x1C2E +#define mmAFMT_GENERIC_7 0x1C2F +#define mmAFMT_GENERIC_HDR 0x1C27 +#define mmAFMT_INFOFRAME_CONTROL0 0x1C4D +#define mmAFMT_INTERRUPT_STATUS 0x1C14 +#define mmAFMT_ISRC1_0 0x1C18 +#define mmAFMT_ISRC1_1 0x1C19 +#define mmAFMT_ISRC1_2 0x1C1A +#define mmAFMT_ISRC1_3 0x1C1B +#define mmAFMT_ISRC1_4 0x1C1C +#define mmAFMT_ISRC2_0 0x1C1D +#define mmAFMT_ISRC2_1 0x1C1E +#define mmAFMT_ISRC2_2 0x1C1F +#define mmAFMT_ISRC2_3 0x1C20 +#define mmAFMT_MPEG_INFO0 0x1C25 +#define mmAFMT_MPEG_INFO1 0x1C26 +#define mmAFMT_RAMP_CONTROL0 0x1C44 +#define mmAFMT_RAMP_CONTROL1 0x1C45 +#define mmAFMT_RAMP_CONTROL2 0x1C46 +#define mmAFMT_RAMP_CONTROL3 0x1C47 +#define mmAFMT_STATUS 0x1C4A +#define mmAFMT_VBI_PACKET_CONTROL 0x1C4C +#define mmATTRDR 0x00F0 +#define mmATTRDW 0x00F0 +#define mmATTRX 0x00F0 +#define mmAUX_ARB_CONTROL 0x1882 +#define mmAUX_CONTROL 0x1880 +#define mmAUX_DPHY_RX_CONTROL0 0x188A +#define mmAUX_DPHY_RX_CONTROL1 0x188B +#define mmAUX_DPHY_RX_STATUS 0x188D +#define mmAUX_DPHY_TX_CONTROL 0x1889 +#define mmAUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmAUX_DPHY_TX_STATUS 0x188C +#define mmAUX_GTC_SYNC_CONTROL 0x188E +#define mmAUX_GTC_SYNC_DATA 0x1890 +#define mmAUX_INTERRUPT_CONTROL 0x1883 +#define mmAUX_LS_DATA 0x1887 +#define mmAUX_LS_STATUS 0x1885 +#define mmAUXN_IMPCAL 0x190C +#define mmAUXP_IMPCAL 0x190B +#define mmAUX_SW_CONTROL 0x1881 +#define mmAUX_SW_DATA 0x1886 +#define mmAUX_SW_STATUS 0x1884 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17C9 +#define mmAZALIA_AUDIO_DTO 0x17BA +#define mmAZALIA_AUDIO_DTO_CONTROL 0x17BB +#define mmAZALIA_BDL_DMA_CONTROL 0x17BF +#define mmAZALIA_CONTROLLER_DEBUG 0x17CF +#define mmAZALIA_CORB_DMA_CONTROL 0x17C1 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17CA +#define mmAZALIA_DATA_DMA_CONTROL 0x17BE +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17D5 +#define mmAZALIA_F0_CODEC_DEBUG 0x17DF +#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17DE +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17DB +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17DC +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17DD +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17D7 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17DA +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17D9 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17D8 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17D6 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17D3 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17D2 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x17CB +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17CC +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17CD +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0 +#define mmAZALIA_SCLK_CONTROL 0x17BC +#define mmAZALIA_STREAM_DATA 0x17E9 +#define mmAZALIA_STREAM_INDEX 0x17E8 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17BD +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178D +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178C +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179F +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179E +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17E9 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17E8 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ED +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17EC +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17F1 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17F0 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17F5 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17F4 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17F9 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17F8 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17FD +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17FC +#define mmAZ_TEST_DEBUG_DATA 0x17D1 +#define mmAZ_TEST_DEBUG_INDEX 0x17D0 +#define mmBL1_PWM_ABM_CNTL 0x162E +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162F +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162B +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162C +#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162D +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162A +#define mmBL1_PWM_USER_LEVEL 0x1629 +#define mmBL_PWM_CNTL 0x191E +#define mmBL_PWM_CNTL2 0x191F +#define mmBL_PWM_GRP1_REG_LOCK 0x1921 +#define mmBL_PWM_PERIOD_CNTL 0x1920 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19FE +#define mmBPHYC_DAC_MACRO_CNTL 0x19FD +#define mmCC_DC_PIPE_DIS 0x177F +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17D4 +#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1A43 +#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1A44 +#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1A45 +#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1A46 +#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1A47 +#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1A48 +#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1A49 +#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1A4A +#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1A4B +#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1A4C +#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1A4D +#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1A4E +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1B78 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 +#define mmCRTC0_CRTC_BLACK_COLOR 0x1BA2 +#define mmCRTC0_CRTC_BLANK_CONTROL 0x1B9D +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1BA1 +#define mmCRTC0_CRTC_CONTROL 0x1B9C +#define mmCRTC0_CRTC_COUNT_CONTROL 0x1BA9 +#define mmCRTC0_CRTC_COUNT_RESET 0x1BAA +#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1B7C +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1B92 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1B93 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x1B99 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1B98 +#define mmCRTC0_CRTC_GSL_CONTROL 0x1B7B +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1B79 +#define mmCRTC0_CRTC_GSL_WINDOW 0x1B7A +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1B7D +#define mmCRTC0_CRTC_H_BLANK_START_END 0x1B81 +#define mmCRTC0_CRTC_H_SYNC_A 0x1B82 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1B83 +#define mmCRTC0_CRTC_H_SYNC_B 0x1B84 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1B85 +#define mmCRTC0_CRTC_H_TOTAL 0x1B80 +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1B9E +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1B9F +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1BB4 +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB +#define mmCRTC0_CRTC_MASTER_EN 0x1BC2 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1BBF +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 +#define mmCRTC0_CRTC_MVP_STATUS 0x1BC1 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1BA5 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1BA0 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1BB0 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1BB2 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1BB1 +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1BAF +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1BB3 +#define mmCRTC0_CRTC_STATUS 0x1BA3 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1BA6 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1BA8 +#define mmCRTC0_CRTC_STATUS_POSITION 0x1BA4 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1BA7 +#define mmCRTC0_CRTC_STEREO_CONTROL 0x1BAE +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1B9B +#define mmCRTC0_CRTC_STEREO_STATUS 0x1BAD +#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1BC7 +#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1BC6 +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1BBC +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1BBA +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1BBB +#define mmCRTC0_CRTC_TRIGA_CNTL 0x1B94 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1B95 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x1B96 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1B97 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x1BB5 +#define mmCRTC0_CRTC_VBI_END 0x1B86 +#define mmCRTC0_CRTC_V_BLANK_START_END 0x1B8D +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1BAC +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 +#define mmCRTC0_CRTC_V_SYNC_A 0x1B8E +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1B8F +#define mmCRTC0_CRTC_V_SYNC_B 0x1B90 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1B91 +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1B8C +#define mmCRTC0_CRTC_V_TOTAL 0x1B87 +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1B8A +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1B8B +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1B89 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1B88 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1BC4 +#define mmCRTC0_DCFE_DBG_SEL 0x1B7E +#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F +#define mmCRTC0_MASTER_UPDATE_LOCK 0x1BBD +#define mmCRTC0_MASTER_UPDATE_MODE 0x1BBE +#define mmCRTC0_PIXEL_RATE_CNTL 0x0140 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1E78 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1EC3 +#define mmCRTC1_CRTC_BLACK_COLOR 0x1EA2 +#define mmCRTC1_CRTC_BLANK_CONTROL 0x1E9D +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1EA1 +#define mmCRTC1_CRTC_CONTROL 0x1E9C +#define mmCRTC1_CRTC_COUNT_CONTROL 0x1EA9 +#define mmCRTC1_CRTC_COUNT_RESET 0x1EAA +#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1E7C +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1EB6 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1E92 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1E93 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x1E99 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1E98 +#define mmCRTC1_CRTC_GSL_CONTROL 0x1E7B +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1E79 +#define mmCRTC1_CRTC_GSL_WINDOW 0x1E7A +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1E7D +#define mmCRTC1_CRTC_H_BLANK_START_END 0x1E81 +#define mmCRTC1_CRTC_H_SYNC_A 0x1E82 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1E83 +#define mmCRTC1_CRTC_H_SYNC_B 0x1E84 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1E85 +#define mmCRTC1_CRTC_H_TOTAL 0x1E80 +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1E9E +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1E9F +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1EB4 +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1EAB +#define mmCRTC1_CRTC_MASTER_EN 0x1EC2 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1EBF +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1EC0 +#define mmCRTC1_CRTC_MVP_STATUS 0x1EC1 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1EA5 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1EA0 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1EB0 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1EB2 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1EB1 +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1EAF +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1EB3 +#define mmCRTC1_CRTC_STATUS 0x1EA3 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1EA6 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1EA8 +#define mmCRTC1_CRTC_STATUS_POSITION 0x1EA4 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1EA7 +#define mmCRTC1_CRTC_STEREO_CONTROL 0x1EAE +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1E9B +#define mmCRTC1_CRTC_STEREO_STATUS 0x1EAD +#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1EC7 +#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1EC6 +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1EBC +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1EBA +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1EBB +#define mmCRTC1_CRTC_TRIGA_CNTL 0x1E94 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1E95 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x1E96 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1E97 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x1EB5 +#define mmCRTC1_CRTC_VBI_END 0x1E86 +#define mmCRTC1_CRTC_V_BLANK_START_END 0x1E8D +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1EAC +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1EB7 +#define mmCRTC1_CRTC_V_SYNC_A 0x1E8E +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1E8F +#define mmCRTC1_CRTC_V_SYNC_B 0x1E90 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1E91 +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1E8C +#define mmCRTC1_CRTC_V_TOTAL 0x1E87 +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1E8A +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1E8B +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1E89 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1E88 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1EC4 +#define mmCRTC1_DCFE_DBG_SEL 0x1E7E +#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1E7F +#define mmCRTC1_MASTER_UPDATE_LOCK 0x1EBD +#define mmCRTC1_MASTER_UPDATE_MODE 0x1EBE +#define mmCRTC1_PIXEL_RATE_CNTL 0x0144 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41C3 +#define mmCRTC2_CRTC_BLACK_COLOR 0x41A2 +#define mmCRTC2_CRTC_BLANK_CONTROL 0x419D +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41A1 +#define mmCRTC2_CRTC_CONTROL 0x419C +#define mmCRTC2_CRTC_COUNT_CONTROL 0x41A9 +#define mmCRTC2_CRTC_COUNT_RESET 0x41AA +#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417C +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41B6 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define mmCRTC2_CRTC_GSL_CONTROL 0x417B +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 +#define mmCRTC2_CRTC_GSL_WINDOW 0x417A +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417D +#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 +#define mmCRTC2_CRTC_H_SYNC_A 0x4182 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 +#define mmCRTC2_CRTC_H_SYNC_B 0x4184 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 +#define mmCRTC2_CRTC_H_TOTAL 0x4180 +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419E +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419F +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41B4 +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41AB +#define mmCRTC2_CRTC_MASTER_EN 0x41C2 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41BF +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41C0 +#define mmCRTC2_CRTC_MVP_STATUS 0x41C1 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41A5 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41A0 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41B0 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41B2 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41B1 +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41AF +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41B3 +#define mmCRTC2_CRTC_STATUS 0x41A3 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41A6 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41A8 +#define mmCRTC2_CRTC_STATUS_POSITION 0x41A4 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41A7 +#define mmCRTC2_CRTC_STEREO_CONTROL 0x41AE +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419B +#define mmCRTC2_CRTC_STEREO_STATUS 0x41AD +#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41C7 +#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41C6 +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41BC +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41BA +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41BB +#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x41B5 +#define mmCRTC2_CRTC_VBI_END 0x4186 +#define mmCRTC2_CRTC_V_BLANK_START_END 0x418D +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41AC +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41B7 +#define mmCRTC2_CRTC_V_SYNC_A 0x418E +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418F +#define mmCRTC2_CRTC_V_SYNC_B 0x4190 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418C +#define mmCRTC2_CRTC_V_TOTAL 0x4187 +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418A +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418B +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41C4 +#define mmCRTC2_DCFE_DBG_SEL 0x417E +#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417F +#define mmCRTC2_MASTER_UPDATE_LOCK 0x41BD +#define mmCRTC2_MASTER_UPDATE_MODE 0x41BE +#define mmCRTC2_PIXEL_RATE_CNTL 0x0148 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44C3 +#define mmCRTC3_CRTC_BLACK_COLOR 0x44A2 +#define mmCRTC3_CRTC_BLANK_CONTROL 0x449D +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44A1 +#define mmCRTC3_CRTC_CONTROL 0x449C +#define mmCRTC3_CRTC_COUNT_CONTROL 0x44A9 +#define mmCRTC3_CRTC_COUNT_RESET 0x44AA +#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447C +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44B6 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 +#define mmCRTC3_CRTC_GSL_CONTROL 0x447B +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 +#define mmCRTC3_CRTC_GSL_WINDOW 0x447A +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447D +#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 +#define mmCRTC3_CRTC_H_SYNC_A 0x4482 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 +#define mmCRTC3_CRTC_H_SYNC_B 0x4484 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 +#define mmCRTC3_CRTC_H_TOTAL 0x4480 +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449E +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449F +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44B4 +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44AB +#define mmCRTC3_CRTC_MASTER_EN 0x44C2 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44BF +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44C0 +#define mmCRTC3_CRTC_MVP_STATUS 0x44C1 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44A5 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44A0 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44B0 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44B2 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44B1 +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44AF +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44B3 +#define mmCRTC3_CRTC_STATUS 0x44A3 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44A6 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44A8 +#define mmCRTC3_CRTC_STATUS_POSITION 0x44A4 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44A7 +#define mmCRTC3_CRTC_STEREO_CONTROL 0x44AE +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449B +#define mmCRTC3_CRTC_STEREO_STATUS 0x44AD +#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44C7 +#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44C6 +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44BC +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44BA +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44BB +#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x44B5 +#define mmCRTC3_CRTC_VBI_END 0x4486 +#define mmCRTC3_CRTC_V_BLANK_START_END 0x448D +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44AC +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44B7 +#define mmCRTC3_CRTC_V_SYNC_A 0x448E +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448F +#define mmCRTC3_CRTC_V_SYNC_B 0x4490 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448C +#define mmCRTC3_CRTC_V_TOTAL 0x4487 +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448A +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448B +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44C4 +#define mmCRTC3_DCFE_DBG_SEL 0x447E +#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447F +#define mmCRTC_3D_STRUCTURE_CONTROL 0x1B78 +#define mmCRTC3_MASTER_UPDATE_LOCK 0x44BD +#define mmCRTC3_MASTER_UPDATE_MODE 0x44BE +#define mmCRTC3_PIXEL_RATE_CNTL 0x014C +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47C3 +#define mmCRTC4_CRTC_BLACK_COLOR 0x47A2 +#define mmCRTC4_CRTC_BLANK_CONTROL 0x479D +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47A1 +#define mmCRTC4_CRTC_CONTROL 0x479C +#define mmCRTC4_CRTC_COUNT_CONTROL 0x47A9 +#define mmCRTC4_CRTC_COUNT_RESET 0x47AA +#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477C +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47B6 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 +#define mmCRTC4_CRTC_GSL_CONTROL 0x477B +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 +#define mmCRTC4_CRTC_GSL_WINDOW 0x477A +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477D +#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 +#define mmCRTC4_CRTC_H_SYNC_A 0x4782 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 +#define mmCRTC4_CRTC_H_SYNC_B 0x4784 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 +#define mmCRTC4_CRTC_H_TOTAL 0x4780 +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479E +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479F +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47B4 +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47AB +#define mmCRTC4_CRTC_MASTER_EN 0x47C2 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47BF +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47C0 +#define mmCRTC4_CRTC_MVP_STATUS 0x47C1 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47A5 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47A0 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47B0 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47B2 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47B1 +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47AF +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47B3 +#define mmCRTC4_CRTC_STATUS 0x47A3 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47A6 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47A8 +#define mmCRTC4_CRTC_STATUS_POSITION 0x47A4 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47A7 +#define mmCRTC4_CRTC_STEREO_CONTROL 0x47AE +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479B +#define mmCRTC4_CRTC_STEREO_STATUS 0x47AD +#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47C7 +#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47C6 +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47BC +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47BA +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47BB +#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x47B5 +#define mmCRTC4_CRTC_VBI_END 0x4786 +#define mmCRTC4_CRTC_V_BLANK_START_END 0x478D +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47AC +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47B7 +#define mmCRTC4_CRTC_V_SYNC_A 0x478E +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478F +#define mmCRTC4_CRTC_V_SYNC_B 0x4790 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478C +#define mmCRTC4_CRTC_V_TOTAL 0x4787 +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478A +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478B +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47C4 +#define mmCRTC4_DCFE_DBG_SEL 0x477E +#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477F +#define mmCRTC4_MASTER_UPDATE_LOCK 0x47BD +#define mmCRTC4_MASTER_UPDATE_MODE 0x47BE +#define mmCRTC4_PIXEL_RATE_CNTL 0x0150 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4A78 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4AC3 +#define mmCRTC5_CRTC_BLACK_COLOR 0x4AA2 +#define mmCRTC5_CRTC_BLANK_CONTROL 0x4A9D +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4AA1 +#define mmCRTC5_CRTC_CONTROL 0x4A9C +#define mmCRTC5_CRTC_COUNT_CONTROL 0x4AA9 +#define mmCRTC5_CRTC_COUNT_RESET 0x4AAA +#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4A7C +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4AB6 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4A92 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4A93 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x4A99 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4A98 +#define mmCRTC5_CRTC_GSL_CONTROL 0x4A7B +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4A79 +#define mmCRTC5_CRTC_GSL_WINDOW 0x4A7A +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4A7D +#define mmCRTC5_CRTC_H_BLANK_START_END 0x4A81 +#define mmCRTC5_CRTC_H_SYNC_A 0x4A82 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4A83 +#define mmCRTC5_CRTC_H_SYNC_B 0x4A84 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4A85 +#define mmCRTC5_CRTC_H_TOTAL 0x4A80 +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4A9E +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4A9F +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4AB4 +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4AAB +#define mmCRTC5_CRTC_MASTER_EN 0x4AC2 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4ABF +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4AC0 +#define mmCRTC5_CRTC_MVP_STATUS 0x4AC1 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4AA5 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4AA0 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4AB0 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4AB2 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4AB1 +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4AAF +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4AB3 +#define mmCRTC5_CRTC_STATUS 0x4AA3 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4AA6 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4AA8 +#define mmCRTC5_CRTC_STATUS_POSITION 0x4AA4 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4AA7 +#define mmCRTC5_CRTC_STEREO_CONTROL 0x4AAE +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4A9B +#define mmCRTC5_CRTC_STEREO_STATUS 0x4AAD +#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4AC7 +#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4AC6 +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4ABC +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4ABA +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4ABB +#define mmCRTC5_CRTC_TRIGA_CNTL 0x4A94 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4A95 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x4A96 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4A97 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x4AB5 +#define mmCRTC5_CRTC_VBI_END 0x4A86 +#define mmCRTC5_CRTC_V_BLANK_START_END 0x4A8D +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4AAC +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4AB7 +#define mmCRTC5_CRTC_V_SYNC_A 0x4A8E +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4A8F +#define mmCRTC5_CRTC_V_SYNC_B 0x4A90 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4A91 +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4A8C +#define mmCRTC5_CRTC_V_TOTAL 0x4A87 +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4A8A +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4A8B +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4A89 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4A88 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4AC4 +#define mmCRTC5_DCFE_DBG_SEL 0x4A7E +#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4A7F +#define mmCRTC5_MASTER_UPDATE_LOCK 0x4ABD +#define mmCRTC5_MASTER_UPDATE_MODE 0x4ABE +#define mmCRTC5_PIXEL_RATE_CNTL 0x0154 +#define mmCRTC8_DATA 0x00ED +#define mmCRTC8_IDX 0x00ED +#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 +#define mmCRTC_BLACK_COLOR 0x1BA2 +#define mmCRTC_BLANK_CONTROL 0x1B9D +#define mmCRTC_BLANK_DATA_COLOR 0x1BA1 +#define mmCRTC_CONTROL 0x1B9C +#define mmCRTC_COUNT_CONTROL 0x1BA9 +#define mmCRTC_COUNT_RESET 0x1BAA +#define mmCRTC_DCFE_CLOCK_CONTROL 0x1B7C +#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 +#define mmCRTC_DTMTEST_CNTL 0x1B92 +#define mmCRTC_DTMTEST_STATUS_POSITION 0x1B93 +#define mmCRTC_FLOW_CONTROL 0x1B99 +#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1B98 +#define mmCRTC_GSL_CONTROL 0x1B7B +#define mmCRTC_GSL_VSYNC_GAP 0x1B79 +#define mmCRTC_GSL_WINDOW 0x1B7A +#define mmCRTC_H_BLANK_EARLY_NUM 0x1B7D +#define mmCRTC_H_BLANK_START_END 0x1B81 +#define mmCRTC_H_SYNC_A 0x1B82 +#define mmCRTC_H_SYNC_A_CNTL 0x1B83 +#define mmCRTC_H_SYNC_B 0x1B84 +#define mmCRTC_H_SYNC_B_CNTL 0x1B85 +#define mmCRTC_H_TOTAL 0x1B80 +#define mmCRTC_INTERLACE_CONTROL 0x1B9E +#define mmCRTC_INTERLACE_STATUS 0x1B9F +#define mmCRTC_INTERRUPT_CONTROL 0x1BB4 +#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB +#define mmCRTC_MASTER_EN 0x1BC2 +#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1BBF +#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 +#define mmCRTC_MVP_STATUS 0x1BC1 +#define mmCRTC_NOM_VERT_POSITION 0x1BA5 +#define mmCRTC_OVERSCAN_COLOR 0x1BA0 +#define mmCRTC_SNAPSHOT_CONTROL 0x1BB0 +#define mmCRTC_SNAPSHOT_FRAME 0x1BB2 +#define mmCRTC_SNAPSHOT_POSITION 0x1BB1 +#define mmCRTC_SNAPSHOT_STATUS 0x1BAF +#define mmCRTC_START_LINE_CONTROL 0x1BB3 +#define mmCRTC_STATUS 0x1BA3 +#define mmCRTC_STATUS_FRAME_COUNT 0x1BA6 +#define mmCRTC_STATUS_HV_COUNT 0x1BA8 +#define mmCRTC_STATUS_POSITION 0x1BA4 +#define mmCRTC_STATUS_VF_COUNT 0x1BA7 +#define mmCRTC_STEREO_CONTROL 0x1BAE +#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1B9B +#define mmCRTC_STEREO_STATUS 0x1BAD +#define mmCRTC_TEST_DEBUG_DATA 0x1BC7 +#define mmCRTC_TEST_DEBUG_INDEX 0x1BC6 +#define mmCRTC_TEST_PATTERN_COLOR 0x1BBC +#define mmCRTC_TEST_PATTERN_CONTROL 0x1BBA +#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1BBB +#define mmCRTC_TRIGA_CNTL 0x1B94 +#define mmCRTC_TRIGA_MANUAL_TRIG 0x1B95 +#define mmCRTC_TRIGB_CNTL 0x1B96 +#define mmCRTC_TRIGB_MANUAL_TRIG 0x1B97 +#define mmCRTC_UPDATE_LOCK 0x1BB5 +#define mmCRTC_VBI_END 0x1B86 +#define mmCRTC_V_BLANK_START_END 0x1B8D +#define mmCRTC_VERT_SYNC_CONTROL 0x1BAC +#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 +#define mmCRTC_V_SYNC_A 0x1B8E +#define mmCRTC_V_SYNC_A_CNTL 0x1B8F +#define mmCRTC_V_SYNC_B 0x1B90 +#define mmCRTC_V_SYNC_B_CNTL 0x1B91 +#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1B8C +#define mmCRTC_V_TOTAL 0x1B87 +#define mmCRTC_V_TOTAL_CONTROL 0x1B8A +#define mmCRTC_V_TOTAL_INT_STATUS 0x1B8B +#define mmCRTC_V_TOTAL_MAX 0x1B89 +#define mmCRTC_V_TOTAL_MIN 0x1B88 +#define mmCRTC_V_UPDATE_INT_STATUS 0x1BC4 +#define mmCUR_COLOR1 0x1A6C +#define mmCUR_COLOR2 0x1A6D +#define mmCUR_CONTROL 0x1A66 +#define mmCUR_HOT_SPOT 0x1A6B +#define mmCUR_POSITION 0x1A6A +#define mmCUR_REQUEST_FILTER_CNTL 0x1A99 +#define mmCUR_SIZE 0x1A68 +#define mmCUR_SURFACE_ADDRESS 0x1A67 +#define mmCUR_SURFACE_ADDRESS_HIGH 0x1A69 +#define mmCUR_UPDATE 0x1A6E +#define mmD1VGA_CONTROL 0x00CC +#define mmD2VGA_CONTROL 0x00CE +#define mmD3VGA_CONTROL 0x00F8 +#define mmD4VGA_CONTROL 0x00F9 +#define mmD5VGA_CONTROL 0x00FA +#define mmD6VGA_CONTROL 0x00FB +#define mmDAC_AUTODETECT_CONTROL 0x19EE +#define mmDAC_AUTODETECT_CONTROL2 0x19EF +#define mmDAC_AUTODETECT_CONTROL3 0x19F0 +#define mmDAC_AUTODETECT_INT_CONTROL 0x19F2 +#define mmDAC_AUTODETECT_STATUS 0x19F1 +#define mmDAC_CLK_ENABLE 0x0128 +#define mmDAC_COMPARATOR_ENABLE 0x19F7 +#define mmDAC_COMPARATOR_OUTPUT 0x19F8 +#define mmDAC_CONTROL 0x19F6 +#define mmDAC_CRC_CONTROL 0x19E7 +#define mmDAC_CRC_EN 0x19E6 +#define mmDAC_CRC_SIG_CONTROL 0x19EB +#define mmDAC_CRC_SIG_CONTROL_MASK 0x19E9 +#define mmDAC_CRC_SIG_RGB 0x19EA +#define mmDAC_CRC_SIG_RGB_MASK 0x19E8 +#define mmDAC_DATA 0x00F2 +#define mmDAC_DFT_CONFIG 0x19FA +#define mmDAC_ENABLE 0x19E4 +#define mmDAC_FIFO_STATUS 0x19FB +#define mmDAC_FORCE_DATA 0x19F4 +#define mmDAC_FORCE_OUTPUT_CNTL 0x19F3 +#define mmDAC_MACRO_CNTL_RESERVED0 0x19FC +#define mmDAC_MACRO_CNTL_RESERVED1 0x19FD +#define mmDAC_MACRO_CNTL_RESERVED2 0x19FE +#define mmDAC_MACRO_CNTL_RESERVED3 0x19FF +#define mmDAC_MASK 0x00F1 +#define mmDAC_POWERDOWN 0x19F5 +#define mmDAC_PWR_CNTL 0x19F9 +#define mmDAC_R_INDEX 0x00F1 +#define mmDAC_SOURCE_SELECT 0x19E5 +#define mmDAC_STEREOSYNC_SELECT 0x19ED +#define mmDAC_SYNC_TRISTATE_CONTROL 0x19EC +#define mmDAC_W_INDEX 0x00F2 +#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163A +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163B +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163C +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163D +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163E +#define mmDC_ABM1_ACE_THRES_12 0x163F +#define mmDC_ABM1_ACE_THRES_34 0x1640 +#define mmDC_ABM1_BL_MASTER_LOCK 0x169C +#define mmDC_ABM1_CNTL 0x1638 +#define mmDC_ABM1_DEBUG_MISC 0x1649 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165A +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164A +#define mmDC_ABM1_HG_MISC_CTRL 0x164B +#define mmDC_ABM1_HG_RESULT_10 0x1664 +#define mmDC_ABM1_HG_RESULT_1 0x165B +#define mmDC_ABM1_HG_RESULT_11 0x1665 +#define mmDC_ABM1_HG_RESULT_12 0x1666 +#define mmDC_ABM1_HG_RESULT_13 0x1667 +#define mmDC_ABM1_HG_RESULT_14 0x1668 +#define mmDC_ABM1_HG_RESULT_15 0x1669 +#define mmDC_ABM1_HG_RESULT_16 0x166A +#define mmDC_ABM1_HG_RESULT_17 0x166B +#define mmDC_ABM1_HG_RESULT_18 0x166C +#define mmDC_ABM1_HG_RESULT_19 0x166D +#define mmDC_ABM1_HG_RESULT_20 0x166E +#define mmDC_ABM1_HG_RESULT_2 0x165C +#define mmDC_ABM1_HG_RESULT_21 0x166F +#define mmDC_ABM1_HG_RESULT_22 0x1670 +#define mmDC_ABM1_HG_RESULT_23 0x1671 +#define mmDC_ABM1_HG_RESULT_24 0x1672 +#define mmDC_ABM1_HG_RESULT_3 0x165D +#define mmDC_ABM1_HG_RESULT_4 0x165E +#define mmDC_ABM1_HG_RESULT_5 0x165F +#define mmDC_ABM1_HG_RESULT_6 0x1660 +#define mmDC_ABM1_HG_RESULT_7 0x1661 +#define mmDC_ABM1_HG_RESULT_8 0x1662 +#define mmDC_ABM1_HG_RESULT_9 0x1663 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164E +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164D +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define mmDC_ABM1_LS_PIXEL_COUNT 0x164F +#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164C +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169B +#define mmDCCG_AUDIO_DTO0_MODULE 0x016D +#define mmDCCG_AUDIO_DTO0_PHASE 0x016C +#define mmDCCG_AUDIO_DTO1_MODULE 0x0171 +#define mmDCCG_AUDIO_DTO1_PHASE 0x0170 +#define mmDCCG_AUDIO_DTO_SOURCE 0x016B +#define mmDCCG_CAC_STATUS 0x0137 +#define mmDCCG_GATE_DISABLE_CNTL 0x0134 +#define mmDCCG_GTC_CNTL 0x0120 +#define mmDCCG_GTC_CURRENT 0x0123 +#define mmDCCG_GTC_DTO_MODULO 0x0122 +#define mmDCCG_PERFMON_CNTL 0x0133 +#define mmDCCG_PLL0_PLL_ANALOG 0x1708 +#define mmDCCG_PLL0_PLL_CNTL 0x1707 +#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170B +#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170F +#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170E +#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 +#define mmDCCG_PLL0_PLL_FB_DIV 0x1701 +#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 +#define mmDCCG_PLL0_PLL_POST_DIV 0x1702 +#define mmDCCG_PLL0_PLL_REF_DIV 0x1700 +#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 +#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170A +#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170D +#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170C +#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 +#define mmDCCG_PLL1_PLL_ANALOG 0x1718 +#define mmDCCG_PLL1_PLL_CNTL 0x1717 +#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171B +#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x171F +#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x171E +#define mmDCCG_PLL1_PLL_DS_CNTL 0x1715 +#define mmDCCG_PLL1_PLL_FB_DIV 0x1711 +#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x1716 +#define mmDCCG_PLL1_PLL_POST_DIV 0x1712 +#define mmDCCG_PLL1_PLL_REF_DIV 0x1710 +#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1713 +#define mmDCCG_PLL1_PLL_SS_CNTL 0x1714 +#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171A +#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x171D +#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x171C +#define mmDCCG_PLL1_PLL_VREG_CNTL 0x1719 +#define mmDCCG_PLL2_PLL_ANALOG 0x1728 +#define mmDCCG_PLL2_PLL_CNTL 0x1727 +#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x172B +#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x172F +#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x172E +#define mmDCCG_PLL2_PLL_DS_CNTL 0x1725 +#define mmDCCG_PLL2_PLL_FB_DIV 0x1721 +#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x1726 +#define mmDCCG_PLL2_PLL_POST_DIV 0x1722 +#define mmDCCG_PLL2_PLL_REF_DIV 0x1720 +#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1723 +#define mmDCCG_PLL2_PLL_SS_CNTL 0x1724 +#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x172A +#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x172D +#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x172C +#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1729 +#define mmDCCG_SOFT_RESET 0x015F +#define mmDCCG_TEST_CLK_SEL 0x017E +#define mmDCCG_TEST_DEBUG_DATA 0x017D +#define mmDCCG_TEST_DEBUG_INDEX 0x017C +#define mmDCCG_VPCLK_CNTL 0x031F +#define mmDCDEBUG_BUS_CLK1_SEL 0x1860 +#define mmDCDEBUG_BUS_CLK2_SEL 0x1861 +#define mmDCDEBUG_BUS_CLK3_SEL 0x1862 +#define mmDCDEBUG_BUS_CLK4_SEL 0x1863 +#define mmDCDEBUG_OUT_CNTL 0x186B +#define mmDCDEBUG_OUT_DATA 0x186E +#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186A +#define mmDC_DMCU_SCRATCH 0x1618 +#define mmDC_DVODATA_CONFIG 0x1905 +#define mmDCFE0_SOFT_RESET 0x0158 +#define mmDCFE1_SOFT_RESET 0x0159 +#define mmDCFE2_SOFT_RESET 0x015A +#define mmDCFE3_SOFT_RESET 0x015B +#define mmDCFE4_SOFT_RESET 0x015C +#define mmDCFE5_SOFT_RESET 0x015D +#define mmDCFE_DBG_SEL 0x1B7E +#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F +#define mmDC_GENERICA 0x1900 +#define mmDC_GENERICB 0x1901 +#define mmDC_GPIO_DDC1_A 0x194D +#define mmDC_GPIO_DDC1_EN 0x194E +#define mmDC_GPIO_DDC1_MASK 0x194C +#define mmDC_GPIO_DDC1_Y 0x194F +#define mmDC_GPIO_DDC2_A 0x1951 +#define mmDC_GPIO_DDC2_EN 0x1952 +#define mmDC_GPIO_DDC2_MASK 0x1950 +#define mmDC_GPIO_DDC2_Y 0x1953 +#define mmDC_GPIO_DDC3_A 0x1955 +#define mmDC_GPIO_DDC3_EN 0x1956 +#define mmDC_GPIO_DDC3_MASK 0x1954 +#define mmDC_GPIO_DDC3_Y 0x1957 +#define mmDC_GPIO_DDC4_A 0x1959 +#define mmDC_GPIO_DDC4_EN 0x195A +#define mmDC_GPIO_DDC4_MASK 0x1958 +#define mmDC_GPIO_DDC4_Y 0x195B +#define mmDC_GPIO_DDC5_A 0x195D +#define mmDC_GPIO_DDC5_EN 0x195E +#define mmDC_GPIO_DDC5_MASK 0x195C +#define mmDC_GPIO_DDC5_Y 0x195F +#define mmDC_GPIO_DDC6_A 0x1961 +#define mmDC_GPIO_DDC6_EN 0x1962 +#define mmDC_GPIO_DDC6_MASK 0x1960 +#define mmDC_GPIO_DDC6_Y 0x1963 +#define mmDC_GPIO_DDCVGA_A 0x1971 +#define mmDC_GPIO_DDCVGA_EN 0x1972 +#define mmDC_GPIO_DDCVGA_MASK 0x1970 +#define mmDC_GPIO_DDCVGA_Y 0x1973 +#define mmDC_GPIO_DEBUG 0x1904 +#define mmDC_GPIO_DVODATA_A 0x1949 +#define mmDC_GPIO_DVODATA_EN 0x194A +#define mmDC_GPIO_DVODATA_MASK 0x1948 +#define mmDC_GPIO_DVODATA_Y 0x194B +#define mmDC_GPIO_GENERIC_A 0x1945 +#define mmDC_GPIO_GENERIC_EN 0x1946 +#define mmDC_GPIO_GENERIC_MASK 0x1944 +#define mmDC_GPIO_GENERIC_Y 0x1947 +#define mmDC_GPIO_GENLK_A 0x1969 +#define mmDC_GPIO_GENLK_EN 0x196A +#define mmDC_GPIO_GENLK_MASK 0x1968 +#define mmDC_GPIO_GENLK_Y 0x196B +#define mmDC_GPIO_HPD_A 0x196D +#define mmDC_GPIO_HPD_EN 0x196E +#define mmDC_GPIO_HPD_MASK 0x196C +#define mmDC_GPIO_HPD_Y 0x196F +#define mmDC_GPIO_I2CPAD_A 0x1975 +#define mmDC_GPIO_I2CPAD_EN 0x1976 +#define mmDC_GPIO_I2CPAD_MASK 0x1974 +#define mmDC_GPIO_I2CPAD_STRENGTH 0x197A +#define mmDC_GPIO_I2CPAD_Y 0x1977 +#define mmDC_GPIO_PAD_STRENGTH_1 0x1978 +#define mmDC_GPIO_PAD_STRENGTH_2 0x1979 +#define mmDC_GPIO_PWRSEQ_A 0x1941 +#define mmDC_GPIO_PWRSEQ_EN 0x1942 +#define mmDC_GPIO_PWRSEQ_MASK 0x1940 +#define mmDC_GPIO_PWRSEQ_Y 0x1943 +#define mmDC_GPIO_SYNCA_A 0x1965 +#define mmDC_GPIO_SYNCA_EN 0x1966 +#define mmDC_GPIO_SYNCA_MASK 0x1964 +#define mmDC_GPIO_SYNCA_Y 0x1967 +#define mmDC_GPU_TIMER_READ 0x1929 +#define mmDC_GPU_TIMER_READ_CNTL 0x192A +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 +#define mmDC_HPD1_CONTROL 0x1809 +#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 +#define mmDC_HPD1_INT_CONTROL 0x1808 +#define mmDC_HPD1_INT_STATUS 0x1807 +#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18BC +#define mmDC_HPD2_CONTROL 0x180C +#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 +#define mmDC_HPD2_INT_CONTROL 0x180B +#define mmDC_HPD2_INT_STATUS 0x180A +#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18BD +#define mmDC_HPD3_CONTROL 0x180F +#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 +#define mmDC_HPD3_INT_CONTROL 0x180E +#define mmDC_HPD3_INT_STATUS 0x180D +#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18BE +#define mmDC_HPD4_CONTROL 0x1812 +#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 +#define mmDC_HPD4_INT_CONTROL 0x1811 +#define mmDC_HPD4_INT_STATUS 0x1810 +#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18FC +#define mmDC_HPD5_CONTROL 0x1815 +#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 +#define mmDC_HPD5_INT_CONTROL 0x1814 +#define mmDC_HPD5_INT_STATUS 0x1813 +#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18FD +#define mmDC_HPD6_CONTROL 0x1818 +#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 +#define mmDC_HPD6_INT_CONTROL 0x1817 +#define mmDC_HPD6_INT_STATUS 0x1816 +#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18FE +#define mmDC_I2C_ARBITRATION 0x181A +#define mmDC_I2C_CONTROL 0x1819 +#define mmDC_I2C_DATA 0x1833 +#define mmDC_I2C_DDC1_HW_STATUS 0x181D +#define mmDC_I2C_DDC1_SETUP 0x1824 +#define mmDC_I2C_DDC1_SPEED 0x1823 +#define mmDC_I2C_DDC2_HW_STATUS 0x181E +#define mmDC_I2C_DDC2_SETUP 0x1826 +#define mmDC_I2C_DDC2_SPEED 0x1825 +#define mmDC_I2C_DDC3_HW_STATUS 0x181F +#define mmDC_I2C_DDC3_SETUP 0x1828 +#define mmDC_I2C_DDC3_SPEED 0x1827 +#define mmDC_I2C_DDC4_HW_STATUS 0x1820 +#define mmDC_I2C_DDC4_SETUP 0x182A +#define mmDC_I2C_DDC4_SPEED 0x1829 +#define mmDC_I2C_DDC5_HW_STATUS 0x1821 +#define mmDC_I2C_DDC5_SETUP 0x182C +#define mmDC_I2C_DDC5_SPEED 0x182B +#define mmDC_I2C_DDC6_HW_STATUS 0x1822 +#define mmDC_I2C_DDC6_SETUP 0x182E +#define mmDC_I2C_DDC6_SPEED 0x182D +#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 +#define mmDC_I2C_DDCVGA_SETUP 0x1857 +#define mmDC_I2C_DDCVGA_SPEED 0x1856 +#define mmDC_I2C_EDID_DETECT_CTRL 0x186F +#define mmDC_I2C_INTERRUPT_CONTROL 0x181B +#define mmDC_I2C_SW_STATUS 0x181C +#define mmDC_I2C_TRANSACTION0 0x182F +#define mmDC_I2C_TRANSACTION1 0x1830 +#define mmDC_I2C_TRANSACTION2 0x1831 +#define mmDC_I2C_TRANSACTION3 0x1832 +#define mmDCI_CLK_CNTL 0x031E +#define mmDCI_CLK_RAMP_CNTL 0x0324 +#define mmDCI_DEBUG_CONFIG 0x0323 +#define mmDCI_MEM_PWR_CNTL 0x0326 +#define mmDCI_MEM_PWR_STATE 0x031B +#define mmDCI_MEM_PWR_STATE2 0x0322 +#define mmDCIO_DEBUG 0x192E +#define mmDCIO_GSL0_CNTL 0x1924 +#define mmDCIO_GSL1_CNTL 0x1925 +#define mmDCIO_GSL2_CNTL 0x1926 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 +#define mmDCIO_IMPCAL_CNTL_AB 0x190D +#define mmDCIO_IMPCAL_CNTL_CD 0x1911 +#define mmDCIO_IMPCAL_CNTL_EF 0x1915 +#define mmDCIO_TEST_DEBUG_DATA 0x1930 +#define mmDCIO_TEST_DEBUG_INDEX 0x192F +#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198C +#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198E +#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198A +#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198D +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 +#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198B +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 +#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199C +#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199E +#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199A +#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199D +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 +#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 +#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199B +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 +#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19AC +#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19AE +#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19AA +#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19AD +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19A6 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19A7 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19A5 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19A9 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19A8 +#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19A4 +#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19AB +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19A0 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19A1 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19A2 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19A3 +#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19BC +#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19BE +#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19BA +#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19BD +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19B6 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19B7 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19B5 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19B9 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19B8 +#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19B4 +#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19BB +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19B0 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19B1 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19B2 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19B3 +#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19CC +#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19CE +#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19CA +#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19CD +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19C6 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19C7 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19C5 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19C9 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19C8 +#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19C4 +#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19CB +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19C0 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19C1 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19C2 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19C3 +#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19DC +#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19DE +#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19DA +#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19DD +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19D6 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19D7 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19D5 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19D9 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19D8 +#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19D4 +#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19DB +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19D0 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19D1 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19D2 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19D3 +#define mmDCI_SOFT_RESET 0x015E +#define mmDCI_TEST_DEBUG_DATA 0x0321 +#define mmDCI_TEST_DEBUG_INDEX 0x0320 +#define mmDC_LUT_30_COLOR 0x1A7C +#define mmDC_LUT_AUTOFILL 0x1A7F +#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1A81 +#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1A82 +#define mmDC_LUT_BLACK_OFFSET_RED 0x1A83 +#define mmDC_LUT_CONTROL 0x1A80 +#define mmDC_LUT_PWL_DATA 0x1A7B +#define mmDC_LUT_RW_INDEX 0x1A79 +#define mmDC_LUT_RW_MODE 0x1A78 +#define mmDC_LUT_SEQ_COLOR 0x1A7A +#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1A7D +#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1A84 +#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1A85 +#define mmDC_LUT_WHITE_OFFSET_RED 0x1A86 +#define mmDC_LUT_WRITE_EN_MASK 0x1A7E +#define mmDC_MVP_LB_CONTROL 0x1ADB +#define mmDCO_CLK_CNTL 0x192B +#define mmDCO_CLK_RAMP_CNTL 0x192C +#define mmDCO_LIGHT_SLEEP_DIS 0x1907 +#define mmDCO_MEM_POWER_STATE 0x1906 +#define mmDCO_SOFT_RESET 0x0167 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1A43 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1A44 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1A45 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1A46 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1A47 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1A48 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1A49 +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1A4A +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1A4B +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1A4C +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1A4D +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1A4E +#define mmDCP0_CUR_COLOR1 0x1A6C +#define mmDCP0_CUR_COLOR2 0x1A6D +#define mmDCP0_CUR_CONTROL 0x1A66 +#define mmDCP0_CUR_HOT_SPOT 0x1A6B +#define mmDCP0_CUR_POSITION 0x1A6A +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1A99 +#define mmDCP0_CUR_SIZE 0x1A68 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x1A67 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1A69 +#define mmDCP0_CUR_UPDATE 0x1A6E +#define mmDCP0_DC_LUT_30_COLOR 0x1A7C +#define mmDCP0_DC_LUT_AUTOFILL 0x1A7F +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1A81 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1A82 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1A83 +#define mmDCP0_DC_LUT_CONTROL 0x1A80 +#define mmDCP0_DC_LUT_PWL_DATA 0x1A7B +#define mmDCP0_DC_LUT_RW_INDEX 0x1A79 +#define mmDCP0_DC_LUT_RW_MODE 0x1A78 +#define mmDCP0_DC_LUT_SEQ_COLOR 0x1A7A +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1A7D +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1A84 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1A85 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1A86 +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1A7E +#define mmDCP0_DCP_CRC_CONTROL 0x1A87 +#define mmDCP0_DCP_CRC_CURRENT 0x1A89 +#define mmDCP0_DCP_CRC_LAST 0x1A8B +#define mmDCP0_DCP_CRC_MASK 0x1A88 +#define mmDCP0_DCP_DEBUG 0x1A8D +#define mmDCP0_DCP_DEBUG2 0x1A98 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1A65 +#define mmDCP0_DCP_GSL_CONTROL 0x1A90 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 +#define mmDCP0_DCP_RANDOM_SEEDS 0x1A61 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1A60 +#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1A96 +#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1A95 +#define mmDCP0_DEGAMMA_CONTROL 0x1A58 +#define mmDCP0_DENORM_CONTROL 0x1A50 +#define mmDCP0_GAMUT_REMAP_C11_C12 0x1A5A +#define mmDCP0_GAMUT_REMAP_C13_C14 0x1A5B +#define mmDCP0_GAMUT_REMAP_C21_C22 0x1A5C +#define mmDCP0_GAMUT_REMAP_C23_C24 0x1A5D +#define mmDCP0_GAMUT_REMAP_C31_C32 0x1A5E +#define mmDCP0_GAMUT_REMAP_C33_C34 0x1A5F +#define mmDCP0_GAMUT_REMAP_CONTROL 0x1A59 +#define mmDCP0_GRPH_COMPRESS_PITCH 0x1A1A +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B +#define mmDCP0_GRPH_CONTROL 0x1A01 +#define mmDCP0_GRPH_DFQ_CONTROL 0x1A14 +#define mmDCP0_GRPH_DFQ_STATUS 0x1A15 +#define mmDCP0_GRPH_ENABLE 0x1A00 +#define mmDCP0_GRPH_FLIP_CONTROL 0x1A12 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1A17 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1A16 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1A02 +#define mmDCP0_GRPH_PITCH 0x1A06 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1A97 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1A13 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1A09 +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1A0A +#define mmDCP0_GRPH_SWAP_CNTL 0x1A03 +#define mmDCP0_GRPH_UPDATE 0x1A11 +#define mmDCP0_GRPH_X_END 0x1A0D +#define mmDCP0_GRPH_X_START 0x1A0B +#define mmDCP0_GRPH_Y_END 0x1A0E +#define mmDCP0_GRPH_Y_START 0x1A0C +#define mmDCP0_INPUT_CSC_C11_C12 0x1A36 +#define mmDCP0_INPUT_CSC_C13_C14 0x1A37 +#define mmDCP0_INPUT_CSC_C21_C22 0x1A38 +#define mmDCP0_INPUT_CSC_C23_C24 0x1A39 +#define mmDCP0_INPUT_CSC_C31_C32 0x1A3A +#define mmDCP0_INPUT_CSC_C33_C34 0x1A3B +#define mmDCP0_INPUT_CSC_CONTROL 0x1A35 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x1A10 +#define mmDCP0_KEY_CONTROL 0x1A53 +#define mmDCP0_KEY_RANGE_ALPHA 0x1A54 +#define mmDCP0_KEY_RANGE_BLUE 0x1A57 +#define mmDCP0_KEY_RANGE_GREEN 0x1A56 +#define mmDCP0_KEY_RANGE_RED 0x1A55 +#define mmDCP0_OUTPUT_CSC_C11_C12 0x1A3D +#define mmDCP0_OUTPUT_CSC_C13_C14 0x1A3E +#define mmDCP0_OUTPUT_CSC_C21_C22 0x1A3F +#define mmDCP0_OUTPUT_CSC_C23_C24 0x1A40 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x1A41 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x1A42 +#define mmDCP0_OUTPUT_CSC_CONTROL 0x1A3C +#define mmDCP0_OUT_ROUND_CONTROL 0x1A51 +#define mmDCP0_OVL_CONTROL1 0x1A1D +#define mmDCP0_OVL_CONTROL2 0x1A1E +#define mmDCP0_OVL_DFQ_CONTROL 0x1A29 +#define mmDCP0_OVL_DFQ_STATUS 0x1A2A +#define mmDCP0_OVL_ENABLE 0x1A1C +#define mmDCP0_OVL_END 0x1A26 +#define mmDCP0_OVL_PITCH 0x1A21 +#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1A2C +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1A92 +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 +#define mmDCP0_OVL_START 0x1A25 +#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1A93 +#define mmDCP0_OVL_SURFACE_ADDRESS 0x1A20 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1A22 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B +#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1A28 +#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1A23 +#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1A24 +#define mmDCP0_OVL_SWAP_CNTL 0x1A1F +#define mmDCP0_OVL_UPDATE 0x1A27 +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1A2D +#define mmDCP0_PRESCALE_OVL_CONTROL 0x1A31 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1A30 +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1A2F +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1A2E +#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1A32 +#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1A34 +#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1A33 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1AA6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1AA7 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1AA8 +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1AAD +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1AAE +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1AAF +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1AA9 +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1AAA +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1AAB +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1AAC +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1AA4 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1AB2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1AB3 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1AB4 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1AB9 +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1ABA +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1ABB +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1AB5 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1AB6 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1AB7 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1AB8 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1AB0 +#define mmDCP0_REGAMMA_CONTROL 0x1AA0 +#define mmDCP0_REGAMMA_LUT_DATA 0x1AA2 +#define mmDCP0_REGAMMA_LUT_INDEX 0x1AA1 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1AA3 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1D43 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1D44 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1D45 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1D46 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1D47 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1D48 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1D49 +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1D4A +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1D4B +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1D4C +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1D4D +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1D4E +#define mmDCP1_CUR_COLOR1 0x1D6C +#define mmDCP1_CUR_COLOR2 0x1D6D +#define mmDCP1_CUR_CONTROL 0x1D66 +#define mmDCP1_CUR_HOT_SPOT 0x1D6B +#define mmDCP1_CUR_POSITION 0x1D6A +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1D99 +#define mmDCP1_CUR_SIZE 0x1D68 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x1D67 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1D69 +#define mmDCP1_CUR_UPDATE 0x1D6E +#define mmDCP1_DC_LUT_30_COLOR 0x1D7C +#define mmDCP1_DC_LUT_AUTOFILL 0x1D7F +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1D81 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1D82 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1D83 +#define mmDCP1_DC_LUT_CONTROL 0x1D80 +#define mmDCP1_DC_LUT_PWL_DATA 0x1D7B +#define mmDCP1_DC_LUT_RW_INDEX 0x1D79 +#define mmDCP1_DC_LUT_RW_MODE 0x1D78 +#define mmDCP1_DC_LUT_SEQ_COLOR 0x1D7A +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1D7D +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1D84 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1D85 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1D86 +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1D7E +#define mmDCP1_DCP_CRC_CONTROL 0x1D87 +#define mmDCP1_DCP_CRC_CURRENT 0x1D89 +#define mmDCP1_DCP_CRC_LAST 0x1D8B +#define mmDCP1_DCP_CRC_MASK 0x1D88 +#define mmDCP1_DCP_DEBUG 0x1D8D +#define mmDCP1_DCP_DEBUG2 0x1D98 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1D65 +#define mmDCP1_DCP_GSL_CONTROL 0x1D90 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1D91 +#define mmDCP1_DCP_RANDOM_SEEDS 0x1D61 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1D60 +#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1D96 +#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1D95 +#define mmDCP1_DEGAMMA_CONTROL 0x1D58 +#define mmDCP1_DENORM_CONTROL 0x1D50 +#define mmDCP1_GAMUT_REMAP_C11_C12 0x1D5A +#define mmDCP1_GAMUT_REMAP_C13_C14 0x1D5B +#define mmDCP1_GAMUT_REMAP_C21_C22 0x1D5C +#define mmDCP1_GAMUT_REMAP_C23_C24 0x1D5D +#define mmDCP1_GAMUT_REMAP_C31_C32 0x1D5E +#define mmDCP1_GAMUT_REMAP_C33_C34 0x1D5F +#define mmDCP1_GAMUT_REMAP_CONTROL 0x1D59 +#define mmDCP1_GRPH_COMPRESS_PITCH 0x1D1A +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1D19 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1D1B +#define mmDCP1_GRPH_CONTROL 0x1D01 +#define mmDCP1_GRPH_DFQ_CONTROL 0x1D14 +#define mmDCP1_GRPH_DFQ_STATUS 0x1D15 +#define mmDCP1_GRPH_ENABLE 0x1D00 +#define mmDCP1_GRPH_FLIP_CONTROL 0x1D12 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1D17 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1D16 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1D02 +#define mmDCP1_GRPH_PITCH 0x1D06 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1D04 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1D07 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1D05 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D08 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1D97 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1D18 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1D13 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1D09 +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1D0A +#define mmDCP1_GRPH_SWAP_CNTL 0x1D03 +#define mmDCP1_GRPH_UPDATE 0x1D11 +#define mmDCP1_GRPH_X_END 0x1D0D +#define mmDCP1_GRPH_X_START 0x1D0B +#define mmDCP1_GRPH_Y_END 0x1D0E +#define mmDCP1_GRPH_Y_START 0x1D0C +#define mmDCP1_INPUT_CSC_C11_C12 0x1D36 +#define mmDCP1_INPUT_CSC_C13_C14 0x1D37 +#define mmDCP1_INPUT_CSC_C21_C22 0x1D38 +#define mmDCP1_INPUT_CSC_C23_C24 0x1D39 +#define mmDCP1_INPUT_CSC_C31_C32 0x1D3A +#define mmDCP1_INPUT_CSC_C33_C34 0x1D3B +#define mmDCP1_INPUT_CSC_CONTROL 0x1D35 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x1D10 +#define mmDCP1_KEY_CONTROL 0x1D53 +#define mmDCP1_KEY_RANGE_ALPHA 0x1D54 +#define mmDCP1_KEY_RANGE_BLUE 0x1D57 +#define mmDCP1_KEY_RANGE_GREEN 0x1D56 +#define mmDCP1_KEY_RANGE_RED 0x1D55 +#define mmDCP1_OUTPUT_CSC_C11_C12 0x1D3D +#define mmDCP1_OUTPUT_CSC_C13_C14 0x1D3E +#define mmDCP1_OUTPUT_CSC_C21_C22 0x1D3F +#define mmDCP1_OUTPUT_CSC_C23_C24 0x1D40 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x1D41 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x1D42 +#define mmDCP1_OUTPUT_CSC_CONTROL 0x1D3C +#define mmDCP1_OUT_ROUND_CONTROL 0x1D51 +#define mmDCP1_OVL_CONTROL1 0x1D1D +#define mmDCP1_OVL_CONTROL2 0x1D1E +#define mmDCP1_OVL_DFQ_CONTROL 0x1D29 +#define mmDCP1_OVL_DFQ_STATUS 0x1D2A +#define mmDCP1_OVL_ENABLE 0x1D1C +#define mmDCP1_OVL_END 0x1D26 +#define mmDCP1_OVL_PITCH 0x1D21 +#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1D2C +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1D92 +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D94 +#define mmDCP1_OVL_START 0x1D25 +#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1D93 +#define mmDCP1_OVL_SURFACE_ADDRESS 0x1D20 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1D22 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1D2B +#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1D28 +#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1D23 +#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1D24 +#define mmDCP1_OVL_SWAP_CNTL 0x1D1F +#define mmDCP1_OVL_UPDATE 0x1D27 +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1D2D +#define mmDCP1_PRESCALE_OVL_CONTROL 0x1D31 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1D30 +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1D2F +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1D2E +#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1D32 +#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1D34 +#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1D33 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1DA6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1DA7 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1DA8 +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1DAD +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1DAE +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1DAF +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1DA9 +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1DAA +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1DAB +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1DAC +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1DA5 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1DA4 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1DB2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1DB3 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1DB4 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1DB9 +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1DBA +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1DBB +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1DB5 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1DB6 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1DB7 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1DB8 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1DB1 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1DB0 +#define mmDCP1_REGAMMA_CONTROL 0x1DA0 +#define mmDCP1_REGAMMA_LUT_DATA 0x1DA2 +#define mmDCP1_REGAMMA_LUT_INDEX 0x1DA1 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1DA3 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404A +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404B +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404C +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404D +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404E +#define mmDCP2_CUR_COLOR1 0x406C +#define mmDCP2_CUR_COLOR2 0x406D +#define mmDCP2_CUR_CONTROL 0x4066 +#define mmDCP2_CUR_HOT_SPOT 0x406B +#define mmDCP2_CUR_POSITION 0x406A +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 +#define mmDCP2_CUR_SIZE 0x4068 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define mmDCP2_CUR_UPDATE 0x406E +#define mmDCP2_DC_LUT_30_COLOR 0x407C +#define mmDCP2_DC_LUT_AUTOFILL 0x407F +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define mmDCP2_DC_LUT_CONTROL 0x4080 +#define mmDCP2_DC_LUT_PWL_DATA 0x407B +#define mmDCP2_DC_LUT_RW_INDEX 0x4079 +#define mmDCP2_DC_LUT_RW_MODE 0x4078 +#define mmDCP2_DC_LUT_SEQ_COLOR 0x407A +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407D +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407E +#define mmDCP2_DCP_CRC_CONTROL 0x4087 +#define mmDCP2_DCP_CRC_CURRENT 0x4089 +#define mmDCP2_DCP_CRC_LAST 0x408B +#define mmDCP2_DCP_CRC_MASK 0x4088 +#define mmDCP2_DCP_DEBUG 0x408D +#define mmDCP2_DCP_DEBUG2 0x4098 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 +#define mmDCP2_DCP_GSL_CONTROL 0x4090 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define mmDCP2_DCP_RANDOM_SEEDS 0x4061 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 +#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 +#define mmDCP2_DEGAMMA_CONTROL 0x4058 +#define mmDCP2_DENORM_CONTROL 0x4050 +#define mmDCP2_GAMUT_REMAP_C11_C12 0x405A +#define mmDCP2_GAMUT_REMAP_C13_C14 0x405B +#define mmDCP2_GAMUT_REMAP_C21_C22 0x405C +#define mmDCP2_GAMUT_REMAP_C23_C24 0x405D +#define mmDCP2_GAMUT_REMAP_C31_C32 0x405E +#define mmDCP2_GAMUT_REMAP_C33_C34 0x405F +#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 +#define mmDCP2_GRPH_COMPRESS_PITCH 0x401A +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401B +#define mmDCP2_GRPH_CONTROL 0x4001 +#define mmDCP2_GRPH_DFQ_CONTROL 0x4014 +#define mmDCP2_GRPH_DFQ_STATUS 0x4015 +#define mmDCP2_GRPH_ENABLE 0x4000 +#define mmDCP2_GRPH_FLIP_CONTROL 0x4012 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 +#define mmDCP2_GRPH_PITCH 0x4006 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400A +#define mmDCP2_GRPH_SWAP_CNTL 0x4003 +#define mmDCP2_GRPH_UPDATE 0x4011 +#define mmDCP2_GRPH_X_END 0x400D +#define mmDCP2_GRPH_X_START 0x400B +#define mmDCP2_GRPH_Y_END 0x400E +#define mmDCP2_GRPH_Y_START 0x400C +#define mmDCP2_INPUT_CSC_C11_C12 0x4036 +#define mmDCP2_INPUT_CSC_C13_C14 0x4037 +#define mmDCP2_INPUT_CSC_C21_C22 0x4038 +#define mmDCP2_INPUT_CSC_C23_C24 0x4039 +#define mmDCP2_INPUT_CSC_C31_C32 0x403A +#define mmDCP2_INPUT_CSC_C33_C34 0x403B +#define mmDCP2_INPUT_CSC_CONTROL 0x4035 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 +#define mmDCP2_KEY_CONTROL 0x4053 +#define mmDCP2_KEY_RANGE_ALPHA 0x4054 +#define mmDCP2_KEY_RANGE_BLUE 0x4057 +#define mmDCP2_KEY_RANGE_GREEN 0x4056 +#define mmDCP2_KEY_RANGE_RED 0x4055 +#define mmDCP2_OUTPUT_CSC_C11_C12 0x403D +#define mmDCP2_OUTPUT_CSC_C13_C14 0x403E +#define mmDCP2_OUTPUT_CSC_C21_C22 0x403F +#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 +#define mmDCP2_OUTPUT_CSC_CONTROL 0x403C +#define mmDCP2_OUT_ROUND_CONTROL 0x4051 +#define mmDCP2_OVL_CONTROL1 0x401D +#define mmDCP2_OVL_CONTROL2 0x401E +#define mmDCP2_OVL_DFQ_CONTROL 0x4029 +#define mmDCP2_OVL_DFQ_STATUS 0x402A +#define mmDCP2_OVL_ENABLE 0x401C +#define mmDCP2_OVL_END 0x4026 +#define mmDCP2_OVL_PITCH 0x4021 +#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402C +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 +#define mmDCP2_OVL_START 0x4025 +#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 +#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402B +#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 +#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 +#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 +#define mmDCP2_OVL_SWAP_CNTL 0x401F +#define mmDCP2_OVL_UPDATE 0x4027 +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402D +#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402F +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402E +#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 +#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 +#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40A6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40A7 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40A8 +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40AD +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40AE +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40AF +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40A9 +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40AA +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40AB +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40AC +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40A5 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40A4 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40B2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40B3 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40B4 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40B9 +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40BA +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40BB +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40B5 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40B6 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40B7 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40B8 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40B1 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40B0 +#define mmDCP2_REGAMMA_CONTROL 0x40A0 +#define mmDCP2_REGAMMA_LUT_DATA 0x40A2 +#define mmDCP2_REGAMMA_LUT_INDEX 0x40A1 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40A3 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434A +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434B +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434C +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434D +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434E +#define mmDCP3_CUR_COLOR1 0x436C +#define mmDCP3_CUR_COLOR2 0x436D +#define mmDCP3_CUR_CONTROL 0x4366 +#define mmDCP3_CUR_HOT_SPOT 0x436B +#define mmDCP3_CUR_POSITION 0x436A +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 +#define mmDCP3_CUR_SIZE 0x4368 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 +#define mmDCP3_CUR_UPDATE 0x436E +#define mmDCP3_DC_LUT_30_COLOR 0x437C +#define mmDCP3_DC_LUT_AUTOFILL 0x437F +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 +#define mmDCP3_DC_LUT_CONTROL 0x4380 +#define mmDCP3_DC_LUT_PWL_DATA 0x437B +#define mmDCP3_DC_LUT_RW_INDEX 0x4379 +#define mmDCP3_DC_LUT_RW_MODE 0x4378 +#define mmDCP3_DC_LUT_SEQ_COLOR 0x437A +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437D +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437E +#define mmDCP3_DCP_CRC_CONTROL 0x4387 +#define mmDCP3_DCP_CRC_CURRENT 0x4389 +#define mmDCP3_DCP_CRC_LAST 0x438B +#define mmDCP3_DCP_CRC_MASK 0x4388 +#define mmDCP3_DCP_DEBUG 0x438D +#define mmDCP3_DCP_DEBUG2 0x4398 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 +#define mmDCP3_DCP_GSL_CONTROL 0x4390 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 +#define mmDCP3_DCP_RANDOM_SEEDS 0x4361 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 +#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 +#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 +#define mmDCP3_DEGAMMA_CONTROL 0x4358 +#define mmDCP3_DENORM_CONTROL 0x4350 +#define mmDCP3_GAMUT_REMAP_C11_C12 0x435A +#define mmDCP3_GAMUT_REMAP_C13_C14 0x435B +#define mmDCP3_GAMUT_REMAP_C21_C22 0x435C +#define mmDCP3_GAMUT_REMAP_C23_C24 0x435D +#define mmDCP3_GAMUT_REMAP_C31_C32 0x435E +#define mmDCP3_GAMUT_REMAP_C33_C34 0x435F +#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 +#define mmDCP3_GRPH_COMPRESS_PITCH 0x431A +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431B +#define mmDCP3_GRPH_CONTROL 0x4301 +#define mmDCP3_GRPH_DFQ_CONTROL 0x4314 +#define mmDCP3_GRPH_DFQ_STATUS 0x4315 +#define mmDCP3_GRPH_ENABLE 0x4300 +#define mmDCP3_GRPH_FLIP_CONTROL 0x4312 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 +#define mmDCP3_GRPH_PITCH 0x4306 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430A +#define mmDCP3_GRPH_SWAP_CNTL 0x4303 +#define mmDCP3_GRPH_UPDATE 0x4311 +#define mmDCP3_GRPH_X_END 0x430D +#define mmDCP3_GRPH_X_START 0x430B +#define mmDCP3_GRPH_Y_END 0x430E +#define mmDCP3_GRPH_Y_START 0x430C +#define mmDCP3_INPUT_CSC_C11_C12 0x4336 +#define mmDCP3_INPUT_CSC_C13_C14 0x4337 +#define mmDCP3_INPUT_CSC_C21_C22 0x4338 +#define mmDCP3_INPUT_CSC_C23_C24 0x4339 +#define mmDCP3_INPUT_CSC_C31_C32 0x433A +#define mmDCP3_INPUT_CSC_C33_C34 0x433B +#define mmDCP3_INPUT_CSC_CONTROL 0x4335 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 +#define mmDCP3_KEY_CONTROL 0x4353 +#define mmDCP3_KEY_RANGE_ALPHA 0x4354 +#define mmDCP3_KEY_RANGE_BLUE 0x4357 +#define mmDCP3_KEY_RANGE_GREEN 0x4356 +#define mmDCP3_KEY_RANGE_RED 0x4355 +#define mmDCP3_OUTPUT_CSC_C11_C12 0x433D +#define mmDCP3_OUTPUT_CSC_C13_C14 0x433E +#define mmDCP3_OUTPUT_CSC_C21_C22 0x433F +#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 +#define mmDCP3_OUTPUT_CSC_CONTROL 0x433C +#define mmDCP3_OUT_ROUND_CONTROL 0x4351 +#define mmDCP3_OVL_CONTROL1 0x431D +#define mmDCP3_OVL_CONTROL2 0x431E +#define mmDCP3_OVL_DFQ_CONTROL 0x4329 +#define mmDCP3_OVL_DFQ_STATUS 0x432A +#define mmDCP3_OVL_ENABLE 0x431C +#define mmDCP3_OVL_END 0x4326 +#define mmDCP3_OVL_PITCH 0x4321 +#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432C +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 +#define mmDCP3_OVL_START 0x4325 +#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 +#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432B +#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 +#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 +#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 +#define mmDCP3_OVL_SWAP_CNTL 0x431F +#define mmDCP3_OVL_UPDATE 0x4327 +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432D +#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432F +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432E +#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 +#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 +#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43A6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43A7 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43A8 +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43AD +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43AE +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43AF +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43A9 +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43AA +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43AB +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43AC +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43A5 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43A4 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43B2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43B3 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43B4 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43B9 +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43BA +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43BB +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43B5 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43B6 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43B7 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43B8 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43B1 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43B0 +#define mmDCP3_REGAMMA_CONTROL 0x43A0 +#define mmDCP3_REGAMMA_LUT_DATA 0x43A2 +#define mmDCP3_REGAMMA_LUT_INDEX 0x43A1 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43A3 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464A +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464B +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464C +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464D +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464E +#define mmDCP4_CUR_COLOR1 0x466C +#define mmDCP4_CUR_COLOR2 0x466D +#define mmDCP4_CUR_CONTROL 0x4666 +#define mmDCP4_CUR_HOT_SPOT 0x466B +#define mmDCP4_CUR_POSITION 0x466A +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 +#define mmDCP4_CUR_SIZE 0x4668 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 +#define mmDCP4_CUR_UPDATE 0x466E +#define mmDCP4_DC_LUT_30_COLOR 0x467C +#define mmDCP4_DC_LUT_AUTOFILL 0x467F +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 +#define mmDCP4_DC_LUT_CONTROL 0x4680 +#define mmDCP4_DC_LUT_PWL_DATA 0x467B +#define mmDCP4_DC_LUT_RW_INDEX 0x4679 +#define mmDCP4_DC_LUT_RW_MODE 0x4678 +#define mmDCP4_DC_LUT_SEQ_COLOR 0x467A +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467D +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467E +#define mmDCP4_DCP_CRC_CONTROL 0x4687 +#define mmDCP4_DCP_CRC_CURRENT 0x4689 +#define mmDCP4_DCP_CRC_LAST 0x468B +#define mmDCP4_DCP_CRC_MASK 0x4688 +#define mmDCP4_DCP_DEBUG 0x468D +#define mmDCP4_DCP_DEBUG2 0x4698 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 +#define mmDCP4_DCP_GSL_CONTROL 0x4690 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 +#define mmDCP4_DCP_RANDOM_SEEDS 0x4661 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 +#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 +#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 +#define mmDCP4_DEGAMMA_CONTROL 0x4658 +#define mmDCP4_DENORM_CONTROL 0x4650 +#define mmDCP4_GAMUT_REMAP_C11_C12 0x465A +#define mmDCP4_GAMUT_REMAP_C13_C14 0x465B +#define mmDCP4_GAMUT_REMAP_C21_C22 0x465C +#define mmDCP4_GAMUT_REMAP_C23_C24 0x465D +#define mmDCP4_GAMUT_REMAP_C31_C32 0x465E +#define mmDCP4_GAMUT_REMAP_C33_C34 0x465F +#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 +#define mmDCP4_GRPH_COMPRESS_PITCH 0x461A +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461B +#define mmDCP4_GRPH_CONTROL 0x4601 +#define mmDCP4_GRPH_DFQ_CONTROL 0x4614 +#define mmDCP4_GRPH_DFQ_STATUS 0x4615 +#define mmDCP4_GRPH_ENABLE 0x4600 +#define mmDCP4_GRPH_FLIP_CONTROL 0x4612 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 +#define mmDCP4_GRPH_PITCH 0x4606 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460A +#define mmDCP4_GRPH_SWAP_CNTL 0x4603 +#define mmDCP4_GRPH_UPDATE 0x4611 +#define mmDCP4_GRPH_X_END 0x460D +#define mmDCP4_GRPH_X_START 0x460B +#define mmDCP4_GRPH_Y_END 0x460E +#define mmDCP4_GRPH_Y_START 0x460C +#define mmDCP4_INPUT_CSC_C11_C12 0x4636 +#define mmDCP4_INPUT_CSC_C13_C14 0x4637 +#define mmDCP4_INPUT_CSC_C21_C22 0x4638 +#define mmDCP4_INPUT_CSC_C23_C24 0x4639 +#define mmDCP4_INPUT_CSC_C31_C32 0x463A +#define mmDCP4_INPUT_CSC_C33_C34 0x463B +#define mmDCP4_INPUT_CSC_CONTROL 0x4635 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 +#define mmDCP4_KEY_CONTROL 0x4653 +#define mmDCP4_KEY_RANGE_ALPHA 0x4654 +#define mmDCP4_KEY_RANGE_BLUE 0x4657 +#define mmDCP4_KEY_RANGE_GREEN 0x4656 +#define mmDCP4_KEY_RANGE_RED 0x4655 +#define mmDCP4_OUTPUT_CSC_C11_C12 0x463D +#define mmDCP4_OUTPUT_CSC_C13_C14 0x463E +#define mmDCP4_OUTPUT_CSC_C21_C22 0x463F +#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 +#define mmDCP4_OUTPUT_CSC_CONTROL 0x463C +#define mmDCP4_OUT_ROUND_CONTROL 0x4651 +#define mmDCP4_OVL_CONTROL1 0x461D +#define mmDCP4_OVL_CONTROL2 0x461E +#define mmDCP4_OVL_DFQ_CONTROL 0x4629 +#define mmDCP4_OVL_DFQ_STATUS 0x462A +#define mmDCP4_OVL_ENABLE 0x461C +#define mmDCP4_OVL_END 0x4626 +#define mmDCP4_OVL_PITCH 0x4621 +#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462C +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 +#define mmDCP4_OVL_START 0x4625 +#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 +#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462B +#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 +#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 +#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 +#define mmDCP4_OVL_SWAP_CNTL 0x461F +#define mmDCP4_OVL_UPDATE 0x4627 +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462D +#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462F +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462E +#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 +#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 +#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46A6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46A7 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46A8 +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46AD +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46AE +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46AF +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46A9 +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46AA +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46AB +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46AC +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46A5 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46A4 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46B2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46B3 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46B4 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46B9 +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46BA +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46BB +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46B5 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46B6 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46B7 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46B8 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46B1 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46B0 +#define mmDCP4_REGAMMA_CONTROL 0x46A0 +#define mmDCP4_REGAMMA_LUT_DATA 0x46A2 +#define mmDCP4_REGAMMA_LUT_INDEX 0x46A1 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46A3 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494A +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494B +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494C +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494D +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494E +#define mmDCP5_CUR_COLOR1 0x496C +#define mmDCP5_CUR_COLOR2 0x496D +#define mmDCP5_CUR_CONTROL 0x4966 +#define mmDCP5_CUR_HOT_SPOT 0x496B +#define mmDCP5_CUR_POSITION 0x496A +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 +#define mmDCP5_CUR_SIZE 0x4968 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 +#define mmDCP5_CUR_UPDATE 0x496E +#define mmDCP5_DC_LUT_30_COLOR 0x497C +#define mmDCP5_DC_LUT_AUTOFILL 0x497F +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 +#define mmDCP5_DC_LUT_CONTROL 0x4980 +#define mmDCP5_DC_LUT_PWL_DATA 0x497B +#define mmDCP5_DC_LUT_RW_INDEX 0x4979 +#define mmDCP5_DC_LUT_RW_MODE 0x4978 +#define mmDCP5_DC_LUT_SEQ_COLOR 0x497A +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497D +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497E +#define mmDCP5_DCP_CRC_CONTROL 0x4987 +#define mmDCP5_DCP_CRC_CURRENT 0x4989 +#define mmDCP5_DCP_CRC_LAST 0x498B +#define mmDCP5_DCP_CRC_MASK 0x4988 +#define mmDCP5_DCP_DEBUG 0x498D +#define mmDCP5_DCP_DEBUG2 0x4998 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 +#define mmDCP5_DCP_GSL_CONTROL 0x4990 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 +#define mmDCP5_DCP_RANDOM_SEEDS 0x4961 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 +#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 +#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 +#define mmDCP5_DEGAMMA_CONTROL 0x4958 +#define mmDCP5_DENORM_CONTROL 0x4950 +#define mmDCP5_GAMUT_REMAP_C11_C12 0x495A +#define mmDCP5_GAMUT_REMAP_C13_C14 0x495B +#define mmDCP5_GAMUT_REMAP_C21_C22 0x495C +#define mmDCP5_GAMUT_REMAP_C23_C24 0x495D +#define mmDCP5_GAMUT_REMAP_C31_C32 0x495E +#define mmDCP5_GAMUT_REMAP_C33_C34 0x495F +#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 +#define mmDCP5_GRPH_COMPRESS_PITCH 0x491A +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491B +#define mmDCP5_GRPH_CONTROL 0x4901 +#define mmDCP5_GRPH_DFQ_CONTROL 0x4914 +#define mmDCP5_GRPH_DFQ_STATUS 0x4915 +#define mmDCP5_GRPH_ENABLE 0x4900 +#define mmDCP5_GRPH_FLIP_CONTROL 0x4912 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 +#define mmDCP5_GRPH_PITCH 0x4906 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490A +#define mmDCP5_GRPH_SWAP_CNTL 0x4903 +#define mmDCP5_GRPH_UPDATE 0x4911 +#define mmDCP5_GRPH_X_END 0x490D +#define mmDCP5_GRPH_X_START 0x490B +#define mmDCP5_GRPH_Y_END 0x490E +#define mmDCP5_GRPH_Y_START 0x490C +#define mmDCP5_INPUT_CSC_C11_C12 0x4936 +#define mmDCP5_INPUT_CSC_C13_C14 0x4937 +#define mmDCP5_INPUT_CSC_C21_C22 0x4938 +#define mmDCP5_INPUT_CSC_C23_C24 0x4939 +#define mmDCP5_INPUT_CSC_C31_C32 0x493A +#define mmDCP5_INPUT_CSC_C33_C34 0x493B +#define mmDCP5_INPUT_CSC_CONTROL 0x4935 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 +#define mmDCP5_KEY_CONTROL 0x4953 +#define mmDCP5_KEY_RANGE_ALPHA 0x4954 +#define mmDCP5_KEY_RANGE_BLUE 0x4957 +#define mmDCP5_KEY_RANGE_GREEN 0x4956 +#define mmDCP5_KEY_RANGE_RED 0x4955 +#define mmDCP5_OUTPUT_CSC_C11_C12 0x493D +#define mmDCP5_OUTPUT_CSC_C13_C14 0x493E +#define mmDCP5_OUTPUT_CSC_C21_C22 0x493F +#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 +#define mmDCP5_OUTPUT_CSC_CONTROL 0x493C +#define mmDCP5_OUT_ROUND_CONTROL 0x4951 +#define mmDCP5_OVL_CONTROL1 0x491D +#define mmDCP5_OVL_CONTROL2 0x491E +#define mmDCP5_OVL_DFQ_CONTROL 0x4929 +#define mmDCP5_OVL_DFQ_STATUS 0x492A +#define mmDCP5_OVL_ENABLE 0x491C +#define mmDCP5_OVL_END 0x4926 +#define mmDCP5_OVL_PITCH 0x4921 +#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492C +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 +#define mmDCP5_OVL_START 0x4925 +#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 +#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492B +#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 +#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 +#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 +#define mmDCP5_OVL_SWAP_CNTL 0x491F +#define mmDCP5_OVL_UPDATE 0x4927 +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492D +#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492F +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492E +#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 +#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 +#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49A6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49A7 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49A8 +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49AD +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49AE +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49AF +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49A9 +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49AA +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49AB +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49AC +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49A5 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49A4 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49B2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49B3 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49B4 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49B9 +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49BA +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49BB +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49B5 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49B6 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49B7 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49B8 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49B1 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49B0 +#define mmDCP5_REGAMMA_CONTROL 0x49A0 +#define mmDCP5_REGAMMA_LUT_DATA 0x49A2 +#define mmDCP5_REGAMMA_LUT_INDEX 0x49A1 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49A3 +#define mmDC_PAD_EXTERN_SIG 0x1902 +#define mmDCP_CRC_CONTROL 0x1A87 +#define mmDCP_CRC_CURRENT 0x1A89 +#define mmDCP_CRC_LAST 0x1A8B +#define mmDCP_CRC_MASK 0x1A88 +#define mmDCP_DEBUG 0x1A8D +#define mmDCP_DEBUG2 0x1A98 +#define mmDCP_FP_CONVERTED_FIELD 0x1A65 +#define mmDC_PGCNTL_STATUS_REG 0x177E +#define mmDC_PGFSM_CONFIG_REG 0x177C +#define mmDC_PGFSM_WRITE_REG 0x177D +#define mmDCP_GSL_CONTROL 0x1A90 +#define mmDCPG_TEST_DEBUG_DATA 0x177B +#define mmDCPG_TEST_DEBUG_INDEX 0x1779 +#define mmDC_PINSTRAPS 0x1917 +#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 +#define mmDCP_RANDOM_SEEDS 0x1A61 +#define mmDCP_SPATIAL_DITHER_CNTL 0x1A60 +#define mmDCP_TEST_DEBUG_DATA 0x1A96 +#define mmDCP_TEST_DEBUG_INDEX 0x1A95 +#define mmDC_RBBMIF_RDWR_CNTL1 0x031A +#define mmDC_RBBMIF_RDWR_CNTL2 0x031D +#define mmDC_REF_CLK_CNTL 0x1903 +#define mmDC_XDMA_INTERFACE_CNTL 0x0327 +#define mmDEGAMMA_CONTROL 0x1A58 +#define mmDENORM_CONTROL 0x1A50 +#define mmDENTIST_DISPCLK_CNTL 0x0124 +#define mmDIG0_AFMT_60958_0 0x1C41 +#define mmDIG0_AFMT_60958_1 0x1C42 +#define mmDIG0_AFMT_60958_2 0x1C48 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1C43 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1C49 +#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1C52 +#define mmDIG0_AFMT_AUDIO_INFO0 0x1C3F +#define mmDIG0_AFMT_AUDIO_INFO1 0x1C40 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1C4B +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1C17 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1C4F +#define mmDIG0_AFMT_AVI_INFO0 0x1C21 +#define mmDIG0_AFMT_AVI_INFO1 0x1C22 +#define mmDIG0_AFMT_AVI_INFO2 0x1C23 +#define mmDIG0_AFMT_AVI_INFO3 0x1C24 +#define mmDIG0_AFMT_GENERIC_0 0x1C28 +#define mmDIG0_AFMT_GENERIC_1 0x1C29 +#define mmDIG0_AFMT_GENERIC_2 0x1C2A +#define mmDIG0_AFMT_GENERIC_3 0x1C2B +#define mmDIG0_AFMT_GENERIC_4 0x1C2C +#define mmDIG0_AFMT_GENERIC_5 0x1C2D +#define mmDIG0_AFMT_GENERIC_6 0x1C2E +#define mmDIG0_AFMT_GENERIC_7 0x1C2F +#define mmDIG0_AFMT_GENERIC_HDR 0x1C27 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1C4D +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1C14 +#define mmDIG0_AFMT_ISRC1_0 0x1C18 +#define mmDIG0_AFMT_ISRC1_1 0x1C19 +#define mmDIG0_AFMT_ISRC1_2 0x1C1A +#define mmDIG0_AFMT_ISRC1_3 0x1C1B +#define mmDIG0_AFMT_ISRC1_4 0x1C1C +#define mmDIG0_AFMT_ISRC2_0 0x1C1D +#define mmDIG0_AFMT_ISRC2_1 0x1C1E +#define mmDIG0_AFMT_ISRC2_2 0x1C1F +#define mmDIG0_AFMT_ISRC2_3 0x1C20 +#define mmDIG0_AFMT_MPEG_INFO0 0x1C25 +#define mmDIG0_AFMT_MPEG_INFO1 0x1C26 +#define mmDIG0_AFMT_RAMP_CONTROL0 0x1C44 +#define mmDIG0_AFMT_RAMP_CONTROL1 0x1C45 +#define mmDIG0_AFMT_RAMP_CONTROL2 0x1C46 +#define mmDIG0_AFMT_RAMP_CONTROL3 0x1C47 +#define mmDIG0_AFMT_STATUS 0x1C4A +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1C4C +#define mmDIG0_DIG_BE_CNTL 0x1C50 +#define mmDIG0_DIG_BE_EN_CNTL 0x1C51 +#define mmDIG0_DIG_CLOCK_PATTERN 0x1C03 +#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1C08 +#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1C09 +#define mmDIG0_DIG_FE_CNTL 0x1C00 +#define mmDIG0_DIG_FIFO_STATUS 0x1C0A +#define mmDIG0_DIG_LANE_ENABLE 0x1C8D +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1C01 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1C02 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1C05 +#define mmDIG0_DIG_TEST_PATTERN 0x1C04 +#define mmDIG0_HDMI_ACR_32_0 0x1C37 +#define mmDIG0_HDMI_ACR_32_1 0x1C38 +#define mmDIG0_HDMI_ACR_44_0 0x1C39 +#define mmDIG0_HDMI_ACR_44_1 0x1C3A +#define mmDIG0_HDMI_ACR_48_0 0x1C3B +#define mmDIG0_HDMI_ACR_48_1 0x1C3C +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1C0F +#define mmDIG0_HDMI_ACR_STATUS_0 0x1C3D +#define mmDIG0_HDMI_ACR_STATUS_1 0x1C3E +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1C0E +#define mmDIG0_HDMI_CONTROL 0x1C0C +#define mmDIG0_HDMI_GC 0x1C16 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1C13 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1C30 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1C11 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1C12 +#define mmDIG0_HDMI_STATUS 0x1C0D +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1C10 +#define mmDIG0_LVDS_DATA_CNTL 0x1C8C +#define mmDIG0_TMDS_CNTL 0x1C7C +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1C7E +#define mmDIG0_TMDS_CONTROL_CHAR 0x1C7D +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1C86 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1C87 +#define mmDIG0_TMDS_CTL_BITS 0x1C83 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1C84 +#define mmDIG0_TMDS_DEBUG 0x1C82 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1C7F +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 +#define mmDIG1_AFMT_60958_0 0x1F41 +#define mmDIG1_AFMT_60958_1 0x1F42 +#define mmDIG1_AFMT_60958_2 0x1F48 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1F43 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1F49 +#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1F52 +#define mmDIG1_AFMT_AUDIO_INFO0 0x1F3F +#define mmDIG1_AFMT_AUDIO_INFO1 0x1F40 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1F4B +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1F17 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1F4F +#define mmDIG1_AFMT_AVI_INFO0 0x1F21 +#define mmDIG1_AFMT_AVI_INFO1 0x1F22 +#define mmDIG1_AFMT_AVI_INFO2 0x1F23 +#define mmDIG1_AFMT_AVI_INFO3 0x1F24 +#define mmDIG1_AFMT_GENERIC_0 0x1F28 +#define mmDIG1_AFMT_GENERIC_1 0x1F29 +#define mmDIG1_AFMT_GENERIC_2 0x1F2A +#define mmDIG1_AFMT_GENERIC_3 0x1F2B +#define mmDIG1_AFMT_GENERIC_4 0x1F2C +#define mmDIG1_AFMT_GENERIC_5 0x1F2D +#define mmDIG1_AFMT_GENERIC_6 0x1F2E +#define mmDIG1_AFMT_GENERIC_7 0x1F2F +#define mmDIG1_AFMT_GENERIC_HDR 0x1F27 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1F4D +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1F14 +#define mmDIG1_AFMT_ISRC1_0 0x1F18 +#define mmDIG1_AFMT_ISRC1_1 0x1F19 +#define mmDIG1_AFMT_ISRC1_2 0x1F1A +#define mmDIG1_AFMT_ISRC1_3 0x1F1B +#define mmDIG1_AFMT_ISRC1_4 0x1F1C +#define mmDIG1_AFMT_ISRC2_0 0x1F1D +#define mmDIG1_AFMT_ISRC2_1 0x1F1E +#define mmDIG1_AFMT_ISRC2_2 0x1F1F +#define mmDIG1_AFMT_ISRC2_3 0x1F20 +#define mmDIG1_AFMT_MPEG_INFO0 0x1F25 +#define mmDIG1_AFMT_MPEG_INFO1 0x1F26 +#define mmDIG1_AFMT_RAMP_CONTROL0 0x1F44 +#define mmDIG1_AFMT_RAMP_CONTROL1 0x1F45 +#define mmDIG1_AFMT_RAMP_CONTROL2 0x1F46 +#define mmDIG1_AFMT_RAMP_CONTROL3 0x1F47 +#define mmDIG1_AFMT_STATUS 0x1F4A +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1F4C +#define mmDIG1_DIG_BE_CNTL 0x1F50 +#define mmDIG1_DIG_BE_EN_CNTL 0x1F51 +#define mmDIG1_DIG_CLOCK_PATTERN 0x1F03 +#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1F08 +#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1F09 +#define mmDIG1_DIG_FE_CNTL 0x1F00 +#define mmDIG1_DIG_FIFO_STATUS 0x1F0A +#define mmDIG1_DIG_LANE_ENABLE 0x1F8D +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1F01 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1F02 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1F05 +#define mmDIG1_DIG_TEST_PATTERN 0x1F04 +#define mmDIG1_HDMI_ACR_32_0 0x1F37 +#define mmDIG1_HDMI_ACR_32_1 0x1F38 +#define mmDIG1_HDMI_ACR_44_0 0x1F39 +#define mmDIG1_HDMI_ACR_44_1 0x1F3A +#define mmDIG1_HDMI_ACR_48_0 0x1F3B +#define mmDIG1_HDMI_ACR_48_1 0x1F3C +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1F0F +#define mmDIG1_HDMI_ACR_STATUS_0 0x1F3D +#define mmDIG1_HDMI_ACR_STATUS_1 0x1F3E +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1F0E +#define mmDIG1_HDMI_CONTROL 0x1F0C +#define mmDIG1_HDMI_GC 0x1F16 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1F13 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1F30 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1F11 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1F12 +#define mmDIG1_HDMI_STATUS 0x1F0D +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1F10 +#define mmDIG1_LVDS_DATA_CNTL 0x1F8C +#define mmDIG1_TMDS_CNTL 0x1F7C +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1F7E +#define mmDIG1_TMDS_CONTROL_CHAR 0x1F7D +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1F86 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1F87 +#define mmDIG1_TMDS_CTL_BITS 0x1F83 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1F84 +#define mmDIG1_TMDS_DEBUG 0x1F82 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1F7F +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1F80 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1F81 +#define mmDIG2_AFMT_60958_0 0x4241 +#define mmDIG2_AFMT_60958_1 0x4242 +#define mmDIG2_AFMT_60958_2 0x4248 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 +#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 +#define mmDIG2_AFMT_AUDIO_INFO0 0x423F +#define mmDIG2_AFMT_AUDIO_INFO1 0x4240 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424B +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424F +#define mmDIG2_AFMT_AVI_INFO0 0x4221 +#define mmDIG2_AFMT_AVI_INFO1 0x4222 +#define mmDIG2_AFMT_AVI_INFO2 0x4223 +#define mmDIG2_AFMT_AVI_INFO3 0x4224 +#define mmDIG2_AFMT_GENERIC_0 0x4228 +#define mmDIG2_AFMT_GENERIC_1 0x4229 +#define mmDIG2_AFMT_GENERIC_2 0x422A +#define mmDIG2_AFMT_GENERIC_3 0x422B +#define mmDIG2_AFMT_GENERIC_4 0x422C +#define mmDIG2_AFMT_GENERIC_5 0x422D +#define mmDIG2_AFMT_GENERIC_6 0x422E +#define mmDIG2_AFMT_GENERIC_7 0x422F +#define mmDIG2_AFMT_GENERIC_HDR 0x4227 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424D +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 +#define mmDIG2_AFMT_ISRC1_0 0x4218 +#define mmDIG2_AFMT_ISRC1_1 0x4219 +#define mmDIG2_AFMT_ISRC1_2 0x421A +#define mmDIG2_AFMT_ISRC1_3 0x421B +#define mmDIG2_AFMT_ISRC1_4 0x421C +#define mmDIG2_AFMT_ISRC2_0 0x421D +#define mmDIG2_AFMT_ISRC2_1 0x421E +#define mmDIG2_AFMT_ISRC2_2 0x421F +#define mmDIG2_AFMT_ISRC2_3 0x4220 +#define mmDIG2_AFMT_MPEG_INFO0 0x4225 +#define mmDIG2_AFMT_MPEG_INFO1 0x4226 +#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 +#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 +#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 +#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 +#define mmDIG2_AFMT_STATUS 0x424A +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424C +#define mmDIG2_DIG_BE_CNTL 0x4250 +#define mmDIG2_DIG_BE_EN_CNTL 0x4251 +#define mmDIG2_DIG_CLOCK_PATTERN 0x4203 +#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 +#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 +#define mmDIG2_DIG_FE_CNTL 0x4200 +#define mmDIG2_DIG_FIFO_STATUS 0x420A +#define mmDIG2_DIG_LANE_ENABLE 0x428D +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 +#define mmDIG2_DIG_TEST_PATTERN 0x4204 +#define mmDIG2_HDMI_ACR_32_0 0x4237 +#define mmDIG2_HDMI_ACR_32_1 0x4238 +#define mmDIG2_HDMI_ACR_44_0 0x4239 +#define mmDIG2_HDMI_ACR_44_1 0x423A +#define mmDIG2_HDMI_ACR_48_0 0x423B +#define mmDIG2_HDMI_ACR_48_1 0x423C +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420F +#define mmDIG2_HDMI_ACR_STATUS_0 0x423D +#define mmDIG2_HDMI_ACR_STATUS_1 0x423E +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420E +#define mmDIG2_HDMI_CONTROL 0x420C +#define mmDIG2_HDMI_GC 0x4216 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 +#define mmDIG2_HDMI_STATUS 0x420D +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 +#define mmDIG2_LVDS_DATA_CNTL 0x428C +#define mmDIG2_TMDS_CNTL 0x427C +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427E +#define mmDIG2_TMDS_CONTROL_CHAR 0x427D +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 +#define mmDIG2_TMDS_CTL_BITS 0x4283 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 +#define mmDIG2_TMDS_DEBUG 0x4282 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427F +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 +#define mmDIG3_AFMT_60958_0 0x4541 +#define mmDIG3_AFMT_60958_1 0x4542 +#define mmDIG3_AFMT_60958_2 0x4548 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 +#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 +#define mmDIG3_AFMT_AUDIO_INFO0 0x453F +#define mmDIG3_AFMT_AUDIO_INFO1 0x4540 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454B +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454F +#define mmDIG3_AFMT_AVI_INFO0 0x4521 +#define mmDIG3_AFMT_AVI_INFO1 0x4522 +#define mmDIG3_AFMT_AVI_INFO2 0x4523 +#define mmDIG3_AFMT_AVI_INFO3 0x4524 +#define mmDIG3_AFMT_GENERIC_0 0x4528 +#define mmDIG3_AFMT_GENERIC_1 0x4529 +#define mmDIG3_AFMT_GENERIC_2 0x452A +#define mmDIG3_AFMT_GENERIC_3 0x452B +#define mmDIG3_AFMT_GENERIC_4 0x452C +#define mmDIG3_AFMT_GENERIC_5 0x452D +#define mmDIG3_AFMT_GENERIC_6 0x452E +#define mmDIG3_AFMT_GENERIC_7 0x452F +#define mmDIG3_AFMT_GENERIC_HDR 0x4527 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454D +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 +#define mmDIG3_AFMT_ISRC1_0 0x4518 +#define mmDIG3_AFMT_ISRC1_1 0x4519 +#define mmDIG3_AFMT_ISRC1_2 0x451A +#define mmDIG3_AFMT_ISRC1_3 0x451B +#define mmDIG3_AFMT_ISRC1_4 0x451C +#define mmDIG3_AFMT_ISRC2_0 0x451D +#define mmDIG3_AFMT_ISRC2_1 0x451E +#define mmDIG3_AFMT_ISRC2_2 0x451F +#define mmDIG3_AFMT_ISRC2_3 0x4520 +#define mmDIG3_AFMT_MPEG_INFO0 0x4525 +#define mmDIG3_AFMT_MPEG_INFO1 0x4526 +#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 +#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 +#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 +#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 +#define mmDIG3_AFMT_STATUS 0x454A +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454C +#define mmDIG3_DIG_BE_CNTL 0x4550 +#define mmDIG3_DIG_BE_EN_CNTL 0x4551 +#define mmDIG3_DIG_CLOCK_PATTERN 0x4503 +#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 +#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 +#define mmDIG3_DIG_FE_CNTL 0x4500 +#define mmDIG3_DIG_FIFO_STATUS 0x450A +#define mmDIG3_DIG_LANE_ENABLE 0x458D +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 +#define mmDIG3_DIG_TEST_PATTERN 0x4504 +#define mmDIG3_HDMI_ACR_32_0 0x4537 +#define mmDIG3_HDMI_ACR_32_1 0x4538 +#define mmDIG3_HDMI_ACR_44_0 0x4539 +#define mmDIG3_HDMI_ACR_44_1 0x453A +#define mmDIG3_HDMI_ACR_48_0 0x453B +#define mmDIG3_HDMI_ACR_48_1 0x453C +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450F +#define mmDIG3_HDMI_ACR_STATUS_0 0x453D +#define mmDIG3_HDMI_ACR_STATUS_1 0x453E +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450E +#define mmDIG3_HDMI_CONTROL 0x450C +#define mmDIG3_HDMI_GC 0x4516 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 +#define mmDIG3_HDMI_STATUS 0x450D +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 +#define mmDIG3_LVDS_DATA_CNTL 0x458C +#define mmDIG3_TMDS_CNTL 0x457C +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457E +#define mmDIG3_TMDS_CONTROL_CHAR 0x457D +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 +#define mmDIG3_TMDS_CTL_BITS 0x4583 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 +#define mmDIG3_TMDS_DEBUG 0x4582 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457F +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 +#define mmDIG4_AFMT_60958_0 0x4841 +#define mmDIG4_AFMT_60958_1 0x4842 +#define mmDIG4_AFMT_60958_2 0x4848 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 +#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 +#define mmDIG4_AFMT_AUDIO_INFO0 0x483F +#define mmDIG4_AFMT_AUDIO_INFO1 0x4840 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484B +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484F +#define mmDIG4_AFMT_AVI_INFO0 0x4821 +#define mmDIG4_AFMT_AVI_INFO1 0x4822 +#define mmDIG4_AFMT_AVI_INFO2 0x4823 +#define mmDIG4_AFMT_AVI_INFO3 0x4824 +#define mmDIG4_AFMT_GENERIC_0 0x4828 +#define mmDIG4_AFMT_GENERIC_1 0x4829 +#define mmDIG4_AFMT_GENERIC_2 0x482A +#define mmDIG4_AFMT_GENERIC_3 0x482B +#define mmDIG4_AFMT_GENERIC_4 0x482C +#define mmDIG4_AFMT_GENERIC_5 0x482D +#define mmDIG4_AFMT_GENERIC_6 0x482E +#define mmDIG4_AFMT_GENERIC_7 0x482F +#define mmDIG4_AFMT_GENERIC_HDR 0x4827 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484D +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 +#define mmDIG4_AFMT_ISRC1_0 0x4818 +#define mmDIG4_AFMT_ISRC1_1 0x4819 +#define mmDIG4_AFMT_ISRC1_2 0x481A +#define mmDIG4_AFMT_ISRC1_3 0x481B +#define mmDIG4_AFMT_ISRC1_4 0x481C +#define mmDIG4_AFMT_ISRC2_0 0x481D +#define mmDIG4_AFMT_ISRC2_1 0x481E +#define mmDIG4_AFMT_ISRC2_2 0x481F +#define mmDIG4_AFMT_ISRC2_3 0x4820 +#define mmDIG4_AFMT_MPEG_INFO0 0x4825 +#define mmDIG4_AFMT_MPEG_INFO1 0x4826 +#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 +#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 +#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 +#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 +#define mmDIG4_AFMT_STATUS 0x484A +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484C +#define mmDIG4_DIG_BE_CNTL 0x4850 +#define mmDIG4_DIG_BE_EN_CNTL 0x4851 +#define mmDIG4_DIG_CLOCK_PATTERN 0x4803 +#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 +#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 +#define mmDIG4_DIG_FE_CNTL 0x4800 +#define mmDIG4_DIG_FIFO_STATUS 0x480A +#define mmDIG4_DIG_LANE_ENABLE 0x488D +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 +#define mmDIG4_DIG_TEST_PATTERN 0x4804 +#define mmDIG4_HDMI_ACR_32_0 0x4837 +#define mmDIG4_HDMI_ACR_32_1 0x4838 +#define mmDIG4_HDMI_ACR_44_0 0x4839 +#define mmDIG4_HDMI_ACR_44_1 0x483A +#define mmDIG4_HDMI_ACR_48_0 0x483B +#define mmDIG4_HDMI_ACR_48_1 0x483C +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480F +#define mmDIG4_HDMI_ACR_STATUS_0 0x483D +#define mmDIG4_HDMI_ACR_STATUS_1 0x483E +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480E +#define mmDIG4_HDMI_CONTROL 0x480C +#define mmDIG4_HDMI_GC 0x4816 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 +#define mmDIG4_HDMI_STATUS 0x480D +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 +#define mmDIG4_LVDS_DATA_CNTL 0x488C +#define mmDIG4_TMDS_CNTL 0x487C +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487E +#define mmDIG4_TMDS_CONTROL_CHAR 0x487D +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 +#define mmDIG4_TMDS_CTL_BITS 0x4883 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 +#define mmDIG4_TMDS_DEBUG 0x4882 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487F +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 +#define mmDIG5_AFMT_60958_0 0x4B41 +#define mmDIG5_AFMT_60958_1 0x4B42 +#define mmDIG5_AFMT_60958_2 0x4B48 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4B43 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4B49 +#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4B52 +#define mmDIG5_AFMT_AUDIO_INFO0 0x4B3F +#define mmDIG5_AFMT_AUDIO_INFO1 0x4B40 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4B4B +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4B17 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4B4F +#define mmDIG5_AFMT_AVI_INFO0 0x4B21 +#define mmDIG5_AFMT_AVI_INFO1 0x4B22 +#define mmDIG5_AFMT_AVI_INFO2 0x4B23 +#define mmDIG5_AFMT_AVI_INFO3 0x4B24 +#define mmDIG5_AFMT_GENERIC_0 0x4B28 +#define mmDIG5_AFMT_GENERIC_1 0x4B29 +#define mmDIG5_AFMT_GENERIC_2 0x4B2A +#define mmDIG5_AFMT_GENERIC_3 0x4B2B +#define mmDIG5_AFMT_GENERIC_4 0x4B2C +#define mmDIG5_AFMT_GENERIC_5 0x4B2D +#define mmDIG5_AFMT_GENERIC_6 0x4B2E +#define mmDIG5_AFMT_GENERIC_7 0x4B2F +#define mmDIG5_AFMT_GENERIC_HDR 0x4B27 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4B4D +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4B14 +#define mmDIG5_AFMT_ISRC1_0 0x4B18 +#define mmDIG5_AFMT_ISRC1_1 0x4B19 +#define mmDIG5_AFMT_ISRC1_2 0x4B1A +#define mmDIG5_AFMT_ISRC1_3 0x4B1B +#define mmDIG5_AFMT_ISRC1_4 0x4B1C +#define mmDIG5_AFMT_ISRC2_0 0x4B1D +#define mmDIG5_AFMT_ISRC2_1 0x4B1E +#define mmDIG5_AFMT_ISRC2_2 0x4B1F +#define mmDIG5_AFMT_ISRC2_3 0x4B20 +#define mmDIG5_AFMT_MPEG_INFO0 0x4B25 +#define mmDIG5_AFMT_MPEG_INFO1 0x4B26 +#define mmDIG5_AFMT_RAMP_CONTROL0 0x4B44 +#define mmDIG5_AFMT_RAMP_CONTROL1 0x4B45 +#define mmDIG5_AFMT_RAMP_CONTROL2 0x4B46 +#define mmDIG5_AFMT_RAMP_CONTROL3 0x4B47 +#define mmDIG5_AFMT_STATUS 0x4B4A +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4B4C +#define mmDIG5_DIG_BE_CNTL 0x4B50 +#define mmDIG5_DIG_BE_EN_CNTL 0x4B51 +#define mmDIG5_DIG_CLOCK_PATTERN 0x4B03 +#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4B08 +#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4B09 +#define mmDIG5_DIG_FE_CNTL 0x4B00 +#define mmDIG5_DIG_FIFO_STATUS 0x4B0A +#define mmDIG5_DIG_LANE_ENABLE 0x4B8D +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4B01 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4B02 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4B05 +#define mmDIG5_DIG_TEST_PATTERN 0x4B04 +#define mmDIG5_HDMI_ACR_32_0 0x4B37 +#define mmDIG5_HDMI_ACR_32_1 0x4B38 +#define mmDIG5_HDMI_ACR_44_0 0x4B39 +#define mmDIG5_HDMI_ACR_44_1 0x4B3A +#define mmDIG5_HDMI_ACR_48_0 0x4B3B +#define mmDIG5_HDMI_ACR_48_1 0x4B3C +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4B0F +#define mmDIG5_HDMI_ACR_STATUS_0 0x4B3D +#define mmDIG5_HDMI_ACR_STATUS_1 0x4B3E +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4B0E +#define mmDIG5_HDMI_CONTROL 0x4B0C +#define mmDIG5_HDMI_GC 0x4B16 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4B13 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4B30 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4B11 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4B12 +#define mmDIG5_HDMI_STATUS 0x4B0D +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4B10 +#define mmDIG5_LVDS_DATA_CNTL 0x4B8C +#define mmDIG5_TMDS_CNTL 0x4B7C +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4B7E +#define mmDIG5_TMDS_CONTROL_CHAR 0x4B7D +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4B86 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4B87 +#define mmDIG5_TMDS_CTL_BITS 0x4B83 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4B84 +#define mmDIG5_TMDS_DEBUG 0x4B82 +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4B7F +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4B80 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4B81 +#define mmDIG_BE_CNTL 0x1C50 +#define mmDIG_BE_EN_CNTL 0x1C51 +#define mmDIG_CLOCK_PATTERN 0x1C03 +#define mmDIG_DISPCLK_SWITCH_CNTL 0x1C08 +#define mmDIG_DISPCLK_SWITCH_STATUS 0x1C09 +#define mmDIG_FE_CNTL 0x1C00 +#define mmDIG_FIFO_STATUS 0x1C0A +#define mmDIG_LANE_ENABLE 0x1C8D +#define mmDIG_OUTPUT_CRC_CNTL 0x1C01 +#define mmDIG_OUTPUT_CRC_RESULT 0x1C02 +#define mmDIG_RANDOM_PATTERN_SEED 0x1C05 +#define mmDIG_SOFT_RESET 0x013D +#define mmDIG_TEST_PATTERN 0x1C04 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0135 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0131 +#define mmDISP_INTERRUPT_STATUS 0x183D +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183E +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183F +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 +#define mmDISPOUT_STEREOSYNC_SEL 0x18BF +#define mmDISPPLL_BG_CNTL 0x013C +#define mmDISP_TIMER_CONTROL 0x1842 +#define mmDMCU_CTRL 0x1600 +#define mmDMCU_ERAM_RD_CTRL 0x160B +#define mmDMCU_ERAM_RD_DATA 0x160C +#define mmDMCU_ERAM_WR_CTRL 0x1609 +#define mmDMCU_ERAM_WR_DATA 0x160A +#define mmDMCU_EVENT_TRIGGER 0x1611 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161A +#define mmDMCU_FW_CS_HI 0x1606 +#define mmDMCU_FW_CS_LO 0x1607 +#define mmDMCU_FW_END_ADDR 0x1604 +#define mmDMCU_FW_ISR_START_ADDR 0x1605 +#define mmDMCU_FW_START_ADDR 0x1603 +#define mmDMCU_INT_CNT 0x1619 +#define mmDMCU_INTERRUPT_STATUS 0x1614 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define mmDMCU_IRAM_RD_CTRL 0x160F +#define mmDMCU_IRAM_RD_DATA 0x1610 +#define mmDMCU_IRAM_WR_CTRL 0x160D +#define mmDMCU_IRAM_WR_DATA 0x160E +#define mmDMCU_PC_START_ADDR 0x1602 +#define mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define mmDMCU_STATUS 0x1601 +#define mmDMCU_TEST_DEBUG_DATA 0x1627 +#define mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define mmDMCU_UC_CLK_GATING_CNTL 0x161B +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define mmDMIF_ADDR_CALC 0x0300 +#define mmDMIF_ADDR_CONFIG 0x02F5 +#define mmDMIF_ARBITRATION_CONTROL 0x02F9 +#define mmDMIF_CONTROL 0x02F6 +#define mmDMIF_HW_DEBUG 0x02F8 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1B30 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1B31 +#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1B34 +#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1B35 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1B33 +#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1B39 +#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1B38 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1E30 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1E31 +#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1E34 +#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1E36 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1E35 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1E37 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1E33 +#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1E39 +#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1E38 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 +#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 +#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 +#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 +#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 +#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 +#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 +#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 +#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 +#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4A30 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4A31 +#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4A34 +#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4A36 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4A35 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4A37 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4A33 +#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4A39 +#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4A38 +#define mmDMIF_STATUS 0x02F7 +#define mmDMIF_STATUS2 0x0301 +#define mmDMIF_TEST_DEBUG_DATA 0x0313 +#define mmDMIF_TEST_DEBUG_INDEX 0x0312 +#define mmDOUT_DCE_VCE_CONTROL 0x18FF +#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 +#define mmDOUT_SCRATCH0 0x1844 +#define mmDOUT_SCRATCH1 0x1845 +#define mmDOUT_SCRATCH2 0x1846 +#define mmDOUT_SCRATCH3 0x1847 +#define mmDOUT_SCRATCH4 0x1848 +#define mmDOUT_SCRATCH5 0x1849 +#define mmDOUT_SCRATCH6 0x184A +#define mmDOUT_SCRATCH7 0x184B +#define mmDOUT_TEST_DEBUG_DATA 0x184E +#define mmDOUT_TEST_DEBUG_INDEX 0x184D +#define mmDP0_DP_CONFIG 0x1CC2 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x1CD3 +#define mmDP0_DP_DPHY_CNTL 0x1CD0 +#define mmDP0_DP_DPHY_CRC_CNTL 0x1CD7 +#define mmDP0_DP_DPHY_CRC_EN 0x1CD6 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1CC6 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1CC7 +#define mmDP0_DP_DPHY_CRC_RESULT 0x1CD8 +#define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1CE9 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x1CD4 +#define mmDP0_DP_DPHY_SYM0 0x1CD2 +#define mmDP0_DP_DPHY_SYM1 0x1CE0 +#define mmDP0_DP_DPHY_SYM2 0x1CDF +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x1CC8 +#define mmDP0_DP_LINK_CNTL 0x1CC0 +#define mmDP0_DP_LINK_FRAMING_CNTL 0x1CCC +#define mmDP0_DP_MSA_COLORIMETRY 0x1CDA +#define mmDP0_DP_MSA_MISC 0x1CC5 +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1CEA +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1CEB +#define mmDP0_DP_MSE_LINK_TIMING 0x1CE8 +#define mmDP0_DP_MSE_MISC_CNTL 0x1CDB +#define mmDP0_DP_MSE_RATE_CNTL 0x1CE1 +#define mmDP0_DP_MSE_RATE_UPDATE 0x1CE3 +#define mmDP0_DP_MSE_SAT0 0x1CE4 +#define mmDP0_DP_MSE_SAT1 0x1CE5 +#define mmDP0_DP_MSE_SAT2 0x1CE6 +#define mmDP0_DP_MSE_SAT_UPDATE 0x1CE7 +#define mmDP0_DP_PIXEL_FORMAT 0x1CC1 +#define mmDP0_DP_SEC_AUD_M 0x1CA7 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x1CA8 +#define mmDP0_DP_SEC_AUD_N 0x1CA5 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x1CA6 +#define mmDP0_DP_SEC_CNTL 0x1CA0 +#define mmDP0_DP_SEC_CNTL1 0x1CAB +#define mmDP0_DP_SEC_FRAMING1 0x1CA1 +#define mmDP0_DP_SEC_FRAMING2 0x1CA2 +#define mmDP0_DP_SEC_FRAMING3 0x1CA3 +#define mmDP0_DP_SEC_FRAMING4 0x1CA4 +#define mmDP0_DP_SEC_PACKET_CNTL 0x1CAA +#define mmDP0_DP_SEC_TIMESTAMP 0x1CA9 +#define mmDP0_DP_STEER_FIFO 0x1CC4 +#define mmDP0_DP_TEST_DEBUG_DATA 0x1CFD +#define mmDP0_DP_TEST_DEBUG_INDEX 0x1CFC +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1CCF +#define mmDP0_DP_VID_M 0x1CCB +#define mmDP0_DP_VID_MSA_VBID 0x1CCD +#define mmDP0_DP_VID_N 0x1CCA +#define mmDP0_DP_VID_STREAM_CNTL 0x1CC3 +#define mmDP0_DP_VID_TIMING 0x1CC9 +#define mmDP1_DP_CONFIG 0x1FC2 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x1FD3 +#define mmDP1_DP_DPHY_CNTL 0x1FD0 +#define mmDP1_DP_DPHY_CRC_CNTL 0x1FD7 +#define mmDP1_DP_DPHY_CRC_EN 0x1FD6 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1FC6 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1FC7 +#define mmDP1_DP_DPHY_CRC_RESULT 0x1FD8 +#define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1FE9 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4 +#define mmDP1_DP_DPHY_SYM0 0x1FD2 +#define mmDP1_DP_DPHY_SYM1 0x1FE0 +#define mmDP1_DP_DPHY_SYM2 0x1FDF +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1FD1 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x1FC8 +#define mmDP1_DP_LINK_CNTL 0x1FC0 +#define mmDP1_DP_LINK_FRAMING_CNTL 0x1FCC +#define mmDP1_DP_MSA_COLORIMETRY 0x1FDA +#define mmDP1_DP_MSA_MISC 0x1FC5 +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1FEA +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1FEB +#define mmDP1_DP_MSE_LINK_TIMING 0x1FE8 +#define mmDP1_DP_MSE_MISC_CNTL 0x1FDB +#define mmDP1_DP_MSE_RATE_CNTL 0x1FE1 +#define mmDP1_DP_MSE_RATE_UPDATE 0x1FE3 +#define mmDP1_DP_MSE_SAT0 0x1FE4 +#define mmDP1_DP_MSE_SAT1 0x1FE5 +#define mmDP1_DP_MSE_SAT2 0x1FE6 +#define mmDP1_DP_MSE_SAT_UPDATE 0x1FE7 +#define mmDP1_DP_PIXEL_FORMAT 0x1FC1 +#define mmDP1_DP_SEC_AUD_M 0x1FA7 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x1FA8 +#define mmDP1_DP_SEC_AUD_N 0x1FA5 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x1FA6 +#define mmDP1_DP_SEC_CNTL 0x1FA0 +#define mmDP1_DP_SEC_CNTL1 0x1FAB +#define mmDP1_DP_SEC_FRAMING1 0x1FA1 +#define mmDP1_DP_SEC_FRAMING2 0x1FA2 +#define mmDP1_DP_SEC_FRAMING3 0x1FA3 +#define mmDP1_DP_SEC_FRAMING4 0x1FA4 +#define mmDP1_DP_SEC_PACKET_CNTL 0x1FAA +#define mmDP1_DP_SEC_TIMESTAMP 0x1FA9 +#define mmDP1_DP_STEER_FIFO 0x1FC4 +#define mmDP1_DP_TEST_DEBUG_DATA 0x1FFD +#define mmDP1_DP_TEST_DEBUG_INDEX 0x1FFC +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1FCF +#define mmDP1_DP_VID_M 0x1FCB +#define mmDP1_DP_VID_MSA_VBID 0x1FCD +#define mmDP1_DP_VID_N 0x1FCA +#define mmDP1_DP_VID_STREAM_CNTL 0x1FC3 +#define mmDP1_DP_VID_TIMING 0x1FC9 +#define mmDP2_DP_CONFIG 0x42C2 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x42D3 +#define mmDP2_DP_DPHY_CNTL 0x42D0 +#define mmDP2_DP_DPHY_CRC_CNTL 0x42D7 +#define mmDP2_DP_DPHY_CRC_EN 0x42D6 +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42C6 +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42C7 +#define mmDP2_DP_DPHY_CRC_RESULT 0x42D8 +#define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42E9 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x42D4 +#define mmDP2_DP_DPHY_SYM0 0x42D2 +#define mmDP2_DP_DPHY_SYM1 0x42E0 +#define mmDP2_DP_DPHY_SYM2 0x42DF +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42D1 +#define mmDP2_DP_HBR2_EYE_PATTERN 0x42C8 +#define mmDP2_DP_LINK_CNTL 0x42C0 +#define mmDP2_DP_LINK_FRAMING_CNTL 0x42CC +#define mmDP2_DP_MSA_COLORIMETRY 0x42DA +#define mmDP2_DP_MSA_MISC 0x42C5 +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42EA +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42EB +#define mmDP2_DP_MSE_LINK_TIMING 0x42E8 +#define mmDP2_DP_MSE_MISC_CNTL 0x42DB +#define mmDP2_DP_MSE_RATE_CNTL 0x42E1 +#define mmDP2_DP_MSE_RATE_UPDATE 0x42E3 +#define mmDP2_DP_MSE_SAT0 0x42E4 +#define mmDP2_DP_MSE_SAT1 0x42E5 +#define mmDP2_DP_MSE_SAT2 0x42E6 +#define mmDP2_DP_MSE_SAT_UPDATE 0x42E7 +#define mmDP2_DP_PIXEL_FORMAT 0x42C1 +#define mmDP2_DP_SEC_AUD_M 0x42A7 +#define mmDP2_DP_SEC_AUD_M_READBACK 0x42A8 +#define mmDP2_DP_SEC_AUD_N 0x42A5 +#define mmDP2_DP_SEC_AUD_N_READBACK 0x42A6 +#define mmDP2_DP_SEC_CNTL 0x42A0 +#define mmDP2_DP_SEC_CNTL1 0x42AB +#define mmDP2_DP_SEC_FRAMING1 0x42A1 +#define mmDP2_DP_SEC_FRAMING2 0x42A2 +#define mmDP2_DP_SEC_FRAMING3 0x42A3 +#define mmDP2_DP_SEC_FRAMING4 0x42A4 +#define mmDP2_DP_SEC_PACKET_CNTL 0x42AA +#define mmDP2_DP_SEC_TIMESTAMP 0x42A9 +#define mmDP2_DP_STEER_FIFO 0x42C4 +#define mmDP2_DP_TEST_DEBUG_DATA 0x42FD +#define mmDP2_DP_TEST_DEBUG_INDEX 0x42FC +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42CF +#define mmDP2_DP_VID_M 0x42CB +#define mmDP2_DP_VID_MSA_VBID 0x42CD +#define mmDP2_DP_VID_N 0x42CA +#define mmDP2_DP_VID_STREAM_CNTL 0x42C3 +#define mmDP2_DP_VID_TIMING 0x42C9 +#define mmDP3_DP_CONFIG 0x45C2 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x45D3 +#define mmDP3_DP_DPHY_CNTL 0x45D0 +#define mmDP3_DP_DPHY_CRC_CNTL 0x45D7 +#define mmDP3_DP_DPHY_CRC_EN 0x45D6 +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45C6 +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45C7 +#define mmDP3_DP_DPHY_CRC_RESULT 0x45D8 +#define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45E9 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x45D4 +#define mmDP3_DP_DPHY_SYM0 0x45D2 +#define mmDP3_DP_DPHY_SYM1 0x45E0 +#define mmDP3_DP_DPHY_SYM2 0x45DF +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45D1 +#define mmDP3_DP_HBR2_EYE_PATTERN 0x45C8 +#define mmDP3_DP_LINK_CNTL 0x45C0 +#define mmDP3_DP_LINK_FRAMING_CNTL 0x45CC +#define mmDP3_DP_MSA_COLORIMETRY 0x45DA +#define mmDP3_DP_MSA_MISC 0x45C5 +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45EA +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45EB +#define mmDP3_DP_MSE_LINK_TIMING 0x45E8 +#define mmDP3_DP_MSE_MISC_CNTL 0x45DB +#define mmDP3_DP_MSE_RATE_CNTL 0x45E1 +#define mmDP3_DP_MSE_RATE_UPDATE 0x45E3 +#define mmDP3_DP_MSE_SAT0 0x45E4 +#define mmDP3_DP_MSE_SAT1 0x45E5 +#define mmDP3_DP_MSE_SAT2 0x45E6 +#define mmDP3_DP_MSE_SAT_UPDATE 0x45E7 +#define mmDP3_DP_PIXEL_FORMAT 0x45C1 +#define mmDP3_DP_SEC_AUD_M 0x45A7 +#define mmDP3_DP_SEC_AUD_M_READBACK 0x45A8 +#define mmDP3_DP_SEC_AUD_N 0x45A5 +#define mmDP3_DP_SEC_AUD_N_READBACK 0x45A6 +#define mmDP3_DP_SEC_CNTL 0x45A0 +#define mmDP3_DP_SEC_CNTL1 0x45AB +#define mmDP3_DP_SEC_FRAMING1 0x45A1 +#define mmDP3_DP_SEC_FRAMING2 0x45A2 +#define mmDP3_DP_SEC_FRAMING3 0x45A3 +#define mmDP3_DP_SEC_FRAMING4 0x45A4 +#define mmDP3_DP_SEC_PACKET_CNTL 0x45AA +#define mmDP3_DP_SEC_TIMESTAMP 0x45A9 +#define mmDP3_DP_STEER_FIFO 0x45C4 +#define mmDP3_DP_TEST_DEBUG_DATA 0x45FD +#define mmDP3_DP_TEST_DEBUG_INDEX 0x45FC +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45CF +#define mmDP3_DP_VID_M 0x45CB +#define mmDP3_DP_VID_MSA_VBID 0x45CD +#define mmDP3_DP_VID_N 0x45CA +#define mmDP3_DP_VID_STREAM_CNTL 0x45C3 +#define mmDP3_DP_VID_TIMING 0x45C9 +#define mmDP4_DP_CONFIG 0x48C2 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x48D3 +#define mmDP4_DP_DPHY_CNTL 0x48D0 +#define mmDP4_DP_DPHY_CRC_CNTL 0x48D7 +#define mmDP4_DP_DPHY_CRC_EN 0x48D6 +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48C6 +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48C7 +#define mmDP4_DP_DPHY_CRC_RESULT 0x48D8 +#define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48E9 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x48D4 +#define mmDP4_DP_DPHY_SYM0 0x48D2 +#define mmDP4_DP_DPHY_SYM1 0x48E0 +#define mmDP4_DP_DPHY_SYM2 0x48DF +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48D1 +#define mmDP4_DP_HBR2_EYE_PATTERN 0x48C8 +#define mmDP4_DP_LINK_CNTL 0x48C0 +#define mmDP4_DP_LINK_FRAMING_CNTL 0x48CC +#define mmDP4_DP_MSA_COLORIMETRY 0x48DA +#define mmDP4_DP_MSA_MISC 0x48C5 +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48EA +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48EB +#define mmDP4_DP_MSE_LINK_TIMING 0x48E8 +#define mmDP4_DP_MSE_MISC_CNTL 0x48DB +#define mmDP4_DP_MSE_RATE_CNTL 0x48E1 +#define mmDP4_DP_MSE_RATE_UPDATE 0x48E3 +#define mmDP4_DP_MSE_SAT0 0x48E4 +#define mmDP4_DP_MSE_SAT1 0x48E5 +#define mmDP4_DP_MSE_SAT2 0x48E6 +#define mmDP4_DP_MSE_SAT_UPDATE 0x48E7 +#define mmDP4_DP_PIXEL_FORMAT 0x48C1 +#define mmDP4_DP_SEC_AUD_M 0x48A7 +#define mmDP4_DP_SEC_AUD_M_READBACK 0x48A8 +#define mmDP4_DP_SEC_AUD_N 0x48A5 +#define mmDP4_DP_SEC_AUD_N_READBACK 0x48A6 +#define mmDP4_DP_SEC_CNTL 0x48A0 +#define mmDP4_DP_SEC_CNTL1 0x48AB +#define mmDP4_DP_SEC_FRAMING1 0x48A1 +#define mmDP4_DP_SEC_FRAMING2 0x48A2 +#define mmDP4_DP_SEC_FRAMING3 0x48A3 +#define mmDP4_DP_SEC_FRAMING4 0x48A4 +#define mmDP4_DP_SEC_PACKET_CNTL 0x48AA +#define mmDP4_DP_SEC_TIMESTAMP 0x48A9 +#define mmDP4_DP_STEER_FIFO 0x48C4 +#define mmDP4_DP_TEST_DEBUG_DATA 0x48FD +#define mmDP4_DP_TEST_DEBUG_INDEX 0x48FC +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48CF +#define mmDP4_DP_VID_M 0x48CB +#define mmDP4_DP_VID_MSA_VBID 0x48CD +#define mmDP4_DP_VID_N 0x48CA +#define mmDP4_DP_VID_STREAM_CNTL 0x48C3 +#define mmDP4_DP_VID_TIMING 0x48C9 +#define mmDP5_DP_CONFIG 0x4BC2 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x4BD3 +#define mmDP5_DP_DPHY_CNTL 0x4BD0 +#define mmDP5_DP_DPHY_CRC_CNTL 0x4BD7 +#define mmDP5_DP_DPHY_CRC_EN 0x4BD6 +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4BC6 +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4BC7 +#define mmDP5_DP_DPHY_CRC_RESULT 0x4BD8 +#define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4BE9 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x4BD4 +#define mmDP5_DP_DPHY_SYM0 0x4BD2 +#define mmDP5_DP_DPHY_SYM1 0x4BE0 +#define mmDP5_DP_DPHY_SYM2 0x4BDF +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4BD1 +#define mmDP5_DP_HBR2_EYE_PATTERN 0x4BC8 +#define mmDP5_DP_LINK_CNTL 0x4BC0 +#define mmDP5_DP_LINK_FRAMING_CNTL 0x4BCC +#define mmDP5_DP_MSA_COLORIMETRY 0x4BDA +#define mmDP5_DP_MSA_MISC 0x4BC5 +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4BEA +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4BEB +#define mmDP5_DP_MSE_LINK_TIMING 0x4BE8 +#define mmDP5_DP_MSE_MISC_CNTL 0x4BDB +#define mmDP5_DP_MSE_RATE_CNTL 0x4BE1 +#define mmDP5_DP_MSE_RATE_UPDATE 0x4BE3 +#define mmDP5_DP_MSE_SAT0 0x4BE4 +#define mmDP5_DP_MSE_SAT1 0x4BE5 +#define mmDP5_DP_MSE_SAT2 0x4BE6 +#define mmDP5_DP_MSE_SAT_UPDATE 0x4BE7 +#define mmDP5_DP_PIXEL_FORMAT 0x4BC1 +#define mmDP5_DP_SEC_AUD_M 0x4BA7 +#define mmDP5_DP_SEC_AUD_M_READBACK 0x4BA8 +#define mmDP5_DP_SEC_AUD_N 0x4BA5 +#define mmDP5_DP_SEC_AUD_N_READBACK 0x4BA6 +#define mmDP5_DP_SEC_CNTL 0x4BA0 +#define mmDP5_DP_SEC_CNTL1 0x4BAB +#define mmDP5_DP_SEC_FRAMING1 0x4BA1 +#define mmDP5_DP_SEC_FRAMING2 0x4BA2 +#define mmDP5_DP_SEC_FRAMING3 0x4BA3 +#define mmDP5_DP_SEC_FRAMING4 0x4BA4 +#define mmDP5_DP_SEC_PACKET_CNTL 0x4BAA +#define mmDP5_DP_SEC_TIMESTAMP 0x4BA9 +#define mmDP5_DP_STEER_FIFO 0x4BC4 +#define mmDP5_DP_TEST_DEBUG_DATA 0x4BFD +#define mmDP5_DP_TEST_DEBUG_INDEX 0x4BFC +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4BCF +#define mmDP5_DP_VID_M 0x4BCB +#define mmDP5_DP_VID_MSA_VBID 0x4BCD +#define mmDP5_DP_VID_N 0x4BCA +#define mmDP5_DP_VID_STREAM_CNTL 0x4BC3 +#define mmDP5_DP_VID_TIMING 0x4BC9 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 +#define mmDP_AUX0_AUX_CONTROL 0x1880 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188A +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188B +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188D +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188C +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188E +#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1890 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 +#define mmDP_AUX0_AUX_LS_DATA 0x1887 +#define mmDP_AUX0_AUX_LS_STATUS 0x1885 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1881 +#define mmDP_AUX0_AUX_SW_DATA 0x1886 +#define mmDP_AUX0_AUX_SW_STATUS 0x1884 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 +#define mmDP_AUX1_AUX_CONTROL 0x1894 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189E +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189F +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18A1 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189D +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189C +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18A0 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18A2 +#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18A4 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 +#define mmDP_AUX1_AUX_LS_DATA 0x189B +#define mmDP_AUX1_AUX_LS_STATUS 0x1899 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1895 +#define mmDP_AUX1_AUX_SW_DATA 0x189A +#define mmDP_AUX1_AUX_SW_STATUS 0x1898 +#define mmDP_AUX2_AUX_ARB_CONTROL 0x18AA +#define mmDP_AUX2_AUX_CONTROL 0x18A8 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18B2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18B3 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18B5 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18B1 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18B0 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18B4 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18B6 +#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18B8 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18AB +#define mmDP_AUX2_AUX_LS_DATA 0x18AF +#define mmDP_AUX2_AUX_LS_STATUS 0x18AD +#define mmDP_AUX2_AUX_SW_CONTROL 0x18A9 +#define mmDP_AUX2_AUX_SW_DATA 0x18AE +#define mmDP_AUX2_AUX_SW_STATUS 0x18AC +#define mmDP_AUX3_AUX_ARB_CONTROL 0x18C2 +#define mmDP_AUX3_AUX_CONTROL 0x18C0 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18CA +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18CB +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18CD +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18C9 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18C8 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18CC +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18CE +#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18D0 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18C3 +#define mmDP_AUX3_AUX_LS_DATA 0x18C7 +#define mmDP_AUX3_AUX_LS_STATUS 0x18C5 +#define mmDP_AUX3_AUX_SW_CONTROL 0x18C1 +#define mmDP_AUX3_AUX_SW_DATA 0x18C6 +#define mmDP_AUX3_AUX_SW_STATUS 0x18C4 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x18D6 +#define mmDP_AUX4_AUX_CONTROL 0x18D4 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18DE +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18DF +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18E1 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18DD +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18DC +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18E0 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18E2 +#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18E4 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18D7 +#define mmDP_AUX4_AUX_LS_DATA 0x18DB +#define mmDP_AUX4_AUX_LS_STATUS 0x18D9 +#define mmDP_AUX4_AUX_SW_CONTROL 0x18D5 +#define mmDP_AUX4_AUX_SW_DATA 0x18DA +#define mmDP_AUX4_AUX_SW_STATUS 0x18D8 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x18EA +#define mmDP_AUX5_AUX_CONTROL 0x18E8 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18F2 +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18F3 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18F5 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18F1 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18F0 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18F4 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18F6 +#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18F8 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18EB +#define mmDP_AUX5_AUX_LS_DATA 0x18EF +#define mmDP_AUX5_AUX_LS_STATUS 0x18ED +#define mmDP_AUX5_AUX_SW_CONTROL 0x18E9 +#define mmDP_AUX5_AUX_SW_DATA 0x18EE +#define mmDP_AUX5_AUX_SW_STATUS 0x18EC +#define mmDP_CONFIG 0x1CC2 +#define mmDP_DPHY_8B10B_CNTL 0x1CD3 +#define mmDP_DPHY_CNTL 0x1CD0 +#define mmDP_DPHY_CRC_CNTL 0x1CD7 +#define mmDP_DPHY_CRC_EN 0x1CD6 +#define mmDP_DPHY_CRC_MST_CNTL 0x1CC6 +#define mmDP_DPHY_CRC_MST_STATUS 0x1CC7 +#define mmDP_DPHY_CRC_RESULT 0x1CD8 +#define mmDP_DPHY_FAST_TRAINING 0x1CCE +#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1CE9 +#define mmDP_DPHY_PRBS_CNTL 0x1CD4 +#define mmDP_DPHY_SYM0 0x1CD2 +#define mmDP_DPHY_SYM1 0x1CE0 +#define mmDP_DPHY_SYM2 0x1CDF +#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 +#define mmDP_DTO0_MODULO 0x0142 +#define mmDP_DTO0_PHASE 0x0141 +#define mmDP_DTO1_MODULO 0x0146 +#define mmDP_DTO1_PHASE 0x0145 +#define mmDP_DTO2_MODULO 0x014A +#define mmDP_DTO2_PHASE 0x0149 +#define mmDP_DTO3_MODULO 0x014E +#define mmDP_DTO3_PHASE 0x014D +#define mmDP_DTO4_MODULO 0x0152 +#define mmDP_DTO4_PHASE 0x0151 +#define mmDP_DTO5_MODULO 0x0156 +#define mmDP_DTO5_PHASE 0x0155 +#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1B30 +#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1B31 +#define mmDPG_PIPE_DPM_CONTROL 0x1B34 +#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 +#define mmDPG_PIPE_STUTTER_CONTROL 0x1B35 +#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 +#define mmDPG_PIPE_URGENCY_CONTROL 0x1B33 +#define mmDPG_TEST_DEBUG_DATA 0x1B39 +#define mmDPG_TEST_DEBUG_INDEX 0x1B38 +#define mmDP_HBR2_EYE_PATTERN 0x1CC8 +#define mmDP_LINK_CNTL 0x1CC0 +#define mmDP_LINK_FRAMING_CNTL 0x1CCC +#define mmDP_MSA_COLORIMETRY 0x1CDA +#define mmDP_MSA_MISC 0x1CC5 +#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1CEA +#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1CEB +#define mmDP_MSE_LINK_TIMING 0x1CE8 +#define mmDP_MSE_MISC_CNTL 0x1CDB +#define mmDP_MSE_RATE_CNTL 0x1CE1 +#define mmDP_MSE_RATE_UPDATE 0x1CE3 +#define mmDP_MSE_SAT0 0x1CE4 +#define mmDP_MSE_SAT1 0x1CE5 +#define mmDP_MSE_SAT2 0x1CE6 +#define mmDP_MSE_SAT_UPDATE 0x1CE7 +#define mmDP_PIXEL_FORMAT 0x1CC1 +#define mmDP_SEC_AUD_M 0x1CA7 +#define mmDP_SEC_AUD_M_READBACK 0x1CA8 +#define mmDP_SEC_AUD_N 0x1CA5 +#define mmDP_SEC_AUD_N_READBACK 0x1CA6 +#define mmDP_SEC_CNTL 0x1CA0 +#define mmDP_SEC_CNTL1 0x1CAB +#define mmDP_SEC_FRAMING1 0x1CA1 +#define mmDP_SEC_FRAMING2 0x1CA2 +#define mmDP_SEC_FRAMING3 0x1CA3 +#define mmDP_SEC_FRAMING4 0x1CA4 +#define mmDP_SEC_PACKET_CNTL 0x1CAA +#define mmDP_SEC_TIMESTAMP 0x1CA9 +#define mmDP_STEER_FIFO 0x1CC4 +#define mmDP_TEST_DEBUG_DATA 0x1CFD +#define mmDP_TEST_DEBUG_INDEX 0x1CFC +#define mmDP_VID_INTERRUPT_CNTL 0x1CCF +#define mmDP_VID_M 0x1CCB +#define mmDP_VID_MSA_VBID 0x1CCD +#define mmDP_VID_N 0x1CCA +#define mmDP_VID_STREAM_CNTL 0x1CC3 +#define mmDP_VID_TIMING 0x1CC9 +#define mmDVOACLKC_CNTL 0x016A +#define mmDVOACLKC_MVP_CNTL 0x0169 +#define mmDVOACLKD_CNTL 0x0168 +#define mmDVO_CLK_ENABLE 0x0129 +#define mmDVO_CONTROL 0x185B +#define mmDVO_CRC2_SIG_MASK 0x185D +#define mmDVO_CRC2_SIG_RESULT 0x185E +#define mmDVO_CRC_EN 0x185C +#define mmDVO_ENABLE 0x1858 +#define mmDVO_FIFO_ERROR_STATUS 0x185F +#define mmDVO_OUTPUT 0x185A +#define mmDVO_SKEW_ADJUST 0x197D +#define mmDVO_SOURCE_SELECT 0x1859 +#define mmDVO_STRENGTH_CONTROL 0x197B +#define mmDVO_VREF_CONTROL 0x197C +#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1B5E +#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1B5F +#define mmFBC_CLIENT_REGION_MASK 0x16EB +#define mmFBC_CNTL 0x16D0 +#define mmFBC_COMP_CNTL 0x16D4 +#define mmFBC_COMP_MODE 0x16D5 +#define mmFBC_CSM_REGION_OFFSET_01 0x16E9 +#define mmFBC_CSM_REGION_OFFSET_23 0x16EA +#define mmFBC_DEBUG0 0x16D6 +#define mmFBC_DEBUG1 0x16D7 +#define mmFBC_DEBUG2 0x16D8 +#define mmFBC_DEBUG_COMP 0x16EC +#define mmFBC_DEBUG_CSR 0x16ED +#define mmFBC_DEBUG_CSR_RDATA 0x16EE +#define mmFBC_DEBUG_CSR_RDATA_HI 0x16F6 +#define mmFBC_DEBUG_CSR_WDATA 0x16EF +#define mmFBC_DEBUG_CSR_WDATA_HI 0x16F7 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16D2 +#define mmFBC_IDLE_MASK 0x16D1 +#define mmFBC_IND_LUT0 0x16D9 +#define mmFBC_IND_LUT10 0x16E3 +#define mmFBC_IND_LUT1 0x16DA +#define mmFBC_IND_LUT11 0x16E4 +#define mmFBC_IND_LUT12 0x16E5 +#define mmFBC_IND_LUT13 0x16E6 +#define mmFBC_IND_LUT14 0x16E7 +#define mmFBC_IND_LUT15 0x16E8 +#define mmFBC_IND_LUT2 0x16DB +#define mmFBC_IND_LUT3 0x16DC +#define mmFBC_IND_LUT4 0x16DD +#define mmFBC_IND_LUT5 0x16DE +#define mmFBC_IND_LUT6 0x16DF +#define mmFBC_IND_LUT7 0x16E0 +#define mmFBC_IND_LUT8 0x16E1 +#define mmFBC_IND_LUT9 0x16E2 +#define mmFBC_MISC 0x16F0 +#define mmFBC_START_STOP_DELAY 0x16D3 +#define mmFBC_STATUS 0x16F1 +#define mmFBC_TEST_DEBUG_DATA 0x16F5 +#define mmFBC_TEST_DEBUG_INDEX 0x16F4 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1BF2 +#define mmFMT0_FMT_CLAMP_CNTL 0x1BF9 +#define mmFMT0_FMT_CONTROL 0x1BEE +#define mmFMT0_FMT_CRC_CNTL 0x1BFA +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1BFE +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1BFD +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1BFB +#define mmFMT0_FMT_DEBUG_CNTL 0x1BFF +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1BF5 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1BF4 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1BF3 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1BED +#define mmFMT0_FMT_FORCE_DATA_0_1 0x1BF0 +#define mmFMT0_FMT_FORCE_DATA_2_3 0x1BF1 +#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1BEF +#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 +#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1BEC +#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1BEB +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1EF2 +#define mmFMT1_FMT_CLAMP_CNTL 0x1EF9 +#define mmFMT1_FMT_CONTROL 0x1EEE +#define mmFMT1_FMT_CRC_CNTL 0x1EFA +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1EFE +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1EFC +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1EFD +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1EFB +#define mmFMT1_FMT_DEBUG_CNTL 0x1EFF +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1EF5 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1EF4 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1EF3 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1EED +#define mmFMT1_FMT_FORCE_DATA_0_1 0x1EF0 +#define mmFMT1_FMT_FORCE_DATA_2_3 0x1EF1 +#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1EEF +#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1EF6 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1EF7 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1EF8 +#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1EEC +#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1EEB +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41F2 +#define mmFMT2_FMT_CLAMP_CNTL 0x41F9 +#define mmFMT2_FMT_CONTROL 0x41EE +#define mmFMT2_FMT_CRC_CNTL 0x41FA +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41FE +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41FC +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41FD +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41FB +#define mmFMT2_FMT_DEBUG_CNTL 0x41FF +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41F5 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41F4 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41F3 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ED +#define mmFMT2_FMT_FORCE_DATA_0_1 0x41F0 +#define mmFMT2_FMT_FORCE_DATA_2_3 0x41F1 +#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41EF +#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41F6 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41F7 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41F8 +#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41EC +#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41EB +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44F2 +#define mmFMT3_FMT_CLAMP_CNTL 0x44F9 +#define mmFMT3_FMT_CONTROL 0x44EE +#define mmFMT3_FMT_CRC_CNTL 0x44FA +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44FE +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44FC +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44FD +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44FB +#define mmFMT3_FMT_DEBUG_CNTL 0x44FF +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44F5 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44F4 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44F3 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ED +#define mmFMT3_FMT_FORCE_DATA_0_1 0x44F0 +#define mmFMT3_FMT_FORCE_DATA_2_3 0x44F1 +#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44EF +#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44F6 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44F7 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44F8 +#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44EC +#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44EB +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47F2 +#define mmFMT4_FMT_CLAMP_CNTL 0x47F9 +#define mmFMT4_FMT_CONTROL 0x47EE +#define mmFMT4_FMT_CRC_CNTL 0x47FA +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47FE +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47FC +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47FD +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47FB +#define mmFMT4_FMT_DEBUG_CNTL 0x47FF +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47F5 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47F4 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47F3 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ED +#define mmFMT4_FMT_FORCE_DATA_0_1 0x47F0 +#define mmFMT4_FMT_FORCE_DATA_2_3 0x47F1 +#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47EF +#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47F6 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47F7 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47F8 +#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47EC +#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47EB +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4AF2 +#define mmFMT5_FMT_CLAMP_CNTL 0x4AF9 +#define mmFMT5_FMT_CONTROL 0x4AEE +#define mmFMT5_FMT_CRC_CNTL 0x4AFA +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4AFE +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4AFC +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4AFD +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4AFB +#define mmFMT5_FMT_DEBUG_CNTL 0x4AFF +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4AF5 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4AF4 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4AF3 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4AED +#define mmFMT5_FMT_FORCE_DATA_0_1 0x4AF0 +#define mmFMT5_FMT_FORCE_DATA_2_3 0x4AF1 +#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4AEF +#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4AF6 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4AF7 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4AF8 +#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4AEC +#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4AEB +#define mmFMT_BIT_DEPTH_CONTROL 0x1BF2 +#define mmFMT_CLAMP_CNTL 0x1BF9 +#define mmFMT_CONTROL 0x1BEE +#define mmFMT_CRC_CNTL 0x1BFA +#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1BFE +#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC +#define mmFMT_CRC_SIG_RED_GREEN 0x1BFD +#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1BFB +#define mmFMT_DEBUG_CNTL 0x1BFF +#define mmFMT_DITHER_RAND_B_SEED 0x1BF5 +#define mmFMT_DITHER_RAND_G_SEED 0x1BF4 +#define mmFMT_DITHER_RAND_R_SEED 0x1BF3 +#define mmFMT_DYNAMIC_EXP_CNTL 0x1BED +#define mmFMT_FORCE_DATA_0_1 0x1BF0 +#define mmFMT_FORCE_DATA_2_3 0x1BF1 +#define mmFMT_FORCE_OUTPUT_CNTL 0x1BEF +#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 +#define mmFMT_TEST_DEBUG_DATA 0x1BEC +#define mmFMT_TEST_DEBUG_INDEX 0x1BEB +#define mmGAMUT_REMAP_C11_C12 0x1A5A +#define mmGAMUT_REMAP_C13_C14 0x1A5B +#define mmGAMUT_REMAP_C21_C22 0x1A5C +#define mmGAMUT_REMAP_C23_C24 0x1A5D +#define mmGAMUT_REMAP_C31_C32 0x1A5E +#define mmGAMUT_REMAP_C33_C34 0x1A5F +#define mmGAMUT_REMAP_CONTROL 0x1A59 +#define mmGENENB 0x00F0 +#define mmGENERIC_I2C_CONTROL 0x1834 +#define mmGENERIC_I2C_DATA 0x183A +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 +#define mmGENERIC_I2C_PIN_DEBUG 0x183C +#define mmGENERIC_I2C_PIN_SELECTION 0x183B +#define mmGENERIC_I2C_SETUP 0x1838 +#define mmGENERIC_I2C_SPEED 0x1837 +#define mmGENERIC_I2C_STATUS 0x1836 +#define mmGENERIC_I2C_TRANSACTION 0x1839 +#define mmGENFC_RD 0x00F2 +#define mmGENFC_WT 0x00EE +#define mmGENMO_RD 0x00F3 +#define mmGENMO_WT 0x00F0 +#define mmGENS0 0x00F0 +#define mmGENS1 0x00EE +#define mmGRPH8_DATA 0x00F3 +#define mmGRPH8_IDX 0x00F3 +#define mmGRPH_COMPRESS_PITCH 0x1A1A +#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 +#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B +#define mmGRPH_CONTROL 0x1A01 +#define mmGRPH_DFQ_CONTROL 0x1A14 +#define mmGRPH_DFQ_STATUS 0x1A15 +#define mmGRPH_ENABLE 0x1A00 +#define mmGRPH_FLIP_CONTROL 0x1A12 +#define mmGRPH_INTERRUPT_CONTROL 0x1A17 +#define mmGRPH_INTERRUPT_STATUS 0x1A16 +#define mmGRPH_LUT_10BIT_BYPASS 0x1A02 +#define mmGRPH_PITCH 0x1A06 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 +#define mmGRPH_STEREOSYNC_FLIP 0x1A97 +#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 +#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1A13 +#define mmGRPH_SURFACE_OFFSET_X 0x1A09 +#define mmGRPH_SURFACE_OFFSET_Y 0x1A0A +#define mmGRPH_SWAP_CNTL 0x1A03 +#define mmGRPH_UPDATE 0x1A11 +#define mmGRPH_X_END 0x1A0D +#define mmGRPH_X_START 0x1A0B +#define mmGRPH_Y_END 0x1A0E +#define mmGRPH_Y_START 0x1A0C +#define mmHDMI_ACR_32_0 0x1C37 +#define mmHDMI_ACR_32_1 0x1C38 +#define mmHDMI_ACR_44_0 0x1C39 +#define mmHDMI_ACR_44_1 0x1C3A +#define mmHDMI_ACR_48_0 0x1C3B +#define mmHDMI_ACR_48_1 0x1C3C +#define mmHDMI_ACR_PACKET_CONTROL 0x1C0F +#define mmHDMI_ACR_STATUS_0 0x1C3D +#define mmHDMI_ACR_STATUS_1 0x1C3E +#define mmHDMI_AUDIO_PACKET_CONTROL 0x1C0E +#define mmHDMI_CONTROL 0x1C0C +#define mmHDMI_GC 0x1C16 +#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1C13 +#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1C30 +#define mmHDMI_INFOFRAME_CONTROL0 0x1C11 +#define mmHDMI_INFOFRAME_CONTROL1 0x1C12 +#define mmHDMI_STATUS 0x1C0D +#define mmHDMI_VBI_PACKET_CONTROL 0x1C10 +#define mmINPUT_CSC_C11_C12 0x1A36 +#define mmINPUT_CSC_C13_C14 0x1A37 +#define mmINPUT_CSC_C21_C22 0x1A38 +#define mmINPUT_CSC_C23_C24 0x1A39 +#define mmINPUT_CSC_C31_C32 0x1A3A +#define mmINPUT_CSC_C33_C34 0x1A3B +#define mmINPUT_CSC_CONTROL 0x1A35 +#define mmINPUT_GAMMA_CONTROL 0x1A10 +#define mmKEY_CONTROL 0x1A53 +#define mmKEY_RANGE_ALPHA 0x1A54 +#define mmKEY_RANGE_BLUE 0x1A57 +#define mmKEY_RANGE_GREEN 0x1A56 +#define mmKEY_RANGE_RED 0x1A55 +#define mmLB0_DC_MVP_LB_CONTROL 0x1ADB +#define mmLB0_LB_DEBUG 0x1AFC +#define mmLB0_LB_DEBUG2 0x1AC9 +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 +#define mmLB0_LB_SYNC_RESET_SEL 0x1ACA +#define mmLB0_LB_TEST_DEBUG_DATA 0x1AFF +#define mmLB0_LB_TEST_DEBUG_INDEX 0x1AFE +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9 +#define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA +#define mmLB1_DC_MVP_LB_CONTROL 0x1DDB +#define mmLB1_LB_DEBUG 0x1DFC +#define mmLB1_LB_DEBUG2 0x1DC9 +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8 +#define mmLB1_LB_SYNC_RESET_SEL 0x1DCA +#define mmLB1_LB_TEST_DEBUG_DATA 0x1DFF +#define mmLB1_LB_TEST_DEBUG_INDEX 0x1DFE +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9 +#define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA +#define mmLB2_DC_MVP_LB_CONTROL 0x40DB +#define mmLB2_LB_DEBUG 0x40FC +#define mmLB2_LB_DEBUG2 0x40C9 +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8 +#define mmLB2_LB_SYNC_RESET_SEL 0x40CA +#define mmLB2_LB_TEST_DEBUG_DATA 0x40FF +#define mmLB2_LB_TEST_DEBUG_INDEX 0x40FE +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9 +#define mmLB2_MVP_AFR_FLIP_MODE 0x40D8 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA +#define mmLB3_DC_MVP_LB_CONTROL 0x43DB +#define mmLB3_LB_DEBUG 0x43FC +#define mmLB3_LB_DEBUG2 0x43C9 +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8 +#define mmLB3_LB_SYNC_RESET_SEL 0x43CA +#define mmLB3_LB_TEST_DEBUG_DATA 0x43FF +#define mmLB3_LB_TEST_DEBUG_INDEX 0x43FE +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9 +#define mmLB3_MVP_AFR_FLIP_MODE 0x43D8 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA +#define mmLB4_DC_MVP_LB_CONTROL 0x46DB +#define mmLB4_LB_DEBUG 0x46FC +#define mmLB4_LB_DEBUG2 0x46C9 +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8 +#define mmLB4_LB_SYNC_RESET_SEL 0x46CA +#define mmLB4_LB_TEST_DEBUG_DATA 0x46FF +#define mmLB4_LB_TEST_DEBUG_INDEX 0x46FE +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9 +#define mmLB4_MVP_AFR_FLIP_MODE 0x46D8 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA +#define mmLB5_DC_MVP_LB_CONTROL 0x49DB +#define mmLB5_LB_DEBUG 0x49FC +#define mmLB5_LB_DEBUG2 0x49C9 +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8 +#define mmLB5_LB_SYNC_RESET_SEL 0x49CA +#define mmLB5_LB_TEST_DEBUG_DATA 0x49FF +#define mmLB5_LB_TEST_DEBUG_INDEX 0x49FE +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9 +#define mmLB5_MVP_AFR_FLIP_MODE 0x49D8 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA +#define mmLB_DEBUG 0x1AFC +#define mmLB_DEBUG2 0x1AC9 +#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 +#define mmLB_SYNC_RESET_SEL 0x1ACA +#define mmLB_TEST_DEBUG_DATA 0x1AFF +#define mmLB_TEST_DEBUG_INDEX 0x1AFE +#define mmLIGHT_SLEEP_CNTL 0x0132 +#define mmLOW_POWER_TILING_CONTROL 0x0325 +#define mmLVDS_DATA_CNTL 0x1C8C +#define mmLVTMA_PWRSEQ_CNTL 0x1919 +#define mmLVTMA_PWRSEQ_DELAY1 0x191C +#define mmLVTMA_PWRSEQ_DELAY2 0x191D +#define mmLVTMA_PWRSEQ_REF_DIV 0x191B +#define mmLVTMA_PWRSEQ_STATE 0x191A +#define mmMASTER_COMM_CMD_REG 0x161F +#define mmMASTER_COMM_CNTL_REG 0x1620 +#define mmMASTER_COMM_DATA_REG1 0x161C +#define mmMASTER_COMM_DATA_REG2 0x161D +#define mmMASTER_COMM_DATA_REG3 0x161E +#define mmMASTER_UPDATE_LOCK 0x1BBD +#define mmMASTER_UPDATE_MODE 0x1BBE +#define mmMC_DC_INTERFACE_NACK_STATUS 0x031C +#define mmMCIF_CONTROL 0x0314 +#define mmMCIF_MEM_CONTROL 0x0319 +#define mmMCIF_TEST_DEBUG_DATA 0x0317 +#define mmMCIF_TEST_DEBUG_INDEX 0x0316 +#define mmMCIF_VMID 0x0318 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x0315 +#define mmMICROSECOND_TIME_BASE_DIV 0x013B +#define mmMILLISECOND_TIME_BASE_DIV 0x0130 +#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1AD9 +#define mmMVP_AFR_FLIP_MODE 0x1AD8 +#define mmMVP_BLACK_KEYER 0x1686 +#define mmMVP_CONTROL1 0x1680 +#define mmMVP_CONTROL2 0x1681 +#define mmMVP_CONTROL3 0x168A +#define mmMVP_CRC_CNTL 0x1687 +#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 +#define mmMVP_CRC_RESULT_RED 0x1689 +#define mmMVP_DEBUG 0x168F +#define mmMVP_FIFO_CONTROL 0x1682 +#define mmMVP_FIFO_STATUS 0x1683 +#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ADA +#define mmMVP_INBAND_CNTL_CAP 0x1685 +#define mmMVP_RECEIVE_CNT_CNTL1 0x168B +#define mmMVP_RECEIVE_CNT_CNTL2 0x168C +#define mmMVP_SLAVE_STATUS 0x1684 +#define mmMVP_TEST_DEBUG_DATA 0x168E +#define mmMVP_TEST_DEBUG_INDEX 0x168D +#define mmOUTPUT_CSC_C11_C12 0x1A3D +#define mmOUTPUT_CSC_C13_C14 0x1A3E +#define mmOUTPUT_CSC_C21_C22 0x1A3F +#define mmOUTPUT_CSC_C23_C24 0x1A40 +#define mmOUTPUT_CSC_C31_C32 0x1A41 +#define mmOUTPUT_CSC_C33_C34 0x1A42 +#define mmOUTPUT_CSC_CONTROL 0x1A3C +#define mmOUT_ROUND_CONTROL 0x1A51 +#define mmOVL_CONTROL1 0x1A1D +#define mmOVL_CONTROL2 0x1A1E +#define mmOVL_DFQ_CONTROL 0x1A29 +#define mmOVL_DFQ_STATUS 0x1A2A +#define mmOVL_ENABLE 0x1A1C +#define mmOVL_END 0x1A26 +#define mmOVL_PITCH 0x1A21 +#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1A2C +#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1A92 +#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 +#define mmOVL_START 0x1A25 +#define mmOVL_STEREOSYNC_FLIP 0x1A93 +#define mmOVL_SURFACE_ADDRESS 0x1A20 +#define mmOVL_SURFACE_ADDRESS_HIGH 0x1A22 +#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B +#define mmOVL_SURFACE_ADDRESS_INUSE 0x1A28 +#define mmOVL_SURFACE_OFFSET_X 0x1A23 +#define mmOVL_SURFACE_OFFSET_Y 0x1A24 +#define mmOVL_SWAP_CNTL 0x1A1F +#define mmOVL_UPDATE 0x1A27 +#define mmPHY_AUX_CNTL 0x197F +#define mmPIPE0_ARBITRATION_CONTROL3 0x02FA +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x0328 +#define mmPIPE0_MAX_REQUESTS 0x0302 +#define mmPIPE0_PG_CONFIG 0x1760 +#define mmPIPE0_PG_ENABLE 0x1761 +#define mmPIPE0_PG_STATUS 0x1762 +#define mmPIPE1_ARBITRATION_CONTROL3 0x02FB +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x0330 +#define mmPIPE1_MAX_REQUESTS 0x0303 +#define mmPIPE1_PG_CONFIG 0x1764 +#define mmPIPE1_PG_ENABLE 0x1765 +#define mmPIPE1_PG_STATUS 0x1766 +#define mmPIPE2_ARBITRATION_CONTROL3 0x02FC +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x0338 +#define mmPIPE2_MAX_REQUESTS 0x0304 +#define mmPIPE2_PG_CONFIG 0x1768 +#define mmPIPE2_PG_ENABLE 0x1769 +#define mmPIPE2_PG_STATUS 0x176A +#define mmPIPE3_ARBITRATION_CONTROL3 0x02FD +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x0340 +#define mmPIPE3_MAX_REQUESTS 0x0305 +#define mmPIPE3_PG_CONFIG 0x176C +#define mmPIPE3_PG_ENABLE 0x176D +#define mmPIPE3_PG_STATUS 0x176E +#define mmPIPE4_ARBITRATION_CONTROL3 0x02FE +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x0348 +#define mmPIPE4_MAX_REQUESTS 0x0306 +#define mmPIPE4_PG_CONFIG 0x1770 +#define mmPIPE4_PG_ENABLE 0x1771 +#define mmPIPE4_PG_STATUS 0x1772 +#define mmPIPE5_ARBITRATION_CONTROL3 0x02FF +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x0350 +#define mmPIPE5_MAX_REQUESTS 0x0307 +#define mmPIPE5_PG_CONFIG 0x1774 +#define mmPIPE5_PG_ENABLE 0x1775 +#define mmPIPE5_PG_STATUS 0x1776 +#define mmPIXCLK0_RESYNC_CNTL 0x013A +#define mmPIXCLK1_RESYNC_CNTL 0x0138 +#define mmPIXCLK2_RESYNC_CNTL 0x0139 +#define mmPLL_ANALOG 0x1708 +#define mmPLL_CNTL 0x1707 +#define mmPLL_DEBUG_CNTL 0x170B +#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170F +#define mmPLL_DISPCLK_DTO_CNTL 0x170E +#define mmPLL_DS_CNTL 0x1705 +#define mmPLL_FB_DIV 0x1701 +#define mmPLL_IDCLK_CNTL 0x1706 +#define mmPLL_POST_DIV 0x1702 +#define mmPLL_REF_DIV 0x1700 +#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmPLL_SS_CNTL 0x1704 +#define mmPLL_UNLOCK_DETECT_CNTL 0x170A +#define mmPLL_UPDATE_CNTL 0x170D +#define mmPLL_UPDATE_LOCK 0x170C +#define mmPLL_VREG_CNTL 0x1709 +#define mmPRESCALE_GRPH_CONTROL 0x1A2D +#define mmPRESCALE_OVL_CONTROL 0x1A31 +#define mmPRESCALE_VALUES_GRPH_B 0x1A30 +#define mmPRESCALE_VALUES_GRPH_G 0x1A2F +#define mmPRESCALE_VALUES_GRPH_R 0x1A2E +#define mmPRESCALE_VALUES_OVL_CB 0x1A32 +#define mmPRESCALE_VALUES_OVL_CR 0x1A34 +#define mmPRESCALE_VALUES_OVL_Y 0x1A33 +#define mmREGAMMA_CNTLA_END_CNTL1 0x1AA6 +#define mmREGAMMA_CNTLA_END_CNTL2 0x1AA7 +#define mmREGAMMA_CNTLA_REGION_0_1 0x1AA8 +#define mmREGAMMA_CNTLA_REGION_10_11 0x1AAD +#define mmREGAMMA_CNTLA_REGION_12_13 0x1AAE +#define mmREGAMMA_CNTLA_REGION_14_15 0x1AAF +#define mmREGAMMA_CNTLA_REGION_2_3 0x1AA9 +#define mmREGAMMA_CNTLA_REGION_4_5 0x1AAA +#define mmREGAMMA_CNTLA_REGION_6_7 0x1AAB +#define mmREGAMMA_CNTLA_REGION_8_9 0x1AAC +#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 +#define mmREGAMMA_CNTLA_START_CNTL 0x1AA4 +#define mmREGAMMA_CNTLB_END_CNTL1 0x1AB2 +#define mmREGAMMA_CNTLB_END_CNTL2 0x1AB3 +#define mmREGAMMA_CNTLB_REGION_0_1 0x1AB4 +#define mmREGAMMA_CNTLB_REGION_10_11 0x1AB9 +#define mmREGAMMA_CNTLB_REGION_12_13 0x1ABA +#define mmREGAMMA_CNTLB_REGION_14_15 0x1ABB +#define mmREGAMMA_CNTLB_REGION_2_3 0x1AB5 +#define mmREGAMMA_CNTLB_REGION_4_5 0x1AB6 +#define mmREGAMMA_CNTLB_REGION_6_7 0x1AB7 +#define mmREGAMMA_CNTLB_REGION_8_9 0x1AB8 +#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 +#define mmREGAMMA_CNTLB_START_CNTL 0x1AB0 +#define mmREGAMMA_CONTROL 0x1AA0 +#define mmREGAMMA_LUT_DATA 0x1AA2 +#define mmREGAMMA_LUT_INDEX 0x1AA1 +#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1AA3 +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1B5E +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1B5F +#define mmSCL0_SCL_ALU_CONTROL 0x1B54 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1B47 +#define mmSCL0_SCL_BYPASS_CONTROL 0x1B45 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL0_SCL_CONTROL 0x1B44 +#define mmSCL0_SCL_DEBUG 0x1B6A +#define mmSCL0_SCL_DEBUG2 0x1B69 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x1B53 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1B4A +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1B4B +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1B46 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1B60 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1B61 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1B62 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1B63 +#define mmSCL0_SCL_TAP_CONTROL 0x1B43 +#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1B6C +#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1B6B +#define mmSCL0_SCL_UPDATE 0x1B51 +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1B4E +#define mmSCL0_SCL_VERT_FILTER_INIT 0x1B50 +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1B57 +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1B4F +#define mmSCL0_VIEWPORT_SIZE 0x1B5D +#define mmSCL0_VIEWPORT_START 0x1B5C +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1E5E +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1E5F +#define mmSCL1_SCL_ALU_CONTROL 0x1E54 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1E47 +#define mmSCL1_SCL_BYPASS_CONTROL 0x1E45 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41 +#define mmSCL1_SCL_CONTROL 0x1E44 +#define mmSCL1_SCL_DEBUG 0x1E6A +#define mmSCL1_SCL_DEBUG2 0x1E69 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x1E53 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1E4A +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1E4B +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1E46 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1E60 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1E61 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1E62 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1E63 +#define mmSCL1_SCL_TAP_CONTROL 0x1E43 +#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1E6C +#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1E6B +#define mmSCL1_SCL_UPDATE 0x1E51 +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1E4E +#define mmSCL1_SCL_VERT_FILTER_INIT 0x1E50 +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1E57 +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1E4F +#define mmSCL1_VIEWPORT_SIZE 0x1E5D +#define mmSCL1_VIEWPORT_START 0x1E5C +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415E +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415F +#define mmSCL2_SCL_ALU_CONTROL 0x4154 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define mmSCL2_SCL_BYPASS_CONTROL 0x4145 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL2_SCL_CONTROL 0x4144 +#define mmSCL2_SCL_DEBUG 0x416A +#define mmSCL2_SCL_DEBUG2 0x4169 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x414A +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x414B +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 +#define mmSCL2_SCL_TAP_CONTROL 0x4143 +#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416C +#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416B +#define mmSCL2_SCL_UPDATE 0x4151 +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414E +#define mmSCL2_SCL_VERT_FILTER_INIT 0x4150 +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x4157 +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414F +#define mmSCL2_VIEWPORT_SIZE 0x415D +#define mmSCL2_VIEWPORT_START 0x415C +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445E +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445F +#define mmSCL3_SCL_ALU_CONTROL 0x4454 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 +#define mmSCL3_SCL_BYPASS_CONTROL 0x4445 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 +#define mmSCL3_SCL_CONTROL 0x4444 +#define mmSCL3_SCL_DEBUG 0x446A +#define mmSCL3_SCL_DEBUG2 0x4469 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x444A +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x444B +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 +#define mmSCL3_SCL_TAP_CONTROL 0x4443 +#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446C +#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446B +#define mmSCL3_SCL_UPDATE 0x4451 +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444E +#define mmSCL3_SCL_VERT_FILTER_INIT 0x4450 +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x4457 +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444F +#define mmSCL3_VIEWPORT_SIZE 0x445D +#define mmSCL3_VIEWPORT_START 0x445C +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475E +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475F +#define mmSCL4_SCL_ALU_CONTROL 0x4754 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 +#define mmSCL4_SCL_BYPASS_CONTROL 0x4745 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 +#define mmSCL4_SCL_CONTROL 0x4744 +#define mmSCL4_SCL_DEBUG 0x476A +#define mmSCL4_SCL_DEBUG2 0x4769 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x474A +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x474B +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 +#define mmSCL4_SCL_TAP_CONTROL 0x4743 +#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476C +#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476B +#define mmSCL4_SCL_UPDATE 0x4751 +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474E +#define mmSCL4_SCL_VERT_FILTER_INIT 0x4750 +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x4757 +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474F +#define mmSCL4_VIEWPORT_SIZE 0x475D +#define mmSCL4_VIEWPORT_START 0x475C +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4A5E +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4A5F +#define mmSCL5_SCL_ALU_CONTROL 0x4A54 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4A47 +#define mmSCL5_SCL_BYPASS_CONTROL 0x4A45 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 +#define mmSCL5_SCL_CONTROL 0x4A44 +#define mmSCL5_SCL_DEBUG 0x4A6A +#define mmSCL5_SCL_DEBUG2 0x4A69 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x4A53 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4A4A +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4A4B +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4A46 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4A60 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4A61 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4A62 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4A63 +#define mmSCL5_SCL_TAP_CONTROL 0x4A43 +#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4A6C +#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4A6B +#define mmSCL5_SCL_UPDATE 0x4A51 +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4A4E +#define mmSCL5_SCL_VERT_FILTER_INIT 0x4A50 +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4A57 +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4A4F +#define mmSCL5_VIEWPORT_SIZE 0x4A5D +#define mmSCL5_VIEWPORT_START 0x4A5C +#define mmSCL_ALU_CONTROL 0x1B54 +#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1B47 +#define mmSCL_BYPASS_CONTROL 0x1B45 +#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55 +#define mmSCL_COEF_RAM_SELECT 0x1B40 +#define mmSCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL_CONTROL 0x1B44 +#define mmSCL_DEBUG 0x1B6A +#define mmSCL_DEBUG2 0x1B69 +#define mmSCL_F_SHARP_CONTROL 0x1B53 +#define mmSCL_HORZ_FILTER_CONTROL 0x1B4A +#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1B4B +#define mmSCLK_CGTT_BLK_CTRL_REG 0x0136 +#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1B46 +#define mmSCL_MODE_CHANGE_DET1 0x1B60 +#define mmSCL_MODE_CHANGE_DET2 0x1B61 +#define mmSCL_MODE_CHANGE_DET3 0x1B62 +#define mmSCL_MODE_CHANGE_MASK 0x1B63 +#define mmSCL_TAP_CONTROL 0x1B43 +#define mmSCL_TEST_DEBUG_DATA 0x1B6C +#define mmSCL_TEST_DEBUG_INDEX 0x1B6B +#define mmSCL_UPDATE 0x1B51 +#define mmSCL_VERT_FILTER_CONTROL 0x1B4E +#define mmSCL_VERT_FILTER_INIT 0x1B50 +#define mmSCL_VERT_FILTER_INIT_BOT 0x1B57 +#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1B4F +#define mmSEQ8_DATA 0x00F1 +#define mmSEQ8_IDX 0x00F1 +#define mmSLAVE_COMM_CMD_REG 0x1624 +#define mmSLAVE_COMM_CNTL_REG 0x1625 +#define mmSLAVE_COMM_DATA_REG1 0x1621 +#define mmSLAVE_COMM_DATA_REG2 0x1622 +#define mmSLAVE_COMM_DATA_REG3 0x1623 +#define mmSYMCLKA_CLOCK_ENABLE 0x0160 +#define mmSYMCLKB_CLOCK_ENABLE 0x0161 +#define mmSYMCLKC_CLOCK_ENABLE 0x0162 +#define mmSYMCLKD_CLOCK_ENABLE 0x0163 +#define mmSYMCLKE_CLOCK_ENABLE 0x0164 +#define mmSYMCLKF_CLOCK_ENABLE 0x0165 +#define mmTMDS_CNTL 0x1C7C +#define mmTMDS_CONTROL0_FEEDBACK 0x1C7E +#define mmTMDS_CONTROL_CHAR 0x1C7D +#define mmTMDS_CTL0_1_GEN_CNTL 0x1C86 +#define mmTMDS_CTL2_3_GEN_CNTL 0x1C87 +#define mmTMDS_CTL_BITS 0x1C83 +#define mmTMDS_DCBALANCER_CONTROL 0x1C84 +#define mmTMDS_DEBUG 0x1C82 +#define mmTMDS_STEREOSYNC_CTL_SEL 0x1C7F +#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 +#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 +#define mmUNIPHYAB_TPG_CONTROL 0x1931 +#define mmUNIPHYAB_TPG_SEED 0x1932 +#define mmUNIPHY_ANG_BIST_CNTL 0x198C +#define mmUNIPHYCD_TPG_CONTROL 0x1933 +#define mmUNIPHYCD_TPG_SEED 0x1934 +#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198E +#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198A +#define mmUNIPHYEF_TPG_CONTROL 0x1935 +#define mmUNIPHYEF_TPG_SEED 0x1936 +#define mmUNIPHY_IMPCAL_LINKA 0x1908 +#define mmUNIPHY_IMPCAL_LINKB 0x1909 +#define mmUNIPHY_IMPCAL_LINKC 0x190F +#define mmUNIPHY_IMPCAL_LINKD 0x1910 +#define mmUNIPHY_IMPCAL_LINKE 0x1913 +#define mmUNIPHY_IMPCAL_LINKF 0x1914 +#define mmUNIPHY_IMPCAL_PERIOD 0x190A +#define mmUNIPHY_IMPCAL_PSW_AB 0x190E +#define mmUNIPHY_IMPCAL_PSW_CD 0x1912 +#define mmUNIPHY_IMPCAL_PSW_EF 0x1916 +#define mmUNIPHY_LINK_CNTL 0x198D +#define mmUNIPHY_PLL_CONTROL1 0x1986 +#define mmUNIPHY_PLL_CONTROL2 0x1987 +#define mmUNIPHY_PLL_FBDIV 0x1985 +#define mmUNIPHY_PLL_SS_CNTL 0x1989 +#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmUNIPHY_POWER_CONTROL 0x1984 +#define mmUNIPHY_REG_TEST_OUTPUT 0x198B +#define mmUNIPHY_SOFT_RESET 0x0166 +#define mmUNIPHY_TX_CONTROL1 0x1980 +#define mmUNIPHY_TX_CONTROL2 0x1981 +#define mmUNIPHY_TX_CONTROL3 0x1982 +#define mmUNIPHY_TX_CONTROL4 0x1983 +#define mmVGA25_PPLL_ANALOG 0x00E4 +#define mmVGA25_PPLL_FB_DIV 0x00DC +#define mmVGA25_PPLL_POST_DIV 0x00E0 +#define mmVGA25_PPLL_REF_DIV 0x00D8 +#define mmVGA28_PPLL_ANALOG 0x00E5 +#define mmVGA28_PPLL_FB_DIV 0x00DD +#define mmVGA28_PPLL_POST_DIV 0x00E1 +#define mmVGA28_PPLL_REF_DIV 0x00D9 +#define mmVGA41_PPLL_ANALOG 0x00E6 +#define mmVGA41_PPLL_FB_DIV 0x00DE +#define mmVGA41_PPLL_POST_DIV 0x00E2 +#define mmVGA41_PPLL_REF_DIV 0x00DA +#define mmVGA_CACHE_CONTROL 0x00CB +#define mmVGA_DEBUG_READBACK_DATA 0x00D7 +#define mmVGA_DEBUG_READBACK_INDEX 0x00D6 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0x00C6 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0x00C8 +#define mmVGA_HDP_CONTROL 0x00CA +#define mmVGA_HW_DEBUG 0x00CF +#define mmVGA_INTERRUPT_CONTROL 0x00D1 +#define mmVGA_INTERRUPT_STATUS 0x00D3 +#define mmVGA_MAIN_CONTROL 0x00D4 +#define mmVGA_MEMORY_BASE_ADDRESS 0x00C4 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x00C9 +#define mmVGA_MEM_READ_PAGE_ADDR 0x0013 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0012 +#define mmVGA_MODE_CONTROL 0x00C2 +#define mmVGA_RENDER_CONTROL 0x00C0 +#define mmVGA_SEQUENCER_RESET_CONTROL 0x00C1 +#define mmVGA_SOURCE_SELECT 0x00FC +#define mmVGA_STATUS 0x00D0 +#define mmVGA_STATUS_CLEAR 0x00D2 +#define mmVGA_SURFACE_PITCH_SELECT 0x00C3 +#define mmVGA_TEST_CONTROL 0x00D5 +#define mmVGA_TEST_DEBUG_DATA 0x00C7 +#define mmVGA_TEST_DEBUG_INDEX 0x00C5 +#define mmVIEWPORT_SIZE 0x1B5D +#define mmVIEWPORT_START 0x1B5C +#define mmXDMA_CLOCK_GATING_CNTL 0x0409 +#define mmXDMA_IF_BIF_STATUS 0x0418 +#define mmXDMA_INTERRUPT 0x0406 +#define mmXDMA_LOCAL_SURFACE_TILING1 0x03F4 +#define mmXDMA_LOCAL_SURFACE_TILING2 0x03F5 +#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x03E9 +#define mmXDMA_MEM_POWER_CNTL 0x040B +#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x03F6 +#define mmXDMA_MSTR_CNTL 0x03E0 +#define mmXDMA_MSTR_HEIGHT 0x03E3 +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x03F1 +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x03F2 +#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x03F3 +#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x03EA +#define mmXDMA_MSTR_MEM_NACK_STATUS 0x040D +#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x03F7 +#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x040C +#define mmXDMA_MSTR_READ_COMMAND 0x03E1 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x03E6 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x03E7 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x03E4 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x03E5 +#define mmXDMA_MSTR_STATUS 0x03E8 +#define mmXDMA_RBBMIF_RDWR_CNTL 0x040A +#define mmXDMA_SLV_CNTL 0x03FB +#define mmXDMA_SLV_FLIP_PENDING 0x0407 +#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x03FD +#define mmXDMA_SLV_MEM_NACK_STATUS 0x040F +#define mmXDMA_SLV_PCIE_NACK_STATUS 0x040E +#define mmXDMA_SLV_READ_LATENCY_AVE 0x0405 +#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x0404 +#define mmXDMA_SLV_READ_LATENCY_TIMER 0x0412 +#define mmXDMA_SLV_READ_URGENT_CNTL 0x03FF +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x0402 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x0403 +#define mmXDMA_SLV_SLS_PITCH 0x03FE +#define mmXDMA_SLV_WB_RATE_CNTL 0x0401 +#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x0400 +#define mmXDMA_TEST_DEBUG_DATA 0x041D +#define mmXDMA_TEST_DEBUG_INDEX 0x041C + +/* Registers that spilled out of sid.h */ +#define mmDATA_FORMAT 0x1AC0 +#define mmDESKTOP_HEIGHT 0x1AC1 +#define mmDC_LB_MEMORY_SPLIT 0x1AC3 +#define mmPRIORITY_A_CNT 0x1AC6 +#define mmPRIORITY_B_CNT 0x1AC7 +#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32 +#define mmINT_MASK 0x1AD0 +#define mmVLINE_STATUS 0x1AEE +#define mmVBLANK_STATUS 0x1AEF + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h new file mode 100644 index 000000000000..9a4d4c299d5b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h @@ -0,0 +1,9836 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_6_0_SH_MASK_H +#define DCE_6_0_SH_MASK_H + +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000 +#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000ff00L +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x00000008 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00f00000L +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000014 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x0000001c +#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x00000002 +#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x00000003 +#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000c0L +#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x00000006 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0f000000L +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000018 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000f0000L +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x00000010 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00f00000L +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000014 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000f0L +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000004 +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000fL +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x00000000 +#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x00000010 +#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x00000012 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000f00L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000008 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000f000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x0000000c +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000f0000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000010 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00f00000L +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000014 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000f000L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0x0000000c +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x00000004 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x00000010 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x00000000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x00000008 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x00000000 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00L +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x00000008 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x00000008 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x00000010 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0x0000000c +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x00000008 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00ff0000L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x00000010 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0x0000000b +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000L +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x00000018 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000ffL +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x00000000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0x0000000f +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x00000010 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0x0000000b +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x0000001c +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000ff00L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x00000008 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x00000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x00000001 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00ff0000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x00000010 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x00000018 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x0000001a +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x00000018 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x00000017 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x00000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0x0000000c +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0x0000000e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x0000001e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x0000001f +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0x0000000b +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x00000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0x0000000c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000c00L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0x0000000a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00c00000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x00000016 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x0000001c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x0000001f +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x00000014 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x00008000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0x0000000f +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0c000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x0000001a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000f0000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x00000010 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x00000018 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x00000008 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x00006000L +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0x0000000d +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0x0000000c +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x00000080L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x00000007 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000f00L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x00000008 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x00000010 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x0000007fL +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x00000000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000c000L +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0x0000000e +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000ffffL +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x00000000 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000L +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x00000010 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000ffffL +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x00000000 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000L +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x00000018 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000ffL +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x00000000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000ff00L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x00000008 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00ff0000L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x00000010 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000L +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x00000018 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000ffL +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x00000000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000ff00L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x00000008 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00ff0000L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x00000010 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000L +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x00000018 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00ff0000L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x00000010 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x00000018 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000ffL +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x00000000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000ff00L +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x00000008 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000ffL +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x00000000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000ff00L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x00000008 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00ff0000L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x00000010 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000L +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x00000018 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000ffL +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x00000000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000ff00L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x00000008 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00ff0000L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x00000010 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000L +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x00000018 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000ffL +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x00000000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000ff00L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x00000008 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00ff0000L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x00000010 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000L +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x00000018 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000ffL +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x00000000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000ff00L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x00000008 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00ff0000L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x00000010 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000L +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x00000018 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000ffL +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x00000000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000ff00L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x00000008 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00ff0000L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x00000010 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000L +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x00000018 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000ffL +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x00000000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000ff00L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x00000008 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00ff0000L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x00000010 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000L +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x00000018 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x00000006 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x00000007 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0x0000000a +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x00000006 +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x00000000 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x00000007 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000ffL +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x00000000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000ff00L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x00000008 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00ff0000L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x00000010 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000L +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x00000018 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000ffL +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x00000000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000ff00L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x00000008 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00ff0000L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x00000010 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000L +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x00000018 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00ff0000L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x00000010 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x00000018 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000ffL +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x00000000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000ff00L +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x00000008 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000ffL +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x00000000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000ff00L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x00000008 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00ff0000L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x00000010 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000L +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x00000018 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000ffL +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x00000000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000ff00L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x00000008 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00ff0000L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x00000010 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000L +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x00000018 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000ffL +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x00000000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000ff00L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x00000008 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00ff0000L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x00000010 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000L +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x00000018 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000ffL +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x00000000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000ff00L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x00000008 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00ff0000L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x00000010 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000L +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x00000018 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000ffL +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x00000000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000ff00L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x00000008 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00ff0000L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x00000010 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000L +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x00000018 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000ffL +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x00000000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000ff00L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x00000008 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00ff0000L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x00000010 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000L +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x00000018 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0x0000000c +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000ffL +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x00000000 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x00000008 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x0000001f +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000L +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x00000018 +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x00000000 +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00ffffffL +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x00000000 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x00000004 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x00000018 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x0000001e +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x00000008 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x00000002 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x00000003 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000L +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x0000001e +#define ATTR00__ATTR_PAL_MASK 0x0000003fL +#define ATTR00__ATTR_PAL__SHIFT 0x00000000 +#define ATTR01__ATTR_PAL_MASK 0x0000003fL +#define ATTR01__ATTR_PAL__SHIFT 0x00000000 +#define ATTR02__ATTR_PAL_MASK 0x0000003fL +#define ATTR02__ATTR_PAL__SHIFT 0x00000000 +#define ATTR03__ATTR_PAL_MASK 0x0000003fL +#define ATTR03__ATTR_PAL__SHIFT 0x00000000 +#define ATTR04__ATTR_PAL_MASK 0x0000003fL +#define ATTR04__ATTR_PAL__SHIFT 0x00000000 +#define ATTR05__ATTR_PAL_MASK 0x0000003fL +#define ATTR05__ATTR_PAL__SHIFT 0x00000000 +#define ATTR06__ATTR_PAL_MASK 0x0000003fL +#define ATTR06__ATTR_PAL__SHIFT 0x00000000 +#define ATTR07__ATTR_PAL_MASK 0x0000003fL +#define ATTR07__ATTR_PAL__SHIFT 0x00000000 +#define ATTR08__ATTR_PAL_MASK 0x0000003fL +#define ATTR08__ATTR_PAL__SHIFT 0x00000000 +#define ATTR09__ATTR_PAL_MASK 0x0000003fL +#define ATTR09__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0A__ATTR_PAL_MASK 0x0000003fL +#define ATTR0A__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0B__ATTR_PAL_MASK 0x0000003fL +#define ATTR0B__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0C__ATTR_PAL_MASK 0x0000003fL +#define ATTR0C__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0D__ATTR_PAL_MASK 0x0000003fL +#define ATTR0D__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0E__ATTR_PAL_MASK 0x0000003fL +#define ATTR0E__ATTR_PAL__SHIFT 0x00000000 +#define ATTR0F__ATTR_PAL_MASK 0x0000003fL +#define ATTR0F__ATTR_PAL__SHIFT 0x00000000 +#define ATTR10__ATTR_BLINK_EN_MASK 0x00000008L +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x00000003 +#define ATTR10__ATTR_CSEL_EN_MASK 0x00000080L +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x00000007 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x00000001L +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x00000000 +#define ATTR10__ATTR_LGRPH_EN_MASK 0x00000004L +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x00000002 +#define ATTR10__ATTR_MONO_EN_MASK 0x00000002L +#define ATTR10__ATTR_MONO_EN__SHIFT 0x00000001 +#define ATTR10__ATTR_PANTOPONLY_MASK 0x00000020L +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x00000005 +#define ATTR10__ATTR_PCLKBY2_MASK 0x00000040L +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x00000006 +#define ATTR11__ATTR_OVSC_MASK 0x000000ffL +#define ATTR11__ATTR_OVSC__SHIFT 0x00000000 +#define ATTR12__ATTR_MAP_EN_MASK 0x0000000fL +#define ATTR12__ATTR_MAP_EN__SHIFT 0x00000000 +#define ATTR12__ATTR_VSMUX_MASK 0x00000030L +#define ATTR12__ATTR_VSMUX__SHIFT 0x00000004 +#define ATTR13__ATTR_PPAN_MASK 0x0000000fL +#define ATTR13__ATTR_PPAN__SHIFT 0x00000000 +#define ATTR14__ATTR_CSEL1_MASK 0x00000003L +#define ATTR14__ATTR_CSEL1__SHIFT 0x00000000 +#define ATTR14__ATTR_CSEL2_MASK 0x0000000cL +#define ATTR14__ATTR_CSEL2__SHIFT 0x00000002 +#define ATTRDR__ATTR_DATA_MASK 0x000000ffL +#define ATTRDR__ATTR_DATA__SHIFT 0x00000000 +#define ATTRDW__ATTR_DATA_MASK 0x000000ffL +#define ATTRDW__ATTR_DATA__SHIFT 0x00000000 +#define ATTRX__ATTR_IDX_MASK 0x0000001fL +#define ATTRX__ATTR_IDX__SHIFT 0x00000000 +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x00000020L +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x00000005 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x00000000 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x00000019 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x00000018 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0x0000000a +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x00000008 +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000cL +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x00000002 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x00000011 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000010 +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x00000010 +#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x0000001d +#define AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define AUX_CONTROL__AUX_EN__SHIFT 0x00000000 +#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x00000014 +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x00000010 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x00000018 +#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x00000008 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0x0000000c +#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x00000012 +#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x0000001c +#define AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define AUX_CONTROL__SPARE_0__SHIFT 0x0000001e +#define AUX_CONTROL__SPARE_1_MASK 0x80000000L +#define AUX_CONTROL__SPARE_1__SHIFT 0x0000001f +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x00000011 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x00000012 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x00000013 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x0000001c +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0x0000000c +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x00000014 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x00000008 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x00000004 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x00000018 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x00000010 +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000ffL +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x00000000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001f0000L +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x00000010 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000L +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x00000015 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x00000000 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001f00L +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x00000008 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x00000000 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003f00L +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x00000008 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x00000004 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01ff0000L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x00000010 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x00000000 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x00000000 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01ff0000L +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x00000010 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x00000004 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x00000000 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x00000005 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x00000004 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x00000006 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x00000001 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x00000000 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x00000002 +#define AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000ff00L +#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x00000008 +#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001f0000L +#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x00000010 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x0000001d +#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x00000000 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x00000009 +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0x0000000b +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000L +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x00000018 +#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x00000001 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x00000013 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0x0000000e +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x00000008 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0x0000000a +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x00000016 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x00000017 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x00000014 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x00000012 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x00000011 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x00000007 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x00000004 +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x0000001f +#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x0000001e +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0x0000000a +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x00000009 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x00000008 +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x00000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0f000000L +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x00000018 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00f00000L +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x00000014 +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000f0000L +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x00000010 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0x0000000a +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x00000009 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x00000008 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x00000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0f000000L +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x00000018 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00f00000L +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x00000014 +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000f0000L +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x00000010 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x00000002 +#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x00000000 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000f0L +#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x00000004 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001f0000L +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x00000010 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x0000001f +#define AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000ff00L +#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x00000000 +#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x00000008 +#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001f0000L +#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x00000010 +#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000L +#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x0000001e +#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x00000000 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x00000009 +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0x0000000b +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000L +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x00000018 +#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x00000001 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x00000013 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0x0000000e +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x00000008 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0x0000000a +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x00000016 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x00000017 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x00000014 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x00000012 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x00000011 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x00000007 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x00000004 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffffL +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x00000000 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000L +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x00000010 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000ffffL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x00000000 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x00000008 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffffL +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x00000000 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffffL +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x00000000 +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffffL +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x00000000 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x00000000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x00000010 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x00000011 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x00000004 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffffL +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00fc0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x00000012 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x0000001b +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007fL +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x0000001f +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x00000019 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000011 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000019 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000ffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00ff0000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000ffL +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x0000001c +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03ffffffL +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003fL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0x0000000f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007fL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000ffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000ffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000c0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x0000001f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000fc00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007fL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000ffL +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffffL +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007f00L +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x00000008 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00ff0000L +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x00000010 +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007fL +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x00000000 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x00000001 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x00000000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000ffffL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x00000000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000L +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x00000010 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000ffL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x00000000 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x00000008 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x00000004 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x00000000 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x00000030L +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x00000004 +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffffL +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x00000000 +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffffL +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x00000000 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000ffL +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x00000000 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x00000008 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffffL +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x00000000 +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffffL +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffffL +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x00000003 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x00000002 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x00000010 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x00000000 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x00000001 +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001ffffL +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x00000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000e0000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x00000011 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x00000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x00000008 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x00000010 +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001ffffL +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x00000000 +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x00000000 +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001ffffL +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x00000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x0000001e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x0000001f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000ffffL +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x00000000 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x0000001c +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000ffffL +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x00000000 +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x0000001f +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x0000001e +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000e0000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x00000011 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x00000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x00000008 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x00000010 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000f0000L +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x00000010 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000ffffL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x00000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x0000001c +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x00000002 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x00000001 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x00000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x00000014 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003ff0L +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x00000004 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0f000000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x00000018 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003f0000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x00000010 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x0000001c +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003f00L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x00000008 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x00000000 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007eL +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x00000001 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x00000004 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x00000010 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000ffffL +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x00000000 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000L +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x00000010 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000ffffL +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x00000000 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000L +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x00000010 +#define CRT00__H_TOTAL_MASK 0x000000ffL +#define CRT00__H_TOTAL__SHIFT 0x00000000 +#define CRT01__H_DISP_END_MASK 0x000000ffL +#define CRT01__H_DISP_END__SHIFT 0x00000000 +#define CRT02__H_BLANK_START_MASK 0x000000ffL +#define CRT02__H_BLANK_START__SHIFT 0x00000000 +#define CRT03__CR10CR11_R_DIS_B_MASK 0x00000080L +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x00000007 +#define CRT03__H_BLANK_END_MASK 0x0000001fL +#define CRT03__H_BLANK_END__SHIFT 0x00000000 +#define CRT03__H_DE_SKEW_MASK 0x00000060L +#define CRT03__H_DE_SKEW__SHIFT 0x00000005 +#define CRT04__H_SYNC_START_MASK 0x000000ffL +#define CRT04__H_SYNC_START__SHIFT 0x00000000 +#define CRT05__H_BLANK_END_B5_MASK 0x00000080L +#define CRT05__H_BLANK_END_B5__SHIFT 0x00000007 +#define CRT05__H_SYNC_END_MASK 0x0000001fL +#define CRT05__H_SYNC_END__SHIFT 0x00000000 +#define CRT05__H_SYNC_SKEW_MASK 0x00000060L +#define CRT05__H_SYNC_SKEW__SHIFT 0x00000005 +#define CRT06__V_TOTAL_MASK 0x000000ffL +#define CRT06__V_TOTAL__SHIFT 0x00000000 +#define CRT07__LINE_CMP_B8_MASK 0x00000010L +#define CRT07__LINE_CMP_B8__SHIFT 0x00000004 +#define CRT07__V_BLANK_START_B8_MASK 0x00000008L +#define CRT07__V_BLANK_START_B8__SHIFT 0x00000003 +#define CRT07__V_DISP_END_B8_MASK 0x00000002L +#define CRT07__V_DISP_END_B8__SHIFT 0x00000001 +#define CRT07__V_DISP_END_B9_MASK 0x00000040L +#define CRT07__V_DISP_END_B9__SHIFT 0x00000006 +#define CRT07__V_SYNC_START_B8_MASK 0x00000004L +#define CRT07__V_SYNC_START_B8__SHIFT 0x00000002 +#define CRT07__V_SYNC_START_B9_MASK 0x00000080L +#define CRT07__V_SYNC_START_B9__SHIFT 0x00000007 +#define CRT07__V_TOTAL_B8_MASK 0x00000001L +#define CRT07__V_TOTAL_B8__SHIFT 0x00000000 +#define CRT07__V_TOTAL_B9_MASK 0x00000020L +#define CRT07__V_TOTAL_B9__SHIFT 0x00000005 +#define CRT08__BYTE_PAN_MASK 0x00000060L +#define CRT08__BYTE_PAN__SHIFT 0x00000005 +#define CRT08__ROW_SCAN_START_MASK 0x0000001fL +#define CRT08__ROW_SCAN_START__SHIFT 0x00000000 +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x00000080L +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x00000007 +#define CRT09__LINE_CMP_B9_MASK 0x00000040L +#define CRT09__LINE_CMP_B9__SHIFT 0x00000006 +#define CRT09__MAX_ROW_SCAN_MASK 0x0000001fL +#define CRT09__MAX_ROW_SCAN__SHIFT 0x00000000 +#define CRT09__V_BLANK_START_B9_MASK 0x00000020L +#define CRT09__V_BLANK_START_B9__SHIFT 0x00000005 +#define CRT0A__CURSOR_DISABLE_MASK 0x00000020L +#define CRT0A__CURSOR_DISABLE__SHIFT 0x00000005 +#define CRT0A__CURSOR_START_MASK 0x0000001fL +#define CRT0A__CURSOR_START__SHIFT 0x00000000 +#define CRT0B__CURSOR_END_MASK 0x0000001fL +#define CRT0B__CURSOR_END__SHIFT 0x00000000 +#define CRT0B__CURSOR_SKEW_MASK 0x00000060L +#define CRT0B__CURSOR_SKEW__SHIFT 0x00000005 +#define CRT0C__DISP_START_MASK 0x000000ffL +#define CRT0C__DISP_START__SHIFT 0x00000000 +#define CRT0D__DISP_START_MASK 0x000000ffL +#define CRT0D__DISP_START__SHIFT 0x00000000 +#define CRT0E__CURSOR_LOC_HI_MASK 0x000000ffL +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x00000000 +#define CRT0F__CURSOR_LOC_LO_MASK 0x000000ffL +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x00000000 +#define CRT10__V_SYNC_START_MASK 0x000000ffL +#define CRT10__V_SYNC_START__SHIFT 0x00000000 +#define CRT11__C0T7_WR_ONLY_MASK 0x00000080L +#define CRT11__C0T7_WR_ONLY__SHIFT 0x00000007 +#define CRT11__SEL5_REFRESH_CYC_MASK 0x00000040L +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x00000006 +#define CRT11__V_INTR_CLR_MASK 0x00000010L +#define CRT11__V_INTR_CLR__SHIFT 0x00000004 +#define CRT11__V_INTR_EN_MASK 0x00000020L +#define CRT11__V_INTR_EN__SHIFT 0x00000005 +#define CRT11__V_SYNC_END_MASK 0x0000000fL +#define CRT11__V_SYNC_END__SHIFT 0x00000000 +#define CRT12__V_DISP_END_MASK 0x000000ffL +#define CRT12__V_DISP_END__SHIFT 0x00000000 +#define CRT13__DISP_PITCH_MASK 0x000000ffL +#define CRT13__DISP_PITCH__SHIFT 0x00000000 +#define CRT14__ADDR_CNT_BY4_MASK 0x00000020L +#define CRT14__ADDR_CNT_BY4__SHIFT 0x00000005 +#define CRT14__DOUBLE_WORD_MASK 0x00000040L +#define CRT14__DOUBLE_WORD__SHIFT 0x00000006 +#define CRT14__UNDRLN_LOC_MASK 0x0000001fL +#define CRT14__UNDRLN_LOC__SHIFT 0x00000000 +#define CRT15__V_BLANK_START_MASK 0x000000ffL +#define CRT15__V_BLANK_START__SHIFT 0x00000000 +#define CRT16__V_BLANK_END_MASK 0x000000ffL +#define CRT16__V_BLANK_END__SHIFT 0x00000000 +#define CRT17__ADDR_CNT_BY2_MASK 0x00000008L +#define CRT17__ADDR_CNT_BY2__SHIFT 0x00000003 +#define CRT17__BYTE_MODE_MASK 0x00000040L +#define CRT17__BYTE_MODE__SHIFT 0x00000006 +#define CRT17__CRTC_SYNC_EN_MASK 0x00000080L +#define CRT17__CRTC_SYNC_EN__SHIFT 0x00000007 +#define CRT17__RA0_AS_A13B_MASK 0x00000001L +#define CRT17__RA0_AS_A13B__SHIFT 0x00000000 +#define CRT17__RA1_AS_A14B_MASK 0x00000002L +#define CRT17__RA1_AS_A14B__SHIFT 0x00000001 +#define CRT17__VCOUNT_BY2_MASK 0x00000004L +#define CRT17__VCOUNT_BY2__SHIFT 0x00000002 +#define CRT17__WRAP_A15TOA0_MASK 0x00000020L +#define CRT17__WRAP_A15TOA0__SHIFT 0x00000005 +#define CRT18__LINE_CMP_MASK 0x000000ffL +#define CRT18__LINE_CMP__SHIFT 0x00000000 +#define CRT1E__GRPH_DEC_RD1_MASK 0x00000002L +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x00000001 +#define CRT1F__GRPH_DEC_RD0_MASK 0x000000ffL +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x00000000 +#define CRT22__GRPH_LATCH_DATA_MASK 0x000000ffL +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x00000000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x00000004 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x00000004 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x00000004 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x00000004 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x00000000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000c0000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x00000011 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x00000010 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x00000012 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0x0000000c +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x00000008 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x00000004 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x00000004 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x00000008 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000c000L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x00000009 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x00000000 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x00000004 +#define CRTC8_DATA__VCRTC_DATA_MASK 0x000000ffL +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x00000000 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x0000003fL +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x00000000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000ffL +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000010 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003ffL +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x00000000 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000ffc00L +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0x0000000a +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000L +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x00000014 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x00000008 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x00000010 +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x00000000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003ffL +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x00000000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000ffc00L +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0x0000000a +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000L +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x00000014 +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x00000010 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x00000008 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x00000018 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0x0000000d +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x00000014 +#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L +#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x00000000 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L +#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x0000001d +#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L +#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x00000001 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x0000001f +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x00000018 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x00000008 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0x0000000c +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x00000004 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x00000010 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x00000008 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x00000000 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001eL +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x00000001 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x00000000 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00001fffL +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x00000010 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x00000018 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x00000008 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x00000004 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x00000018 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x00000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x00000010 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x00000008 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x0000001c +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00001fffL +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x00000000 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001f0000L +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x00000010 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x00000013 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000ff00L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x00000008 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000ffL +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x00000000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x00000017 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x00000011 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x00000014 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x00000018 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x00000010 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000L +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x00000010 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00001fffL +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x00000000 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x00000010 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003ffL +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x00000000 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000L +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x00000010 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00001fffL +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x00000000 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x00000010 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x00000011 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x00000000 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000L +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x00000010 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00001fffL +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x00000000 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x00000010 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x00000011 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x00000000 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000L +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x00000010 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00001fffL +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x00000000 +#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00001fffL +#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x00000000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x00000000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x00000010 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x00000000 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x00000001 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x00000008 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x00000009 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x00000010 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x00000011 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x0000001e +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x0000001f +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x00000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x00000001 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x00000018 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x0000001a +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x00000019 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x0000001b +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x0000001c +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x0000001d +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x00000004 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x00000005 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x00000000 +#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L +#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x00000000 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00L +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x00000008 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x00000000 +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000ffL +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x00000000 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x00000014 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x00000004 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x00000010 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x00000000 +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00001fffL +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x00000000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003ffL +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x00000000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000ffc00L +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0x0000000a +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000L +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x00000014 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00ffffffL +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00001fffL +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x00000001 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x00000002 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x00000000 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000f0000L +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x00000011 +#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L +#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x00000010 +#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L +#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x00000012 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x00000001 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x00000005 +#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L +#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x00000000 +#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L +#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x00000004 +#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L +#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x00000002 +#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L +#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x00000003 +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00ffffffL +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffffL +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000L +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x00000010 +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00001fffL +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x00000000 +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffffL +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x00000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x00000018 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00001fffL +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x00000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0x0000000f +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x00000010 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x00000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x00000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x00000018 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x00000008 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x00000010 +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffffL +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000ffffL +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003f0000L +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x00000018 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x00000008 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000f000L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0x0000000c +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000fL +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x00000000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000f0L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x00000004 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x00000010 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000f00L +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x00000008 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x0000001f +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x00000018 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x00000014 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x00000009 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0x0000000b +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000e0L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x00000005 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0x0000000a +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x00000008 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x00000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x0000001f +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x00000018 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x00000014 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x00000009 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0x0000000b +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000e0L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x00000005 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0x0000000a +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x00000008 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001fL +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x00000000 +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x00000000 +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x00000000 +#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000L +#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x00000010 +#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00001fffL +#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x00000000 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000L +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x00000010 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00001fffL +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x00000000 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x00000010 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x00000008 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x00000000 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x00000000 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x00000000 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000L +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x00000010 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00001fffL +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x00000000 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x00000000 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000L +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x00000010 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00001fffL +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x00000000 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x00000004 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x00000000 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x00000008 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0x0000000c +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000L +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x00000010 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x00000004 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x00000000 +#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00001fffL +#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x00000000 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x00000008 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x00000004 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0x0000000c +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x00000000 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x00000010 +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00001fffL +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x00000000 +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00001fffL +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x00000000 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x00000008 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x00000000 +#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000ffL +#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x00000000 +#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000ff00L +#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x00000008 +#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00ff0000L +#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x00000010 +#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000ffL +#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x00000000 +#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000ff00L +#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x00000008 +#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00ff0000L +#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x00000010 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x00000004 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L +#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x00000010 +#define CUR_CONTROL__CURSOR_EN_MASK 0x00000001L +#define CUR_CONTROL__CURSOR_EN__SHIFT 0x00000000 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L +#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x00000014 +#define CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L +#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x00000008 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L +#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x00000018 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x003f0000L +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x00000010 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000003fL +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x00000000 +#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000L +#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x00000010 +#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003fffL +#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x00000000 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x00000000 +#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000003fL +#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x00000000 +#define CUR_SIZE__CURSOR_WIDTH_MASK 0x003f0000L +#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x00000010 +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffffL +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x00000000 +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L +#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x00000010 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L +#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x00000000 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x00000001 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x00000018 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x00000018 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x00000018 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x00000018 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x00000018 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x00000008 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x00000000 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x00000018 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000ffL +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x00000000 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000ffL +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x00000000 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000ff00L +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x00000010 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000ff00L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x00000008 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x00000000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x00000000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x00000010 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x00000018 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x00000004 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x00000010 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x00000008 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x00000000 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x00000000 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x00000004 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x00000012 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x00000000 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x00000008 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x00000011 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x00000010 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x00000001 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x00000002 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x00000003 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x00000000 +#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L +#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x00000000 +#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L +#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x00000008 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L +#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x00000010 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L +#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x00000000 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x00000100L +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x00000008 +#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L +#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x00000010 +#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L +#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x00000000 +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003fL +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x00000000 +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003fL +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003ffL +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000ffc00L +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0x0000000a +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000L +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x00000014 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003ffL +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000ffc00L +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0x0000000a +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000L +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x00000014 +#define DAC_DATA__DAC_DATA_MASK 0x0000003fL +#define DAC_DATA__DAC_DATA__SHIFT 0x00000000 +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffffL +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x00000000 +#define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L +#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x00000000 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x00000001 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x00000005 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x00000004 +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000cL +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x00000002 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x00000008 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003ffL +#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x00000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x00000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x01000000L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000018 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x00000008 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 +#define DAC_MASK__DAC_MASK_MASK 0x000000ffL +#define DAC_MASK__DAC_MASK__SHIFT 0x00000000 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x00000008 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x00000010 +#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L +#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L +#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x00000018 +#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x00000000 +#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L +#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x00000000 +#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L +#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x00000010 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0x000000ffL +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x00000000 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x00000000 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L +#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x00000003 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x00000000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x00000000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x00000010 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x00000008 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0x000000ffL +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x00000000 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x00000008 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x00000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07ff0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x00000010 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007fffL +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003ffL +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03ff0000L +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x00000010 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x0000001e +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001c +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x0000001f +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x0000001d +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003ffL +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x00000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03ff0000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x00000010 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x0000001f +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x0000001f +#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x00000000 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x00000008 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x00010000L +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x00000010 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x00000001L +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x00000000 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x00000100L +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x00000008 +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffffL +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x00000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x00000002 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x0000001f +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0x0000000a +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x00000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000010 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x00000008 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x00000001 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000018 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x00000009 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000017 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x00000018 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x0000001c +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x0000001e +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x00000010 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0x0000000c +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001d +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x00000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x00000008 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x00000014 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x00000000 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffffL +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x00000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000fL +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x00000000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000f00L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x00000008 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000f0000L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x00000010 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03ff0000L +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x00000010 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003ffL +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x00000000 +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03ff0000L +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x00000010 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003ffL +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03ff0000L +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x00000010 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003ffL +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x00000000 +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00ffffffL +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x00000000 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00ffffffL +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x00000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffffL +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x00000000 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000L +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x00000014 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000ffc00L +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0x0000000a +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003ffL +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffffL +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x00000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000010L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x00000004 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffffL +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x00000000 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x00000004 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x00000005 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x00000000 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x07000000L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x00000018 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x00000001 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x00000014 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x00000006 +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x00000010 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x00000002 +#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000L +#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x0000001c +#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x00000008 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x00000009 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0x0000000a +#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0x0000000b +#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0x0000000c +#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0x0000000d +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x00000000 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffffL +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x00000000 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffffL +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x00000000 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x00000008 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x00000000 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x00000001 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x00000007 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x00000006 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x00000004 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x00000002 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x00000003 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x00000005 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x00000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00010000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0x00000010 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000000ffL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x00000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x01000000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x00000018 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x0000ff00L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x00000008 +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x00001000L +#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0x0000000c +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x04000000L +#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x0000001a +#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x00000001L +#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x00000000 +#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x00010000L +#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 +#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x00000008 +#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x00100000L +#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 +#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x00000009 +#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x00200000L +#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 +#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x00000400L +#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0x0000000a +#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x00400000L +#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 +#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x00000800L +#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0x0000000b +#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x00800000L +#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x00000017 +#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x00001000L +#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0x0000000c +#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x01000000L +#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x00000018 +#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x00002000L +#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0x0000000d +#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x02000000L +#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x00000019 +#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000020L +#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000005 +#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00040000L +#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000012 +#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x00004000L +#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0x0000000e +#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x00080000L +#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 +#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000010L +#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000004 +#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00020000L +#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000011 +#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000002L +#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000001 +#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x00008000L +#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0x0000000f +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x00000000 +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffffL +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x0000001fL +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x00000020L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x00000005 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x00000040L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x00000006 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x00300000L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x00000014 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x00000080L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x00000007 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0x000fff00L +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x00000008 +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffffL +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x00000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x00001000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0x0000000c +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x0000000fL +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x00000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x000001f0L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x00000004 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x0000001c +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0x000f0000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x00000010 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x01f00000L +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x00000014 +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffffL +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x00000000 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x00000015 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x00000014 +#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L +#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x00000013 +#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x00000010L +#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x00000004 +#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x00000008L +#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x00000003 +#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x00000010L +#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x00000004 +#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x00000008L +#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x00000003 +#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x00000010L +#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x00000004 +#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x00000008L +#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x00000003 +#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x00000010L +#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x00000004 +#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x00000008L +#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x00000003 +#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x00000010L +#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x00000004 +#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x00000008L +#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x00000003 +#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x00000010L +#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x00000004 +#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x00000001L +#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 +#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x00000002L +#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x00000001 +#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x00000004L +#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x00000002 +#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x00000008L +#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x00000003 +#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0x0000000fL +#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x00000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x00000300L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x00003000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x0000001d +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x0000001e +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x00030000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x00000010 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0x00c00000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x00000016 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x03000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x00000018 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0x0000c000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x0000001c +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000006 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x00300000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0x000c0000L +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x00000012 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_EN__SHIFT 0x00000000 +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000f00L +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x00000008 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_EN__SHIFT 0x00000000 +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000f00L +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x00000008 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L +#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x00000014 +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x00000004 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x00000016 +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x00000010 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x00000014 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x00000006 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0f000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x00000018 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x00000008 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0x0000000c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0x0000000e +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x0000001c +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x00000000 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x00000008 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x00000010 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x00000008 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x10000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x07000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000L +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x10000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x07000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000L +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x10000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x07000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000L +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x0000001e +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x10000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x0000001c +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x07000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x00000018 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00ffffffL +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x00000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000L +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x0000001e +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x00000017 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x00000017 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x00000004L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x00000002 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x00000004 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x00000005 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x00000040L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x00000006 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000400L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0x0000000a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0x0000000c +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0x0000000d +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x00004000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0x0000000e +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x00040000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x00000012 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00400000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x00000018 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x04000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x0000001a +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x00000000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x00000008 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x00000010 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x00000014 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x00000015 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x00000016 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x00000017 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x00000000 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x00000008 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x00000010 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x00000018 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x00000000 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x00000008 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x00000010 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x00000018 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x00000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x00000003 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000004L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x00000002 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x00000008 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0x0000000b +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00000400L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0x0000000a +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x00000010 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x00000013 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00040000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x00000012 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x00000018 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x0000001b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x04000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x0000001a +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x00000000 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x00000008 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x00000010 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x00000018 +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x00000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x00000008 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x00000010 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x00000018 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x0000001a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x0000001c +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x00000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x00000008 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x00000010 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x00000018 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x0000001a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x0000001c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x00000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x00000040L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x00000006 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x00000008 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x00000009 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000400L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0x0000000a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x00000010 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x00000011 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x00040000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x00000012 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x00000014 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x00000015 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00400000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x00000016 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x00000018 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x00000019 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x04000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x0000001a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x0000001c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x0000001d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x0000001e +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x00000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x00000008 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x00000010 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x00000018 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x0000001a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x0000001c +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x00000001 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x00000002 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x00000004 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x00000005 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x00000006 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x00000000 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x00000001 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0f000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x00000018 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x0000001c +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000f0000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x00000010 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00f00000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x00000014 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000fL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x00000000 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000f0L +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x00000004 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x00000001 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00000040L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x00000006 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0x0000000c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x00004000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0x0000000e +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x00000010 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x00000014 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00400000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x00000016 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x00000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x00000008 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x00000010 +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x00000018 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x00000004 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x00000040L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x00000006 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x0000001c +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x00000008 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0x0000000c +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x00004000L +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0x0000000e +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x00000000 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x00000008 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003fL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x00000000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x00000008 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0x0000000b +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001c000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0x0000000e +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000e0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x00000011 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x00000014 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x00000017 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffffL +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x00000004 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x00000008 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0x0000000c +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x00000010 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x00000014 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x00000000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x00000004 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x00000008 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0x0000000c +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x00000010 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x00000014 +#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000L +#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x0000001c +#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x00000001L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x00000000 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x00010000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x00000010 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x00000100L +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x01000000L +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x00000001L +#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x00000002L +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x00000001 +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000L +#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x0000001c +#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x00000001L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x00000000 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x00010000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x00000010 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x00000100L +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x01000000L +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x00000001L +#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x00000002L +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x00000001 +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000L +#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x0000001c +#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x00000001L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x00000000 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x00010000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x00000010 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x00000100L +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x01000000L +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x00000001L +#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x00000002L +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x00000001 +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000L +#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x0000001c +#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x00000001L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x00000000 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x00010000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x00000010 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x00000100L +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x01000000L +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x00000001L +#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x00000002L +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x00000001 +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000L +#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x0000001c +#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x00000001L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x00000000 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x00010000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x00000010 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x00000100L +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x01000000L +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x00000001L +#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x00000002L +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x00000001 +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x00001fffL +#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x00000000 +#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000L +#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x0000001c +#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x03ff0000L +#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x00000010 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x00000018 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x00000001L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x00000000 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x00010000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x00000010 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x00000100L +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x00000008 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x00100000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x00000014 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x01000000L +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x00000018 +#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x00000001L +#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x00000000 +#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x00000100L +#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x00000008 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x00000010L +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x00000004 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x00000002L +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x00000001 +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0x000000ffL +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x00000000 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0x0ff00000L +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x00000014 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x00000008 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0x0000000c +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x00000019 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x00000018 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x00000004 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000cL +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x00000002 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x00000015 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x00000000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x00000014 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x0000001f +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x00000008 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x00000000 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x00000002 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x00000001 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x00000003 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x00000014 +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000ff00L +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x00000000 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x00000008 +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x00ff0000L +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x00000010 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x0000001f +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x0000001c +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x00000014 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x00000003 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x00000011 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x00000007 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x00000000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x00000004 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x00000005 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x00000006 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000L +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x00000018 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x00000010 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x00000000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00f00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x00000014 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x0000001c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000ffffL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x00000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x00000005 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x00000004 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x00000006 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x00000009 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x00000008 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0x0000000a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0x0000000d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0x0000000c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0x0000000e +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x00000011 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x00000010 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x00000012 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x00000015 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x00000014 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x00000016 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x00000019 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x00000018 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x0000001a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x0000001c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x0000001b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x0000001d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x00000001 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x00000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x00000002 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x00000004 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x00000007 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x00000002 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x00000006 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0x0000000c +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0x0000000d +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0x0000000e +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0x0000000f +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x00000012 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x00000000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x00000008 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x00000005 +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x00000008 +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x00ff0000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x00000010 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x00000000 +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0x0000000c +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0x0000000d +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x00000008 +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000L +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x0000001b +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001fL +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x00000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x0000000f +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x00000010 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x00000011 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x00000012 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x00000013 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x00000014 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x00000015 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x00000009 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x0000000b +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0x0000000d +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x00000006 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x00000005 +#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x00004000L +#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0x0000000e +#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x00000400L +#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0x0000000a +#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x00001000L +#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0x0000000c +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x00400000L +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x00000016 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x00000017 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x00000008 +#define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0x0000000fL +#define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x00000000 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x00003000L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000040L +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000006 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000001 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x0000c000L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000080L +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000007 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00030000L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x000c0000L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000200L +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000009 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00300000L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000400L +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000a +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00c00000L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000800L +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000b +#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x00000003L +#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x00000000 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0x0000000cL +#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x00000002 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x00000030L +#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x00000004 +#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0x00c00000L +#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000L +#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x0000001c +#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x00000003L +#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x00000000 +#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0x0000000cL +#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x00000002 +#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x00000030L +#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x00000004 +#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0x000000c0L +#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x00000006 +#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x00000300L +#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0x00000c00L +#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0x0000000a +#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x00003000L +#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0x0c000000L +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x0000001a +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x03000000L +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x00000018 +#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x00030000L +#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0x000c0000L +#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0x0000c000L +#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x00300000L +#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x00040000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x00000012 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x00008000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x00004000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0x0000000e +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x00002000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0x0000000d +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0x0000000f +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x00100000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x00080000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x00000013 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x00010000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x00000010 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x00000014 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x00400000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x00000016 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x00200000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x00000015 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x08000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x04000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x0000001a +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x0000001b +#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x00800000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x00000017 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x00020000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x00000011 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x02000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x00000019 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x01000000L +#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x00000018 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x00001000L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0x0000000c +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0x000000c0L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x00000003L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x00000000 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x00000006 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0x00000c00L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x00000030L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x00000004 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0x0000000a +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0x0000000cL +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x00000002 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x00000300L +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x00000008 +#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffffL +#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x00000000 +#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffffL +#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x00000000 +#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffffL +#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x00000000 +#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffffL +#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x00000000 +#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffffL +#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x00000000 +#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffffL +#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x00000000 +#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffffL +#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x00000000 +#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffffL +#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x00000000 +#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffffL +#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x00000000 +#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffffL +#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x00000000 +#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffffL +#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x00000000 +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffffL +#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x00000000 +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffffL +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x00000000 +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffffL +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x00000000 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x00000008 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x00000008 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x00000018 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x00000008 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x00000018 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 +#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000fL +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0x0000000c +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x00000005 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x00000008 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x00000004 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x00000005 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x00000006 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x00000007 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x00000008 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x00000009 +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00001000L +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0x0000000c +#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L +#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x00000003 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L +#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x00000002 +#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x00000000 +#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L +#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x00000001 +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003ffL +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x00000000 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000ffc00L +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0x0000000a +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000L +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x00000014 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x00000001 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x00000000 +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000ffffL +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x00000000 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x00000005 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000c0L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x00000006 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x00000004 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0x0000000d +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000c000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0x0000000e +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0x0000000c +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x00000015 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00c00000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x00000016 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x00000014 +#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000fL +#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x00000000 +#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000f00L +#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x00000008 +#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000f0000L +#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x00000010 +#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000ffffL +#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x00000000 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000L +#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x00000010 +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000ffL +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x00000000 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x00000000 +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000ffffL +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x00000000 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x00000000 +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000ffffL +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x00000000 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x0000001f +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x0000001c +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0x0000000c +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x00000010 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x00000008 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x00000014 +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x00000000 +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x0000001fL +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x00000000 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x00000006 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x00000008 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x00000009 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x00000018 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x00000019 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x0000001a +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x0000001b +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x0000001c +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x0000001d +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x00000007 +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x00000010 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x00000011 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x00000012 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x00000013 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x00000014 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x00000015 +#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x00001000L +#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0x0000000c +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x00000005 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x00000040L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x00000006 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x00000100L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x00000008 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x00000200L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x00000009 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x01000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x00000018 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x02000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x00000019 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x04000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x0000001a +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x08000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x0000001b +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x0000001c +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x0000001d +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x00000080L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x00000007 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x00010000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x00000010 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x00020000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x00000011 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x00040000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x00000012 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x00080000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x00000013 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x00100000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x00000014 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x00200000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x00000015 +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x00001000L +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0x0000000c +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x00000020L +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x00000005 +#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x00000008L +#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x00000003 +#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x00020000L +#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x00000011 +#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 +#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x00040000L +#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x00000012 +#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 +#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x00080000L +#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 +#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x00000006 +#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x00100000L +#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 +#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x00000007 +#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x00200000L +#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 +#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x00000008 +#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x00400000L +#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 +#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x00000009 +#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x00000400L +#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0x0000000a +#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x00000800L +#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0x0000000b +#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x00001000L +#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0x0000000c +#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x00002000L +#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0x0000000d +#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x00004000L +#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0x0000000e +#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000002L +#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x00000001 +#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x00000004L +#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x00000002 +#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x00010000L +#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 +#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0x000000c0L +#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x00000006 +#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x00000300L +#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x00000008 +#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0x00000c00L +#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0x0000000a +#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x00003000L +#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0x0000000c +#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0x0000c000L +#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0x0000000e +#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x00030000L +#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x00000010 +#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0x000c0000L +#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x00000012 +#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x00300000L +#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x00000014 +#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0x00c00000L +#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x00000016 +#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x03000000L +#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x00000018 +#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0x0c000000L +#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x0000001a +#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000L +#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x0000001c +#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0x0000000cL +#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x00000002 +#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x00000030L +#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x00000004 +#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x00000003L +#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x00000000 +#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L +#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x00000019 +#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000L +#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x0000001d +#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L +#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x00000000 +#define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x00000002L +#define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x00000001 +#define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x00000003 +#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L +#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x0000001b +#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L +#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x00000010 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L +#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x00000011 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L +#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x00000012 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L +#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x00000013 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L +#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x00000014 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L +#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x00000015 +#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L +#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x00000018 +#define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x00000002 +#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000L +#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x0000001c +#define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x04000000L +#define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x0000001a +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000fL +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x00000000 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x00000004 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x00000000 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x00000008 +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001cL +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x00000002 +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffffL +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x00000000 +#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffffL +#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x00000000 +#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffffL +#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x00000000 +#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffffL +#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x00000000 +#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffffL +#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x00000000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003ffffL +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x00000000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07f00000L +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x00000014 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000L +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x00000010 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x00000004L +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x00000002 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x00000001L +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x00000000 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x00000002L +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x00000001 +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffffL +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x00000000 +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffffL +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x00000000 +#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L +#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x00000000 +#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L +#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x00000001 +#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L +#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x00000002 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x0000001b +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000L +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x0000001c +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x0000f000L +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x0000000c +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00010000L +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x00000010 +#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x00000300L +#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x00000008 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x00000018 +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000c000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0x0000000e +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x00000400L +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0x0000000a +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x00000010 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0x0000000d +#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x00000800L +#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0x0000000b +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000fL +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x00000000 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000000f0L +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x00000004 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00ff0000L +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x00000010 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000ff00L +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x00000008 +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000ffL +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x00000000 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x00000008 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000a +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x00000009 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x00000040L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x00000006 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x00000000 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x00000004 +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0x00000007L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x00000000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x00000070L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x00000004 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x00000080L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0x00000700L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0x00000008 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x00000800L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x0000000b +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x00007000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x0000000c +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x00008000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x0000000f +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0x00070000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x00000010 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x00080000L +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x00000013 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x00000007L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x00000000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0x00000070L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x00000004 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x00000080L +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x00000008 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000 +#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x00400000L +#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x00000016 +#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x00010000L +#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x00000010 +#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x00100000L +#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x00000014 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x0000003fL +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x00000000 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x00000700L +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x00000008 +#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x00200000L +#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x00000015 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000 +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004 +#define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L +#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x00000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x00000013 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0x0000000f +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x00000011 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x00000012 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007f00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x00000008 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007fL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x00000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x00000014 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x00000015 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x00000016 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x00000018 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00003f00L +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x00000008 +#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x0000001c +#define DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x00000010 +#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x00000000 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x00000008 +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003ffL +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x00000000 +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x00000001L +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x00000000 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x00000100L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x00000008 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x00000010L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x00001000L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0x0000000c +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x00000004 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x00000001L +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x00000000 +#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00010000L +#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x00000010 +#define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00100000L +#define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x00000014 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x00000000 +#define DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG_FE_CNTL__DIG_START__SHIFT 0x0000000a +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x00000008 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x00000004 +#define DIG_FE_CNTL__DIG_SWAP_MASK 0x00040000L +#define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x00000012 +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x00000018 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x00000008 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x00000000 +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001f0000L +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x00000008 +#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x00000000 +#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x00000001 +#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x00000002 +#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x00000003 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x00000008 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x00000000 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x00000004 +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffffL +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x00000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00ffffffL +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x00000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x00000018 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x00000001 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x00000000 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x00000005 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x00000004 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x00000009 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x00000008 +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0x0000000d +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0x0000000c +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x00000011 +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x00000010 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x00000015 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x00000014 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x00000001 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x00000004 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x00000005 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03ff0000L +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x00000010 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x00000006 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x00000000 +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x00000100L +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x00000008 +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x00000004L +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x00000002 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x0000001e +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x0000001c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x0000001d +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x0000001f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x00000014 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0e000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x00000019 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003fffL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x00000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000f0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x0000001e +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x0000001c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x0000001d +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x00000014 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x00000013 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x00000018 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x00000007 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x00000008 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x00000016 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x00000017 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x00000011 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x00000012 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x00000019 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x00000018 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x00000015 +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x0000001f +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x0000001b +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x0000001a +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x00000003 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x00000002 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 +#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L +#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x00000000 +#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L +#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x00000010 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0x000000f0L +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x00000004 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x00000001L +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x00000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01ffffffL +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x00000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x00000019 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x08000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x0000001b +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x04000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x0000001a +#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x0000001e +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x0000001d +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000L +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x0000001c +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x00000002 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x00000003 +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x00000004 +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x00000001 +#define DMCU_CTRL__RESET_UC_MASK 0x00000001L +#define DMCU_CTRL__RESET_UC__SHIFT 0x00000000 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000L +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x00000016 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000ffffL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x00000000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000f0000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x00000010 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x00000014 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffffL +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x00000000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000ffffL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x00000000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000f0000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x00000010 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x00000014 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffffL +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x00000000 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x00000000 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x00000017 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007f0000L +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x00000010 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000cL +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x00000002 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x00000000 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffffL +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x00000000 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffffL +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x00000000 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00ff0000L +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x00000010 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000ffL +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x00000000 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000ff00L +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x00000002 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x00000002 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x00000000 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x00000000 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x00000001 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x00000001 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x00000012 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000012 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x0000000c +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0000000c +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x00000013 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000013 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x0000000d +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x0000000d +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x00000014 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000014 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x0000000e +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x0000000e +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x00000015 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000015 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0x0000000f +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x0000000f +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x00000016 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000016 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x00000010 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x00000010 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x00000017 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000017 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x00000011 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x00000011 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x00000008 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x00000003 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x00000009 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0x0000000a +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0x0000000a +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0x0000000b +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0x0000000b +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x00000018 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x00000018 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x00000019 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x00000019 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x0000001a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x0000001a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x0000001b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x0000001b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x0000001c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x0000001c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x0000001d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x0000001d +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x00000009 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0x0000000a +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0x0000000b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x00000008 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x00000003 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x00000018 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x00000019 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x0000001a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x0000001b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x0000001c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x0000001d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x00000002 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000001 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000012 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000013 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000014 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000015 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000f +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000016 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000010 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000017 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000011 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x00000008 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000003 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x00000018 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x00000019 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001d +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003ffL +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x00000000 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000ffL +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x00000000 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003ffL +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x00000000 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000ffL +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x00000000 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000ffL +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x00000000 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000ff00L +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x00000008 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x00000004 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x00000001 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x00000000 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x00000005 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x00000003 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x00000002 +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0x0000ff00L +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x00000008 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x00000000 +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x00000002 +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x00000001 +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x00000008 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x00000000 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x00000010 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x00000003 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x00000000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0x0000000e +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0x0000000f +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x00000009 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x00000002 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0x0000000d +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0x0000000c +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0x0000000b +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0x0000000a +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x00000007 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x00000006 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x00000005 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x00000004 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x00000008 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x00000001 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x0000001c +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000ffffL +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x00000000 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000L +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x00000010 +#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L +#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x00000000 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x0000001d +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000L +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x00000018 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x00000004 +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0000f000L +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0x0000000c +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x00000002 +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x003f0000L +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x00000010 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x00000008 +#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0x0000ffffL +#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x00000000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x00010000L +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x00000010 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0x0ffe0000L +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x00000011 +#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0x0000ffffL +#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x00000000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x00010000L +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x00000010 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0x0ffe0000L +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x00000011 +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffffL +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x00000000 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x00000008 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x00000009 +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x00000000 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x00000001 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x00000002 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x00000003 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x00000004 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x00000005 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003f00L +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x00000008 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00010000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x00000010 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00700000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x00000014 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00020000L +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x00000011 +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003fL +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x00000000 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x07000000L +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x00000018 +#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L +#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x0000001c +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L +#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x00000004 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L +#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x00000000 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x00000008 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x00000000 +#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffffL +#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x00000000 +#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffffL +#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x00000000 +#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffffL +#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x00000000 +#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffffL +#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x00000000 +#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffffL +#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x00000000 +#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffffL +#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x00000000 +#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffffL +#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x00000000 +#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffffL +#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffffL +#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffffL +#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffffL +#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffffL +#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffffL +#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffffL +#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffffL +#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffffL +#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffffL +#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffffL +#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffffL +#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffffL +#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffffL +#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffffL +#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffffL +#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffffL +#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffffL +#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffffL +#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffffL +#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffffL +#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffffL +#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffffL +#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffffL +#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffffL +#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffffL +#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffffL +#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffffL +#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffffL +#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffffL +#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffffL +#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffffL +#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffffL +#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffffL +#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffffL +#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffffL +#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffffL +#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffffL +#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffffL +#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffffL +#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffffL +#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffffL +#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffffL +#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffffL +#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffffL +#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffffL +#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffffL +#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffffL +#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffffL +#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffffL +#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffffL +#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffffL +#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffffL +#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffffL +#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x00000000 +#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffffL +#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x00000000 +#define DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x00000000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x00000018 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x00000010 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x00000008 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x00000000 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x00000001 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x00000002 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x00000003 +#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x00000010 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x00000018 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x00000000 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00ff0000L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x00000010 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x00000004 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x00000004 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x00000000 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003fL +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x00000000 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003f00L +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x00000010 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x00000008 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x00000000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000ff00L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x00000008 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00ff0000L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x00000010 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000L +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x00000018 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000ffL +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x00000000 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000fff00L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x00000008 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x00000014 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x00000002 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x00000000 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x00000001 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0x0000000c +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x00000008 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x00000004 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x00000000 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x00000000 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x00000008 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x00000004 +#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003ffL +#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x00000000 +#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000ffc00L +#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0x0000000a +#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000L +#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x00000014 +#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003ffL +#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x00000000 +#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000ffc00L +#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0x0000000a +#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000L +#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x00000014 +#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003ffL +#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x00000000 +#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000ffc00L +#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0x0000000a +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x00000000 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffffL +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x00000000 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffffL +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x00000000 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffffL +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x00000000 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffffL +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x00000000 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffffL +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x00000000 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffffL +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x00000000 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffffL +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x00000000 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffffL +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x00000000 +#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffffL +#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x00000000 +#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffffL +#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x00000000 +#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffffL +#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x00000000 +#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffffL +#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000L +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x00000010 +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000ffffL +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000ffffL +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x00000004 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x00000100L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x00000008 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x00003000L +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x0000000a +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x00000009 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x00000000 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x00000004 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x00000007 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x00000005 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x00000006 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x0000000b +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x0000000a +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x00000009 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x00000004 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x00000007 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x00000005 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x00000006 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0x0000000b +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0x0000000a +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x00000009 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x00000008 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000L +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x00000010 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000ffffL +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x00000000 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x00000011 +#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x00000008 +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x00000004 +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003ffffL +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x00000000 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x00000018 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x0000001c +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x00000008 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000ffL +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x00000000 +#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000f8L +#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x00000003 +#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000ff00L +#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x00000008 +#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00ff0000L +#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x00000010 +#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000L +#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x00000018 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x00000000 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0001fff0L +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x00000004 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000L +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x00000010 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00001fffL +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x00000000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003ffL +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x00000000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x00000010 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x00000000 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x00000004 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x00000008 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000L +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x0000001a +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03ffffffL +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x00000000 +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x00000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003f00L +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x00000008 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000L +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x00000018 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x00000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x00000010 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003f00L +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x00000008 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000L +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x00000018 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x00000000 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x00000010 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003f00L +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x00000008 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000L +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x00000018 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x00000000 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x00000010 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x00000008 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x00000000 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x00000018 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L +#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x00000008 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000003L +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x00000000 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x00000010 +#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00ffffffL +#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x00000000 +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00ffffffL +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x00000000 +#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00ffffffL +#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x00000000 +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00ffffffL +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x00000000 +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x00000000 +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x00000010 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0x0000000c +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x00000004 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x00000008 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x00000018 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x00000014 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x00000015 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x00000016 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x00000017 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x0000001c +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x00000000 +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000fffL +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x00000000 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000ffffL +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x00000000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003fffL +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x00000000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000L +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x00000010 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x0000001c +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x0000001d +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x00000018 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x00000014 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x00000010 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000eL +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x00000001 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x00000004 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003f00L +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x00000008 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x00000000 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x00000000 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x00000006 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x00000004 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x00000005 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x00000007 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0x0000000c +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x00000008 +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x00000001 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x00000000 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x00000002 +#define DP_VID_M__DP_VID_M_MASK 0x00ffffffL +#define DP_VID_M__DP_VID_M__SHIFT 0x00000000 +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000fffL +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x00000000 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x00000010 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x00000018 +#define DP_VID_N__DP_VID_N_MASK 0x00ffffffL +#define DP_VID_N__DP_VID_N__SHIFT 0x00000000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x00000014 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x00000008 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x00000000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x00000010 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x00000008 +#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000L +#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x00000018 +#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L +#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x00000000 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x00000012 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x00000012 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x00000014 +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x00000018 +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x0000001c +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x00000011 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001f00L +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x00000008 +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x00000010 +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x00000000 +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x00000012 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x00000000 +#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x03000000L +#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x00000018 +#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000L +#define DVO_CONTROL__DVO_CTL3__SHIFT 0x0000001f +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x00000100L +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x00000008 +#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x00040000L +#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x00000012 +#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x00000001L +#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x00000000 +#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x00010000L +#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x00000010 +#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x00000002L +#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x00000001 +#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x00020000L +#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x00000011 +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x07ffffffL +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x00000000 +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x07ffffffL +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x00000000 +#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x00010000L +#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x00000010 +#define DVO_ENABLE__DVO_ENABLE_MASK 0x00000001L +#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x00000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x0000001d +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x00000100L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x00000008 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x00000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 +#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x00000100L +#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x00000008 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x00000003L +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x00000000 +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffffL +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x00000000 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x00000007L +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x00000000 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x00070000L +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x00000010 +#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000f000L +#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0x0000000c +#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000f00L +#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x00000008 +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x0000001c +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x0000001d +#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000f0L +#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x00000004 +#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000fL +#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x00000000 +#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000f0L +#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x00000004 +#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L +#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x00000000 +#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L +#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x00000001 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x0fff0000L +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00000fffL +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00000fffL +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x0fff0000L +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000f0000L +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x00000010 +#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L +#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x00000010 +#define FBC_CNTL__FBC_EN_MASK 0x80000000L +#define FBC_CNTL__FBC_EN__SHIFT 0x0000001f +#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L +#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x00000000 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x00000019 +#define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000eL +#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x00000001 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x00000010 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x00000011 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x00000012 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x00000013 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x00000014 +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000fL +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x00000000 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x00000008 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0x0000000a +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x00000009 +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0x0000000b +#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L +#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x00000010 +#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L +#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x000003ffL +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x03ff0000L +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x00000010 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x000003ffL +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x00000000 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x03ff0000L +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x00000010 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x00010000L +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x00000010 +#define FBC_DEBUG0__FBC_DEBUG0_MASK 0x00fe0000L +#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x00000011 +#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000L +#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x00000018 +#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0x000000ffL +#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x00000000 +#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0x0000ff00L +#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x00000008 +#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffffL +#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x00000000 +#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffffL +#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x00000000 +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x0000000b +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000f0L +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x00000004 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x00000008 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x0000000a +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x00000003 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L +#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x00000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x000003ffL +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x00000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x0000001f +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x00020000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x00000011 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x00010000L +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x00000010 +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffffL +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0x000000ffL +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffffL +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x00000000 +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0x000000ffL +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x00000000 +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffffL +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x00000000 +#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffffL +#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x00000000 +#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0x00ffffffL +#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x00000000 +#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0x00ffffffL +#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x00000000 +#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0x00ffffffL +#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x00000000 +#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0x00ffffffL +#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x00000000 +#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0x00ffffffL +#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x00000000 +#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0x00ffffffL +#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x00000000 +#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0x00ffffffL +#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x00000000 +#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0x00ffffffL +#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x00000000 +#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0x00ffffffL +#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x00000000 +#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0x00ffffffL +#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x00000000 +#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0x00ffffffL +#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x00000000 +#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0x00ffffffL +#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x00000000 +#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0x00ffffffL +#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x00000000 +#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0x00ffffffL +#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x00000000 +#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0x00ffffffL +#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x00000000 +#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0x00ffffffL +#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x00000000 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x00000010 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L +#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x00000000 +#define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L +#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x00000008 +#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L +#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0x0000000a +#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000f0L +#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x00000004 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x00000003 +#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L +#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x00000015 +#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L +#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x00000014 +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0x0000000c +#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L +#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0x0000000b +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000L +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x0000001c +#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L +#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x00000002 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001f00L +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x00000008 +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001fL +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x00000000 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x00000007 +#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L +#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffffL +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0c000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x0000001a +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x0000001c +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x0000001e +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001000L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000c +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x00000008 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00100000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x00000014 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x00000010 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x00000015 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x00000019 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x00000018 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000010L +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x00000004 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x00000000 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x00000000 +#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00010000L +#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x00000010 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x00000000 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x00000004 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x00000004 +#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L +#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x00000000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x00000014 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x00000018 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0x0000000c +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x00000100L +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x00000008 +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x00000010 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000ffffL +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x00000000 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000L +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x00000010 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000ffffL +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000L +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000L +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000ffffL +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x00000000 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000L +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x00000010 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000ffffL +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x00000000 +#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffffL +#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x00000000 +#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffffL +#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x00000000 +#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffffL +#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x00000000 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x00000003L +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x00000000 +#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffffL +#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x00000000 +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x00000000 +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x00000000 +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000ffL +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x00000000 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x00000000 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0x0000ffffL +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x00000000 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000L +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x00000010 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0x0000ffffL +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x00000000 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000L +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x00000010 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x00000001L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x00000000 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x00010000L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000010 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x00000700L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x00000008 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0x0000f000L +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0x0000000c +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x00000010L +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x00000004 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x00000001L +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x00000000 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffffL +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x00000000 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffffL +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffffL +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000ffffL +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x00000000 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000L +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x00000010 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000ffffL +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x00000000 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000L +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x00000010 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000ffffL +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x00000000 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000L +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x00000010 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000ffffL +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x00000000 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000L +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x00000010 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000ffffL +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x00000000 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000L +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x00000010 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000ffffL +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x00000000 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000L +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x00000010 +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x00000030L +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x00000004 +#define GENENB__BLK_IO_BASE_MASK 0x000000ffL +#define GENENB__BLK_IO_BASE__SHIFT 0x00000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x0000001f +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x00000003 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x00000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x00000002 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x00000001 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000ff00L +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x00000000 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x00000008 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000f0000L +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x00000010 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x0000001f +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x00000001 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x00000000 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x00000002 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x00000004L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x00000002 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x00000002L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x00000001 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x00000001L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x00000000 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x00000040L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x00000006 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x00000020L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x00000005 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x00000010L +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x00000004 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007fL +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x00000000 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007f00L +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x00000008 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x00000007 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x00000000 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x00000001 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000ff00L +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x00000008 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000L +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x00000018 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000L +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x00000010 +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x00000000 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x00000005 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x00000004 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0x0000000a +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000fL +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x00000000 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x00000009 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x00000006 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x00000009 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000f0000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x00000010 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x00000000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0x0000000c +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x00000008 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0x0000000d +#define GENFC_RD__VSYNC_SEL_R_MASK 0x00000008L +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x00000003 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x00000008L +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x00000001L +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x00000020L +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 +#define GENMO_RD__VGA_CKSEL_MASK 0x0000000cL +#define GENMO_RD__VGA_CKSEL__SHIFT 0x00000002 +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x00000040L +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006 +#define GENMO_RD__VGA_RAM_EN_MASK 0x00000002L +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x00000001 +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x00000007 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x00000001L +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x00000020L +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 +#define GENMO_WT__VGA_CKSEL_MASK 0x0000000cL +#define GENMO_WT__VGA_CKSEL__SHIFT 0x00000002 +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006 +#define GENMO_WT__VGA_RAM_EN_MASK 0x00000002L +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x00000001 +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x00000080L +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x00000007 +#define GENS0__CRT_INTR_MASK 0x00000080L +#define GENS0__CRT_INTR__SHIFT 0x00000007 +#define GENS0__SENSE_SWITCH_MASK 0x00000010L +#define GENS0__SENSE_SWITCH__SHIFT 0x00000004 +#define GENS1__NO_DISPLAY_MASK 0x00000001L +#define GENS1__NO_DISPLAY__SHIFT 0x00000000 +#define GENS1__PIXEL_READ_BACK_MASK 0x00000030L +#define GENS1__PIXEL_READ_BACK__SHIFT 0x00000004 +#define GENS1__VGA_VSTATUS_MASK 0x00000008L +#define GENS1__VGA_VSTATUS__SHIFT 0x00000003 +#define GRA00__GRPH_SET_RESET0_MASK 0x00000001L +#define GRA00__GRPH_SET_RESET0__SHIFT 0x00000000 +#define GRA00__GRPH_SET_RESET1_MASK 0x00000002L +#define GRA00__GRPH_SET_RESET1__SHIFT 0x00000001 +#define GRA00__GRPH_SET_RESET2_MASK 0x00000004L +#define GRA00__GRPH_SET_RESET2__SHIFT 0x00000002 +#define GRA00__GRPH_SET_RESET3_MASK 0x00000008L +#define GRA00__GRPH_SET_RESET3__SHIFT 0x00000003 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x00000001L +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x00000000 +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x00000002L +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x00000001 +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x00000004L +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x00000002 +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x00000008L +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x00000003 +#define GRA02__GRPH_CCOMP_MASK 0x0000000fL +#define GRA02__GRPH_CCOMP__SHIFT 0x00000000 +#define GRA03__GRPH_FN_SEL_MASK 0x00000018L +#define GRA03__GRPH_FN_SEL__SHIFT 0x00000003 +#define GRA03__GRPH_ROTATE_MASK 0x00000007L +#define GRA03__GRPH_ROTATE__SHIFT 0x00000000 +#define GRA04__GRPH_RMAP_MASK 0x00000003L +#define GRA04__GRPH_RMAP__SHIFT 0x00000000 +#define GRA05__CGA_ODDEVEN_MASK 0x00000010L +#define GRA05__CGA_ODDEVEN__SHIFT 0x00000004 +#define GRA05__GRPH_OES_MASK 0x00000020L +#define GRA05__GRPH_OES__SHIFT 0x00000005 +#define GRA05__GRPH_PACK_MASK 0x00000040L +#define GRA05__GRPH_PACK__SHIFT 0x00000006 +#define GRA05__GRPH_READ1_MASK 0x00000008L +#define GRA05__GRPH_READ1__SHIFT 0x00000003 +#define GRA05__GRPH_WRITE_MODE_MASK 0x00000003L +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x00000000 +#define GRA06__GRPH_ADRSEL_MASK 0x0000000cL +#define GRA06__GRPH_ADRSEL__SHIFT 0x00000002 +#define GRA06__GRPH_GRAPHICS_MASK 0x00000001L +#define GRA06__GRPH_GRAPHICS__SHIFT 0x00000000 +#define GRA06__GRPH_ODDEVEN_MASK 0x00000002L +#define GRA06__GRPH_ODDEVEN__SHIFT 0x00000001 +#define GRA07__GRPH_XCARE0_MASK 0x00000001L +#define GRA07__GRPH_XCARE0__SHIFT 0x00000000 +#define GRA07__GRPH_XCARE1_MASK 0x00000002L +#define GRA07__GRPH_XCARE1__SHIFT 0x00000001 +#define GRA07__GRPH_XCARE2_MASK 0x00000004L +#define GRA07__GRPH_XCARE2__SHIFT 0x00000002 +#define GRA07__GRPH_XCARE3_MASK 0x00000008L +#define GRA07__GRPH_XCARE3__SHIFT 0x00000003 +#define GRA08__GRPH_BMSK_MASK 0x000000ffL +#define GRA08__GRPH_BMSK__SHIFT 0x00000000 +#define GRPH8_DATA__GRPH_DATA_MASK 0x000000ffL +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x00000000 +#define GRPH8_IDX__GRPH_IDX_MASK 0x0000000fL +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x00000000 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001ffc0L +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x00000006 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 +#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L +#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x00001800L +#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0x0000000b +#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0x000000c0L +#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x00000006 +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x0000001f +#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L +#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x00000000 +#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L +#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012 +#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL +#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L +#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x00000018 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 +#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0x0000e000L +#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0x0000000d +#define GRPH_CONTROL__GRPH_Z_MASK 0x00000030L +#define GRPH_CONTROL__GRPH_Z__SHIFT 0x00000004 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x00000000 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x00000004 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x00000009 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x00000008 +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000fL +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x00000000 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 +#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L +#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x00000000 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x00000000 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x00000000 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x00000008 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x00000008 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x00000000 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x00000010 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x00000008 +#define GRPH_PITCH__GRPH_PITCH_MASK 0x00007fffL +#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x00000000 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x00000000 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003fffL +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x00000000 +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003fffL +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x00000000 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000c00L +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0x0000000a +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x00000008 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x00000000 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000c0L +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x00000006 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x00000004 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x00000000 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x00000001 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x0000001c +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x00000002 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x00000003 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x00000100L +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x00000008 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L +#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x00000010 +#define GRPH_X_END__GRPH_X_END_MASK 0x00007fffL +#define GRPH_X_END__GRPH_X_END__SHIFT 0x00000000 +#define GRPH_X_START__GRPH_X_START_MASK 0x00003fffL +#define GRPH_X_START__GRPH_X_START__SHIFT 0x00000000 +#define GRPH_Y_END__GRPH_Y_END_MASK 0x00007fffL +#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x00000000 +#define GRPH_Y_START__GRPH_Y_START_MASK 0x00003fffL +#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x00000000 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000L +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0x0000000c +#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000fffffL +#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x00000000 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000L +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0x0000000c +#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000fffffL +#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x00000000 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000L +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0x0000000c +#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000fffffL +#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x00000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x0000001f +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0x0000000c +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x00000001 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x00000010 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x00000004 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x00000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x00000008 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000L +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0x0000000c +#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000fffffL +#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x00000000 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x00000004 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001f0000L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x00000010 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x00000008 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x0000001c +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x00000018 +#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x00000008 +#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x00000009 +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x00000000 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x00000004 +#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x00000004 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x00000002 +#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x00000000 +#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000f00L +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0x0000000c +#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x00000008 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x00000001 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003f0000L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x00000010 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x00000000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x00000005 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x00000018 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x00000004 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x00000001 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003f0000L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x00000010 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x00000000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x00000005 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x00000018 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x00000004 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x00000005 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x00000004 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x00000001 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x00000000 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x00000009 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x00000008 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003f00L +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x00000008 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003fL +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x00000000 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003f0000L +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x00000010 +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x00000000 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x00000010 +#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x0000001b +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x00000014 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x00000005 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x00000004 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x00000009 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003f0000L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x00000010 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x00000008 +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x00000000 +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffffL +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x00000000 +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffffL +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x00000000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000ffffL +#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x00000000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000L +#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x00000010 +#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000ffffL +#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x00000000 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000L +#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x00000010 +#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000ffffL +#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x00000000 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000L +#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x00000010 +#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000ffffL +#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x00000000 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000L +#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x00000010 +#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000ffffL +#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x00000000 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000L +#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x00000010 +#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000ffffL +#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x00000000 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000L +#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x00000010 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x00000000 +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x00000030L +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x00000004 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000003L +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000 +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004 +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c +#define KEY_CONTROL__KEY_MODE_MASK 0x00000006L +#define KEY_CONTROL__KEY_MODE__SHIFT 0x00000001 +#define KEY_CONTROL__KEY_SELECT_MASK 0x00000001L +#define KEY_CONTROL__KEY_SELECT__SHIFT 0x00000000 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000L +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000ffffL +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x00000000 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000L +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000ffffL +#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x00000000 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000L +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000ffffL +#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x00000000 +#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000L +#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x00000010 +#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000ffffL +#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x00000000 +#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffffL +#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x00000000 +#define LB_DEBUG__LB_DEBUG_MASK 0xffffffffL +#define LB_DEBUG__LB_DEBUG__SHIFT 0x00000000 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x00000000 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x00000004 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x00000000 +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffffL +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x00000001L +#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x00000000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x00000003 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x00000008 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000e0L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x00000005 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0x0000000b +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0x0000000c +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0fff0000L +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x00000010 +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x00000001L +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x00000000 +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x00000010L +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x00000004 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x00000100L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x00000008 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x00000400L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0x0000000a +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x00000200L +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x00000009 +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x00007000L +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0x0000000c +#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x00040000L +#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x00000012 +#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x00010000L +#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x00000010 +#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x00020000L +#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x00000011 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x00000019 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x0000001a +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x00000012 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x00000001 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x00000004 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x00000009 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0x0000000a +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00ff0000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000ffL +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000ff00L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00ff0000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000ffL +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000ff00L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x00000018 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x00000010 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000fffL +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x00000000 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x00000003 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x00000001 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x00000004 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000f00L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x00000008 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x00000002 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x00000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x00000008 +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x00000000 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x00000010 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x00000000 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x00000010L +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x00000004 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x00000001L +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x00000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x00100000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x00000014 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x00010000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x00000010 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x0000001c +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x01000000L +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x00000018 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x00001000L +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0x0000000c +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x00000100L +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x00000008 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000004 +#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00ff0000L +#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x00000010 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000L +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x00000018 +#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x00000003L +#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x00000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x0000001e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x0000001f +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0x0000f000L +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0x0000000c +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000008 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x00000001L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x00000000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x00000030L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x00000004 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x00070000L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x00000010 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0x00007f00L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x00000008 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x00180000L +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x00000013 +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffffL +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define MCIF_VMID__MCIF_WR_VMID_MASK 0x0000000fL +#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x00000000 +#define MCIF_VMID__VIP_WR_VMID_MASK 0x000000f0L +#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x00000004 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000000ffL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000000 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0x0000ff00L +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000008 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007fL +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x00000000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x00000011 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007f00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x00000008 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x00000010 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001ffffL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x00000000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000fL +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x00000000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0x0000000c +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x00000008 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x00000004 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x00000000 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000L +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x00000014 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0x000ffc00L +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0x0000000a +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x000003ffL +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x00000000 +#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000L +#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x0000001c +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x00000400L +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0x0000000a +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x00010000L +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x00000010 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x01000000L +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x00000018 +#define MVP_CONTROL1__MVP_EN_MASK 0x00000001L +#define MVP_CONTROL1__MVP_EN__SHIFT 0x00000000 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x00300000L +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000014 +#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x00000070L +#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x00000004 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x00000200L +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x00000009 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x00000100L +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x00000008 +#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x00001000L +#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0x0000000c +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000L +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x0000001e +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000L +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x0000001f +#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x00010000L +#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x00000010 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x00100000L +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x00000014 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x00000100L +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x00000008 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x00001000L +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0x0000000c +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x00000001L +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x00000000 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x00000010L +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x00000004 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000L +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x0000001c +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x01000000L +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x00000018 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x00000010L +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x00000004 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x00000100L +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x00000008 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x00100000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x00000014 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x0000001c +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x00001000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0x0000000c +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x00010000L +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x00000010 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x00000001L +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x00000000 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x01000000L +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x00000018 +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0x000000ffL +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x00000000 +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000L +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x0000001d +#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000L +#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x0000001c +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0x0000ff00L +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x00000008 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0x00ff0000L +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x00000010 +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000L +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x0000001e +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0x0000ffffL +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x00000000 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000L +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x00000010 +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0x0000ffffL +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x00000000 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x00000001L +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x00000000 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x01fffffeL +#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x00000001 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x00000001L +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x00000000 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x01fffffeL +#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x00000001 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x04000000L +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000001a +#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x02000000L +#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x00000019 +#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000L +#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x0000001b +#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x00100000L +#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x00000014 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x00080000L +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x00000013 +#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x00000007L +#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x00000000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x00020000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x00000011 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x00010000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x00000010 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x00040000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x00000012 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x00008000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000000f +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x00004000L +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0x0000000e +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x00000800L +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0x0000000b +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x00001000L +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0x0000000c +#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x00000400L +#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0x0000000a +#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x00000200L +#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x00000009 +#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x00002000L +#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0x0000000d +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x00000038L +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x00000003 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x000001c0L +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x00000006 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0L +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x00000004 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x00000001L +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x00000000 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x00000008L +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x00000003 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x00000004L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x00000002 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x00000002L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x00000001 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0x00000ff0L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x00000004 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x00001000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0x0000000c +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x00000001L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x00002000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0x0000000d +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0x00ff0000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x00000010 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000L +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x00000018 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x00000002L +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x00000001 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffcL +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x00000002 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x00000001L +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 +#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00L +#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x00000008 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x00000020L +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x00000005 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x00000010L +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x00000004 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x00000080L +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x00000007 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x00000040L +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x00000006 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x00000002L +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x00000001 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x00000008L +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x00000003 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x00000001L +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x00000000 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x00000004L +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x00000002 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0x00ff0000L +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x00000010 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0x0000ff00L +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x00000008 +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0x000000ffL +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x00000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000L +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x0000001f +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000L +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x0000001e +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0x000000ffL +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x00000000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x00010000L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x00000010 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x00000100L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x00001000L +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0x0000000c +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x00000008 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x0000001c +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x00100000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x01000000L +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x00000018 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x00000014 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x0000001e +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007fff00L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x00000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x00000008 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000L +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x00000018 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x00000001L +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x00000000 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00L +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x00000008 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x00000010L +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x00000004 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000L +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x0000001f +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000L +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x00000010 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x00001fffL +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x00000000 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x00001fffL +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000L +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x0000001f +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x00000000 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000L +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x00000010 +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x00001fffL +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffffL +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000ffffL +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x00000000 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000L +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x00000010 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000ffffL +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x00000000 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000L +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x00000010 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000ffffL +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x00000000 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000L +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x00000010 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000ffffL +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x00000000 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000L +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x00000010 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000ffffL +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x00000000 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000L +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x00000010 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000ffffL +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x00000000 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000L +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x00000010 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x00000000 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x00000070L +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x00000004 +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000fL +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x00000000 +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 +#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0x00f00000L +#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x00000014 +#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x00001800L +#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0x0000000b +#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0x000000c0L +#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x00000006 +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x01000000L +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x00000018 +#define OVL_CONTROL1__OVL_DEPTH_MASK 0x00000003L +#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x00000000 +#define OVL_CONTROL1__OVL_FORMAT_MASK 0x00000700L +#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x00000008 +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0x000c0000L +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x00000012 +#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0x0000000cL +#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x00000002 +#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000L +#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x00000019 +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 +#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0x0000e000L +#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0x0000000d +#define OVL_CONTROL1__OVL_Z_MASK 0x00000030L +#define OVL_CONTROL1__OVL_Z__SHIFT 0x00000004 +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x00000001L +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x00000000 +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x00000001L +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x00000000 +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x00000070L +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x00000004 +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0x0000000fL +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x00000000 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x00000200L +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x00000009 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x00000100L +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x00000008 +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 +#define OVL_ENABLE__OVL_ENABLE_MASK 0x00000001L +#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x00000000 +#define OVL_ENABLE__OVLSCL_EN_MASK 0x00000100L +#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x00000008 +#define OVL_END__OVL_X_END_MASK 0x7fff0000L +#define OVL_END__OVL_X_END__SHIFT 0x00000010 +#define OVL_END__OVL_Y_END_MASK 0x00007fffL +#define OVL_END__OVL_Y_END__SHIFT 0x00000000 +#define OVL_PITCH__OVL_PITCH_MASK 0x00007fffL +#define OVL_PITCH__OVL_PITCH__SHIFT 0x00000000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x000003ffL +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x00000000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0x000ffc00L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0x0000000a +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x00000014 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000L +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x0000001f +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x00000001L +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 +#define OVL_START__OVL_X_START_MASK 0x3fff0000L +#define OVL_START__OVL_X_START__SHIFT 0x00000010 +#define OVL_START__OVL_Y_START_MASK 0x00003fffL +#define OVL_START__OVL_Y_START__SHIFT 0x00000000 +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x00010000L +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x00020000L +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x00000001L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x00000300L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x00000001L +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x00000000 +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00L +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x00000008 +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x00003fffL +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x00000000 +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x00003fffL +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x00000000 +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0x00000c00L +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0x0000000a +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x00000300L +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x00000008 +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x00000003L +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x00000000 +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0x000000c0L +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x00000006 +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x00000030L +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x00000004 +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 +#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x00010000L +#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x00000010 +#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x00000001L +#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x00000000 +#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x00000002L +#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x00000001 +#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00010000L +#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x00000010 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L +#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0x0000000c +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x0000000e +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x00000000 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x00000000 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x00000000 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x00000000 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x00000000 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x00000000 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x00000000 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x0000001c +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000L +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x0000001e +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0x00ffffffL +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x00000000 +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000L +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x0000001d +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x00000004 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x00000000 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x00000004 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x00000000 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x00000004 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x00000000 +#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x0000001fL +#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x00000000 +#define PLL_ANALOG__PLL_CP_MASK 0x00000f00L +#define PLL_ANALOG__PLL_CP__SHIFT 0x00000008 +#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000L +#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x00000018 +#define PLL_ANALOG__PLL_LF_MODE_MASK 0x001ff000L +#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0x0000000c +#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x00000060L +#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x00000080L +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x00000007 +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x00002000L +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0x0000000d +#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x00000004L +#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x00000002 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x00000400L +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0x0000000a +#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x00100000L +#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x00000014 +#define PLL_CNTL__PLL_CALREF_MASK 0x00000300L +#define PLL_CNTL__PLL_CALREF__SHIFT 0x00000008 +#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000L +#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x0000001a +#define PLL_CNTL__PLL_LOCKED_MASK 0x00200000L +#define PLL_CNTL__PLL_LOCKED__SHIFT 0x00000015 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x00080000L +#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x00000013 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x00000040L +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x00000006 +#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x00000008L +#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x00000003 +#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x00000002L +#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x00000001 +#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x00001800L +#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0x0000000b +#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x00070000L +#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x00000010 +#define PLL_CNTL__PLL_RESET_MASK 0x00000001L +#define PLL_CNTL__PLL_RESET__SHIFT 0x00000000 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x03000000L +#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x00000018 +#define PLL_CNTL__PLL_VCOREF_MASK 0x00000030L +#define PLL_CNTL__PLL_VCOREF__SHIFT 0x00000004 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x00000f00L +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x00000008 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0x000000f0L +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x00000004 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x00000001L +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x00000000 +#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x000001ffL +#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x00000000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x00000018 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x00010000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x00000010 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x000001ffL +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x00000000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x00400000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x00000016 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x00060000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x00000011 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x00100000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x00000014 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x00200000L +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x00000015 +#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0x0000ffffL +#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x00000000 +#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x00040000L +#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x00000012 +#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x00030000L +#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x00000010 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x00080000L +#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x00000013 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define PLL_FB_DIV__PLL_FB_DIV_MASK 0x0fff0000L +#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x00000010 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0x000f0000L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x00000100L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x00000008 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x00001000L +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0x0000000c +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x00000010 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x00000002L +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x00000001 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x00000001L +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x00000000 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x00000008L +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x00000003 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x00000004L +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x00000002 +#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x00000010L +#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x00000004 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x00000080L +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x00000007 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x00008000L +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0x0000000f +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0x0000f000L +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0x0000000c +#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x000003ffL +#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x00000000 +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0x0000ffffL +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x00000000 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0x000000ffL +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x00000000 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0x00000f00L +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x00000008 +#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x00001000L +#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0x0000000c +#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x00002000L +#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0x0000000d +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000L +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x00000010 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x00000070L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x00000004 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x00000001L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x00000000 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x00000002L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x00000001 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x00000008L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x00000003 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x00000004L +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x00000002 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x00010000L +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x00000010 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x00000001L +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x00000000 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x00000100L +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x00000008 +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x00000001L +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x00000000 +#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x04000000L +#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x0000001a +#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000L +#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x0000001c +#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0x000fffffL +#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x00000000 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x00000003 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x00000004 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x00000002 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x00000001 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x00000000 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x00000010L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x00000004 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x00000002L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x00000001 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x00000008L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x00000003 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x00000001L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x00000000 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x00000004L +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x00000002 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x00000010 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x00000010 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000ffffL +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x00000000 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000L +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x00000010 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0x0000ffffL +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x00000000 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000L +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x00000010 +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000ffffL +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x00000000 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000L +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x00000010 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000ffffL +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003ffffL +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07f00000L +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x00000000 +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000ffffL +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x00000000 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000L +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x00000010 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000ffffL +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003ffffL +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07f00000L +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x00000000 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x00000000 +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x00000070L +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x00000004 +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007ffffL +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x00000000 +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001ffL +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x00000000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x00000008 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x00000000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x00000010 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0x0000000c +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x00000010 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000f00L +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x00000008 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000fL +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x00000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003fffL +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x00000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000L +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x00000010 +#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xffffffffL +#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x00000000 +#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffffL +#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x00000000 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x00000004 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x00000000 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0x0000000c +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x00000008 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x00000000 +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03ffffffL +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00L +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fL +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0fffff80L +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x00000007 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x00000004 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001fffffL +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003fffL +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x00000000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000L +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x00000010 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffffL +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L +#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x00000010 +#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000 +#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L +#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x00000008 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x0000ffffL +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x00070000L +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000010 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x0000ffffL +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x00070000L +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000010 +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03ffffffL +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000 +#define SEQ00__SEQ_RST0B_MASK 0x00000001L +#define SEQ00__SEQ_RST0B__SHIFT 0x00000000 +#define SEQ00__SEQ_RST1B_MASK 0x00000002L +#define SEQ00__SEQ_RST1B__SHIFT 0x00000001 +#define SEQ01__SEQ_DOT8_MASK 0x00000001L +#define SEQ01__SEQ_DOT8__SHIFT 0x00000000 +#define SEQ01__SEQ_MAXBW_MASK 0x00000020L +#define SEQ01__SEQ_MAXBW__SHIFT 0x00000005 +#define SEQ01__SEQ_PCLKBY2_MASK 0x00000008L +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x00000003 +#define SEQ01__SEQ_SHIFT2_MASK 0x00000004L +#define SEQ01__SEQ_SHIFT2__SHIFT 0x00000002 +#define SEQ01__SEQ_SHIFT4_MASK 0x00000010L +#define SEQ01__SEQ_SHIFT4__SHIFT 0x00000004 +#define SEQ02__SEQ_MAP0_EN_MASK 0x00000001L +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x00000000 +#define SEQ02__SEQ_MAP1_EN_MASK 0x00000002L +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x00000001 +#define SEQ02__SEQ_MAP2_EN_MASK 0x00000004L +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x00000002 +#define SEQ02__SEQ_MAP3_EN_MASK 0x00000008L +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x00000003 +#define SEQ03__SEQ_FONT_A0_MASK 0x00000020L +#define SEQ03__SEQ_FONT_A0__SHIFT 0x00000005 +#define SEQ03__SEQ_FONT_A1_MASK 0x00000004L +#define SEQ03__SEQ_FONT_A1__SHIFT 0x00000002 +#define SEQ03__SEQ_FONT_A2_MASK 0x00000008L +#define SEQ03__SEQ_FONT_A2__SHIFT 0x00000003 +#define SEQ03__SEQ_FONT_B0_MASK 0x00000010L +#define SEQ03__SEQ_FONT_B0__SHIFT 0x00000004 +#define SEQ03__SEQ_FONT_B1_MASK 0x00000001L +#define SEQ03__SEQ_FONT_B1__SHIFT 0x00000000 +#define SEQ03__SEQ_FONT_B2_MASK 0x00000002L +#define SEQ03__SEQ_FONT_B2__SHIFT 0x00000001 +#define SEQ04__SEQ_256K_MASK 0x00000002L +#define SEQ04__SEQ_256K__SHIFT 0x00000001 +#define SEQ04__SEQ_CHAIN_MASK 0x00000008L +#define SEQ04__SEQ_CHAIN__SHIFT 0x00000003 +#define SEQ04__SEQ_ODDEVEN_MASK 0x00000004L +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x00000002 +#define SEQ8_DATA__SEQ_DATA_MASK 0x000000ffL +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x00000000 +#define SEQ8_IDX__SEQ_IDX_MASK 0x00000007L +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x00000000 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x00000000 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000ffL +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x00000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x00000008 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x00000008 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x00000000 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x00000004 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x00000008 +#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L +#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 +#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L +#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 +#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x00000000 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x00000008 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x00000000 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x00000000 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x00000001 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x00000002 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x00000003 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x0000001f +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x00000004 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x00000007 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x00000008 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000fL +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x00000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0x0000000b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0x0000000c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0x0000000a +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x00000014 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x00000017 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x00000018 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000f0000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x00000010 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x0000001b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x0000001c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x0000001a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x00000004 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x00000007 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x00000008 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000fL +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x00000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0x0000000b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0x0000000c +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0x0000000a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x00000014 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x00000017 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x00000018 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000f0000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x00000010 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x0000001b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x0000001c +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x0000001a +#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x00000000 +#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x00000008 +#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x00000010 +#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x00000018 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x00000000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x00000018 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x00000008 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000f0000L +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x00000010 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x00000004 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x02000000L +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x00000019 +#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x01000000L +#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x00000018 +#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x00000001L +#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x00000000 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x00000200L +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x00000009 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x00000100L +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x00000008 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x00020000L +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x00000011 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x00010000L +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x00000010 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003ffL +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03ff0000L +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x00000010 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003ffL +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x00000000 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03ff0000L +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x00000010 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x00010000L +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x00000010 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0x000e0000L +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x007fffffL +#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x001f0000L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x00000010 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x00000002L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x00000001 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x01000000L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x00000018 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0x00000f00L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x00000008 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x00000001L +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x00000000 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x00010000L +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x00000010 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0x000e0000L +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x007fffffL +#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x00000000 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x00000008 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x00000010 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x00000018 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x00000040L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x00000006 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x00000030L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x00000004 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x00000001L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x00000000 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x00010000L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x00000010 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x00001000L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0x0000000c +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x00000100L +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x00000008 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x000003ffL +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x00000000 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x00010000L +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x00000010 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0x000e0000L +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x00000011 +#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x007fffffL +#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0x0000000a +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x00000009 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x00000008 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x0000001c +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0f000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x00000018 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x0000001e +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00f00000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x00000014 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000f0000L +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffffL +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x00000010 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007fffL +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x00000000 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000L +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x00000010 +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0x0000000c +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0x0000000d +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0x0000000e +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0x0000000f +#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x00000014 +#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x00030000L +#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x00000010 +#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x00000008 +#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x00000000 +#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0x00ff0000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x00000010 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x00000008L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x00000003 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0x000000f0L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x00000001L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x00000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x00000004L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x00000002 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x00007f00L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x00000008 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x00000002L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x00000001 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x02000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x00000019 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x01000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x00000018 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x04000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x0000001a +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000L +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x0000001c +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x00002000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0x0000000d +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0x0000000cL +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x00000002 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x00001000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0x0000000c +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x00000010L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x00000004 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x00000020L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x00000005 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x00000040L +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x00000006 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x00000800L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0x0000000b +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x00100000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x00000014 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x0000001d +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x00000003L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x00000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x00000700L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x00000008 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x00000018 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x00080000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000013 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x00010000L +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x00000010 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0x0000fffcL +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x00000002 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0x0fff0000L +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x00000010 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x00001000L +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0x0000000c +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x00002000L +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0x0000000d +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0x00000fffL +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x00000000 +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x03ffffffL +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x00000000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0x000f0000L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x00000010 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0x00000f00L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x00000008 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0x0000f000L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0x0000000c +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x00000001L +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x00000000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x00000004L +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x00000002 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x00000002L +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x00000001 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x01f00000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x00000014 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x00008000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0x0000000f +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x00010000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x00000010 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x0000001d +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x0000001c +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0x0e000000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x00000019 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x0000001fL +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x00000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x00020000L +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x00000011 +#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000001L +#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x00000000 +#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000002L +#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x00000001 +#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000004L +#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x00000002 +#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000008L +#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x00000003 +#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000010L +#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x00000004 +#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000020L +#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x00000005 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x00000007L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x00000070L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x00000700L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x00007000L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x00070000L +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x00300000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0x00c00000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x00000016 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x03000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0x0c000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x0000001a +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000L +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x0000001c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x00000003L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x00000030L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x00000300L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x00003000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x00030000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x00100000L +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x00600000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x00000015 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x01800000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x00000017 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x06000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x00000019 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x0000001b +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000L +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x0000001d +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000L +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x0000001f +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x00100000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x00000014 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x00200000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x00000015 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x00400000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x00000016 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x00800000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x00000017 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0x000000f0L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x00000004 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0x00000f00L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x00000008 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x00000003L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0x0000000cL +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x00000002 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x00007000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x00070000L +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x00000010 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000L +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x0000001fL +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x00000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x000003e0L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x00000005 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x07000000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x00000018 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x0000001c +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x0001f000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011 +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x00000008 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x0000001fL +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x00000000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0x00000f00L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x00000008 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x0000001fL +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x00000000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0x00000f00L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x00000008 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x00000018 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x001ff000L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0x0000000c +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x00000060L +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x07ff0000L +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x00000010 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x000003ffL +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x00000000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x00000014 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x00000018 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x00000010 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x00000008 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x00000000 +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffffL +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x00000000 +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0x000000ffL +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x00000000 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01ffffffL +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x00000000 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01ffffffL +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x00000000 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x00000004 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x00000000 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x00000008 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x00000010 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x00000018 +#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffffL +#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x00000000 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x00000010 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x00000000 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x00000018 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x00000008 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x00000002 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x00000000 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x00000003 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x00000001 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x00000000 +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x0000001d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x0000001f +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x00000018 +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x00000010 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x0000001a +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x00000008 +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x08000000L +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x0000001b +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x00000003 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000e0L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x00000005 +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000L +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x0000001c +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000ffL +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x00000000 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffffL +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x00000000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003ffL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x00000000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03ff0000L +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x00000010 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003ffL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x00000000 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03ff0000L +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x00000010 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x00000008 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x00000000 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x00000004 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x00000010 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x00000005 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001fL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x00000000 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x00000007 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x00000008 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x00000018 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x00000019 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x00000010 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000000 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000008 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000001 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000009 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000002 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000a +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000003 +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000b +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000004 +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000c +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000005 +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000d +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x00000010 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00fc0000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x00000012 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x00000011 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x00000000 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x00000008 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x00000010 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x00000000 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x00000018 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x00000008 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x00000002 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x00000000 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x00000003 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x00000001 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x00000008 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x00000000 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x00000000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x00000018 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x00000010 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x00000008 +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffffL +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003fffL +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x00000000 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000L +#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x00000010 +#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000L +#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x00000010 +#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003fffL +#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x00000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x00008000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0x0000000f +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x00080000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x00000013 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x00040000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x00000012 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x00100000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x00000014 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x00010000L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x00000010 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0x0000000fL +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x00000000 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x00000100L +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x00000008 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0x0000000fL +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x00000000 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x00000400L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0x0000000a +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x00000200L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x00000009 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x00000100L +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x00000008 +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x00004000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0x0000000e +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x00002000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0x0000000d +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x00001000L +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0x0000000c +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x00040000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x00000012 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x00020000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x00000011 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x00010000L +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x00000010 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0x0000000fL +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x00000000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0x00000c00L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0x0000000a +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x00000300L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x00000008 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x00003000L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0x0000000c +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x00300000L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x00000014 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x00000070L +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x00000004 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x00c00000L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x00000016 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x0000001b +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x00000007L +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x00010000L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x00000010 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x00000300L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x00000008 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0x0000f000L +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0x0000000c +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x00000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x00010000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000010 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x0000001e +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x00000100L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x01000000L +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000018 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x00040000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x00000012 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x00010000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x00000010 +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x00000200L +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0x00000009 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x00100000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x00000014 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x00003fffL +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x00000000 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000L +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x00000010 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffffL +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x00000000 +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x00003fffL +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x00010000L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x00000010 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x00000300L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x00000008 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0x0000f000L +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x00010000L +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x00000010 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x00003000L +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x000003ffL +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x00000001L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0x0000f000L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0x000000f0L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x00000004 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000L +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x00000010 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x00010000L +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x00000010 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x00003000L +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0x0000000c +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x000003ffL +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x00000000 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000L +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x00000010 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x00003fffL +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffffL +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0x000000ffL +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x00000000 +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffffL +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x00000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x00003fffL +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x00000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0x3fff0000L +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x00000010 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x00000007L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x00000000 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x00000008L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000L +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0x0000000f +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x00000100L +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0x00000008 +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x00010000L +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x00000010 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x00000200L +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x00000009 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x00080000L +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x00000013 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x00100000L +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x00000014 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x00000001L +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x00000000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x00010000L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x00000010 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x00000300L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x00000008 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0x0000f000L +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0x0000000c +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000L +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x0000001f +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x00030000L +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x00000010 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0x0000ffffL +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x00000000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x00010000L +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x00000010 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x00003000L +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0x0000000c +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x000003ffL +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0x000fffffL +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000L +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x00000014 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000L +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x00000010 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0x0000ffffL +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x00000000 +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0x0000ffffL +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x00000000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x00000001L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x00000000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0x0000f000L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0x000000f0L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x00000004 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000L +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x00000010 +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffffL +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x00003fffL +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x00000000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000L +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x00000010 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000L +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x00000010 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x000001ffL +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x00000000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0x0000f000L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0x0000000c +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x00000001L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x00000000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0x00000f00L +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x00000008 +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffffL +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h new file mode 100644 index 000000000000..c75aee25619e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h @@ -0,0 +1,1784 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_6_0_D_H +#define GFX_6_0_D_H + +#define ixCLIPPER_DEBUG_REG00 0x0000 +#define ixCLIPPER_DEBUG_REG01 0x0001 +#define ixCLIPPER_DEBUG_REG02 0x0002 +#define ixCLIPPER_DEBUG_REG03 0x0003 +#define ixCLIPPER_DEBUG_REG04 0x0004 +#define ixCLIPPER_DEBUG_REG05 0x0005 +#define ixCLIPPER_DEBUG_REG06 0x0006 +#define ixCLIPPER_DEBUG_REG07 0x0007 +#define ixCLIPPER_DEBUG_REG08 0x0008 +#define ixCLIPPER_DEBUG_REG09 0x0009 +#define ixCLIPPER_DEBUG_REG10 0x000A +#define ixCLIPPER_DEBUG_REG11 0x000B +#define ixCLIPPER_DEBUG_REG12 0x000C +#define ixCLIPPER_DEBUG_REG13 0x000D +#define ixCLIPPER_DEBUG_REG14 0x000E +#define ixCLIPPER_DEBUG_REG15 0x000F +#define ixCLIPPER_DEBUG_REG16 0x0010 +#define ixCLIPPER_DEBUG_REG17 0x0011 +#define ixCLIPPER_DEBUG_REG18 0x0012 +#define ixCLIPPER_DEBUG_REG19 0x0013 +#define ixGDS_DEBUG_REG0 0x0000 +#define ixGDS_DEBUG_REG1 0x0001 +#define ixGDS_DEBUG_REG2 0x0002 +#define ixGDS_DEBUG_REG3 0x0003 +#define ixGDS_DEBUG_REG4 0x0004 +#define ixGDS_DEBUG_REG5 0x0005 +#define ixGDS_DEBUG_REG6 0x0006 +#define ixIA_DEBUG_REG0 0x0000 +#define ixIA_DEBUG_REG1 0x0001 +#define ixIA_DEBUG_REG2 0x0002 +#define ixIA_DEBUG_REG3 0x0003 +#define ixIA_DEBUG_REG4 0x0004 +#define ixIA_DEBUG_REG5 0x0005 +#define ixIA_DEBUG_REG6 0x0006 +#define ixIA_DEBUG_REG7 0x0007 +#define ixIA_DEBUG_REG8 0x0008 +#define ixIA_DEBUG_REG9 0x0009 +#define ixPA_SC_DEBUG_REG0 0x0000 +#define ixPA_SC_DEBUG_REG1 0x0001 +#define ixSETUP_DEBUG_REG0 0x0018 +#define ixSETUP_DEBUG_REG1 0x0019 +#define ixSETUP_DEBUG_REG2 0x001A +#define ixSETUP_DEBUG_REG3 0x001B +#define ixSETUP_DEBUG_REG4 0x001C +#define ixSETUP_DEBUG_REG5 0x001D +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_INTERRUPT_WORD_AUTO 0x20C0 +#define ixSQ_INTERRUPT_WORD_CMN 0x20C0 +#define ixSQ_INTERRUPT_WORD_WAVE 0x20C0 +#define ixSQ_WAVE_EXEC_HI 0x027F +#define ixSQ_WAVE_EXEC_LO 0x027E +#define ixSQ_WAVE_GPR_ALLOC 0x0015 +#define ixSQ_WAVE_HW_ID 0x0014 +#define ixSQ_WAVE_IB_DBG0 0x001C +#define ixSQ_WAVE_IB_STS 0x0017 +#define ixSQ_WAVE_INST_DW0 0x001A +#define ixSQ_WAVE_INST_DW1 0x001B +#define ixSQ_WAVE_LDS_ALLOC 0x0016 +#define ixSQ_WAVE_M0 0x027C +#define ixSQ_WAVE_MODE 0x0011 +#define ixSQ_WAVE_PC_HI 0x0019 +#define ixSQ_WAVE_PC_LO 0x0018 +#define ixSQ_WAVE_STATUS 0x0012 +#define ixSQ_WAVE_TBA_HI 0x026D +#define ixSQ_WAVE_TBA_LO 0x026C +#define ixSQ_WAVE_TMA_HI 0x026F +#define ixSQ_WAVE_TMA_LO 0x026E +#define ixSQ_WAVE_TRAPSTS 0x0013 +#define ixSQ_WAVE_TTMP0 0x0270 +#define ixSQ_WAVE_TTMP10 0x027A +#define ixSQ_WAVE_TTMP1 0x0271 +#define ixSQ_WAVE_TTMP11 0x027B +#define ixSQ_WAVE_TTMP2 0x0272 +#define ixSQ_WAVE_TTMP3 0x0273 +#define ixSQ_WAVE_TTMP4 0x0274 +#define ixSQ_WAVE_TTMP5 0x0275 +#define ixSQ_WAVE_TTMP6 0x0276 +#define ixSQ_WAVE_TTMP7 0x0277 +#define ixSQ_WAVE_TTMP8 0x0278 +#define ixSQ_WAVE_TTMP9 0x0279 +#define ixSXIFCCG_DEBUG_REG0 0x0014 +#define ixSXIFCCG_DEBUG_REG1 0x0015 +#define ixSXIFCCG_DEBUG_REG2 0x0016 +#define ixSXIFCCG_DEBUG_REG3 0x0017 +#define ixVGT_DEBUG_REG0 0x0000 +#define ixVGT_DEBUG_REG10 0x000A +#define ixVGT_DEBUG_REG1 0x0001 +#define ixVGT_DEBUG_REG11 0x000B +#define ixVGT_DEBUG_REG12 0x000C +#define ixVGT_DEBUG_REG13 0x000D +#define ixVGT_DEBUG_REG14 0x000E +#define ixVGT_DEBUG_REG15 0x000F +#define ixVGT_DEBUG_REG16 0x0010 +#define ixVGT_DEBUG_REG17 0x0011 +#define ixVGT_DEBUG_REG18 0x0012 +#define ixVGT_DEBUG_REG19 0x0013 +#define ixVGT_DEBUG_REG20 0x0014 +#define ixVGT_DEBUG_REG2 0x0002 +#define ixVGT_DEBUG_REG21 0x0015 +#define ixVGT_DEBUG_REG22 0x0016 +#define ixVGT_DEBUG_REG23 0x0017 +#define ixVGT_DEBUG_REG24 0x0018 +#define ixVGT_DEBUG_REG25 0x0019 +#define ixVGT_DEBUG_REG26 0x001A +#define ixVGT_DEBUG_REG27 0x001B +#define ixVGT_DEBUG_REG28 0x001C +#define ixVGT_DEBUG_REG29 0x001D +#define ixVGT_DEBUG_REG30 0x001E +#define ixVGT_DEBUG_REG3 0x0003 +#define ixVGT_DEBUG_REG31 0x001F +#define ixVGT_DEBUG_REG32 0x0020 +#define ixVGT_DEBUG_REG33 0x0021 +#define ixVGT_DEBUG_REG34 0x0022 +#define ixVGT_DEBUG_REG35 0x0023 +#define ixVGT_DEBUG_REG36 0x0024 +#define ixVGT_DEBUG_REG4 0x0004 +#define ixVGT_DEBUG_REG5 0x0005 +#define ixVGT_DEBUG_REG6 0x0006 +#define ixVGT_DEBUG_REG7 0x0007 +#define ixVGT_DEBUG_REG8 0x0008 +#define ixVGT_DEBUG_REG9 0x0009 +#define mmBCI_DEBUG_READ 0x24E3 +#define mmCB_BLEND0_CONTROL 0xA1E0 +#define mmCB_BLEND1_CONTROL 0xA1E1 +#define mmCB_BLEND2_CONTROL 0xA1E2 +#define mmCB_BLEND3_CONTROL 0xA1E3 +#define mmCB_BLEND4_CONTROL 0xA1E4 +#define mmCB_BLEND5_CONTROL 0xA1E5 +#define mmCB_BLEND6_CONTROL 0xA1E6 +#define mmCB_BLEND7_CONTROL 0xA1E7 +#define mmCB_BLEND_ALPHA 0xA108 +#define mmCB_BLEND_BLUE 0xA107 +#define mmCB_BLEND_GREEN 0xA106 +#define mmCB_BLEND_RED 0xA105 +#define mmCB_CGTT_SCLK_CTRL 0x2698 +#define mmCB_COLOR0_ATTRIB 0xA31D +#define mmCB_COLOR0_BASE 0xA318 +#define mmCB_COLOR0_CLEAR_WORD0 0xA323 +#define mmCB_COLOR0_CLEAR_WORD1 0xA324 +#define mmCB_COLOR0_CMASK 0xA31F +#define mmCB_COLOR0_CMASK_SLICE 0xA320 +#define mmCB_COLOR0_FMASK 0xA321 +#define mmCB_COLOR0_FMASK_SLICE 0xA322 +#define mmCB_COLOR0_INFO 0xA31C +#define mmCB_COLOR0_PITCH 0xA319 +#define mmCB_COLOR0_SLICE 0xA31A +#define mmCB_COLOR0_VIEW 0xA31B +#define mmCB_COLOR1_ATTRIB 0xA32C +#define mmCB_COLOR1_BASE 0xA327 +#define mmCB_COLOR1_CLEAR_WORD0 0xA332 +#define mmCB_COLOR1_CLEAR_WORD1 0xA333 +#define mmCB_COLOR1_CMASK 0xA32E +#define mmCB_COLOR1_CMASK_SLICE 0xA32F +#define mmCB_COLOR1_FMASK 0xA330 +#define mmCB_COLOR1_FMASK_SLICE 0xA331 +#define mmCB_COLOR1_INFO 0xA32B +#define mmCB_COLOR1_PITCH 0xA328 +#define mmCB_COLOR1_SLICE 0xA329 +#define mmCB_COLOR1_VIEW 0xA32A +#define mmCB_COLOR2_ATTRIB 0xA33B +#define mmCB_COLOR2_BASE 0xA336 +#define mmCB_COLOR2_CLEAR_WORD0 0xA341 +#define mmCB_COLOR2_CLEAR_WORD1 0xA342 +#define mmCB_COLOR2_CMASK 0xA33D +#define mmCB_COLOR2_CMASK_SLICE 0xA33E +#define mmCB_COLOR2_FMASK 0xA33F +#define mmCB_COLOR2_FMASK_SLICE 0xA340 +#define mmCB_COLOR2_INFO 0xA33A +#define mmCB_COLOR2_PITCH 0xA337 +#define mmCB_COLOR2_SLICE 0xA338 +#define mmCB_COLOR2_VIEW 0xA339 +#define mmCB_COLOR3_ATTRIB 0xA34A +#define mmCB_COLOR3_BASE 0xA345 +#define mmCB_COLOR3_CLEAR_WORD0 0xA350 +#define mmCB_COLOR3_CLEAR_WORD1 0xA351 +#define mmCB_COLOR3_CMASK 0xA34C +#define mmCB_COLOR3_CMASK_SLICE 0xA34D +#define mmCB_COLOR3_FMASK 0xA34E +#define mmCB_COLOR3_FMASK_SLICE 0xA34F +#define mmCB_COLOR3_INFO 0xA349 +#define mmCB_COLOR3_PITCH 0xA346 +#define mmCB_COLOR3_SLICE 0xA347 +#define mmCB_COLOR3_VIEW 0xA348 +#define mmCB_COLOR4_ATTRIB 0xA359 +#define mmCB_COLOR4_BASE 0xA354 +#define mmCB_COLOR4_CLEAR_WORD0 0xA35F +#define mmCB_COLOR4_CLEAR_WORD1 0xA360 +#define mmCB_COLOR4_CMASK 0xA35B +#define mmCB_COLOR4_CMASK_SLICE 0xA35C +#define mmCB_COLOR4_FMASK 0xA35D +#define mmCB_COLOR4_FMASK_SLICE 0xA35E +#define mmCB_COLOR4_INFO 0xA358 +#define mmCB_COLOR4_PITCH 0xA355 +#define mmCB_COLOR4_SLICE 0xA356 +#define mmCB_COLOR4_VIEW 0xA357 +#define mmCB_COLOR5_ATTRIB 0xA368 +#define mmCB_COLOR5_BASE 0xA363 +#define mmCB_COLOR5_CLEAR_WORD0 0xA36E +#define mmCB_COLOR5_CLEAR_WORD1 0xA36F +#define mmCB_COLOR5_CMASK 0xA36A +#define mmCB_COLOR5_CMASK_SLICE 0xA36B +#define mmCB_COLOR5_FMASK 0xA36C +#define mmCB_COLOR5_FMASK_SLICE 0xA36D +#define mmCB_COLOR5_INFO 0xA367 +#define mmCB_COLOR5_PITCH 0xA364 +#define mmCB_COLOR5_SLICE 0xA365 +#define mmCB_COLOR5_VIEW 0xA366 +#define mmCB_COLOR6_ATTRIB 0xA377 +#define mmCB_COLOR6_BASE 0xA372 +#define mmCB_COLOR6_CLEAR_WORD0 0xA37D +#define mmCB_COLOR6_CLEAR_WORD1 0xA37E +#define mmCB_COLOR6_CMASK 0xA379 +#define mmCB_COLOR6_CMASK_SLICE 0xA37A +#define mmCB_COLOR6_FMASK 0xA37B +#define mmCB_COLOR6_FMASK_SLICE 0xA37C +#define mmCB_COLOR6_INFO 0xA376 +#define mmCB_COLOR6_PITCH 0xA373 +#define mmCB_COLOR6_SLICE 0xA374 +#define mmCB_COLOR6_VIEW 0xA375 +#define mmCB_COLOR7_ATTRIB 0xA386 +#define mmCB_COLOR7_BASE 0xA381 +#define mmCB_COLOR7_CLEAR_WORD0 0xA38C +#define mmCB_COLOR7_CLEAR_WORD1 0xA38D +#define mmCB_COLOR7_CMASK 0xA388 +#define mmCB_COLOR7_CMASK_SLICE 0xA389 +#define mmCB_COLOR7_FMASK 0xA38A +#define mmCB_COLOR7_FMASK_SLICE 0xA38B +#define mmCB_COLOR7_INFO 0xA385 +#define mmCB_COLOR7_PITCH 0xA382 +#define mmCB_COLOR7_SLICE 0xA383 +#define mmCB_COLOR7_VIEW 0xA384 +#define mmCB_COLOR_CONTROL 0xA202 +#define mmCB_DEBUG_BUS_10 0x26A2 +#define mmCB_DEBUG_BUS_1 0x2699 +#define mmCB_DEBUG_BUS_11 0x26A3 +#define mmCB_DEBUG_BUS_12 0x26A4 +#define mmCB_DEBUG_BUS_13 0x26A5 +#define mmCB_DEBUG_BUS_14 0x26A6 +#define mmCB_DEBUG_BUS_15 0x26A7 +#define mmCB_DEBUG_BUS_16 0x26A8 +#define mmCB_DEBUG_BUS_17 0x26A9 +#define mmCB_DEBUG_BUS_18 0x26AA +#define mmCB_DEBUG_BUS_2 0x269A +#define mmCB_DEBUG_BUS_3 0x269B +#define mmCB_DEBUG_BUS_4 0x269C +#define mmCB_DEBUG_BUS_5 0x269D +#define mmCB_DEBUG_BUS_6 0x269E +#define mmCB_DEBUG_BUS_7 0x269F +#define mmCB_DEBUG_BUS_8 0x26A0 +#define mmCB_DEBUG_BUS_9 0x26A1 +#define mmCB_HW_CONTROL 0x2684 +#define mmCB_HW_CONTROL_1 0x2685 +#define mmCB_HW_CONTROL_2 0x2686 +#define mmCB_PERFCOUNTER0_HI 0x2691 +#define mmCB_PERFCOUNTER0_LO 0x2690 +#define mmCB_PERFCOUNTER0_SELECT1 0x2689 +#define mmCB_PERFCOUNTER1_HI 0x2693 +#define mmCB_PERFCOUNTER1_LO 0x2692 +#define mmCB_PERFCOUNTER2_HI 0x2695 +#define mmCB_PERFCOUNTER2_LO 0x2694 +#define mmCB_PERFCOUNTER3_HI 0x2697 +#define mmCB_PERFCOUNTER3_LO 0x2696 +#define mmCB_SHADER_MASK 0xA08F +#define mmCB_TARGET_MASK 0xA08E +#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226F +#define mmCC_RB_BACKEND_DISABLE 0x263D +#define mmCC_RB_DAISY_CHAIN 0x2641 +#define mmCC_RB_REDUNDANCY 0x263C +#define mmCC_SQC_BANK_DISABLE 0x2307 +#define mmCGTS_RD_CTRL_REG 0x2455 +#define mmCGTS_RD_REG 0x2456 +#define mmCGTS_SM_CTRL_REG 0x2454 +#define mmCGTS_TCC_DISABLE 0x2452 +#define mmCGTS_USER_TCC_DISABLE 0x2453 +#define mmCGTT_BCI_CLK_CTRL 0x24A9 +#define mmCGTT_CP_CLK_CTRL 0x3059 +#define mmCGTT_GDS_CLK_CTRL 0x25DD +#define mmCGTT_IA_CLK_CTRL 0x2261 +#define mmCGTT_PA_CLK_CTRL 0x2286 +#define mmCGTT_PC_CLK_CTRL 0x24A8 +#define mmCGTT_RLC_CLK_CTRL 0x30E0 +#define mmCGTT_SC_CLK_CTRL 0x22CA +#define mmCGTT_SPI_CLK_CTRL 0x2451 +#define mmCGTT_SQ_CLK_CTRL 0x2362 +#define mmCGTT_SQG_CLK_CTRL 0x2363 +#define mmCGTT_SX_CLK_CTRL0 0x240C +#define mmCGTT_SX_CLK_CTRL1 0x240D +#define mmCGTT_SX_CLK_CTRL2 0x240E +#define mmCGTT_SX_CLK_CTRL3 0x240F +#define mmCGTT_SX_CLK_CTRL4 0x2410 +#define mmCGTT_TCI_CLK_CTRL 0x2B60 +#define mmCGTT_TCP_CLK_CTRL 0x2B15 +#define mmCGTT_VGT_CLK_CTRL 0x225F +#define mmCOHER_DEST_BASE_0 0xA092 +#define mmCOHER_DEST_BASE_1 0xA093 +#define mmCOHER_DEST_BASE_2 0xA07E +#define mmCOHER_DEST_BASE_3 0xA07F +#define mmCOMPUTE_DIM_X 0x2E01 +#define mmCOMPUTE_DIM_Y 0x2E02 +#define mmCOMPUTE_DIM_Z 0x2E03 +#define mmCOMPUTE_DISPATCH_INITIATOR 0x2E00 +#define mmCOMPUTE_NUM_THREAD_X 0x2E07 +#define mmCOMPUTE_NUM_THREAD_Y 0x2E08 +#define mmCOMPUTE_NUM_THREAD_Z 0x2E09 +#define mmCOMPUTE_PGM_HI 0x2E0D +#define mmCOMPUTE_PGM_LO 0x2E0C +#define mmCOMPUTE_PGM_RSRC1 0x2E12 +#define mmCOMPUTE_PGM_RSRC2 0x2E13 +#define mmCOMPUTE_RESOURCE_LIMITS 0x2E15 +#define mmCOMPUTE_START_X 0x2E04 +#define mmCOMPUTE_START_Y 0x2E05 +#define mmCOMPUTE_START_Z 0x2E06 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2E16 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2E17 +#define mmCOMPUTE_TBA_HI 0x2E0F +#define mmCOMPUTE_TBA_LO 0x2E0E +#define mmCOMPUTE_TMA_HI 0x2E11 +#define mmCOMPUTE_TMA_LO 0x2E10 +#define mmCOMPUTE_TMPRING_SIZE 0x2E18 +#define mmCOMPUTE_USER_DATA_0 0x2E40 +#define mmCOMPUTE_USER_DATA_10 0x2E4A +#define mmCOMPUTE_USER_DATA_1 0x2E41 +#define mmCOMPUTE_USER_DATA_11 0x2E4B +#define mmCOMPUTE_USER_DATA_12 0x2E4C +#define mmCOMPUTE_USER_DATA_13 0x2E4D +#define mmCOMPUTE_USER_DATA_14 0x2E4E +#define mmCOMPUTE_USER_DATA_15 0x2E4F +#define mmCOMPUTE_USER_DATA_2 0x2E42 +#define mmCOMPUTE_USER_DATA_3 0x2E43 +#define mmCOMPUTE_USER_DATA_4 0x2E44 +#define mmCOMPUTE_USER_DATA_5 0x2E45 +#define mmCOMPUTE_USER_DATA_6 0x2E46 +#define mmCOMPUTE_USER_DATA_7 0x2E47 +#define mmCOMPUTE_USER_DATA_8 0x2E48 +#define mmCOMPUTE_USER_DATA_9 0x2E49 +#define mmCOMPUTE_VMID 0x2E14 +#define mmCP_APPEND_ADDR_HI 0x2159 +#define mmCP_APPEND_ADDR_LO 0x2158 +#define mmCP_APPEND_DATA 0x215A +#define mmCP_APPEND_LAST_CS_FENCE 0x215B +#define mmCP_APPEND_LAST_PS_FENCE 0x215C +#define mmCP_ATOMIC_PREOP_HI 0x215E +#define mmCP_ATOMIC_PREOP_LO 0x215D +#define mmCP_BUSY_STAT 0x219F +#define mmCP_CE_HEADER_DUMP 0x21A4 +#define mmCP_CE_IB1_BASE_HI 0x21C7 +#define mmCP_CE_IB1_BASE_LO 0x21C6 +#define mmCP_CE_IB1_BUFSZ 0x21C8 +#define mmCP_CE_IB2_BASE_HI 0x21CA +#define mmCP_CE_IB2_BASE_LO 0x21C9 +#define mmCP_CE_IB2_BUFSZ 0x21CB +#define mmCP_CE_INIT_BASE_HI 0x21C4 +#define mmCP_CE_INIT_BASE_LO 0x21C3 +#define mmCP_CE_INIT_BUFSZ 0x21C5 +#define mmCP_CEQ1_AVAIL 0x21E6 +#define mmCP_CEQ2_AVAIL 0x21E7 +#define mmCP_CE_ROQ_IB1_STAT 0x21E9 +#define mmCP_CE_ROQ_IB2_STAT 0x21EA +#define mmCP_CE_ROQ_RB_STAT 0x21E8 +#define mmCP_CE_UCODE_ADDR 0x305A +#define mmCP_CE_UCODE_DATA 0x305B +#define mmCP_CMD_DATA 0x21DF +#define mmCP_CMD_INDEX 0x21DE +#define mmCP_CNTX_STAT 0x21B8 +#define mmCP_COHER_BASE 0x217E +#define mmCP_COHER_CNTL 0x217C +#define mmCP_COHER_SIZE 0x217D +#define mmCP_COHER_START_DELAY 0x217B +#define mmCP_COHER_STATUS 0x217F +#define mmCP_CSF_CNTL 0x21B5 +#define mmCP_CSF_STAT 0x21B4 +#define mmCP_DMA_CNTL 0x218A +#define mmCP_DMA_ME_COMMAND 0x2184 +#define mmCP_DMA_ME_DST_ADDR 0x2182 +#define mmCP_DMA_ME_DST_ADDR_HI 0x2183 +#define mmCP_DMA_ME_SRC_ADDR 0x2180 +#define mmCP_DMA_ME_SRC_ADDR_HI 0x2181 +#define mmCP_DMA_PFP_COMMAND 0x2189 +#define mmCP_DMA_PFP_DST_ADDR 0x2187 +#define mmCP_DMA_PFP_DST_ADDR_HI 0x2188 +#define mmCP_DMA_PFP_SRC_ADDR 0x2185 +#define mmCP_DMA_PFP_SRC_ADDR_HI 0x2186 +#define mmCP_DMA_READ_TAGS 0x218B +#define mmCP_ECC_FIRSTOCCURRENCE 0x307A +#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307B +#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307C +#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307D +#define mmCP_EOP_DONE_ADDR_HI 0x2101 +#define mmCP_EOP_DONE_ADDR_LO 0x2100 +#define mmCP_EOP_DONE_DATA_HI 0x2103 +#define mmCP_EOP_DONE_DATA_LO 0x2102 +#define mmCP_EOP_LAST_FENCE_HI 0x2105 +#define mmCP_EOP_LAST_FENCE_LO 0x2104 +#define mmCP_GDS_ATOMIC0_PREOP_HI 0x2160 +#define mmCP_GDS_ATOMIC0_PREOP_LO 0x215F +#define mmCP_GDS_ATOMIC1_PREOP_HI 0x2162 +#define mmCP_GDS_ATOMIC1_PREOP_LO 0x2161 +#define mmCP_GRBM_FREE_COUNT 0x21A3 +#define mmCP_IB1_BASE_HI 0x21CD +#define mmCP_IB1_BASE_LO 0x21CC +#define mmCP_IB1_BUFSZ 0x21CE +#define mmCP_IB1_OFFSET 0x2192 +#define mmCP_IB1_PREAMBLE_BEGIN 0x2194 +#define mmCP_IB1_PREAMBLE_END 0x2195 +#define mmCP_IB2_BASE_HI 0x21D0 +#define mmCP_IB2_BASE_LO 0x21CF +#define mmCP_IB2_BUFSZ 0x21D1 +#define mmCP_IB2_OFFSET 0x2193 +#define mmCP_IB2_PREAMBLE_BEGIN 0x2196 +#define mmCP_IB2_PREAMBLE_END 0x2197 +#define mmCP_INT_CNTL 0x3049 +#define mmCP_INT_CNTL_RING0 0x306A +#define mmCP_INT_CNTL_RING1 0x306B +#define mmCP_INT_CNTL_RING2 0x306C +#define mmCP_INT_STAT_DEBUG 0x21F7 +#define mmCP_INT_STATUS 0x304A +#define mmCP_INT_STATUS_RING0 0x306D +#define mmCP_INT_STATUS_RING1 0x306E +#define mmCP_INT_STATUS_RING2 0x306F +#define mmCP_MC_PACK_DELAY_CNT 0x21A7 +#define mmCP_ME_CNTL 0x21B6 +#define mmCP_ME_HEADER_DUMP 0x21A1 +#define mmCP_ME_MC_RADDR_HI 0x216E +#define mmCP_ME_MC_RADDR_LO 0x216D +#define mmCP_ME_MC_WADDR_HI 0x216A +#define mmCP_ME_MC_WADDR_LO 0x2169 +#define mmCP_ME_MC_WDATA_HI 0x216C +#define mmCP_ME_MC_WDATA_LO 0x216B +#define mmCP_MEM_SLP_CNTL 0x3079 +#define mmCP_ME_PREEMPTION 0x21B9 +#define mmCP_MEQ_AVAIL 0x21DD +#define mmCP_MEQ_STAT 0x21E5 +#define mmCP_MEQ_THRESHOLDS 0x21D9 +#define mmCP_ME_RAM_DATA 0x3058 +#define mmCP_ME_RAM_RADDR 0x3056 +#define mmCP_ME_RAM_WADDR 0x3057 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0x210B +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0x210A +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0x210F +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0x210E +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0x2113 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0x2112 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0x2117 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0x2116 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0x2109 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0x2108 +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0x210D +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0x210C +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0x2111 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0x2110 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0x2115 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0x2114 +#define mmCP_PA_CINVOC_COUNT_HI 0x2129 +#define mmCP_PA_CINVOC_COUNT_LO 0x2128 +#define mmCP_PA_CPRIM_COUNT_HI 0x212B +#define mmCP_PA_CPRIM_COUNT_LO 0x212A +#define mmCP_PERFMON_CNTL 0x21FF +#define mmCP_PERFMON_CNTX_CNTL 0xA0D8 +#define mmCP_PFP_HEADER_DUMP 0x21A2 +#define mmCP_PFP_IB_CONTROL 0x218D +#define mmCP_PFP_LOAD_CONTROL 0x218E +#define mmCP_PFP_UCODE_ADDR 0x3054 +#define mmCP_PFP_UCODE_DATA 0x3055 +#define mmCP_PIPE_STATS_ADDR_HI 0x2119 +#define mmCP_PIPE_STATS_ADDR_LO 0x2118 +#define mmCP_PWR_CNTL 0x3078 +#define mmCP_QUEUE_THRESHOLDS 0x21D8 +#define mmCP_RB0_BASE 0x3040 +#define mmCP_RB0_CNTL 0x3041 +#define mmCP_RB0_RPTR 0x21C0 +#define mmCP_RB0_RPTR_ADDR 0x3043 +#define mmCP_RB0_RPTR_ADDR_HI 0x3044 +#define mmCP_RB0_WPTR 0x3045 +#define mmCP_RB1_BASE 0x3060 +#define mmCP_RB1_CNTL 0x3061 +#define mmCP_RB1_RPTR 0x21BF +#define mmCP_RB1_RPTR_ADDR 0x3062 +#define mmCP_RB1_RPTR_ADDR_HI 0x3063 +#define mmCP_RB1_WPTR 0x3064 +#define mmCP_RB2_BASE 0x3065 +#define mmCP_RB2_CNTL 0x3066 +#define mmCP_RB2_RPTR 0x21BE +#define mmCP_RB2_RPTR_ADDR 0x3067 +#define mmCP_RB2_RPTR_ADDR_HI 0x3068 +#define mmCP_RB2_WPTR 0x3069 +#define mmCP_RB_BASE 0x3040 +#define mmCP_RB_CNTL 0x3041 +#define mmCP_RB_OFFSET 0x2191 +#define mmCP_RB_RPTR 0x21C0 +#define mmCP_RB_RPTR_ADDR 0x3043 +#define mmCP_RB_RPTR_ADDR_HI 0x3044 +#define mmCP_RB_RPTR_WR 0x3042 +#define mmCP_RB_VMID 0x3051 +#define mmCP_RB_WPTR 0x3045 +#define mmCP_RB_WPTR_DELAY 0x21C1 +#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 +#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 +#define mmCP_RB_WPTR_POLL_CNTL 0x21C2 +#define mmCP_RING0_PRIORITY 0x304D +#define mmCP_RING1_PRIORITY 0x304E +#define mmCP_RING2_PRIORITY 0x304F +#define mmCP_RINGID 0xA0D9 +#define mmCP_RING_PRIORITY_CNTS 0x304C +#define mmCP_ROQ1_THRESHOLDS 0x21D5 +#define mmCP_ROQ2_AVAIL 0x21DC +#define mmCP_ROQ2_THRESHOLDS 0x21D6 +#define mmCP_ROQ_AVAIL 0x21DA +#define mmCP_ROQ_IB1_STAT 0x21E1 +#define mmCP_ROQ_IB2_STAT 0x21E2 +#define mmCP_ROQ_RB_STAT 0x21E0 +#define mmCP_SC_PSINVOC_COUNT0_HI 0x212D +#define mmCP_SC_PSINVOC_COUNT0_LO 0x212C +#define mmCP_SC_PSINVOC_COUNT1_HI 0x212F +#define mmCP_SC_PSINVOC_COUNT1_LO 0x212E +#define mmCP_SCRATCH_DATA 0x2190 +#define mmCP_SCRATCH_INDEX 0x218F +#define mmCP_SEM_INCOMPLETE_TIMER_CNTL 0x2172 +#define mmCP_SEM_WAIT_TIMER 0x216F +#define mmCP_SIG_SEM_ADDR_HI 0x2171 +#define mmCP_SIG_SEM_ADDR_LO 0x2170 +#define mmCP_STALLED_STAT1 0x219D +#define mmCP_STALLED_STAT2 0x219E +#define mmCP_STALLED_STAT3 0x219C +#define mmCP_STAT 0x21A0 +#define mmCP_ST_BASE_HI 0x21D3 +#define mmCP_ST_BASE_LO 0x21D2 +#define mmCP_ST_BUFSZ 0x21D4 +#define mmCP_STQ_AVAIL 0x21DB +#define mmCP_STQ_STAT 0x21E3 +#define mmCP_STQ_THRESHOLDS 0x21D7 +#define mmCP_STREAM_OUT_ADDR_HI 0x2107 +#define mmCP_STREAM_OUT_ADDR_LO 0x2106 +#define mmCP_STRMOUT_CNTL 0x213F +#define mmCP_VGT_CSINVOC_COUNT_HI 0x2131 +#define mmCP_VGT_CSINVOC_COUNT_LO 0x2130 +#define mmCP_VGT_DSINVOC_COUNT_HI 0x2127 +#define mmCP_VGT_DSINVOC_COUNT_LO 0x2126 +#define mmCP_VGT_GSINVOC_COUNT_HI 0x2123 +#define mmCP_VGT_GSINVOC_COUNT_LO 0x2122 +#define mmCP_VGT_GSPRIM_COUNT_HI 0x211F +#define mmCP_VGT_GSPRIM_COUNT_LO 0x211E +#define mmCP_VGT_HSINVOC_COUNT_HI 0x2125 +#define mmCP_VGT_HSINVOC_COUNT_LO 0x2124 +#define mmCP_VGT_IAPRIM_COUNT_HI 0x211D +#define mmCP_VGT_IAPRIM_COUNT_LO 0x211C +#define mmCP_VGT_IAVERT_COUNT_HI 0x211B +#define mmCP_VGT_IAVERT_COUNT_LO 0x211A +#define mmCP_VGT_VSINVOC_COUNT_HI 0x2121 +#define mmCP_VGT_VSINVOC_COUNT_LO 0x2120 +#define mmCP_VMID 0xA0DA +#define mmCP_WAIT_REG_MEM_TIMEOUT 0x2174 +#define mmCP_WAIT_SEM_ADDR_HI 0x2176 +#define mmCP_WAIT_SEM_ADDR_LO 0x2175 +#define mmCS_COPY_STATE 0xA1F3 +#define mmDB_ALPHA_TO_MASK 0xA2DC +#define mmDB_CGTT_CLK_CTRL_0 0x261A +#define mmDB_COUNT_CONTROL 0xA001 +#define mmDB_CREDIT_LIMIT 0x2614 +#define mmDB_DEBUG 0x260C +#define mmDB_DEBUG2 0x260D +#define mmDB_DEBUG3 0x260E +#define mmDB_DEBUG4 0x260F +#define mmDB_DEPTH_BOUNDS_MAX 0xA009 +#define mmDB_DEPTH_BOUNDS_MIN 0xA008 +#define mmDB_DEPTH_CLEAR 0xA00B +#define mmDB_DEPTH_CONTROL 0xA200 +#define mmDB_DEPTH_INFO 0xA00F +#define mmDB_DEPTH_SIZE 0xA016 +#define mmDB_DEPTH_SLICE 0xA017 +#define mmDB_DEPTH_VIEW 0xA002 +#define mmDB_EQAA 0xA201 +#define mmDB_FIFO_DEPTH1 0x2618 +#define mmDB_FIFO_DEPTH2 0x2619 +#define mmDB_FREE_CACHELINES 0x2617 +#define mmDB_HTILE_DATA_BASE 0xA005 +#define mmDB_HTILE_SURFACE 0xA2AF +#define mmDB_PERFCOUNTER0_HI 0x2602 +#define mmDB_PERFCOUNTER0_LO 0x2601 +#define mmDB_PERFCOUNTER0_SELECT 0x2600 +#define mmDB_PERFCOUNTER1_HI 0x2605 +#define mmDB_PERFCOUNTER1_LO 0x2604 +#define mmDB_PERFCOUNTER1_SELECT 0x2603 +#define mmDB_PERFCOUNTER2_HI 0x2608 +#define mmDB_PERFCOUNTER2_LO 0x2607 +#define mmDB_PERFCOUNTER2_SELECT 0x2606 +#define mmDB_PERFCOUNTER3_HI 0x260B +#define mmDB_PERFCOUNTER3_LO 0x260A +#define mmDB_PERFCOUNTER3_SELECT 0x2609 +#define mmDB_PRELOAD_CONTROL 0xA2B2 +#define mmDB_READ_DEBUG_0 0x2620 +#define mmDB_READ_DEBUG_1 0x2621 +#define mmDB_READ_DEBUG_2 0x2622 +#define mmDB_READ_DEBUG_3 0x2623 +#define mmDB_READ_DEBUG_4 0x2624 +#define mmDB_READ_DEBUG_5 0x2625 +#define mmDB_READ_DEBUG_6 0x2626 +#define mmDB_READ_DEBUG_7 0x2627 +#define mmDB_READ_DEBUG_8 0x2628 +#define mmDB_READ_DEBUG_9 0x2629 +#define mmDB_READ_DEBUG_A 0x262A +#define mmDB_READ_DEBUG_B 0x262B +#define mmDB_READ_DEBUG_C 0x262C +#define mmDB_READ_DEBUG_D 0x262D +#define mmDB_READ_DEBUG_E 0x262E +#define mmDB_READ_DEBUG_F 0x262F +#define mmDB_RENDER_CONTROL 0xA000 +#define mmDB_RENDER_OVERRIDE 0xA003 +#define mmDB_RENDER_OVERRIDE2 0xA004 +#define mmDB_SHADER_CONTROL 0xA203 +#define mmDB_SRESULTS_COMPARE_STATE0 0xA2B0 +#define mmDB_SRESULTS_COMPARE_STATE1 0xA2B1 +#define mmDB_STENCIL_CLEAR 0xA00A +#define mmDB_STENCIL_CONTROL 0xA10B +#define mmDB_STENCIL_INFO 0xA011 +#define mmDB_STENCIL_READ_BASE 0xA013 +#define mmDB_STENCILREFMASK 0xA10C +#define mmDB_STENCILREFMASK_BF 0xA10D +#define mmDB_STENCIL_WRITE_BASE 0xA015 +#define mmDB_SUBTILE_CONTROL 0x2616 +#define mmDB_WATERMARKS 0x2615 +#define mmDB_Z_INFO 0xA010 +#define mmDB_ZPASS_COUNT_HI 0x261D +#define mmDB_ZPASS_COUNT_LOW 0x261C +#define mmDB_Z_READ_BASE 0xA012 +#define mmDB_Z_WRITE_BASE 0xA014 +#define mmDEBUG_DATA 0x203D +#define mmDEBUG_INDEX 0x203C +#define mmGB_ADDR_CONFIG 0x263E +#define mmGB_BACKEND_MAP 0x263F +#define mmGB_EDC_MODE 0x307E +#define mmGB_GPU_ID 0x2640 +#define mmGB_TILE_MODE0 0x2644 +#define mmGB_TILE_MODE10 0x264E +#define mmGB_TILE_MODE1 0x2645 +#define mmGB_TILE_MODE11 0x264F +#define mmGB_TILE_MODE12 0x2650 +#define mmGB_TILE_MODE13 0x2651 +#define mmGB_TILE_MODE14 0x2652 +#define mmGB_TILE_MODE15 0x2653 +#define mmGB_TILE_MODE16 0x2654 +#define mmGB_TILE_MODE17 0x2655 +#define mmGB_TILE_MODE18 0x2656 +#define mmGB_TILE_MODE19 0x2657 +#define mmGB_TILE_MODE20 0x2658 +#define mmGB_TILE_MODE2 0x2646 +#define mmGB_TILE_MODE21 0x2659 +#define mmGB_TILE_MODE22 0x265A +#define mmGB_TILE_MODE23 0x265B +#define mmGB_TILE_MODE24 0x265C +#define mmGB_TILE_MODE25 0x265D +#define mmGB_TILE_MODE26 0x265E +#define mmGB_TILE_MODE27 0x265F +#define mmGB_TILE_MODE28 0x2660 +#define mmGB_TILE_MODE29 0x2661 +#define mmGB_TILE_MODE30 0x2662 +#define mmGB_TILE_MODE3 0x2647 +#define mmGB_TILE_MODE31 0x2663 +#define mmGB_TILE_MODE4 0x2648 +#define mmGB_TILE_MODE5 0x2649 +#define mmGB_TILE_MODE6 0x264A +#define mmGB_TILE_MODE7 0x264B +#define mmGB_TILE_MODE8 0x264C +#define mmGB_TILE_MODE9 0x264D +#define mmGC_PRIV_MODE 0x3048 +#define mmGC_USER_RB_BACKEND_DISABLE 0x26DF +#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 +#define mmGDS_ATOM_BASE 0x25CE +#define mmGDS_ATOM_CNTL 0x25CC +#define mmGDS_ATOM_COMPLETE 0x25CD +#define mmGDS_ATOM_DST 0x25D2 +#define mmGDS_ATOM_OFFSET0 0x25D0 +#define mmGDS_ATOM_OFFSET1 0x25D1 +#define mmGDS_ATOM_OP 0x25D3 +#define mmGDS_ATOM_READ0 0x25D8 +#define mmGDS_ATOM_READ0_U 0x25D9 +#define mmGDS_ATOM_READ1 0x25DA +#define mmGDS_ATOM_READ1_U 0x25DB +#define mmGDS_ATOM_SIZE 0x25CF +#define mmGDS_ATOM_SRC0 0x25D4 +#define mmGDS_ATOM_SRC0_U 0x25D5 +#define mmGDS_ATOM_SRC1 0x25D6 +#define mmGDS_ATOM_SRC1_U 0x25D7 +#define mmGDS_CNTL_STATUS 0x25C1 +#define mmGDS_CONFIG 0x25C0 +#define mmGDS_DEBUG_CNTL 0x25DE +#define mmGDS_DEBUG_DATA 0x25DF +#define mmGDS_ENHANCE 0x25DC +#define mmGDS_GRBM_SECDED_CNT 0x25E3 +#define mmGDS_GWS_RESOURCE 0x25E1 +#define mmGDS_GWS_RESOURCE_CNTL 0x25E0 +#define mmGDS_OA_DED 0x25E4 +#define mmGDS_PERFCOUNTER0_HI 0x25E7 +#define mmGDS_PERFCOUNTER0_LO 0x25E6 +#define mmGDS_PERFCOUNTER0_SELECT 0x25E5 +#define mmGDS_PERFCOUNTER1_HI 0x25EA +#define mmGDS_PERFCOUNTER1_LO 0x25E9 +#define mmGDS_PERFCOUNTER1_SELECT 0x25E8 +#define mmGDS_PERFCOUNTER2_HI 0x25ED +#define mmGDS_PERFCOUNTER2_LO 0x25EC +#define mmGDS_PERFCOUNTER2_SELECT 0x25EB +#define mmGDS_PERFCOUNTER3_HI 0x25F0 +#define mmGDS_PERFCOUNTER3_LO 0x25EF +#define mmGDS_PERFCOUNTER3_SELECT 0x25EE +#define mmGDS_RD_ADDR 0x25C2 +#define mmGDS_RD_BURST_ADDR 0x25C4 +#define mmGDS_RD_BURST_COUNT 0x25C5 +#define mmGDS_RD_BURST_DATA 0x25C6 +#define mmGDS_RD_DATA 0x25C3 +#define mmGDS_SECDED_CNT 0x25E2 +#define mmGDS_WR_ADDR 0x25C7 +#define mmGDS_WR_BURST_ADDR 0x25C9 +#define mmGDS_WR_BURST_DATA 0x25CA +#define mmGDS_WR_DATA 0x25C8 +#define mmGDS_WRITE_COMPLETE 0x25CB +#define mmGFX_COPY_STATE 0xA1F4 +#define mmGRBM_CAM_DATA 0x3001 +#define mmGRBM_CAM_INDEX 0x3000 +#define mmGRBM_CNTL 0x2000 +#define mmGRBM_DEBUG 0x2014 +#define mmGRBM_DEBUG_CNTL 0x2009 +#define mmGRBM_DEBUG_DATA 0x200A +#define mmGRBM_DEBUG_SNAPSHOT 0x2015 +#define mmGRBM_GFX_CLKEN_CNTL 0x200C +#define mmGRBM_GFX_INDEX 0x200B +#define mmGRBM_INT_CNTL 0x2018 +#define mmGRBM_NOWHERE 0x203F +#define mmGRBM_PERFCOUNTER0_HI 0x201F +#define mmGRBM_PERFCOUNTER0_LO 0x201E +#define mmGRBM_PERFCOUNTER0_SELECT 0x201C +#define mmGRBM_PERFCOUNTER1_HI 0x2021 +#define mmGRBM_PERFCOUNTER1_LO 0x2020 +#define mmGRBM_PERFCOUNTER1_SELECT 0x201D +#define mmGRBM_PWR_CNTL 0x2003 +#define mmGRBM_READ_ERROR 0x2016 +#define mmGRBM_SCRATCH_REG0 0x2040 +#define mmGRBM_SCRATCH_REG1 0x2041 +#define mmGRBM_SCRATCH_REG2 0x2042 +#define mmGRBM_SCRATCH_REG3 0x2043 +#define mmGRBM_SCRATCH_REG4 0x2044 +#define mmGRBM_SCRATCH_REG5 0x2045 +#define mmGRBM_SCRATCH_REG6 0x2046 +#define mmGRBM_SCRATCH_REG7 0x2047 +#define mmGRBM_SE0_PERFCOUNTER_HI 0x202B +#define mmGRBM_SE0_PERFCOUNTER_LO 0x202A +#define mmGRBM_SE0_PERFCOUNTER_SELECT 0x2026 +#define mmGRBM_SE1_PERFCOUNTER_HI 0x202D +#define mmGRBM_SE1_PERFCOUNTER_LO 0x202C +#define mmGRBM_SE1_PERFCOUNTER_SELECT 0x2027 +#define mmGRBM_SKEW_CNTL 0x2001 +#define mmGRBM_SOFT_RESET 0x2008 +#define mmGRBM_STATUS 0x2004 +#define mmGRBM_STATUS2 0x2002 +#define mmGRBM_STATUS_SE0 0x2005 +#define mmGRBM_STATUS_SE1 0x2006 +#define mmGRBM_WAIT_IDLE_CLOCKS 0x200D +#define mmIA_CNTL_STATUS 0x2237 +#define mmIA_DEBUG_CNTL 0x223A +#define mmIA_DEBUG_DATA 0x223B +#define mmIA_ENHANCE 0xA29C +#define mmIA_MULTI_VGT_PARAM 0xA2AA +#define mmIA_PERFCOUNTER0_HI 0x2225 +#define mmIA_PERFCOUNTER0_LO 0x2224 +#define mmIA_PERFCOUNTER0_SELECT 0x2220 +#define mmIA_PERFCOUNTER1_HI 0x2227 +#define mmIA_PERFCOUNTER1_LO 0x2226 +#define mmIA_PERFCOUNTER1_SELECT 0x2221 +#define mmIA_PERFCOUNTER2_HI 0x2229 +#define mmIA_PERFCOUNTER2_LO 0x2228 +#define mmIA_PERFCOUNTER2_SELECT 0x2222 +#define mmIA_PERFCOUNTER3_HI 0x222B +#define mmIA_PERFCOUNTER3_LO 0x222A +#define mmIA_PERFCOUNTER3_SELECT 0x2223 +#define mmIA_VMID_OVERRIDE 0x2260 +#define mmPA_CL_CLIP_CNTL 0xA204 +#define mmPA_CL_CNTL_STATUS 0x2284 +#define mmPA_CL_ENHANCE 0x2285 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xA2FC +#define mmPA_CL_GB_HORZ_DISC_ADJ 0xA2FD +#define mmPA_CL_GB_VERT_CLIP_ADJ 0xA2FA +#define mmPA_CL_GB_VERT_DISC_ADJ 0xA2FB +#define mmPA_CL_NANINF_CNTL 0xA208 +#define mmPA_CL_POINT_CULL_RAD 0xA1F8 +#define mmPA_CL_POINT_SIZE 0xA1F7 +#define mmPA_CL_POINT_X_RAD 0xA1F5 +#define mmPA_CL_POINT_Y_RAD 0xA1F6 +#define mmPA_CL_UCP_0_W 0xA172 +#define mmPA_CL_UCP_0_X 0xA16F +#define mmPA_CL_UCP_0_Y 0xA170 +#define mmPA_CL_UCP_0_Z 0xA171 +#define mmPA_CL_UCP_1_W 0xA176 +#define mmPA_CL_UCP_1_X 0xA173 +#define mmPA_CL_UCP_1_Y 0xA174 +#define mmPA_CL_UCP_1_Z 0xA175 +#define mmPA_CL_UCP_2_W 0xA17A +#define mmPA_CL_UCP_2_X 0xA177 +#define mmPA_CL_UCP_2_Y 0xA178 +#define mmPA_CL_UCP_2_Z 0xA179 +#define mmPA_CL_UCP_3_W 0xA17E +#define mmPA_CL_UCP_3_X 0xA17B +#define mmPA_CL_UCP_3_Y 0xA17C +#define mmPA_CL_UCP_3_Z 0xA17D +#define mmPA_CL_UCP_4_W 0xA182 +#define mmPA_CL_UCP_4_X 0xA17F +#define mmPA_CL_UCP_4_Y 0xA180 +#define mmPA_CL_UCP_4_Z 0xA181 +#define mmPA_CL_UCP_5_W 0xA186 +#define mmPA_CL_UCP_5_X 0xA183 +#define mmPA_CL_UCP_5_Y 0xA184 +#define mmPA_CL_UCP_5_Z 0xA185 +#define mmPA_CL_VPORT_XOFFSET 0xA110 +#define mmPA_CL_VPORT_XOFFSET_10 0xA14C +#define mmPA_CL_VPORT_XOFFSET_1 0xA116 +#define mmPA_CL_VPORT_XOFFSET_11 0xA152 +#define mmPA_CL_VPORT_XOFFSET_12 0xA158 +#define mmPA_CL_VPORT_XOFFSET_13 0xA15E +#define mmPA_CL_VPORT_XOFFSET_14 0xA164 +#define mmPA_CL_VPORT_XOFFSET_15 0xA16A +#define mmPA_CL_VPORT_XOFFSET_2 0xA11C +#define mmPA_CL_VPORT_XOFFSET_3 0xA122 +#define mmPA_CL_VPORT_XOFFSET_4 0xA128 +#define mmPA_CL_VPORT_XOFFSET_5 0xA12E +#define mmPA_CL_VPORT_XOFFSET_6 0xA134 +#define mmPA_CL_VPORT_XOFFSET_7 0xA13A +#define mmPA_CL_VPORT_XOFFSET_8 0xA140 +#define mmPA_CL_VPORT_XOFFSET_9 0xA146 +#define mmPA_CL_VPORT_XSCALE 0xA10F +#define mmPA_CL_VPORT_XSCALE_10 0xA14B +#define mmPA_CL_VPORT_XSCALE_1 0xA115 +#define mmPA_CL_VPORT_XSCALE_11 0xA151 +#define mmPA_CL_VPORT_XSCALE_12 0xA157 +#define mmPA_CL_VPORT_XSCALE_13 0xA15D +#define mmPA_CL_VPORT_XSCALE_14 0xA163 +#define mmPA_CL_VPORT_XSCALE_15 0xA169 +#define mmPA_CL_VPORT_XSCALE_2 0xA11B +#define mmPA_CL_VPORT_XSCALE_3 0xA121 +#define mmPA_CL_VPORT_XSCALE_4 0xA127 +#define mmPA_CL_VPORT_XSCALE_5 0xA12D +#define mmPA_CL_VPORT_XSCALE_6 0xA133 +#define mmPA_CL_VPORT_XSCALE_7 0xA139 +#define mmPA_CL_VPORT_XSCALE_8 0xA13F +#define mmPA_CL_VPORT_XSCALE_9 0xA145 +#define mmPA_CL_VPORT_YOFFSET 0xA112 +#define mmPA_CL_VPORT_YOFFSET_10 0xA14E +#define mmPA_CL_VPORT_YOFFSET_1 0xA118 +#define mmPA_CL_VPORT_YOFFSET_11 0xA154 +#define mmPA_CL_VPORT_YOFFSET_12 0xA15A +#define mmPA_CL_VPORT_YOFFSET_13 0xA160 +#define mmPA_CL_VPORT_YOFFSET_14 0xA166 +#define mmPA_CL_VPORT_YOFFSET_15 0xA16C +#define mmPA_CL_VPORT_YOFFSET_2 0xA11E +#define mmPA_CL_VPORT_YOFFSET_3 0xA124 +#define mmPA_CL_VPORT_YOFFSET_4 0xA12A +#define mmPA_CL_VPORT_YOFFSET_5 0xA130 +#define mmPA_CL_VPORT_YOFFSET_6 0xA136 +#define mmPA_CL_VPORT_YOFFSET_7 0xA13C +#define mmPA_CL_VPORT_YOFFSET_8 0xA142 +#define mmPA_CL_VPORT_YOFFSET_9 0xA148 +#define mmPA_CL_VPORT_YSCALE 0xA111 +#define mmPA_CL_VPORT_YSCALE_10 0xA14D +#define mmPA_CL_VPORT_YSCALE_1 0xA117 +#define mmPA_CL_VPORT_YSCALE_11 0xA153 +#define mmPA_CL_VPORT_YSCALE_12 0xA159 +#define mmPA_CL_VPORT_YSCALE_13 0xA15F +#define mmPA_CL_VPORT_YSCALE_14 0xA165 +#define mmPA_CL_VPORT_YSCALE_15 0xA16B +#define mmPA_CL_VPORT_YSCALE_2 0xA11D +#define mmPA_CL_VPORT_YSCALE_3 0xA123 +#define mmPA_CL_VPORT_YSCALE_4 0xA129 +#define mmPA_CL_VPORT_YSCALE_5 0xA12F +#define mmPA_CL_VPORT_YSCALE_6 0xA135 +#define mmPA_CL_VPORT_YSCALE_7 0xA13B +#define mmPA_CL_VPORT_YSCALE_8 0xA141 +#define mmPA_CL_VPORT_YSCALE_9 0xA147 +#define mmPA_CL_VPORT_ZOFFSET 0xA114 +#define mmPA_CL_VPORT_ZOFFSET_10 0xA150 +#define mmPA_CL_VPORT_ZOFFSET_1 0xA11A +#define mmPA_CL_VPORT_ZOFFSET_11 0xA156 +#define mmPA_CL_VPORT_ZOFFSET_12 0xA15C +#define mmPA_CL_VPORT_ZOFFSET_13 0xA162 +#define mmPA_CL_VPORT_ZOFFSET_14 0xA168 +#define mmPA_CL_VPORT_ZOFFSET_15 0xA16E +#define mmPA_CL_VPORT_ZOFFSET_2 0xA120 +#define mmPA_CL_VPORT_ZOFFSET_3 0xA126 +#define mmPA_CL_VPORT_ZOFFSET_4 0xA12C +#define mmPA_CL_VPORT_ZOFFSET_5 0xA132 +#define mmPA_CL_VPORT_ZOFFSET_6 0xA138 +#define mmPA_CL_VPORT_ZOFFSET_7 0xA13E +#define mmPA_CL_VPORT_ZOFFSET_8 0xA144 +#define mmPA_CL_VPORT_ZOFFSET_9 0xA14A +#define mmPA_CL_VPORT_ZSCALE 0xA113 +#define mmPA_CL_VPORT_ZSCALE_10 0xA14F +#define mmPA_CL_VPORT_ZSCALE_1 0xA119 +#define mmPA_CL_VPORT_ZSCALE_11 0xA155 +#define mmPA_CL_VPORT_ZSCALE_12 0xA15B +#define mmPA_CL_VPORT_ZSCALE_13 0xA161 +#define mmPA_CL_VPORT_ZSCALE_14 0xA167 +#define mmPA_CL_VPORT_ZSCALE_15 0xA16D +#define mmPA_CL_VPORT_ZSCALE_2 0xA11F +#define mmPA_CL_VPORT_ZSCALE_3 0xA125 +#define mmPA_CL_VPORT_ZSCALE_4 0xA12B +#define mmPA_CL_VPORT_ZSCALE_5 0xA131 +#define mmPA_CL_VPORT_ZSCALE_6 0xA137 +#define mmPA_CL_VPORT_ZSCALE_7 0xA13D +#define mmPA_CL_VPORT_ZSCALE_8 0xA143 +#define mmPA_CL_VPORT_ZSCALE_9 0xA149 +#define mmPA_CL_VS_OUT_CNTL 0xA207 +#define mmPA_CL_VTE_CNTL 0xA206 +#define mmPA_SC_AA_CONFIG 0xA2F8 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xA30E +#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xA30F +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xA2FE +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xA2FF +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xA300 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xA301 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xA306 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xA307 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xA308 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xA309 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xA302 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xA303 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xA304 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xA305 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xA30A +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xA30B +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xA30C +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xA30D +#define mmPA_SC_CENTROID_PRIORITY_0 0xA2F5 +#define mmPA_SC_CENTROID_PRIORITY_1 0xA2F6 +#define mmPA_SC_CLIPRECT_0_BR 0xA085 +#define mmPA_SC_CLIPRECT_0_TL 0xA084 +#define mmPA_SC_CLIPRECT_1_BR 0xA087 +#define mmPA_SC_CLIPRECT_1_TL 0xA086 +#define mmPA_SC_CLIPRECT_2_BR 0xA089 +#define mmPA_SC_CLIPRECT_2_TL 0xA088 +#define mmPA_SC_CLIPRECT_3_BR 0xA08B +#define mmPA_SC_CLIPRECT_3_TL 0xA08A +#define mmPA_SC_CLIPRECT_RULE 0xA083 +#define mmPA_SC_DEBUG_CNTL 0x22F6 +#define mmPA_SC_DEBUG_DATA 0x22F7 +#define mmPA_SC_EDGERULE 0xA08C +#define mmPA_SC_ENHANCE 0x22FC +#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 +#define mmPA_SC_FIFO_SIZE 0x22F3 +#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22C9 +#define mmPA_SC_GENERIC_SCISSOR_BR 0xA091 +#define mmPA_SC_GENERIC_SCISSOR_TL 0xA090 +#define mmPA_SC_IF_FIFO_SIZE 0x22F5 +#define mmPA_SC_LINE_CNTL 0xA2F7 +#define mmPA_SC_LINE_STIPPLE 0xA283 +#define mmPA_SC_LINE_STIPPLE_STATE 0x22C4 +#define mmPA_SC_MODE_CNTL_0 0xA292 +#define mmPA_SC_MODE_CNTL_1 0xA293 +#define mmPA_SC_PERFCOUNTER0_HI 0x22A9 +#define mmPA_SC_PERFCOUNTER0_LO 0x22A8 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x22A0 +#define mmPA_SC_PERFCOUNTER1_HI 0x22AB +#define mmPA_SC_PERFCOUNTER1_LO 0x22AA +#define mmPA_SC_PERFCOUNTER1_SELECT 0x22A1 +#define mmPA_SC_PERFCOUNTER2_HI 0x22AD +#define mmPA_SC_PERFCOUNTER2_LO 0x22AC +#define mmPA_SC_PERFCOUNTER2_SELECT 0x22A2 +#define mmPA_SC_PERFCOUNTER3_HI 0x22AF +#define mmPA_SC_PERFCOUNTER3_LO 0x22AE +#define mmPA_SC_PERFCOUNTER3_SELECT 0x22A3 +#define mmPA_SC_PERFCOUNTER4_HI 0x22B1 +#define mmPA_SC_PERFCOUNTER4_LO 0x22B0 +#define mmPA_SC_PERFCOUNTER4_SELECT 0x22A4 +#define mmPA_SC_PERFCOUNTER5_HI 0x22B3 +#define mmPA_SC_PERFCOUNTER5_LO 0x22B2 +#define mmPA_SC_PERFCOUNTER5_SELECT 0x22A5 +#define mmPA_SC_PERFCOUNTER6_HI 0x22B5 +#define mmPA_SC_PERFCOUNTER6_LO 0x22B4 +#define mmPA_SC_PERFCOUNTER6_SELECT 0x22A6 +#define mmPA_SC_PERFCOUNTER7_HI 0x22B7 +#define mmPA_SC_PERFCOUNTER7_LO 0x22B6 +#define mmPA_SC_PERFCOUNTER7_SELECT 0x22A7 +#define mmPA_SC_RASTER_CONFIG 0xA0D4 +#define mmPA_SC_SCREEN_SCISSOR_BR 0xA00D +#define mmPA_SC_SCREEN_SCISSOR_TL 0xA00C +#define mmPA_SC_VPORT_SCISSOR_0_BR 0xA095 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0xA094 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0xA0A9 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0xA0A8 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0xA0AB +#define mmPA_SC_VPORT_SCISSOR_11_TL 0xA0AA +#define mmPA_SC_VPORT_SCISSOR_12_BR 0xA0AD +#define mmPA_SC_VPORT_SCISSOR_12_TL 0xA0AC +#define mmPA_SC_VPORT_SCISSOR_13_BR 0xA0AF +#define mmPA_SC_VPORT_SCISSOR_13_TL 0xA0AE +#define mmPA_SC_VPORT_SCISSOR_14_BR 0xA0B1 +#define mmPA_SC_VPORT_SCISSOR_14_TL 0xA0B0 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0xA0B3 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0xA0B2 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0xA097 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0xA096 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0xA099 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0xA098 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0xA09B +#define mmPA_SC_VPORT_SCISSOR_3_TL 0xA09A +#define mmPA_SC_VPORT_SCISSOR_4_BR 0xA09D +#define mmPA_SC_VPORT_SCISSOR_4_TL 0xA09C +#define mmPA_SC_VPORT_SCISSOR_5_BR 0xA09F +#define mmPA_SC_VPORT_SCISSOR_5_TL 0xA09E +#define mmPA_SC_VPORT_SCISSOR_6_BR 0xA0A1 +#define mmPA_SC_VPORT_SCISSOR_6_TL 0xA0A0 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0xA0A3 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0xA0A2 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0xA0A5 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0xA0A4 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0xA0A7 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0xA0A6 +#define mmPA_SC_VPORT_ZMAX_0 0xA0B5 +#define mmPA_SC_VPORT_ZMAX_10 0xA0C9 +#define mmPA_SC_VPORT_ZMAX_1 0xA0B7 +#define mmPA_SC_VPORT_ZMAX_11 0xA0CB +#define mmPA_SC_VPORT_ZMAX_12 0xA0CD +#define mmPA_SC_VPORT_ZMAX_13 0xA0CF +#define mmPA_SC_VPORT_ZMAX_14 0xA0D1 +#define mmPA_SC_VPORT_ZMAX_15 0xA0D3 +#define mmPA_SC_VPORT_ZMAX_2 0xA0B9 +#define mmPA_SC_VPORT_ZMAX_3 0xA0BB +#define mmPA_SC_VPORT_ZMAX_4 0xA0BD +#define mmPA_SC_VPORT_ZMAX_5 0xA0BF +#define mmPA_SC_VPORT_ZMAX_6 0xA0C1 +#define mmPA_SC_VPORT_ZMAX_7 0xA0C3 +#define mmPA_SC_VPORT_ZMAX_8 0xA0C5 +#define mmPA_SC_VPORT_ZMAX_9 0xA0C7 +#define mmPA_SC_VPORT_ZMIN_0 0xA0B4 +#define mmPA_SC_VPORT_ZMIN_10 0xA0C8 +#define mmPA_SC_VPORT_ZMIN_1 0xA0B6 +#define mmPA_SC_VPORT_ZMIN_11 0xA0CA +#define mmPA_SC_VPORT_ZMIN_12 0xA0CC +#define mmPA_SC_VPORT_ZMIN_13 0xA0CE +#define mmPA_SC_VPORT_ZMIN_14 0xA0D0 +#define mmPA_SC_VPORT_ZMIN_15 0xA0D2 +#define mmPA_SC_VPORT_ZMIN_2 0xA0B8 +#define mmPA_SC_VPORT_ZMIN_3 0xA0BA +#define mmPA_SC_VPORT_ZMIN_4 0xA0BC +#define mmPA_SC_VPORT_ZMIN_5 0xA0BE +#define mmPA_SC_VPORT_ZMIN_6 0xA0C0 +#define mmPA_SC_VPORT_ZMIN_7 0xA0C2 +#define mmPA_SC_VPORT_ZMIN_8 0xA0C4 +#define mmPA_SC_VPORT_ZMIN_9 0xA0C6 +#define mmPA_SC_WINDOW_OFFSET 0xA080 +#define mmPA_SC_WINDOW_SCISSOR_BR 0xA082 +#define mmPA_SC_WINDOW_SCISSOR_TL 0xA081 +#define mmPA_SU_CNTL_STATUS 0x2294 +#define mmPA_SU_DEBUG_CNTL 0x2280 +#define mmPA_SU_DEBUG_DATA 0x2281 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xA08D +#define mmPA_SU_LINE_CNTL 0xA282 +#define mmPA_SU_LINE_STIPPLE_CNTL 0xA209 +#define mmPA_SU_LINE_STIPPLE_SCALE 0xA20A +#define mmPA_SU_LINE_STIPPLE_VALUE 0x2298 +#define mmPA_SU_PERFCOUNTER0_HI 0x228D +#define mmPA_SU_PERFCOUNTER0_LO 0x228C +#define mmPA_SU_PERFCOUNTER0_SELECT 0x2288 +#define mmPA_SU_PERFCOUNTER1_HI 0x228F +#define mmPA_SU_PERFCOUNTER1_LO 0x228E +#define mmPA_SU_PERFCOUNTER1_SELECT 0x2289 +#define mmPA_SU_PERFCOUNTER2_HI 0x2291 +#define mmPA_SU_PERFCOUNTER2_LO 0x2290 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x228A +#define mmPA_SU_PERFCOUNTER3_HI 0x2293 +#define mmPA_SU_PERFCOUNTER3_LO 0x2292 +#define mmPA_SU_PERFCOUNTER3_SELECT 0x228B +#define mmPA_SU_POINT_MINMAX 0xA281 +#define mmPA_SU_POINT_SIZE 0xA280 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xA2E3 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xA2E2 +#define mmPA_SU_POLY_OFFSET_CLAMP 0xA2DF +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xA2DE +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xA2E1 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xA2E0 +#define mmPA_SU_PRIM_FILTER_CNTL 0xA20B +#define mmPA_SU_SC_MODE_CNTL 0xA205 +#define mmPA_SU_VTX_CNTL 0xA2F9 +#define mmRAS_BCI_SIGNATURE0 0x339E +#define mmRAS_BCI_SIGNATURE1 0x339F +#define mmRAS_CB_SIGNATURE0 0x339D +#define mmRAS_DB_SIGNATURE0 0x338B +#define mmRAS_IA_SIGNATURE0 0x3397 +#define mmRAS_IA_SIGNATURE1 0x3398 +#define mmRAS_PA_SIGNATURE0 0x338C +#define mmRAS_SC_SIGNATURE0 0x338F +#define mmRAS_SC_SIGNATURE1 0x3390 +#define mmRAS_SC_SIGNATURE2 0x3391 +#define mmRAS_SC_SIGNATURE3 0x3392 +#define mmRAS_SC_SIGNATURE4 0x3393 +#define mmRAS_SC_SIGNATURE5 0x3394 +#define mmRAS_SC_SIGNATURE6 0x3395 +#define mmRAS_SC_SIGNATURE7 0x3396 +#define mmRAS_SIGNATURE_CONTROL 0x3380 +#define mmRAS_SIGNATURE_MASK 0x3381 +#define mmRAS_SPI_SIGNATURE0 0x3399 +#define mmRAS_SPI_SIGNATURE1 0x339A +#define mmRAS_SQ_SIGNATURE0 0x338E +#define mmRAS_SX_SIGNATURE0 0x3382 +#define mmRAS_SX_SIGNATURE1 0x3383 +#define mmRAS_SX_SIGNATURE2 0x3384 +#define mmRAS_SX_SIGNATURE3 0x3385 +#define mmRAS_TA_SIGNATURE0 0x339B +#define mmRAS_TD_SIGNATURE0 0x339C +#define mmRAS_VGT_SIGNATURE0 0x338D +#define mmRLC_AUTO_PG_CTRL 0x310D +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30D0 +#define mmRLC_CGCG_CGLS_CTRL 0x3101 +#define mmRLC_CGCG_RAMP_CTRL 0x3102 +#define mmRLC_CGTT_MGCG_OVERRIDE 0x3100 +#define mmRLC_CNTL 0x30C0 +#define mmRLC_CU_STATUS 0x3106 +#define mmRLC_DEBUG 0x30CA +#define mmRLC_DEBUG_SELECT 0x30C9 +#define mmRLC_DRIVER_CPDMA_STATUS 0x30C7 +#define mmRLC_DYN_PG_REQUEST 0x3104 +#define mmRLC_DYN_PG_STATUS 0x3103 +#define mmRLC_GPU_CLOCK_32 0x30D5 +#define mmRLC_GPU_CLOCK_32_RES_SEL 0x30D4 +#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30CE +#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30CF +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3108 +#define mmRLC_LB_CNTL 0x30C3 +#define mmRLC_LB_CNTR_INIT 0x30C6 +#define mmRLC_LB_CNTR_MAX 0x30C5 +#define mmRLC_LB_INIT_CU_MASK 0x3107 +#define mmRLC_LB_PARAMS 0x3109 +#define mmRLC_LOAD_BALANCE_CNTR 0x30F6 +#define mmRLC_MAX_PG_CU 0x310C +#define mmRLC_MC_CNTL 0x30D1 +#define mmRLC_MEM_SLP_CNTL 0x30D8 +#define mmRLC_PERFCOUNTER0_HI 0x30DC +#define mmRLC_PERFCOUNTER0_LO 0x30DB +#define mmRLC_PERFCOUNTER0_SELECT 0x30DA +#define mmRLC_PERFCOUNTER1_HI 0x30DF +#define mmRLC_PERFCOUNTER1_LO 0x30DE +#define mmRLC_PERFCOUNTER1_SELECT 0x30DD +#define mmRLC_PERFMON_CNTL 0x30D9 +#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x310B +#define mmRLC_PG_CNTL 0x30D7 +#define mmRLC_SAVE_AND_RESTORE_BASE 0x30C4 +#define mmRLC_SERDES_RD_DATA_0 0x3112 +#define mmRLC_SERDES_RD_DATA_1 0x3113 +#define mmRLC_SERDES_RD_DATA_2 0x3114 +#define mmRLC_SERDES_RD_MASTER_INDEX 0x3111 +#define mmRLC_SERDES_WR_CTRL 0x3117 +#define mmRLC_SERDES_WR_DATA 0x3118 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x310E +#define mmRLC_SMU_PG_CTRL 0x310F +#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3110 +#define mmRLC_SOFT_RESET_GPU 0x30D6 +#define mmRLC_STAT 0x30D3 +#define mmRLC_THREAD1_DELAY 0x310A +#define mmRLC_UCODE_CNTL 0x30D2 +#define mmSCRATCH_ADDR 0x2151 +#define mmSCRATCH_REG0 0x2140 +#define mmSCRATCH_REG1 0x2141 +#define mmSCRATCH_REG2 0x2142 +#define mmSCRATCH_REG3 0x2143 +#define mmSCRATCH_REG4 0x2144 +#define mmSCRATCH_REG5 0x2145 +#define mmSCRATCH_REG6 0x2146 +#define mmSCRATCH_REG7 0x2147 +#define mmSCRATCH_UMSK 0x2150 +#define mmSPI_ARB_CYCLES_0 0x243D +#define mmSPI_ARB_CYCLES_1 0x243E +#define mmSPI_ARB_PRIORITY 0x243C +#define mmSPI_BARYC_CNTL 0xA1B8 +#define mmSPI_CONFIG_CNTL 0x2440 +#define mmSPI_CONFIG_CNTL_1 0x244F +#define mmSPI_DEBUG_BUSY 0x2450 +#define mmSPI_DEBUG_CNTL 0x2441 +#define mmSPI_DEBUG_READ 0x2442 +#define mmSPI_GDS_CREDITS 0x24D8 +#define mmSPI_INTERP_CONTROL_0 0xA1B5 +#define mmSPI_LB_CTR_CTRL 0x24D4 +#define mmSPI_LB_CU_MASK 0x24D5 +#define mmSPI_LB_DATA_REG 0x24D6 +#define mmSPI_PERFCOUNTER0_HI 0x2447 +#define mmSPI_PERFCOUNTER0_LO 0x2448 +#define mmSPI_PERFCOUNTER0_SELECT 0x2443 +#define mmSPI_PERFCOUNTER1_HI 0x2449 +#define mmSPI_PERFCOUNTER1_LO 0x244A +#define mmSPI_PERFCOUNTER1_SELECT 0x2444 +#define mmSPI_PERFCOUNTER2_HI 0x244B +#define mmSPI_PERFCOUNTER2_LO 0x244C +#define mmSPI_PERFCOUNTER2_SELECT 0x2445 +#define mmSPI_PERFCOUNTER3_HI 0x244D +#define mmSPI_PERFCOUNTER3_LO 0x244E +#define mmSPI_PERFCOUNTER3_SELECT 0x2446 +#define mmSPI_PERFCOUNTER_BINS 0x243F +#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24D7 +#define mmSPI_PS_IN_CONTROL 0xA1B6 +#define mmSPI_PS_INPUT_ADDR 0xA1B4 +#define mmSPI_PS_INPUT_CNTL_0 0xA191 +#define mmSPI_PS_INPUT_CNTL_10 0xA19B +#define mmSPI_PS_INPUT_CNTL_1 0xA192 +#define mmSPI_PS_INPUT_CNTL_11 0xA19C +#define mmSPI_PS_INPUT_CNTL_12 0xA19D +#define mmSPI_PS_INPUT_CNTL_13 0xA19E +#define mmSPI_PS_INPUT_CNTL_14 0xA19F +#define mmSPI_PS_INPUT_CNTL_15 0xA1A0 +#define mmSPI_PS_INPUT_CNTL_16 0xA1A1 +#define mmSPI_PS_INPUT_CNTL_17 0xA1A2 +#define mmSPI_PS_INPUT_CNTL_18 0xA1A3 +#define mmSPI_PS_INPUT_CNTL_19 0xA1A4 +#define mmSPI_PS_INPUT_CNTL_20 0xA1A5 +#define mmSPI_PS_INPUT_CNTL_2 0xA193 +#define mmSPI_PS_INPUT_CNTL_21 0xA1A6 +#define mmSPI_PS_INPUT_CNTL_22 0xA1A7 +#define mmSPI_PS_INPUT_CNTL_23 0xA1A8 +#define mmSPI_PS_INPUT_CNTL_24 0xA1A9 +#define mmSPI_PS_INPUT_CNTL_25 0xA1AA +#define mmSPI_PS_INPUT_CNTL_26 0xA1AB +#define mmSPI_PS_INPUT_CNTL_27 0xA1AC +#define mmSPI_PS_INPUT_CNTL_28 0xA1AD +#define mmSPI_PS_INPUT_CNTL_29 0xA1AE +#define mmSPI_PS_INPUT_CNTL_30 0xA1AF +#define mmSPI_PS_INPUT_CNTL_3 0xA194 +#define mmSPI_PS_INPUT_CNTL_31 0xA1B0 +#define mmSPI_PS_INPUT_CNTL_4 0xA195 +#define mmSPI_PS_INPUT_CNTL_5 0xA196 +#define mmSPI_PS_INPUT_CNTL_6 0xA197 +#define mmSPI_PS_INPUT_CNTL_7 0xA198 +#define mmSPI_PS_INPUT_CNTL_8 0xA199 +#define mmSPI_PS_INPUT_CNTL_9 0xA19A +#define mmSPI_PS_INPUT_ENA 0xA1B3 +#define mmSPI_PS_MAX_WAVE_ID 0x243B +#define mmSPI_SHADER_COL_FORMAT 0xA1C5 +#define mmSPI_SHADER_PGM_HI_ES 0x2CC9 +#define mmSPI_SHADER_PGM_HI_GS 0x2C89 +#define mmSPI_SHADER_PGM_HI_HS 0x2D09 +#define mmSPI_SHADER_PGM_HI_LS 0x2D49 +#define mmSPI_SHADER_PGM_HI_PS 0x2C09 +#define mmSPI_SHADER_PGM_HI_VS 0x2C49 +#define mmSPI_SHADER_PGM_LO_ES 0x2CC8 +#define mmSPI_SHADER_PGM_LO_GS 0x2C88 +#define mmSPI_SHADER_PGM_LO_HS 0x2D08 +#define mmSPI_SHADER_PGM_LO_LS 0x2D48 +#define mmSPI_SHADER_PGM_LO_PS 0x2C08 +#define mmSPI_SHADER_PGM_LO_VS 0x2C48 +#define mmSPI_SHADER_PGM_RSRC1_ES 0x2CCA +#define mmSPI_SHADER_PGM_RSRC1_GS 0x2C8A +#define mmSPI_SHADER_PGM_RSRC1_HS 0x2D0A +#define mmSPI_SHADER_PGM_RSRC1_LS 0x2D4A +#define mmSPI_SHADER_PGM_RSRC1_PS 0x2C0A +#define mmSPI_SHADER_PGM_RSRC1_VS 0x2C4A +#define mmSPI_SHADER_PGM_RSRC2_ES 0x2CCB +#define mmSPI_SHADER_PGM_RSRC2_GS 0x2C8B +#define mmSPI_SHADER_PGM_RSRC2_HS 0x2D0B +#define mmSPI_SHADER_PGM_RSRC2_LS 0x2D4B +#define mmSPI_SHADER_PGM_RSRC2_PS 0x2C0B +#define mmSPI_SHADER_PGM_RSRC2_VS 0x2C4B +#define mmSPI_SHADER_POS_FORMAT 0xA1C3 +#define mmSPI_SHADER_TBA_HI_ES 0x2CC1 +#define mmSPI_SHADER_TBA_HI_GS 0x2C81 +#define mmSPI_SHADER_TBA_HI_HS 0x2D01 +#define mmSPI_SHADER_TBA_HI_LS 0x2D41 +#define mmSPI_SHADER_TBA_HI_PS 0x2C01 +#define mmSPI_SHADER_TBA_HI_VS 0x2C41 +#define mmSPI_SHADER_TBA_LO_ES 0x2CC0 +#define mmSPI_SHADER_TBA_LO_GS 0x2C80 +#define mmSPI_SHADER_TBA_LO_HS 0x2D00 +#define mmSPI_SHADER_TBA_LO_LS 0x2D40 +#define mmSPI_SHADER_TBA_LO_PS 0x2C00 +#define mmSPI_SHADER_TBA_LO_VS 0x2C40 +#define mmSPI_SHADER_TMA_HI_ES 0x2CC3 +#define mmSPI_SHADER_TMA_HI_GS 0x2C83 +#define mmSPI_SHADER_TMA_HI_HS 0x2D03 +#define mmSPI_SHADER_TMA_HI_LS 0x2D43 +#define mmSPI_SHADER_TMA_HI_PS 0x2C03 +#define mmSPI_SHADER_TMA_HI_VS 0x2C43 +#define mmSPI_SHADER_TMA_LO_ES 0x2CC2 +#define mmSPI_SHADER_TMA_LO_GS 0x2C82 +#define mmSPI_SHADER_TMA_LO_HS 0x2D02 +#define mmSPI_SHADER_TMA_LO_LS 0x2D42 +#define mmSPI_SHADER_TMA_LO_PS 0x2C02 +#define mmSPI_SHADER_TMA_LO_VS 0x2C42 +#define mmSPI_SHADER_USER_DATA_ES_0 0x2CCC +#define mmSPI_SHADER_USER_DATA_ES_10 0x2CD6 +#define mmSPI_SHADER_USER_DATA_ES_1 0x2CCD +#define mmSPI_SHADER_USER_DATA_ES_11 0x2CD7 +#define mmSPI_SHADER_USER_DATA_ES_12 0x2CD8 +#define mmSPI_SHADER_USER_DATA_ES_13 0x2CD9 +#define mmSPI_SHADER_USER_DATA_ES_14 0x2CDA +#define mmSPI_SHADER_USER_DATA_ES_15 0x2CDB +#define mmSPI_SHADER_USER_DATA_ES_2 0x2CCE +#define mmSPI_SHADER_USER_DATA_ES_3 0x2CCF +#define mmSPI_SHADER_USER_DATA_ES_4 0x2CD0 +#define mmSPI_SHADER_USER_DATA_ES_5 0x2CD1 +#define mmSPI_SHADER_USER_DATA_ES_6 0x2CD2 +#define mmSPI_SHADER_USER_DATA_ES_7 0x2CD3 +#define mmSPI_SHADER_USER_DATA_ES_8 0x2CD4 +#define mmSPI_SHADER_USER_DATA_ES_9 0x2CD5 +#define mmSPI_SHADER_USER_DATA_GS_0 0x2C8C +#define mmSPI_SHADER_USER_DATA_GS_10 0x2C96 +#define mmSPI_SHADER_USER_DATA_GS_1 0x2C8D +#define mmSPI_SHADER_USER_DATA_GS_11 0x2C97 +#define mmSPI_SHADER_USER_DATA_GS_12 0x2C98 +#define mmSPI_SHADER_USER_DATA_GS_13 0x2C99 +#define mmSPI_SHADER_USER_DATA_GS_14 0x2C9A +#define mmSPI_SHADER_USER_DATA_GS_15 0x2C9B +#define mmSPI_SHADER_USER_DATA_GS_2 0x2C8E +#define mmSPI_SHADER_USER_DATA_GS_3 0x2C8F +#define mmSPI_SHADER_USER_DATA_GS_4 0x2C90 +#define mmSPI_SHADER_USER_DATA_GS_5 0x2C91 +#define mmSPI_SHADER_USER_DATA_GS_6 0x2C92 +#define mmSPI_SHADER_USER_DATA_GS_7 0x2C93 +#define mmSPI_SHADER_USER_DATA_GS_8 0x2C94 +#define mmSPI_SHADER_USER_DATA_GS_9 0x2C95 +#define mmSPI_SHADER_USER_DATA_HS_0 0x2D0C +#define mmSPI_SHADER_USER_DATA_HS_10 0x2D16 +#define mmSPI_SHADER_USER_DATA_HS_1 0x2D0D +#define mmSPI_SHADER_USER_DATA_HS_11 0x2D17 +#define mmSPI_SHADER_USER_DATA_HS_12 0x2D18 +#define mmSPI_SHADER_USER_DATA_HS_13 0x2D19 +#define mmSPI_SHADER_USER_DATA_HS_14 0x2D1A +#define mmSPI_SHADER_USER_DATA_HS_15 0x2D1B +#define mmSPI_SHADER_USER_DATA_HS_2 0x2D0E +#define mmSPI_SHADER_USER_DATA_HS_3 0x2D0F +#define mmSPI_SHADER_USER_DATA_HS_4 0x2D10 +#define mmSPI_SHADER_USER_DATA_HS_5 0x2D11 +#define mmSPI_SHADER_USER_DATA_HS_6 0x2D12 +#define mmSPI_SHADER_USER_DATA_HS_7 0x2D13 +#define mmSPI_SHADER_USER_DATA_HS_8 0x2D14 +#define mmSPI_SHADER_USER_DATA_HS_9 0x2D15 +#define mmSPI_SHADER_USER_DATA_LS_0 0x2D4C +#define mmSPI_SHADER_USER_DATA_LS_10 0x2D56 +#define mmSPI_SHADER_USER_DATA_LS_1 0x2D4D +#define mmSPI_SHADER_USER_DATA_LS_11 0x2D57 +#define mmSPI_SHADER_USER_DATA_LS_12 0x2D58 +#define mmSPI_SHADER_USER_DATA_LS_13 0x2D59 +#define mmSPI_SHADER_USER_DATA_LS_14 0x2D5A +#define mmSPI_SHADER_USER_DATA_LS_15 0x2D5B +#define mmSPI_SHADER_USER_DATA_LS_2 0x2D4E +#define mmSPI_SHADER_USER_DATA_LS_3 0x2D4F +#define mmSPI_SHADER_USER_DATA_LS_4 0x2D50 +#define mmSPI_SHADER_USER_DATA_LS_5 0x2D51 +#define mmSPI_SHADER_USER_DATA_LS_6 0x2D52 +#define mmSPI_SHADER_USER_DATA_LS_7 0x2D53 +#define mmSPI_SHADER_USER_DATA_LS_8 0x2D54 +#define mmSPI_SHADER_USER_DATA_LS_9 0x2D55 +#define mmSPI_SHADER_USER_DATA_PS_0 0x2C0C +#define mmSPI_SHADER_USER_DATA_PS_10 0x2C16 +#define mmSPI_SHADER_USER_DATA_PS_1 0x2C0D +#define mmSPI_SHADER_USER_DATA_PS_11 0x2C17 +#define mmSPI_SHADER_USER_DATA_PS_12 0x2C18 +#define mmSPI_SHADER_USER_DATA_PS_13 0x2C19 +#define mmSPI_SHADER_USER_DATA_PS_14 0x2C1A +#define mmSPI_SHADER_USER_DATA_PS_15 0x2C1B +#define mmSPI_SHADER_USER_DATA_PS_2 0x2C0E +#define mmSPI_SHADER_USER_DATA_PS_3 0x2C0F +#define mmSPI_SHADER_USER_DATA_PS_4 0x2C10 +#define mmSPI_SHADER_USER_DATA_PS_5 0x2C11 +#define mmSPI_SHADER_USER_DATA_PS_6 0x2C12 +#define mmSPI_SHADER_USER_DATA_PS_7 0x2C13 +#define mmSPI_SHADER_USER_DATA_PS_8 0x2C14 +#define mmSPI_SHADER_USER_DATA_PS_9 0x2C15 +#define mmSPI_SHADER_USER_DATA_VS_0 0x2C4C +#define mmSPI_SHADER_USER_DATA_VS_10 0x2C56 +#define mmSPI_SHADER_USER_DATA_VS_1 0x2C4D +#define mmSPI_SHADER_USER_DATA_VS_11 0x2C57 +#define mmSPI_SHADER_USER_DATA_VS_12 0x2C58 +#define mmSPI_SHADER_USER_DATA_VS_13 0x2C59 +#define mmSPI_SHADER_USER_DATA_VS_14 0x2C5A +#define mmSPI_SHADER_USER_DATA_VS_15 0x2C5B +#define mmSPI_SHADER_USER_DATA_VS_2 0x2C4E +#define mmSPI_SHADER_USER_DATA_VS_3 0x2C4F +#define mmSPI_SHADER_USER_DATA_VS_4 0x2C50 +#define mmSPI_SHADER_USER_DATA_VS_5 0x2C51 +#define mmSPI_SHADER_USER_DATA_VS_6 0x2C52 +#define mmSPI_SHADER_USER_DATA_VS_7 0x2C53 +#define mmSPI_SHADER_USER_DATA_VS_8 0x2C54 +#define mmSPI_SHADER_USER_DATA_VS_9 0x2C55 +#define mmSPI_SHADER_Z_FORMAT 0xA1C4 +#define mmSPI_SLAVE_DEBUG_BUSY 0x24D3 +#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24D9 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24DA +#define mmSPI_TMPRING_SIZE 0xA1BA +#define mmSPI_VS_OUT_CONFIG 0xA1B1 +#define mmSQ_ALU_CLK_CTRL 0x2360 +#define mmSQ_BUF_RSRC_WORD0 0x23C0 +#define mmSQ_BUF_RSRC_WORD1 0x23C1 +#define mmSQ_BUF_RSRC_WORD2 0x23C2 +#define mmSQ_BUF_RSRC_WORD3 0x23C3 +#define mmSQC_CACHES 0x2302 +#define mmSQC_CONFIG 0x2301 +#define mmSQ_CONFIG 0x2300 +#define mmSQC_SECDED_CNT 0x23A0 +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 +#define mmSQ_DED_CNT 0x23A2 +#define mmSQ_DED_INFO 0x23A3 +#define mmSQ_DS_0 0x237F +#define mmSQ_DS_1 0x237F +#define mmSQ_EXP_0 0x237F +#define mmSQ_EXP_1 0x237F +#define mmSQ_FIFO_SIZES 0x2305 +#define mmSQ_IMG_RSRC_WORD0 0x23C4 +#define mmSQ_IMG_RSRC_WORD1 0x23C5 +#define mmSQ_IMG_RSRC_WORD2 0x23C6 +#define mmSQ_IMG_RSRC_WORD3 0x23C7 +#define mmSQ_IMG_RSRC_WORD4 0x23C8 +#define mmSQ_IMG_RSRC_WORD5 0x23C9 +#define mmSQ_IMG_RSRC_WORD6 0x23CA +#define mmSQ_IMG_RSRC_WORD7 0x23CB +#define mmSQ_IMG_SAMP_WORD0 0x23CC +#define mmSQ_IMG_SAMP_WORD1 0x23CD +#define mmSQ_IMG_SAMP_WORD2 0x23CE +#define mmSQ_IMG_SAMP_WORD3 0x23CF +#define mmSQ_IND_CMD 0x237A +#define mmSQ_IND_DATA 0x2379 +#define mmSQ_IND_INDEX 0x2378 +#define mmSQ_INST 0x237F +#define mmSQ_LB_CTR_CTRL 0x2398 +#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 +#define mmSQ_LB_DATA_ALU_STALLS 0x239B +#define mmSQ_LB_DATA_TEX_CYCLES 0x239A +#define mmSQ_LB_DATA_TEX_STALLS 0x239C +#define mmSQ_MIMG_0 0x237F +#define mmSQ_MIMG_1 0x237F +#define mmSQ_MTBUF_0 0x237F +#define mmSQ_MTBUF_1 0x237F +#define mmSQ_MUBUF_0 0x237F +#define mmSQ_MUBUF_1 0x237F +#define mmSQ_PERFCOUNTER0_HI 0x2321 +#define mmSQ_PERFCOUNTER0_LO 0x2320 +#define mmSQ_PERFCOUNTER0_SELECT 0x2340 +#define mmSQ_PERFCOUNTER10_HI 0x2335 +#define mmSQ_PERFCOUNTER10_LO 0x2334 +#define mmSQ_PERFCOUNTER10_SELECT 0x234A +#define mmSQ_PERFCOUNTER11_HI 0x2337 +#define mmSQ_PERFCOUNTER11_LO 0x2336 +#define mmSQ_PERFCOUNTER11_SELECT 0x234B +#define mmSQ_PERFCOUNTER12_HI 0x2339 +#define mmSQ_PERFCOUNTER12_LO 0x2338 +#define mmSQ_PERFCOUNTER12_SELECT 0x234C +#define mmSQ_PERFCOUNTER13_HI 0x233B +#define mmSQ_PERFCOUNTER13_LO 0x233A +#define mmSQ_PERFCOUNTER13_SELECT 0x234D +#define mmSQ_PERFCOUNTER14_HI 0x233D +#define mmSQ_PERFCOUNTER14_LO 0x233C +#define mmSQ_PERFCOUNTER14_SELECT 0x234E +#define mmSQ_PERFCOUNTER15_HI 0x233F +#define mmSQ_PERFCOUNTER15_LO 0x233E +#define mmSQ_PERFCOUNTER15_SELECT 0x234F +#define mmSQ_PERFCOUNTER1_HI 0x2323 +#define mmSQ_PERFCOUNTER1_LO 0x2322 +#define mmSQ_PERFCOUNTER1_SELECT 0x2341 +#define mmSQ_PERFCOUNTER2_HI 0x2325 +#define mmSQ_PERFCOUNTER2_LO 0x2324 +#define mmSQ_PERFCOUNTER2_SELECT 0x2342 +#define mmSQ_PERFCOUNTER3_HI 0x2327 +#define mmSQ_PERFCOUNTER3_LO 0x2326 +#define mmSQ_PERFCOUNTER3_SELECT 0x2343 +#define mmSQ_PERFCOUNTER4_HI 0x2329 +#define mmSQ_PERFCOUNTER4_LO 0x2328 +#define mmSQ_PERFCOUNTER4_SELECT 0x2344 +#define mmSQ_PERFCOUNTER5_HI 0x232B +#define mmSQ_PERFCOUNTER5_LO 0x232A +#define mmSQ_PERFCOUNTER5_SELECT 0x2345 +#define mmSQ_PERFCOUNTER6_HI 0x232D +#define mmSQ_PERFCOUNTER6_LO 0x232C +#define mmSQ_PERFCOUNTER6_SELECT 0x2346 +#define mmSQ_PERFCOUNTER7_HI 0x232F +#define mmSQ_PERFCOUNTER7_LO 0x232E +#define mmSQ_PERFCOUNTER7_SELECT 0x2347 +#define mmSQ_PERFCOUNTER8_HI 0x2331 +#define mmSQ_PERFCOUNTER8_LO 0x2330 +#define mmSQ_PERFCOUNTER8_SELECT 0x2348 +#define mmSQ_PERFCOUNTER9_HI 0x2333 +#define mmSQ_PERFCOUNTER9_LO 0x2332 +#define mmSQ_PERFCOUNTER9_SELECT 0x2349 +#define mmSQ_PERFCOUNTER_CTRL 0x2306 +#define mmSQ_POWER_THROTTLE 0x2396 +#define mmSQ_POWER_THROTTLE2 0x2397 +#define mmSQ_RANDOM_WAVE_PRI 0x2303 +#define mmSQ_REG_CREDITS 0x2304 +#define mmSQ_SEC_CNT 0x23A1 +#define mmSQ_SMRD 0x237F +#define mmSQ_SOP1 0x237F +#define mmSQ_SOP2 0x237F +#define mmSQ_SOPC 0x237F +#define mmSQ_SOPK 0x237F +#define mmSQ_SOPP 0x237F +#define mmSQ_TEX_CLK_CTRL 0x2361 +#define mmSQ_THREAD_TRACE_BASE 0x2380 +#define mmSQ_THREAD_TRACE_CNTR 0x2390 +#define mmSQ_THREAD_TRACE_CTRL 0x238F +#define mmSQ_THREAD_TRACE_HIWATER 0x2392 +#define mmSQ_THREAD_TRACE_MASK 0x2382 +#define mmSQ_THREAD_TRACE_MODE 0x238E +#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384 +#define mmSQ_THREAD_TRACE_SIZE 0x2381 +#define mmSQ_THREAD_TRACE_STATUS 0x238D +#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383 +#define mmSQ_THREAD_TRACE_USERDATA_0 0x2388 +#define mmSQ_THREAD_TRACE_USERDATA_1 0x2389 +#define mmSQ_THREAD_TRACE_USERDATA_2 0x238A +#define mmSQ_THREAD_TRACE_USERDATA_3 0x238B +#define mmSQ_THREAD_TRACE_WORD_CMN 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_MISC 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIME 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23B1 +#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23B0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23B0 +#define mmSQ_THREAD_TRACE_WPTR 0x238C +#define mmSQ_TIME_HI 0x237C +#define mmSQ_TIME_LO 0x237D +#define mmSQ_VINTRP 0x237F +#define mmSQ_VOP1 0x237F +#define mmSQ_VOP2 0x237F +#define mmSQ_VOP3_0 0x237F +#define mmSQ_VOP3_0_SDST_ENC 0x237F +#define mmSQ_VOP3_1 0x237F +#define mmSQ_VOPC 0x237F +#define mmSX_DEBUG_1 0x2418 +#define mmSX_DEBUG_BUSY 0x2414 +#define mmSX_DEBUG_BUSY_2 0x2415 +#define mmSX_DEBUG_BUSY_3 0x2416 +#define mmSX_DEBUG_BUSY_4 0x2417 +#define mmSX_PERFCOUNTER0_HI 0x2421 +#define mmSX_PERFCOUNTER0_LO 0x2420 +#define mmSX_PERFCOUNTER0_SELECT 0x241C +#define mmSX_PERFCOUNTER1_HI 0x2423 +#define mmSX_PERFCOUNTER1_LO 0x2422 +#define mmSX_PERFCOUNTER1_SELECT 0x241D +#define mmSX_PERFCOUNTER2_HI 0x2425 +#define mmSX_PERFCOUNTER2_LO 0x2424 +#define mmSX_PERFCOUNTER2_SELECT 0x241E +#define mmSX_PERFCOUNTER3_HI 0x2427 +#define mmSX_PERFCOUNTER3_LO 0x2426 +#define mmSX_PERFCOUNTER3_SELECT 0x241F +#define mmTA_BC_BASE_ADDR 0xA020 +#define mmTA_CGTT_CTRL 0x2544 +#define mmTA_CNTL 0x2541 +#define mmTA_CNTL_AUX 0x2542 +#define mmTA_CS_BC_BASE_ADDR 0x2543 +#define mmTA_DEBUG_DATA 0x254D +#define mmTA_DEBUG_INDEX 0x254C +#define mmTA_PERFCOUNTER0_HI 0x2556 +#define mmTA_PERFCOUNTER0_LO 0x2555 +#define mmTA_PERFCOUNTER0_SELECT 0x2554 +#define mmTA_PERFCOUNTER1_HI 0x2562 +#define mmTA_PERFCOUNTER1_LO 0x2561 +#define mmTA_PERFCOUNTER1_SELECT 0x2560 +#define mmTA_SCRATCH 0x2564 +#define mmTA_STATUS 0x2548 +#define mmTCA_CGTT_SCLK_CTRL 0x2BC1 +#define mmTCA_CTRL 0x2BC0 +#define mmTCA_PERFCOUNTER0_HI 0x2BD2 +#define mmTCA_PERFCOUNTER0_LO 0x2BD1 +#define mmTCA_PERFCOUNTER0_SELECT 0x2BD0 +#define mmTCA_PERFCOUNTER1_HI 0x2BD5 +#define mmTCA_PERFCOUNTER1_LO 0x2BD4 +#define mmTCA_PERFCOUNTER1_SELECT 0x2BD3 +#define mmTCA_PERFCOUNTER2_HI 0x2BD8 +#define mmTCA_PERFCOUNTER2_LO 0x2BD7 +#define mmTCA_PERFCOUNTER2_SELECT 0x2BD6 +#define mmTCA_PERFCOUNTER3_HI 0x2BDB +#define mmTCA_PERFCOUNTER3_LO 0x2BDA +#define mmTCA_PERFCOUNTER3_SELECT 0x2BD9 +#define mmTCC_CGTT_SCLK_CTRL 0x2B81 +#define mmTCC_CTRL 0x2B80 +#define mmTCC_EDC_COUNTER 0x2B82 +#define mmTCC_PERFCOUNTER0_HI 0x2B92 +#define mmTCC_PERFCOUNTER0_LO 0x2B91 +#define mmTCC_PERFCOUNTER0_SELECT 0x2B90 +#define mmTCC_PERFCOUNTER1_HI 0x2B95 +#define mmTCC_PERFCOUNTER1_LO 0x2B94 +#define mmTCC_PERFCOUNTER1_SELECT 0x2B93 +#define mmTCC_PERFCOUNTER2_HI 0x2B98 +#define mmTCC_PERFCOUNTER2_LO 0x2B97 +#define mmTCC_PERFCOUNTER2_SELECT 0x2B96 +#define mmTCC_PERFCOUNTER3_HI 0x2B9B +#define mmTCC_PERFCOUNTER3_LO 0x2B9A +#define mmTCC_PERFCOUNTER3_SELECT 0x2B99 +#define mmTCI_CNTL_1 0x2B62 +#define mmTCI_CNTL_2 0x2B63 +#define mmTCI_STATUS 0x2B61 +#define mmTCP_ADDR_CONFIG 0x2B05 +#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2B16 +#define mmTCP_CHAN_STEER_HI 0x2B04 +#define mmTCP_CHAN_STEER_LO 0x2B03 +#define mmTCP_CNTL 0x2B02 +#define mmTCP_CREDIT 0x2B06 +#define mmTCP_EDC_COUNTER 0x2B17 +#define mmTCP_INVALIDATE 0x2B00 +#define mmTCP_PERFCOUNTER0_HI 0x2B0A +#define mmTCP_PERFCOUNTER0_LO 0x2B0B +#define mmTCP_PERFCOUNTER0_SELECT 0x2B09 +#define mmTCP_PERFCOUNTER1_HI 0x2B0D +#define mmTCP_PERFCOUNTER1_LO 0x2B0E +#define mmTCP_PERFCOUNTER1_SELECT 0x2B0C +#define mmTCP_PERFCOUNTER2_HI 0x2B10 +#define mmTCP_PERFCOUNTER2_LO 0x2B11 +#define mmTCP_PERFCOUNTER2_SELECT 0x2B0F +#define mmTCP_PERFCOUNTER3_HI 0x2B13 +#define mmTCP_PERFCOUNTER3_LO 0x2B14 +#define mmTCP_PERFCOUNTER3_SELECT 0x2B12 +#define mmTCP_STATUS 0x2B01 +#define mmTD_CGTT_CTRL 0x2527 +#define mmTD_CNTL 0x2525 +#define mmTD_DEBUG_DATA 0x2529 +#define mmTD_DEBUG_INDEX 0x2528 +#define mmTD_PERFCOUNTER0_HI 0x252E +#define mmTD_PERFCOUNTER0_LO 0x252D +#define mmTD_PERFCOUNTER0_SELECT 0x252C +#define mmTD_SCRATCH 0x2530 +#define mmTD_STATUS 0x2526 +#define mmUSER_SQC_BANK_DISABLE 0x2308 +#define mmVGT_CACHE_INVALIDATION 0x2231 +#define mmVGT_CNTL_STATUS 0x223C +#define mmVGT_DEBUG_CNTL 0x2238 +#define mmVGT_DEBUG_DATA 0x2239 +#define mmVGT_DMA_BASE 0xA1FA +#define mmVGT_DMA_BASE_HI 0xA1F9 +#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222D +#define mmVGT_DMA_INDEX_TYPE 0xA29F +#define mmVGT_DMA_MAX_SIZE 0xA29E +#define mmVGT_DMA_NUM_INSTANCES 0xA2A2 +#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222E +#define mmVGT_DMA_SIZE 0xA29D +#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222F +#define mmVGT_DRAW_INITIATOR 0xA1FC +#define mmVGT_ENHANCE 0xA294 +#define mmVGT_ESGS_RING_ITEMSIZE 0xA2AB +#define mmVGT_ESGS_RING_SIZE 0x2232 +#define mmVGT_ES_PER_GS 0xA296 +#define mmVGT_EVENT_ADDRESS_REG 0xA1FE +#define mmVGT_EVENT_INITIATOR 0xA2A4 +#define mmVGT_FIFO_DEPTHS 0x2234 +#define mmVGT_GROUP_DECR 0xA28B +#define mmVGT_GROUP_FIRST_DECR 0xA28A +#define mmVGT_GROUP_PRIM_TYPE 0xA289 +#define mmVGT_GROUP_VECT_0_CNTL 0xA28C +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xA28E +#define mmVGT_GROUP_VECT_1_CNTL 0xA28D +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xA28F +#define mmVGT_GS_INSTANCE_CNT 0xA2E4 +#define mmVGT_GS_MAX_VERT_OUT 0xA2CE +#define mmVGT_GS_MODE 0xA290 +#define mmVGT_GS_OUT_PRIM_TYPE 0xA29B +#define mmVGT_GS_PER_ES 0xA295 +#define mmVGT_GS_PER_VS 0xA297 +#define mmVGT_GS_VERTEX_REUSE 0x2235 +#define mmVGT_GS_VERT_ITEMSIZE 0xA2D7 +#define mmVGT_GS_VERT_ITEMSIZE_1 0xA2D8 +#define mmVGT_GS_VERT_ITEMSIZE_2 0xA2D9 +#define mmVGT_GS_VERT_ITEMSIZE_3 0xA2DA +#define mmVGT_GSVS_RING_ITEMSIZE 0xA2AC +#define mmVGT_GSVS_RING_OFFSET_1 0xA298 +#define mmVGT_GSVS_RING_OFFSET_2 0xA299 +#define mmVGT_GSVS_RING_OFFSET_3 0xA29A +#define mmVGT_GSVS_RING_SIZE 0x2233 +#define mmVGT_HOS_CNTL 0xA285 +#define mmVGT_HOS_MAX_TESS_LEVEL 0xA286 +#define mmVGT_HOS_MIN_TESS_LEVEL 0xA287 +#define mmVGT_HOS_REUSE_DEPTH 0xA288 +#define mmVGT_HS_OFFCHIP_PARAM 0x226C +#define mmVGT_IMMED_DATA 0xA1FD +#define mmVGT_INDEX_TYPE 0x2257 +#define mmVGT_INDX_OFFSET 0xA102 +#define mmVGT_INSTANCE_STEP_RATE_0 0xA2A8 +#define mmVGT_INSTANCE_STEP_RATE_1 0xA2A9 +#define mmVGT_LAST_COPY_STATE 0x2230 +#define mmVGT_LS_HS_CONFIG 0xA2D6 +#define mmVGT_MAX_VTX_INDX 0xA100 +#define mmVGT_MC_LAT_CNTL 0x2236 +#define mmVGT_MIN_VTX_INDX 0xA101 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xA2A5 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xA103 +#define mmVGT_NUM_INDICES 0x225C +#define mmVGT_NUM_INSTANCES 0x225D +#define mmVGT_OUT_DEALLOC_CNTL 0xA317 +#define mmVGT_OUTPUT_PATH_CNTL 0xA284 +#define mmVGT_PERFCOUNTER0_HI 0x224D +#define mmVGT_PERFCOUNTER0_LO 0x224C +#define mmVGT_PERFCOUNTER0_SELECT 0x2248 +#define mmVGT_PERFCOUNTER1_HI 0x224F +#define mmVGT_PERFCOUNTER1_LO 0x224E +#define mmVGT_PERFCOUNTER1_SELECT 0x2249 +#define mmVGT_PERFCOUNTER2_HI 0x2251 +#define mmVGT_PERFCOUNTER2_LO 0x2250 +#define mmVGT_PERFCOUNTER2_SELECT 0x224A +#define mmVGT_PERFCOUNTER3_HI 0x2253 +#define mmVGT_PERFCOUNTER3_LO 0x2252 +#define mmVGT_PERFCOUNTER3_SELECT 0x224B +#define mmVGT_PERFCOUNTER_SEID_MASK 0x2247 +#define mmVGT_PRIMITIVEID_EN 0xA2A1 +#define mmVGT_PRIMITIVEID_RESET 0xA2A3 +#define mmVGT_PRIMITIVE_TYPE 0x2256 +#define mmVGT_REUSE_OFF 0xA2AD +#define mmVGT_SHADER_STAGES_EN 0xA2D5 +#define mmVGT_STRMOUT_BUFFER_CONFIG 0xA2E6 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x2258 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x2259 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x225A +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x225B +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xA2B7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xA2BB +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xA2BF +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xA2C3 +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xA2B4 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xA2B8 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xA2BC +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xA2C0 +#define mmVGT_STRMOUT_CONFIG 0xA2E5 +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xA2CB +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xA2CA +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xA2CC +#define mmVGT_STRMOUT_VTX_STRIDE_0 0xA2B5 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0xA2B9 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0xA2BD +#define mmVGT_STRMOUT_VTX_STRIDE_3 0xA2C1 +#define mmVGT_SYS_CONFIG 0x2263 +#define mmVGT_TF_MEMORY_BASE 0x226E +#define mmVGT_TF_PARAM 0xA2DB +#define mmVGT_TF_RING_SIZE 0x2262 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xA316 +#define mmVGT_VTX_CNT_EN 0xA2AE +#define mmVGT_VTX_VECT_EJECT_REG 0x222C + +/* manually added from old sid.h */ +#define mmCB_PERFCOUNTER0_SELECT0 0x2688 +#define mmCB_PERFCOUNTER1_SELECT0 0x268A +#define mmCB_PERFCOUNTER1_SELECT1 0x268B +#define mmCB_PERFCOUNTER2_SELECT0 0x268C +#define mmCB_PERFCOUNTER2_SELECT1 0x268D +#define mmCB_PERFCOUNTER3_SELECT0 0x268E +#define mmCB_PERFCOUNTER3_SELECT1 0x268F +#define mmCP_COHER_CNTL2 0x217A +#define mmCP_DEBUG 0x307F +#define mmRLC_SERDES_MASTER_BUSY_0 0x3119 +#define mmRLC_SERDES_MASTER_BUSY_1 0x311A +#define mmRLC_RL_BASE 0x30C1 +#define mmRLC_RL_SIZE 0x30C2 +#define mmRLC_UCODE_ADDR 0x30CB +#define mmRLC_UCODE_DATA 0x30CC +#define mmRLC_GCPM_GENERAL_3 0x311E +#define mmRLC_SERDES_WR_MASTER_MASK_0 0x3115 +#define mmRLC_SERDES_WR_MASTER_MASK_1 0x3116 +#define mmRLC_TTOP_D 0x3105 +#define mmRLC_CLEAR_STATE_RESTORE_BASE 0x30C8 +#define mmRLC_PG_AO_CU_MASK 0x310B +#define mmSPI_STATIC_THREAD_MGMT_3 0x243A + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h new file mode 100644 index 000000000000..b5e634749665 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h @@ -0,0 +1,12821 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_6_0_SH_MASK_H +#define GFX_6_0_SH_MASK_H + +#define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL +#define BCI_DEBUG_READ__DATA__SHIFT 0x00000000 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x0000001e +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffffL +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffffL +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffffL +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 +#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffffL +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005 +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011 +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f +#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L +#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffffL +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000 +#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL +#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffffL +#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x00000000 +#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x00000010 +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0x0000000f +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014 +#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L +#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013 +#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L +#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0x0000000e +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0x0000000b +#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L +#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x00000000 +#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L +#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0x0000000d +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a +#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007cL +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x00000002 +#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x00000007 +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x00000008 +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x00000012 +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x00000011 +#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L +#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014 +#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007ffL +#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003fffffL +#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x00000000 +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007ffL +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x00000000 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x00000003 +#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L +#define CB_COLOR_CONTROL__MODE__SHIFT 0x00000004 +#define CB_COLOR_CONTROL__ROP3_MASK 0x00ff0000L +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x00000010 +#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x00000008L +#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x00000003 +#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x00000020L +#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x00000005 +#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x00000010L +#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x00000004 +#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x00000200L +#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x00000009 +#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x00000100L +#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x00000008 +#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x00000080L +#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x00000007 +#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x00000400L +#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0x0000000a +#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x00000040L +#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x00000006 +#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x00000002L +#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x00000001 +#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x0007f800L +#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0x0000000b +#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x00000001L +#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x00000000 +#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x00000004L +#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x00000002 +#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x00000010L +#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x00000004 +#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x00000008L +#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x00000003 +#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x00000100L +#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x00000008 +#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x00000002L +#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x00000001 +#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x00000004L +#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x00000002 +#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x00000020L +#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x00000005 +#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x00000040L +#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x00000006 +#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x00000080L +#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x00000007 +#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x00000001L +#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x00000000 +#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x00000010L +#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x00000004 +#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x00000040L +#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x00000006 +#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x00000100L +#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x00000008 +#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x00000020L +#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x00000005 +#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x00000008L +#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x00000003 +#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x00000004L +#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x00000002 +#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x00000003L +#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x00000000 +#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x00000080L +#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x00000007 +#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x00100000L +#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x00000014 +#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x00400000L +#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x00000016 +#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x00200000L +#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x00000015 +#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x000003c0L +#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x00000006 +#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0x000f0000L +#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x00000010 +#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x0000003fL +#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x00000000 +#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0x0000fc00L +#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0x0000000a +#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x00000008L +#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x00000003 +#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x00000004L +#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x00000002 +#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x00000001L +#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x00000000 +#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x00000020L +#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x00000005 +#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x00000002L +#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x00000001 +#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x00000010L +#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x00000004 +#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x00000080L +#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x00000007 +#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x00000040L +#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x00000006 +#define CB_DEBUG_BUS_18__NOT_USED_MASK 0x00ffffffL +#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x00000000 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001f800L +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0000000b +#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000L +#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x0000001a +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001fL +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x00000000 +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03fe0000L +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x00000011 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007e0L +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x00000005 +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000ffL +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x00000000 +#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff800000L +#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x00000017 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007f8000L +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0x0000000f +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007f00L +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x00000008 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x00000000 +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x00000010 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000f000L +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0x0000000c +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000fL +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x00000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000019 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000001a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000018 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x00000015 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x0000001b +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x0000001e +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x00000016 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x00000012 +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x0000001f +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x00000017 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003c0L +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x00000006 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x00000014 +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x00000013 +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x0000001d +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x0000001c +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001ffL +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007fc00L +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000fL +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x00000000 +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000f0L +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x00000004 +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000f00L +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x00000008 +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000f000L +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0x0000000c +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000f0000L +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x00000010 +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00f00000L +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x00000014 +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0f000000L +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x00000018 +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000L +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x0000001c +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000fL +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x00000000 +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000f0L +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x00000004 +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000f00L +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x00000008 +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000f000L +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0x0000000c +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000f0000L +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x00000010 +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00f00000L +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x00000014 +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0f000000L +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x00000018 +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000L +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x0000001c +#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L +#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001 +#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L +#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 +#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000fL +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x00000000 +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000f0L +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x00000004 +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000f00L +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x00000008 +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000f000L +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0x0000000c +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000f0000L +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x00000010 +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00f00000L +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x00000014 +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0f000000L +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x00000018 +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000L +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x0000001c +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0x0000000c +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x00000014 +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000f00L +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x00000008 +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000f0000L +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x00000010 +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010 +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014 +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018 +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c +#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001f00L +#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x00000008 +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x00000000 +#define CGTS_RD_REG__READ_DATA_MASK 0x00003fffL +#define CGTS_RD_REG__READ_DATA__SHIFT 0x00000000 +#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L +#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x00000010 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L +#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x00000016 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L +#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0x0000000c +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000ff0L +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x00000004 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x00000017 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000L +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x00000018 +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000fL +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x00000000 +#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L +#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x00000015 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x00000014 +#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L +#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x00000011 +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010 +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x0000001a +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x00000019 +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x00000018 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x00fff000L +#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0x0000000c +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001d +#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L +#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x0000001e +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0000001f +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x0000001d +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x02000000L +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x00000019 +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x04000000L +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x0000001a +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x0000001a +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x0000001e +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x0000001d +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x0000001c +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x0000001b +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000fL +#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x00000000 +#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x00fff000L +#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0x0000000c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x0000001d +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019 +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0x000000ffL +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x08000000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00200000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00400000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x00000600L +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00100000L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x01000000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x02000000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x04000000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0x000000ffL +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x00000700L +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000L +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000L +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x000e0000L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00100000L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x0001c000L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00003800L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x01000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x0c000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x02000000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00800000L +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00400000L +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00200000L +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x00000007L +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x04000000L +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000L +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x00100000L +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x00200000L +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x08000000L +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000L +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x01000000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x00400000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x00800000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x02000000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0x000f0000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x00000038L +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00800000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x07000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0x000fc000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00700000L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00800000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x07000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0x000fc000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00700000L +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00800000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x07000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0x000fc000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00700000L +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00800000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x07000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0x000fc000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00700000L +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00f00000L +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x00000008L +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x08000000L +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000L +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000f0000L +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x00000004L +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x04000000L +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000L +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x00000002L +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x02000000L +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000L +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x01000000L +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000L +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0x000000ffL +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x00300000L +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000L +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000L +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000L +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x04000000L +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x08000000L +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x01000000L +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x02000000L +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x00003000L +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x00008000L +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x001e0000L +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x00000020L +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x00000007L +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000L +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000L +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000L +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x00800000L +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x00600000L +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x00000008L +#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x00000080L +#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x00000010L +#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x00080000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x00100000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x0003f000L +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x00040000L +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000L +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000001a +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x03e00000L +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x001f0000L +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000L +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000L +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x0000007fL +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x00000080L +#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000L +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000L +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x0000007fL +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x00000080L +#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000L +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000L +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x0000007fL +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x00000080L +#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000L +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x00001f00L +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f +#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000L +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000L +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x0000001e +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x0000007fL +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x00000080L +#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x0003e000L +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0x0000000d +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffffL +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x00000000 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffffL +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x00000000 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffffL +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x00000000 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffffL +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x00000000 +#define COMPUTE_DIM_X__SIZE_MASK 0xffffffffL +#define COMPUTE_DIM_X__SIZE__SHIFT 0x00000000 +#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffffL +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x00000000 +#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffffL +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x00000000 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x00000000 +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x00001000L +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0x0000000c +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x00000380L +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x00000007 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x00000002 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x00000003 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x00000004 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x00000006 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x00000001 +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0x0000000e +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0x0000000a +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x00000005 +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0x0000000b +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000ffffL +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x00000000 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000L +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x00000010 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000ffffL +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x00000000 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000L +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x00000010 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000ffffL +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x00000000 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000L +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x00000010 +#define COMPUTE_PGM_HI__DATA_MASK 0x000000ffL +#define COMPUTE_PGM_HI__DATA__SHIFT 0x00000000 +#define COMPUTE_PGM_HI__INST_ATC_MASK 0x00000100L +#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x00000008 +#define COMPUTE_PGM_LO__DATA_MASK 0xffffffffL +#define COMPUTE_PGM_LO__DATA__SHIFT 0x00000000 +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x00000018 +#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L +#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x00000019 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L +#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x00000016 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x00000015 +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000ff000L +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0x0000000c +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x00000017 +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000c00L +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0x0000000a +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x00000014 +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003c0L +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x00000006 +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003fL +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x00000000 +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0x0000000d +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x00000018 +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00ff8000L +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0x0000000f +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x00000000 +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x00000007 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x00000008 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x00000009 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0x0000000a +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0x0000000b +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x00000006 +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003eL +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x00000001 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x00000018 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x00000017 +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003f0000L +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x00000010 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x00000016 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000f000L +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0x0000000c +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x0000003fL +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x00000000 +#define COMPUTE_START_X__START_MASK 0xffffffffL +#define COMPUTE_START_X__START__SHIFT 0x00000000 +#define COMPUTE_START_Y__START_MASK 0xffffffffL +#define COMPUTE_START_Y__START__SHIFT 0x00000000 +#define COMPUTE_START_Z__START_MASK 0xffffffffL +#define COMPUTE_START_Z__START__SHIFT 0x00000000 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000ffffL +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x00000000 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000L +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x00000010 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000ffffL +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x00000000 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000L +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x00000010 +#define COMPUTE_TBA_HI__DATA_MASK 0x000000ffL +#define COMPUTE_TBA_HI__DATA__SHIFT 0x00000000 +#define COMPUTE_TBA_LO__DATA_MASK 0xffffffffL +#define COMPUTE_TBA_LO__DATA__SHIFT 0x00000000 +#define COMPUTE_TMA_HI__DATA_MASK 0x000000ffL +#define COMPUTE_TMA_HI__DATA__SHIFT 0x00000000 +#define COMPUTE_TMA_LO__DATA_MASK 0xffffffffL +#define COMPUTE_TMA_LO__DATA__SHIFT 0x00000000 +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000fffL +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x00000000 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffffL +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x00000000 +#define COMPUTE_VMID__DATA_MASK 0x0000000fL +#define COMPUTE_VMID__DATA__SHIFT 0x00000000 +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000L +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x0000001d +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x00000010 +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x000000ffL +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x00000000 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffcL +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x00000002 +#define CP_APPEND_DATA__DATA_MASK 0xffffffffL +#define CP_APPEND_DATA__DATA__SHIFT 0x00000000 +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffffL +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x00000000 +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffffL +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x00000000 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000 +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x00000016 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x00000006 +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x00000012 +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0x0000000f +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x00000011 +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x00000008 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x00000007 +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x00000014 +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x00000015 +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0x0000000a +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x00000009 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000 +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0x0000000c +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0x0000000d +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0x0000000e +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x00000013 +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffffL +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x00000000 +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x000000ffL +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x00000000 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0L +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x00000005 +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000fffL +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x00000000 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07ff0000L +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x00000010 +#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007ffL +#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x00000000 +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007ffL +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x00000000 +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003ffL +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03ff0000L +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010 +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003ffL +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03ff0000L +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x00000010 +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003ffL +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010 +#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL +#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 +#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL +#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007ffL +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0x0000000c +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0ff00000L +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x00000014 +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000ffL +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x00000000 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x0000001c +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x00000008 +#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL +#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000 +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000ffL +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x00000000 +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x00000006 +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x00000007 +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x00000008 +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x00000009 +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0x0000000a +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0x0000000b +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0x0000000c +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0x0000000d +#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L +#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x00000019 +#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L +#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x0000001a +#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L +#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0x0000000e +#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L +#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x00000000 +#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L +#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x00000001 +#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L +#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x00000013 +#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L +#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x00000015 +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x0000001d +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x0000001b +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x0000001c +#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L +#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x00000017 +#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L +#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x00000016 +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0x0000000f +#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x00010000L +#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x00000010 +#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L +#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x00000012 +#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL +#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000 +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000ffL +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x00000000 +#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003fL +#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x00000000 +#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000ffL +#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x00000000 +#define CP_COHER_STATUS__MEID_MASK 0x03000000L +#define CP_COHER_STATUS__MEID__SHIFT 0x00000018 +#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000L +#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x0000001e +#define CP_COHER_STATUS__STATUS_MASK 0x80000000L +#define CP_COHER_STATUS__STATUS__SHIFT 0x0000001f +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0x0000000fL +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x00000000 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x00003f00L +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x00000008 +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0x0000000fL +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x00000000 +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000f0000L +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x00000010 +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x00000004 +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000L +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x0000001e +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x0000001c +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x0000001d +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x001fffffL +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x00000000 +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x0000001d +#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x0000001b +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x00200000L +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x00000015 +#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x03000000L +#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x00000018 +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x0000001e +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x0000001c +#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x0000001a +#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0x00c00000L +#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x00000016 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffffL +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x00000000 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x001fffffL +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x00000000 +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x0000001d +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x0000001b +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x00200000L +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x00000015 +#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x03000000L +#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x00000018 +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x0000001e +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x0000001c +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x0000001a +#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0x00c00000L +#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x00000016 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffffL +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x00000000 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000 +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03ffffffL +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x00000000 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x0000001c +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x00000000 +#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0x000000f0L +#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x00000004 +#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x00000000 +#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0x000000f0L +#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x00000004 +#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x00003c00L +#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0x0000000a +#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0x000f0000L +#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x00000010 +#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x00000000 +#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0x000000f0L +#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x00000004 +#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x00003c00L +#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0x0000000a +#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0x000f0000L +#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x00000010 +#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x00000000 +#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0x000000f0L +#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x00000004 +#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x00003c00L +#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0x0000000a +#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0x000f0000L +#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x00000010 +#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x00003c00L +#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0x0000000a +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000f0000L +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x00000010 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x00000000 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffcL +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x00000002 +#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x00000003L +#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x00000000 +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0x0000ffffL +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x00000000 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000L +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x0000001d +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x00000010 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x00000018 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffffL +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x00000000 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffffL +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x00000000 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffffL +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x00000000 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffffL +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x00000000 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003f00L +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x00000008 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003f0000L +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x00000010 +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000fffffL +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x00000000 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000fffffL +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x00000000 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000fffffL +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x00000000 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000fffffL +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x00000000 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x0000001f +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x0000001e +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x0000001d +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x0000001f +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x0000001e +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x0000001d +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014 +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x0000001f +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x0000001e +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x0000001d +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x00000017 +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x00000013 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x00000014 +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x00000016 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017 +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x0000001f +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x0000001f +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x0000001f +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014 +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x0000001f +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x00000016 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011 +#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x0000001fL +#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x00000000 +#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L +#define CP_ME_CNTL__CE_HALT__SHIFT 0x00000018 +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x00000004 +#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L +#define CP_ME_CNTL__CE_STEP__SHIFT 0x00000019 +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x00000008 +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L +#define CP_ME_CNTL__ME_STEP__SHIFT 0x0000001d +#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x0000001a +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x00000006 +#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x0000001b +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffffL +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x00000000 +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x000000ffL +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x00000000 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffcL +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x00000002 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x00000003L +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x00000000 +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x000000ffL +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x00000000 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffcL +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x00000002 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x00000003L +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x00000000 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffffL +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x00000000 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffffL +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x00000000 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x00000001 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x00000000 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00ff0000L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x00000010 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000ff00L +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x00000008 +#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L +#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 +#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL +#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 +#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x00000001L +#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x00000000 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003ffL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000ffL +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x00000000 +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000ff00L +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x00000008 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00000fffL +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00000fffL +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x00000000 +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffffL +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x00000000 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffffL +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x00000000 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffffL +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000f0L +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x00000004 +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x0000001f +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffffL +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x00000000 +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x00000001L +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x00000000 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x00000001 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x00000000 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x00000018 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010 +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0x0000000f +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffffffffL +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x00000000 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffcL +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x00000002 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x00000003L +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x00000000 +#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x00000001L +#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x00000008 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000ffL +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 +#define CP_RB0_BASE__RB_BASE_MASK 0xffffffffL +#define CP_RB0_BASE__RB_BASE__SHIFT 0x00000000 +#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018 +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f +#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x0000001a +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB0_RPTR__RB_RPTR_MASK 0x000fffffL +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x00000000 +#define CP_RB0_WPTR__RB_WPTR_MASK 0x000fffffL +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x00000000 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000ffL +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 +#define CP_RB1_BASE__RB_BASE_MASK 0xffffffffL +#define CP_RB1_BASE__RB_BASE__SHIFT 0x00000000 +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x00000018 +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f +#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x0000001a +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB1_RPTR__RB_RPTR_MASK 0x000fffffL +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x00000000 +#define CP_RB1_WPTR__RB_WPTR_MASK 0x000fffffL +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x00000000 +#define CP_RB2_BASE__RB_BASE_MASK 0xffffffffL +#define CP_RB2_BASE__RB_BASE__SHIFT 0x00000000 +#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x00000018 +#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L +#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 +#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f +#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x0000001a +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB2_RPTR__RB_RPTR_MASK 0x000fffffL +#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x00000000 +#define CP_RB2_WPTR__RB_WPTR_MASK 0x000fffffL +#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x00000000 +#define CP_RB_BASE__RB_BASE_MASK 0xffffffffL +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000000 +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x00000018 +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x00000014 +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016 +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f +#define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L +#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x0000001a +#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 +#define CP_RB_VMID__RB0_VMID_MASK 0x0000000fL +#define CP_RB_VMID__RB0_VMID__SHIFT 0x00000000 +#define CP_RB_VMID__RB1_VMID_MASK 0x00000f00L +#define CP_RB_VMID__RB1_VMID__SHIFT 0x00000008 +#define CP_RB_VMID__RB2_VMID_MASK 0x000f0000L +#define CP_RB_VMID__RB2_VMID__SHIFT 0x00000010 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0x000000ffL +#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x00000000 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x000000ffL +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000000 +#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffcL +#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x00000002 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffcL +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000002 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000ffffL +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x00000000 +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x00000000 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x00000000 +#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L +#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x00000000 +#define CP_RINGID__RINGID_MASK 0x00000003L +#define CP_RINGID__RINGID__SHIFT 0x00000000 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000L +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x00000018 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000ffL +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x00000000 +#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000ff00L +#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007ffL +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x00000000 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000ff00L +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x00000010 +#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000ffL +#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x00000000 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000L +#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x00000018 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07ff0000L +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007ffL +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03ff0000L +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x00000010 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003ffL +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03ff0000L +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x00000010 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003ffL +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03ff0000L +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x00000010 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffffL +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x00000000 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffffL +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x00000000 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffffL +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x00000000 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffffL +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x00000000 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffffL +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x00000000 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000ffL +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x00000000 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffffL +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x00000000 +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0x0000000a +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0x0000000b +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x0000000d +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x0000000c +#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x00004000L +#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0x0000000e +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0x0000000f +#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x00010000L +#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x00000010 +#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x00020000L +#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x00000011 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x00000000 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x00000004 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x00000002 +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x0000001c +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x0000001c +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x0000001b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x0000001a +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x00000017 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x00000018 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x00000019 +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x0000001c +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x00000019 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x0000001a +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x0000001d +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x0000001b +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x00000015 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x00000016 +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0x0000000b +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000010 +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0x0000000c +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0x0000000d +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0x0000000e +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x00000012 +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0x0000000f +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0x0000000a +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x00000009 +#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x00000040L +#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x00000006 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x00000005 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x00000014 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x00000013 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x00000001 +#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000007 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x00000002 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x00000004 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x00000008 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x00000018 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000011 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x00000017 +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x0000001f +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x0000001e +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000006 +#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000100L +#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000008 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x00000004 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x00000001 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x00000003 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x00000005 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000007 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0x0000000a +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0x0000000b +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x00000002 +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0x0000000c +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0x0000000d +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0x0000000e +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0x0000000f +#define CP_STAT__CE_BUSY_MASK 0x04000000L +#define CP_STAT__CE_BUSY__SHIFT 0x0000001a +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f +#define CP_STAT__CPC_CPG_BUSY_MASK 0x02000000L +#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x00000019 +#define CP_STAT__DC_BUSY_MASK 0x00002000L +#define CP_STAT__DC_BUSY__SHIFT 0x0000000d +#define CP_STAT__DMA_BUSY_MASK 0x00400000L +#define CP_STAT__DMA_BUSY__SHIFT 0x00000016 +#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x00000014 +#define CP_STAT__ME_BUSY_MASK 0x00020000L +#define CP_STAT__ME_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_BUSY_MASK 0x00010000L +#define CP_STAT__MEQ_BUSY__SHIFT 0x00000010 +#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x00000080L +#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x00000007 +#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x00000100L +#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x00000008 +#define CP_STAT__PFP_BUSY_MASK 0x00008000L +#define CP_STAT__PFP_BUSY__SHIFT 0x0000000f +#define CP_STAT__QUERY_BUSY_MASK 0x00040000L +#define CP_STAT__QUERY_BUSY__SHIFT 0x00000012 +#define CP_STAT__RCIU_BUSY_MASK 0x00800000L +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000017 +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x0000001d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x0000001e +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x0000001c +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0x0000000a +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0x0000000b +#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x00000009 +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0x0000000c +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x00000018 +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x00000013 +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x00000015 +#define CP_STAT__TCIU_BUSY_MASK 0x08000000L +#define CP_STAT__TCIU_BUSY__SHIFT 0x0000001b +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x000000ffL +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x00000000 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffcL +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x00000002 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001ffL +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x00000000 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003ffL +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x00000000 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000ffL +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x00000000 +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000ff00L +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x00000008 +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00ff0000L +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x00000010 +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffffffffL +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x00000000 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffcL +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x00000002 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x00000003L +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x00000000 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x00000000 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x00000000 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffffL +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x00000000 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffffL +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x00000000 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000ffffL +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x00000000 +#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000L +#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x00000010 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000ffffL +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x00000000 +#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000L +#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x00000010 +#define CP_VMID__VMID_MASK 0x0000000fL +#define CP_VMID__VMID__SHIFT 0x00000000 +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffffL +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x00000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000 +#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000008 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000c00L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000000a +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000000c +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000c000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000000e +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x00000010 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000ff0L +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x00000004 +#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000fL +#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x00000000 +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x00fff000L +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x0000000c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00f00000L +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x00000014 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x00000001 +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x00000004 +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000f0000L +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x00000010 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0f000000L +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x00000018 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000L +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x0000001c +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000f000L +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0x0000000c +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000f00L +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x00000008 +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x00000000 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001c00L +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0x0000000a +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000L +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x00000018 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003e0L +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x00000005 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001fL +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x00000000 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x00000000 +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003e00L +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x00000009 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x00000012 +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x00000010 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x00000011 +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x00000100L +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x00000008 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x00000020L +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x00000080L +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x00000007 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x00000005 +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x0000001d +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x00000013 +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x80000000L +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x0000001f +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x00000002 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x00000001 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0x0000000e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x0000001f +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x00000004 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x00000003 +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x00000040L +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x00000006 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x0000001c +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0x0000000f +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00020000L +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x00000011 +#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xfc000000L +#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x0000001a +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x00000019 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x00000018 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x00000004 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00200000L +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x00000015 +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00004000L +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0x0000000e +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00010000L +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0x00000010 +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00008000L +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0x0000000f +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00080000L +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x00000013 +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00002000L +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0x0000000d +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x0000001b +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x00000017 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000800L +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0x0000000b +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000400L +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x0000000a +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x00000007 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00100000L +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x00000014 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x00000003 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x00000008 +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x0000001d +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x0000001c +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x0000001a +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00001000L +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0x0000000c +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00400000L +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x00000016 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00800000L +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x00000017 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x00000005 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x00000006 +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x00000002 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00040000L +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x00000012 +#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffffc0L +#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x00000006 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000020L +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x00000005 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x00000001 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x00000000 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x00000002 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x00000001 +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0x0000000f +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0x0000000e +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x00000006 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x00000013 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000c00L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0x0000000a +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0x0000000c +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x00000008 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x00000007 +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x00000010 +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x00000000 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0f000000L +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x00000018 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x00000012 +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x0000001e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x0000001f +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x00000011 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x00000017 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x00000003 +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x00000002 +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x0000001d +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x00000004 +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x00000015 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x0000001c +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x00000016 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffffL +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x00000000 +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffffL +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x00000000 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x00000003 +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x0000001f +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x0000001e +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x00000008 +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x00000001 +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x00000004 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0x0000000fL +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x00000000 +#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0x000000f0L +#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x00000004 +#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x00018000L +#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0x0000000f +#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x00006000L +#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0x0000000d +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x00060000L +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x00000011 +#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x00180000L +#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x00000013 +#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x00001f00L +#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x00000008 +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x003ff800L +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0x0000000b +#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x000007ffL +#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x00000000 +#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x003fffffL +#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x00000000 +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00ffe000L +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x0000000d +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007ffL +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x00000000 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x00000019 +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x00000018 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x00000015 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0x0000000c +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x0000001b +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x00000010 +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x00000011 +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x00000012 +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x00000013 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x00000008 +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x00000000 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x00000018 +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x00000004 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x00000014 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000L +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x00000015 +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000fc00L +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x0000000a +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x0000001fL +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x00000000 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x000003e0L +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x00000005 +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001f0000L +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x00000010 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000ffL +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x00000000 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007f00L +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x00000008 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01ff8000L +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x0000000f +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000L +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x00000019 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007fL +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x00000000 +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x01e00000L +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x00000015 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003f80L +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x00000007 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x001fc000L +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x0000000e +#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000L +#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x00000019 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffffL +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x00000000 +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x00000010 +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x00000001 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x00000002 +#define DB_HTILE_SURFACE__LINEAR_MASK 0x00000001L +#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x00000000 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000fc00L +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0x0000000a +#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003f0L +#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x00000004 +#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L +#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x00000003 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0f000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0f000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00ff0000L +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x00000010 +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000L +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x00000018 +#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000ffL +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x00000000 +#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000ff00L +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x00000008 +#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffffL +#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x00000000 +#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffffL +#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x00000000 +#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffffL +#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x00000000 +#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x00000000 +#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffffL +#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x00000000 +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x00000007 +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000f00L +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x00000008 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000000 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x00000006 +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x00000002 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x00000004 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x00000001 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x00000005 +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x00000003 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x00000008 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x0000000a +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x00000007 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x00000017 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x00000009 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000006 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000005 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001c0000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x00000012 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0x0000000f +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0x0000000c +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x00000000 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001cL +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x00000002 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x00000016 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x00000015 +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0x0000000b +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x00000012 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x0000001a +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x00000010 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x00000008 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x00000007 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0x0000000a +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x0000000d +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000cL +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x00000002 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x00000004 +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x00000000 +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0x0000000f +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x00000006 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x0000001c +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0x0000000c +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x0000001e +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x0000001b +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x00000013 +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0x0000000b +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x0000001d +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x00000011 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03e00000L +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x00000015 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x00000009 +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x0000001f +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0x0000000b +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x0000000d +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x00000007 +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0x0000000c +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x00000009 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0x0000000a +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x00000006 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x00000008 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x00000002 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x00000001 +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x00000000 +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x00000004 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x00000000 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000ff000L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0x0000000c +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000ff0L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x00000004 +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x00000018 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x00000000 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000ff000L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0x0000000c +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000ff0L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x00000004 +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x00000018 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000ffL +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x00000000 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000f000L +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0x0000000c +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000fL +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x00000000 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00f00000L +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x00000014 +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000f00L +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x00000008 +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000f0000L +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x00000010 +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000f0L +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x00000004 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b +#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x00000000 +#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x00700000L +#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x00000014 +#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0x0000e000L +#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0x0000000d +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x0000001d +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffffL +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x00000000 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000L +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x00000018 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000ffL +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x00000000 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 +#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000L +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x00000018 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000ffL +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x00000000 +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffffL +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x00000000 +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x00000010 +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000c0000L +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x00000012 +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x00000000 +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000cL +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x00000002 +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x00000004 +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000c0L +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x00000006 +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x00000008 +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000c00L +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0x0000000a +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0x0000000c +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000c000L +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0x0000000e +#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L +#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x0000001e +#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L +#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x0000001f +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x07f00000L +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x00000014 +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007e0L +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x00000005 +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001fL +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x00000000 +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000f8000L +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x0000000f +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x08000000L +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x0000001b +#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L +#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0x0000000b +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000L +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x0000001c +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000L +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x0000001d +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b +#define DB_Z_INFO__FORMAT_MASK 0x00000003L +#define DB_Z_INFO__FORMAT__SHIFT 0x00000000 +#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000cL +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x00000002 +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L +#define DB_Z_INFO__READ_SIZE__SHIFT 0x0000001c +#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x00700000L +#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x00000014 +#define DB_Z_INFO__TILE_SPLIT_MASK 0x0000e000L +#define DB_Z_INFO__TILE_SPLIT__SHIFT 0x0000000d +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x0000001d +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x0000001f +#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffffL +#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x00000000 +#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffffL +#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x00000000 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffffL +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x00000000 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffffL +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x00000000 +#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL +#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000 +#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x0003ffffL +#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x00000000 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffffL +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x00000000 +#define GB_EDC_MODE__BYPASS_MASK 0x80000000L +#define GB_EDC_MODE__BYPASS__SHIFT 0x0000001f +#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L +#define GB_EDC_MODE__DED_MODE__SHIFT 0x00000014 +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00010000L +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x00000010 +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L +#define GB_EDC_MODE__PROP_FED__SHIFT 0x0000001d +#define GB_GPU_ID__GPU_ID_MASK 0x0000000fL +#define GB_GPU_ID__GPU_ID__SHIFT 0x00000000 +#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0x0000000b +#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003cL +#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x00000002 +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01c00000L +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x00000016 +#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007c0L +#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x00000006 +#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L +#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x00000019 +#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L +#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0x0000000b +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 +#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L +#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001 +#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L +#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010 +#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L +#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003 +#define GDS_ATOM_BASE__BASE_MASK 0x0000ffffL +#define GDS_ATOM_BASE__BASE__SHIFT 0x00000000 +#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000L +#define GDS_ATOM_BASE__UNUSED__SHIFT 0x00000010 +#define GDS_ATOM_CNTL__AINC_MASK 0x0000003fL +#define GDS_ATOM_CNTL__AINC__SHIFT 0x00000000 +#define GDS_ATOM_CNTL__DMODE_MASK 0x00000100L +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x00000008 +#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000c0L +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x00000006 +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00L +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x00000009 +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x00000000 +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffeL +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x00000001 +#define GDS_ATOM_DST__DST_MASK 0xffffffffL +#define GDS_ATOM_DST__DST__SHIFT 0x00000000 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000ffL +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x00000000 +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00L +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x00000008 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000ffL +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x00000000 +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00L +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x00000008 +#define GDS_ATOM_OP__OP_MASK 0x000000ffL +#define GDS_ATOM_OP__OP__SHIFT 0x00000000 +#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00L +#define GDS_ATOM_OP__UNUSED__SHIFT 0x00000008 +#define GDS_ATOM_READ0__DATA_MASK 0xffffffffL +#define GDS_ATOM_READ0__DATA__SHIFT 0x00000000 +#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffffL +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x00000000 +#define GDS_ATOM_READ1__DATA_MASK 0xffffffffL +#define GDS_ATOM_READ1__DATA__SHIFT 0x00000000 +#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffffL +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x00000000 +#define GDS_ATOM_SIZE__SIZE_MASK 0x0000ffffL +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x00000000 +#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000L +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x00000010 +#define GDS_ATOM_SRC0__DATA_MASK 0xffffffffL +#define GDS_ATOM_SRC0__DATA__SHIFT 0x00000000 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffffL +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x00000000 +#define GDS_ATOM_SRC1__DATA_MASK 0xffffffffL +#define GDS_ATOM_SRC1__DATA__SHIFT 0x00000000 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffffL +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x00000000 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x00000004 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x00000003 +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x00000006 +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x00000005 +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x00000000 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x00000001 +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x00000002 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L +#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x00000001 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L +#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x00000003 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L +#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x00000005 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L +#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x00000007 +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x0000001fL +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x00000000 +#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0L +#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x00000005 +#define GDS_DEBUG_DATA__DATA_MASK 0xffffffffL +#define GDS_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define GDS_DEBUG_REG0__buff_write_MASK 0x00020000L +#define GDS_DEBUG_REG0__buff_write__SHIFT 0x00000011 +#define GDS_DEBUG_REG0__cstate_MASK 0x0001e000L +#define GDS_DEBUG_REG0__cstate__SHIFT 0x0000000d +#define GDS_DEBUG_REG0__flush_request_MASK 0x00040000L +#define GDS_DEBUG_REG0__flush_request__SHIFT 0x00000012 +#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x00001000L +#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0x0000000c +#define GDS_DEBUG_REG0__spare1_MASK 0x00000001L +#define GDS_DEBUG_REG0__spare1__SHIFT 0x00000000 +#define GDS_DEBUG_REG0__spare_MASK 0xff000000L +#define GDS_DEBUG_REG0__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x00100000L +#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x00000014 +#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x00200000L +#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x00000015 +#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x00080000L +#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x00000013 +#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x00000040L +#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x00000006 +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0x00000f80L +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x00000007 +#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x00200000L +#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x00000015 +#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x00100000L +#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x00000014 +#define GDS_DEBUG_REG1__awaiting_data_MASK 0x00080000L +#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x00000013 +#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x00800000L +#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x00000017 +#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x00400000L +#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x00000016 +#define GDS_DEBUG_REG1__data_ready_MASK 0x00040000L +#define GDS_DEBUG_REG1__data_ready__SHIFT 0x00000012 +#define GDS_DEBUG_REG1__pixel_addr_MASK 0x0001fffcL +#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x00000002 +#define GDS_DEBUG_REG1__pixel_vld_MASK 0x00020000L +#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x00000011 +#define GDS_DEBUG_REG1__spare_MASK 0xff000000L +#define GDS_DEBUG_REG1__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG1__tag_hit_MASK 0x00000001L +#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x00000000 +#define GDS_DEBUG_REG1__tag_miss_MASK 0x00000002L +#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x00000001 +#define GDS_DEBUG_REG2__app_sel_MASK 0x000000f0L +#define GDS_DEBUG_REG2__app_sel__SHIFT 0x00000004 +#define GDS_DEBUG_REG2__cmd_write_MASK 0x00000008L +#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x00000003 +#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x00000002L +#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x00000001 +#define GDS_DEBUG_REG2__ds_full_MASK 0x00000001L +#define GDS_DEBUG_REG2__ds_full__SHIFT 0x00000000 +#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x00000004L +#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x00000002 +#define GDS_DEBUG_REG2__req_MASK 0x007fff00L +#define GDS_DEBUG_REG2__req__SHIFT 0x00000008 +#define GDS_DEBUG_REG2__spare_MASK 0xff000000L +#define GDS_DEBUG_REG2__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x00007800L +#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0x0000000b +#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x000007ffL +#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x00000000 +#define GDS_DEBUG_REG3__spare_MASK 0xff000000L +#define GDS_DEBUG_REG3__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG4__cmd_write_MASK 0x00020000L +#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x00000011 +#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x00010000L +#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x00000010 +#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x00002000L +#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0x0000000d +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x00008000L +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0x0000000f +#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x00001000L +#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0x0000000c +#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x00004000L +#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0x0000000e +#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x00000400L +#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0x0000000a +#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x00000800L +#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0x0000000b +#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x00000200L +#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x00000009 +#define GDS_DEBUG_REG4__cur_reso_MASK 0x000001f8L +#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x00000003 +#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x00080000L +#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x00000013 +#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x00040000L +#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x00000012 +#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x00200000L +#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x00000015 +#define GDS_DEBUG_REG4__gws_busy_MASK 0x00000001L +#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x00000000 +#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x00000004L +#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x00000002 +#define GDS_DEBUG_REG4__gws_req_MASK 0x00000002L +#define GDS_DEBUG_REG4__gws_req__SHIFT 0x00000001 +#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x00400000L +#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x00000016 +#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x00800000L +#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x00000017 +#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x00100000L +#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x00000014 +#define GDS_DEBUG_REG4__spare_MASK 0xff000000L +#define GDS_DEBUG_REG4__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x00000004L +#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x00000002 +#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x00000008L +#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x00000003 +#define GDS_DEBUG_REG5__dec_error_MASK 0x00000002L +#define GDS_DEBUG_REG5__dec_error__SHIFT 0x00000001 +#define GDS_DEBUG_REG5__error_ds_address_MASK 0x003fff00L +#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x00000008 +#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000L +#define GDS_DEBUG_REG5__spare1__SHIFT 0x00000016 +#define GDS_DEBUG_REG5__spare_MASK 0xff000000L +#define GDS_DEBUG_REG5__spare__SHIFT 0x00000018 +#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x00000010L +#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x00000004 +#define GDS_DEBUG_REG5__write_dis_MASK 0x00000001L +#define GDS_DEBUG_REG5__write_dis__SHIFT 0x00000000 +#define GDS_DEBUG_REG6__counters_busy_MASK 0x001fffe0L +#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x00000005 +#define GDS_DEBUG_REG6__counters_enabled_MASK 0x0000001eL +#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x00000001 +#define GDS_DEBUG_REG6__oa_busy_MASK 0x00000001L +#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x00000000 +#define GDS_DEBUG_REG6__spare_MASK 0xff000000L +#define GDS_DEBUG_REG6__spare__SHIFT 0x00000018 +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x00000010 +#define GDS_ENHANCE__MISC_MASK 0x0000ffffL +#define GDS_ENHANCE__MISC__SHIFT 0x00000000 +#define GDS_ENHANCE__UNUSED_MASK 0xffff0000L +#define GDS_ENHANCE__UNUSED__SHIFT 0x00000010 +#define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff0000L +#define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x00000010 +#define GDS_GRBM_SECDED_CNT__SEC_MASK 0x0000ffffL +#define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003fL +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0L +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x00000006 +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000ffffL +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000L +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x00000010 +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001ffeL +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x00000001 +#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L +#define GDS_GWS_RESOURCE__DED__SHIFT 0x0000000e +#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000L +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x0000001c +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x07ff0000L +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x00000010 +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x08000000L +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x0000001b +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x0000000f +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x00000000 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000ff00L +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x00000008 +#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0x0000000d +#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000L +#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x0000001d +#define GDS_OA_DED__ME0_CS_DED_MASK 0x00000004L +#define GDS_OA_DED__ME0_CS_DED__SHIFT 0x00000002 +#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L +#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x00000000 +#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L +#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x00000001 +#define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L +#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x00000004 +#define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L +#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x00000005 +#define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L +#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x00000006 +#define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L +#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x00000007 +#define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L +#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x00000008 +#define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L +#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x00000009 +#define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L +#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0x0000000a +#define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L +#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0x0000000b +#define GDS_OA_DED__UNUSED0_MASK 0x00000008L +#define GDS_OA_DED__UNUSED0__SHIFT 0x00000003 +#define GDS_OA_DED__UNUSED1_MASK 0xfffff000L +#define GDS_OA_DED__UNUSED1__SHIFT 0x0000000c +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffffL +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x00000000 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffffL +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x00000000 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffffL +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x00000000 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffffL +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x00000000 +#define GDS_RD_DATA__READ_DATA_MASK 0xffffffffL +#define GDS_RD_DATA__READ_DATA__SHIFT 0x00000000 +#define GDS_SECDED_CNT__DED_MASK 0xffff0000L +#define GDS_SECDED_CNT__DED__SHIFT 0x00000010 +#define GDS_SECDED_CNT__SEC_MASK 0x0000ffffL +#define GDS_SECDED_CNT__SEC__SHIFT 0x00000000 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffffL +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x00000000 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffffL +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x00000000 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffffL +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x00000000 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffffL +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x00000000 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffffL +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x00000000 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 +#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x0000003fL +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x00000000 +#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffffL +#define GRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000040L +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000006 +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x00001000L +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x0000000c +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0x00000f00L +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x00000008 +#define GRBM_DEBUG__IGNORE_FAO_MASK 0x00000020L +#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x00000005 +#define GRBM_DEBUG__IGNORE_RDY_MASK 0x00000002L +#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000001 +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x00000001L +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x00000000 +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x00000002L +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x00000001 +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000080L +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000007 +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x00000200L +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x00000009 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x00000040L +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x00000006 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x00004000L +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0x0000000e +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x00000080L +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x00000007 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x00008000L +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0x0000000f +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x00000100L +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x00000008 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x00010000L +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x00000010 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x00000200L +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x00000009 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x00020000L +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x00000011 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x00000400L +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0x0000000a +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x00040000L +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x00000012 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x00000800L +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0x0000000b +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x00080000L +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x00000013 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x00001000L +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0x0000000c +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x00100000L +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x00000014 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x00002000L +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0x0000000d +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x00200000L +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x00000015 +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x00000002L +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x00000001 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x00000008L +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x00000003 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x00000010L +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x00000004 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x0000001e +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000ffL +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x00000000 +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x0000001f +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00ff0000L +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x00000010 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x0000001d +#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000ff00L +#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x00000008 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x00000013 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x00000000 +#define GRBM_NOWHERE__DATA_MASK 0xffffffffL +#define GRBM_NOWHERE__DATA__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000019 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x00000016 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x00000018 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000017 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001a +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000e +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001b +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x0000001c +#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0x0000000fL +#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x00000000 +#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0x000000f0L +#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x00000004 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x00000013 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x00000014 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x00000015 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x00000016 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x00000017 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x00000018 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x00000019 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x0000001a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x0000001b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x0000001c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x0000001d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x0000001e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x0000001f +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x00000012 +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x00020000L +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x00000011 +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f +#define GRBM_READ_ERROR__READ_MEID_MASK 0x00c00000L +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x00000016 +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x00000014 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x00000015 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000012 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000b +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x00000011 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0x0000000a +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x00000014 +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003fL +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x00000000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x00000010 +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000f +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000d +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0x0000000c +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x00000013 +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000fc0L +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000006 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003fL +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x00000012 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x00000011 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x00000013 +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x00000010 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x00000002 +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x0000001c +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x00000004 +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000fL +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x00000000 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x00000005 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x00000006 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x00000007 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x00000008 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x00000009 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0x0000000a +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0x0000000b +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0x0000000c +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0x0000000d +#define GRBM_STATUS2__RLC_BUSY_MASK 0x00000100L +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x00000008 +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00000001L +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0x00000000 +#define GRBM_STATUS2__TC_BUSY_MASK 0x00000200L +#define GRBM_STATUS2__TC_BUSY__SHIFT 0x00000009 +#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L +#define GRBM_STATUS__CB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L +#define GRBM_STATUS__CB_CLEAN__SHIFT 0x0000000d +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L +#define GRBM_STATUS__CP_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x0000001c +#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L +#define GRBM_STATUS__DB_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L +#define GRBM_STATUS__DB_CLEAN__SHIFT 0x0000000c +#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L +#define GRBM_STATUS__GDS_BUSY__SHIFT 0x0000000f +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x00000009 +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f +#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L +#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L +#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x00000012 +#define GRBM_STATUS__IA_BUSY__SHIFT 0x00000013 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x00000007 +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000fL +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x00000000 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x00000008 +#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L +#define GRBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L +#define GRBM_STATUS__SC_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x0000001f +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x00000002 +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x00000001 +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x0000001b +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x0000001f +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x00000002 +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x00000001 +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x0000001b +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x0000001f +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x00000002 +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x00000001 +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x0000001b +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x0000001f +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x00000002 +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x0000001e +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x00000001 +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x00000018 +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x0000001d +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x0000001b +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x0000001a +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x00000019 +#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L +#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x00000017 +#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x00000016 +#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x00000005 +#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L +#define GRBM_STATUS__SX_BUSY__SHIFT 0x00000014 +#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L +#define GRBM_STATUS__TA_BUSY__SHIFT 0x0000000e +#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L +#define GRBM_STATUS__VGT_BUSY__SHIFT 0x00000011 +#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L +#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L +#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x00000010 +#define GRBM_STATUS__WD_BUSY__SHIFT 0x00000015 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000ffL +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x00000000 +#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L +#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x00000004 +#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L +#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x00000000 +#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L +#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x00000001 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x00000002 +#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L +#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x00000003 +#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x0000003fL +#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x00000000 +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x00000040L +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x00000006 +#define IA_DEBUG_DATA__DATA_MASK 0xffffffffL +#define IA_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define IA_DEBUG_REG0__core_clk_busy_MASK 0x04000000L +#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a +#define IA_DEBUG_REG0__dma_busy_MASK 0x00000040L +#define IA_DEBUG_REG0__dma_busy__SHIFT 0x00000006 +#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x00001000L +#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0x0000000c +#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x00000400L +#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0x0000000a +#define IA_DEBUG_REG0__dma_req_busy_MASK 0x00000020L +#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x00000005 +#define IA_DEBUG_REG0__grp_busy_MASK 0x00000100L +#define IA_DEBUG_REG0__grp_busy__SHIFT 0x00000008 +#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x00002000L +#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0x0000000d +#define IA_DEBUG_REG0__grp_dma_read_MASK 0x00000800L +#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0x0000000b +#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x00000001L +#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x00000000 +#define IA_DEBUG_REG0__ia_busy_MASK 0x00000004L +#define IA_DEBUG_REG0__ia_busy__SHIFT 0x00000002 +#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x00000002L +#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x00000001 +#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x00000008L +#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x00000003 +#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x00000080L +#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x00000007 +#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L +#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 +#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L +#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d +#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000L +#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x0000001c +#define IA_DEBUG_REG0__SPARE0_MASK 0x00000010L +#define IA_DEBUG_REG0__SPARE0__SHIFT 0x00000004 +#define IA_DEBUG_REG0__SPARE1_MASK 0x00000200L +#define IA_DEBUG_REG0__SPARE1__SHIFT 0x00000009 +#define IA_DEBUG_REG0__SPARE2_MASK 0x00ffc000L +#define IA_DEBUG_REG0__SPARE2__SHIFT 0x0000000e +#define IA_DEBUG_REG0__SPARE3_MASK 0x00100000L +#define IA_DEBUG_REG0__SPARE3__SHIFT 0x00000014 +#define IA_DEBUG_REG0__SPARE4_MASK 0x08000000L +#define IA_DEBUG_REG0__SPARE4__SHIFT 0x0000001b +#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000L +#define IA_DEBUG_REG0__SPARE5__SHIFT 0x0000001e +#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000L +#define IA_DEBUG_REG0__SPARE6__SHIFT 0x0000001f +#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000L +#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x0000001c +#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x00000100L +#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x00000008 +#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x00000200L +#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x00000009 +#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x00000060L +#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x00000005 +#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x00004000L +#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0x0000000e +#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x00008000L +#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0x0000000f +#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x04000000L +#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x0000001a +#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x00000001L +#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x00000000 +#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x00000002L +#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x00000001 +#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x00002000L +#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0x0000000d +#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000L +#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x0000001e +#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x00000008L +#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x00000003 +#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x00010000L +#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x00000010 +#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x00020000L +#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x00000011 +#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x00000080L +#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x00000007 +#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000L +#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x0000001f +#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x01000000L +#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x00000018 +#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x02000000L +#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x00000019 +#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x00000800L +#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0x0000000b +#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x00000010L +#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x00000004 +#define IA_DEBUG_REG1__grp_dma_read_MASK 0x08000000L +#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x0000001b +#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x00001000L +#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0x0000000c +#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000L +#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x0000001d +#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x00000400L +#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0x0000000a +#define IA_DEBUG_REG1__stage2_dr_MASK 0x00040000L +#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x00000012 +#define IA_DEBUG_REG1__stage2_rtr_MASK 0x00080000L +#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x00000013 +#define IA_DEBUG_REG1__stage3_dr_MASK 0x00100000L +#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x00000014 +#define IA_DEBUG_REG1__stage3_rtr_MASK 0x00200000L +#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x00000015 +#define IA_DEBUG_REG1__stage4_dr_MASK 0x00400000L +#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x00000016 +#define IA_DEBUG_REG1__stage4_rtr_MASK 0x00800000L +#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x00000017 +#define IA_DEBUG_REG1__start_new_packet_MASK 0x00000004L +#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x00000002 +#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000L +#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x0000001c +#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x00000100L +#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x00000008 +#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x00000200L +#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x00000009 +#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x00000060L +#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x00000005 +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x00004000L +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0x0000000e +#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x00008000L +#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0x0000000f +#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x04000000L +#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x0000001a +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x00000001L +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x00000000 +#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x00000002L +#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x00000001 +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x00002000L +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0x0000000d +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000L +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x0000001e +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x00000008L +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x00000003 +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x00010000L +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x00000010 +#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x00020000L +#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x00000011 +#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x00000080L +#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x00000007 +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000L +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x0000001f +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x01000000L +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x00000018 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x02000000L +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x00000019 +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x00000800L +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0x0000000b +#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x00000010L +#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x00000004 +#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x08000000L +#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x0000001b +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x00001000L +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0x0000000c +#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000L +#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x0000001d +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x00000400L +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0x0000000a +#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x00040000L +#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x00000012 +#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x00080000L +#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x00000013 +#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x00100000L +#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x00000014 +#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x00200000L +#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x00000015 +#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x00400000L +#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x00000016 +#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x00800000L +#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x00000017 +#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x00000004L +#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x00000002 +#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x04000000L +#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x0000001a +#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x08000000L +#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x0000001b +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x00000008L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x00000003 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x00000004L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x00000002 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x00000002L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x00000001 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x00000010L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x00000004 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x00000001L +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x00000000 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x00000800L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0x0000000b +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x00000400L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0x0000000a +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x00000200L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x00000009 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x00001000L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0x0000000c +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x00000100L +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x00000008 +#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x00008000L +#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0x0000000f +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x00000020L +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x00000005 +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x00002000L +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0x0000000d +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x00040000L +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x00000012 +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000L +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x0000001d +#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000L +#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x0000001c +#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x00004000L +#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0x0000000e +#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x00000040L +#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x00000006 +#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x00100000L +#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x00000014 +#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x00200000L +#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x00000015 +#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x00400000L +#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x00000016 +#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x00800000L +#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x00000017 +#define IA_DEBUG_REG3__pipe0_dr_MASK 0x00010000L +#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x00000010 +#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x00020000L +#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x00000011 +#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x00000080L +#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x00000007 +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000L +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x0000001f +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000L +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x0000001e +#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x00080000L +#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x00000013 +#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x03000000L +#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x00000018 +#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000L +#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x0000001f +#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x00100000L +#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x00000014 +#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000L +#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x0000001d +#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x00010000L +#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x00000010 +#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0x0c000000L +#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x0000001a +#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0x00e00000L +#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x00000015 +#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x02000000L +#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x00000019 +#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x01000000L +#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x00000018 +#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x00000040L +#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x00000006 +#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x00000080L +#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x00000007 +#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0x000e0000L +#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x00000011 +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x00008000L +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0x0000000f +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x00004000L +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0x0000000e +#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000L +#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x0000001e +#define IA_DEBUG_REG4__pipe0_dr_MASK 0x00000001L +#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x00000000 +#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x00000100L +#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x00000008 +#define IA_DEBUG_REG4__pipe1_dr_MASK 0x00000002L +#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x00000001 +#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x00000200L +#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x00000009 +#define IA_DEBUG_REG4__pipe2_dr_MASK 0x00000004L +#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x00000002 +#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x00000400L +#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0x0000000a +#define IA_DEBUG_REG4__pipe3_dr_MASK 0x00000008L +#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x00000003 +#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x00000800L +#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0x0000000b +#define IA_DEBUG_REG4__pipe4_dr_MASK 0x00000010L +#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x00000004 +#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x00001000L +#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0x0000000c +#define IA_DEBUG_REG4__pipe5_dr_MASK 0x00000020L +#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x00000005 +#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x00002000L +#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0x0000000d +#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000L +#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x0000001c +#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0x0000ffffL +#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x00000000 +#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000L +#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x0000001f +#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000L +#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x0000001e +#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000L +#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x00000010 +#define IA_DEBUG_REG6__after_group_partial_MASK 0x00400000L +#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x00000016 +#define IA_DEBUG_REG6__current_shift_q_MASK 0x0000000fL +#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x00000000 +#define IA_DEBUG_REG6__current_stride_pre_MASK 0x000000f0L +#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x00000004 +#define IA_DEBUG_REG6__current_stride_q_MASK 0x00001f00L +#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x00000008 +#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x00008000L +#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0x0000000f +#define IA_DEBUG_REG6__extract_group_MASK 0x00800000L +#define IA_DEBUG_REG6__extract_group__SHIFT 0x00000017 +#define IA_DEBUG_REG6__first_group_partial_MASK 0x00002000L +#define IA_DEBUG_REG6__first_group_partial__SHIFT 0x0000000d +#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000L +#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x00000018 +#define IA_DEBUG_REG6__next_group_partial_MASK 0x00200000L +#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x00000015 +#define IA_DEBUG_REG6__next_stride_q_MASK 0x001f0000L +#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x00000010 +#define IA_DEBUG_REG6__second_group_partial_MASK 0x00004000L +#define IA_DEBUG_REG6__second_group_partial__SHIFT 0x0000000e +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x02000000L +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x00000019 +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x04000000L +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x0000001a +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x08000000L +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x0000001b +#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x00800000L +#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x00000017 +#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x00700000L +#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x00000014 +#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0x0000000fL +#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x00000000 +#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x01000000L +#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x00000018 +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000L +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x0000001f +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000L +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x0000001e +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000L +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x0000001d +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000L +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x0000001c +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0x0000f000L +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0x0000000c +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0x000f0000L +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x00000010 +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0x00000f00L +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x00000008 +#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0x000000f0L +#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x00000004 +#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x0000001fL +#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x00000000 +#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000L +#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x0000001c +#define IA_DEBUG_REG8__grp_continued_MASK 0x00000800L +#define IA_DEBUG_REG8__grp_continued__SHIFT 0x0000000b +#define IA_DEBUG_REG8__grp_eopg_MASK 0x04000000L +#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x0000001a +#define IA_DEBUG_REG8__grp_eop_MASK 0x02000000L +#define IA_DEBUG_REG8__grp_eop__SHIFT 0x00000019 +#define IA_DEBUG_REG8__grp_event_flag_MASK 0x08000000L +#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x0000001b +#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x01000000L +#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x00000018 +#define IA_DEBUG_REG8__grp_output_path_MASK 0x00e00000L +#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x00000015 +#define IA_DEBUG_REG8__grp_state_sel_MASK 0x00007000L +#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0x0000000c +#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x001f8000L +#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0x0000000f +#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x00000100L +#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x00000008 +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x00000400L +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0x0000000a +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x00000200L +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x00000009 +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x00000080L +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x00000007 +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x00000020L +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x00000005 +#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x00000040L +#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x00000006 +#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x00000400L +#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0x0000000a +#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x00000200L +#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x00000009 +#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x00000002L +#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x00000001 +#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x00040000L +#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x00000012 +#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x00080000L +#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x00000013 +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x00000008L +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x00000003 +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x00000004L +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x00000002 +#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x00000020L +#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x00000005 +#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x00000080L +#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x00000007 +#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x00000010L +#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x00000004 +#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x00000100L +#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x00000008 +#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x00000040L +#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x00000006 +#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x00020000L +#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x00000011 +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x00000800L +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0x0000000b +#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfffc0000L +#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x00000012 +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x00001000L +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0x0000000c +#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x00000001L +#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x00000000 +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x00010000L +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x00000010 +#define IA_DEBUG_REG9__SPARE0_MASK 0x00004000L +#define IA_DEBUG_REG9__SPARE0__SHIFT 0x0000000e +#define IA_DEBUG_REG9__SPARE1_MASK 0x00008000L +#define IA_DEBUG_REG9__SPARE1__SHIFT 0x0000000f +#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x00002000L +#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0x0000000d +#define IA_ENHANCE__MISC_MASK 0xffffffffL +#define IA_ENHANCE__MISC__SHIFT 0x00000000 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x00000012 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x00000010 +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000ffffL +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x00000000 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x00000013 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x00000011 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x00000014 +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define IA_VMID_OVERRIDE__ENABLE_MASK 0x00000001L +#define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x00000000 +#define IA_VMID_OVERRIDE__VMID_MASK 0x0000001eL +#define IA_VMID_OVERRIDE__VMID__SHIFT 0x00000001 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x00000018 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000c000L +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0x0000000e +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0x0000000d +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x00000011 +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x00000000 +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x00000001 +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x00000002 +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x00000003 +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x00000004 +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x00000005 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x00000019 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x0000001b +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x0000001a +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x00000003 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x00000001 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x00000004 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x00000005 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0x0000000e +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0x0000000d +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0x0000000c +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x00000009 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x00000008 +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0x0000000b +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0x0000000a +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x00000003 +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x00000014 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x00000002 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x00000006 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x00000007 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x00000000 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x00000004 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x00000001 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x00000005 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffffL +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x00000000 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x00000001 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x00000002 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x00000003 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x00000004 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x00000005 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x00000006 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x00000007 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x00000008 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x00000009 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0x0000000a +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0x0000000b +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0x0000000c +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0x0000000d +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0x0000000e +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0x0000000f +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x00000011 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x00000019 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x00000014 +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x00000010 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x00000012 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x00000013 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x00000016 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x00000017 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x00000018 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x00000015 +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x00000004 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x00000018 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x00000014 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000ffffL +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x00000000 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000L +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x00000010 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000ffffL +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x00000000 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000L +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x0000001c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000fL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x00000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000f0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x00000004 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000f00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x00000008 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000f000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0x0000000c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000f0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x00000010 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00f00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x00000014 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0f000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x00000018 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x0000001c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000fL +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x00000000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000f0L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x00000004 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000f00L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x00000008 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000f000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0x0000000c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000f0000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x00000010 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00f00000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x00000014 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0f000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x00000018 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x0000001c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000f00L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x00000008 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000f000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0x0000000c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000f0000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x00000010 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00f00000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x00000014 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0f000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x00000018 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x0000001c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000fL +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x00000000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000f0L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x00000004 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007fffL +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000ffffL +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x00000000 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000003fL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x00000003L +#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x00000000 +#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0x0000000cL +#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x00000002 +#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x00000003L +#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x00000000 +#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0x0000000cL +#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x00000002 +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000L +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x0000001c +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003f000L +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0x0000000c +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00fc0000L +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x00000012 +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0f000000L +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x00000018 +#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000f0L +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x00000004 +#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000f00L +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x00000008 +#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000fL +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x00000000 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x00000002 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000200L +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x00000009 +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00004000L +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0x0000000e +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00200000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000015 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00800000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x00000017 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00040000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x00000012 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00010000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x00000010 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00400000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x00000016 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00080000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x00000013 +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00002000L +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0x0000000d +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0x000000c0L +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x00000006 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x00000001 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x00000005 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000400L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x0000000a +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000800L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x0000000b +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00001000L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0x0000000c +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x00000003 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x00000004 +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00008000L +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0x0000000f +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x01000000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x00000018 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00020000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x00000011 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00100000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x00000014 +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x00000000 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000100L +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x00000008 +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000000ffL +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x00000000 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007fc0L +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x00000006 +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000L +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x00000017 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003fL +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x00000000 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001f8000L +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0x0000000f +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000ffffL +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x00000000 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000L +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x00000010 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00fc0000L +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x00000012 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000fc0L +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x00000006 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003fL +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x00000000 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003f000L +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0x0000000c +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0x0000000c +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0x0000000b +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x00000002 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x00000000 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x00000003 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x00000001 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x00000019 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x0000001a +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x00000013 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00f00000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x00000014 +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0x0000000f +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0x0000000e +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x00000018 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x00000012 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x00000011 +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x0000001b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x0000001c +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x00000010 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x00000007 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x00000009 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0x0000000a +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x00000008 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x00000002 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x00000001 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x00000003 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x00000004 +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x00000000 +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0x0000000b +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0x0000000c +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0x0000000d +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x00000000 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000cL +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x00000002 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x00000004 +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x00000008 +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000c000L +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0x0000000e +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000c00L +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0x0000000a +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0x0000000c +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x00000000 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000cL +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x00000002 +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x00000004 +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x00000006 +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x00000007 +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x00000010 +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000c0000L +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x00000012 +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x00000014 +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x00000018 +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0c000000L +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x0000001a +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x0000001c +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000ffffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000L +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000ffffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000L +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007fffL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffffL +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffffL +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000ffffL +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000L +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000L +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001ffL +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x00000000 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01ff0000L +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x00000010 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x00000004 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x00000002 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x00000003 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x00000000 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffffL +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x00000000 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00ffffffL +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x00000008 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000ffL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x00000005 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x00000001 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x00000006 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x00000002 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000ff00L +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x00000008 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x00000007 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x00000003 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x00000004 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x00000000 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x0000001e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x0000001f +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x00000000 +#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffffL +#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x00000000 +#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L +#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x00000000 +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffffL +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x00000000 +#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffffL +#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x00000000 +#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffffL +#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x00000000 +#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffffL +#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x00000000 +#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffffL +#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x00000000 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x00000001 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x00000000 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x00000002 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007fff8L +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x00000003 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000L +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x00000013 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x00000000 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffeL +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x00000001 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x0000001b +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x00000000 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x0000ff00L +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x00000008 +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x0000001c +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x00000001 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000fcL +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x00000002 +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x0000001d +#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000L +#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x0000001f +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000fL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x00000000 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000f0L +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x00000004 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0fff0000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x00000010 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x0000001c +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000f00L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x00000008 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000f000L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0x0000000c +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffffL +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x00000000 +#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x00000001 +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x00000002 +#define RLC_CNTL__RESERVED_MASK 0xffffff00L +#define RLC_CNTL__RESERVED__SHIFT 0x00000008 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x00000000 +#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x00000003 +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x00000010L +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x00000004 +#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffffL +#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x00000000 +#define RLC_DEBUG__DATA_MASK 0xffffffffL +#define RLC_DEBUG__DATA__SHIFT 0x00000000 +#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffff8000L +#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x0000000f +#define RLC_DEBUG_SELECT__SELECT_MASK 0x000000ffL +#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x00000000 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x00000010L +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x00000004 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x00000001L +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x00000000 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0x0000000eL +#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x00000001 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0L +#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x00000005 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffffL +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x00000000 +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001ffL +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x00000000 +#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00L +#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x00000009 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffffL +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x00000000 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0L +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x00000006 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003fL +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x00000000 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffffL +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x00000000 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffffL +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x00000000 +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffffL +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x00000000 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000ff0L +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x00000004 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L +#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x00000001 +#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L +#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x00000003 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x00000002 +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x00000000 +#define RLC_LB_CNTL__RESERVED_MASK 0xfffffff0L +#define RLC_LB_CNTL__RESERVED__SHIFT 0x00000004 +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffffL +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x00000000 +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffffL +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x00000000 +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffffL +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x00000000 +#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000feL +#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x00000001 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000L +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x00000010 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000ff00L +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x00000008 +#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L +#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x00000000 +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffffL +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x00000000 +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000ffL +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x00000000 +#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00L +#define RLC_MAX_PG_CU__SPARE__SHIFT 0x00000008 +#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000L +#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x0000001c +#define RLC_MC_CNTL__RDNFO_URG_MASK 0x00f00000L +#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x00000014 +#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x08000000L +#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x0000001b +#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x03000000L +#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x00000018 +#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x04000000L +#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x0000001a +#define RLC_MC_CNTL__RESERVED_B_MASK 0x000fe000L +#define RLC_MC_CNTL__RESERVED_B__SHIFT 0x0000000d +#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000L +#define RLC_MC_CNTL__RESERVED__SHIFT 0x0000001d +#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x00000010L +#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x00000004 +#define RLC_MC_CNTL__WRNFO_URG_MASK 0x000001e0L +#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x00000005 +#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x00001e00L +#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x00000009 +#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x00000008L +#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x00000003 +#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x00000003L +#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x00000000 +#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x00000004L +#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x00000002 +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x00000001 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x00000000 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00ff0000L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x00000010 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000ff00L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x00000008 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffffL +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x00000000 +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x00000010 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x00000002 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x00000000 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x00000001 +#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000L +#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x00000018 +#define RLC_PG_CNTL__RESERVED1_MASK 0x00f80000L +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x00000013 +#define RLC_PG_CNTL__RESERVED_MASK 0xfffffff0L +#define RLC_PG_CNTL__RESERVED__SHIFT 0x00000004 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x00000012 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x00000011 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x00000003 +#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffffL +#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x00000000 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffffL +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x00000000 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffffL +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x00000000 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffffL +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x00000000 +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000fL +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x00000000 +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x0000c000L +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x0000000e +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x00003800L +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0x0000000b +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001c0L +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x00000006 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000200L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x00000009 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00000400L +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0x0000000a +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x00000004 +#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffffc000L +#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x0000000e +#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000ffL +#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x00000000 +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x00100000L +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x00000014 +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x00200000L +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x00000015 +#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x00020000L +#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x00000011 +#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x00010000L +#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x00000010 +#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x00080000L +#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x00000013 +#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x00040000L +#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x00000012 +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x00400000L +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x00000016 +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x00800000L +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x00000017 +#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L +#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0x0000000a +#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L +#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0x0000000b +#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L +#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x00000008 +#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L +#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x00000009 +#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L +#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0x0000000d +#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000L +#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x0000001c +#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0x0000c000L +#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0x0000000e +#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0x0f000000L +#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x00000018 +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0x0000000c +#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffffL +#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x00000000 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffeL +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x00000001 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x00000000 +#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffeL +#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x00000001 +#define RLC_SMU_PG_CTRL__START_PG_MASK 0x00000001L +#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x00000000 +#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffeL +#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x00000001 +#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x00000001L +#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x00000000 +#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffeL +#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x00000001 +#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x00000001L +#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x00000000 +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffffL +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x00000000 +#define RLC_STAT__RESERVED_MASK 0xfffffff0L +#define RLC_STAT__RESERVED__SHIFT 0x00000004 +#define RLC_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_STAT__RLC_BUSY__SHIFT 0x00000000 +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x00000001 +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x00000002 +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000ffL +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x00000000 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000ff00L +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x00000008 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00ff0000L +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x00000010 +#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000L +#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x00000018 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffffL +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x00000000 +#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffffL +#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x00000000 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L +#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x00000010 +#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000L +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x0000001f +#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG0__event_id_gated_MASK 0x0fc00000L +#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00200000L +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000015 +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00008000L +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00004000L +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00080000L +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x00000013 +#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x0000001d +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x00003f00L +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000008 +#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x00000003L +#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x00030000L +#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00040000L +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x00000012 +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00100000L +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000014 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000003cL +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000002 +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000L +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x0000001e +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000L +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x00000010 +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0x0000ffffL +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000L +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x00000010 +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0x0000ffffL +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000L +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x00000010 +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0x0000ffffL +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x00003fffL +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00008000L +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000f +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00080000L +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000013 +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x00700000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x03000000L +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000018 +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000L +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001f +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000L +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001d +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00004000L +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000e +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x00070000L +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000L +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00800000L +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x0fffc000L +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000e +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x00003fffL +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000L +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x0000001f +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000L +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000L +#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x0000001e +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000ffffL +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x00000000 +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000L +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x00000010 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000ffffL +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x00000000 +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000L +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x00000010 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x00000000 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x00000003 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001c0L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x00000006 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000e00L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x00000009 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0x0000000c +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000c000L +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0x0000000e +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x00000010 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000c0000L +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x00000012 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x00000018 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x00000008 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0x0000000c +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x00000000 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x00000004 +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x00000010 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x00000014 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x00000008 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x00000004 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003c00L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0x0000000a +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x00000009 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x00000006 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x00000010 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x00000007 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000fL +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x00000000 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x00000019 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x00000018 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00e00000L +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x00000015 +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001fffffL +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x00000000 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x0000001a +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x0000001b +#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000080L +#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x00000007 +#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000100L +#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x00000008 +#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000200L +#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0x00000009 +#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L +#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0x0000000b +#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L +#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0x0000000c +#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L +#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0x0000000d +#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L +#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0x0000000e +#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L +#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0x0000000f +#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L +#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x00000007 +#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L +#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x00000002 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00008000L +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x0000000f +#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00010000L +#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x00000010 +#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L +#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x00000003 +#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L +#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x00000001 +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00000400L +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x0000000a +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00000800L +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x0000000b +#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L +#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x00000000 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x00000014 +#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L +#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x00000005 +#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L +#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x00000006 +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00001000L +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x0000000c +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00002000L +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x0000000d +#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00020000L +#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x00000011 +#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L +#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x00000004 +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x00000001L +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x00000000 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x000003e0L +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x00000005 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0x0e000000L +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x00000019 +#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000L +#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x0000001f +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x00010000L +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x00000010 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0x0000fc00L +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0x0000000a +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0x0000001eL +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x00000001 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x00020000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x00000011 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x00040000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x00000012 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x00080000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x00000013 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x00100000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x00000014 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x00200000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x00000015 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x00400000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x00000016 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x00800000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x00000017 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x01000000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x00000018 +#define SPI_DEBUG_READ__DATA_MASK 0x00ffffffL +#define SPI_DEBUG_READ__DATA__SHIFT 0x00000000 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000ff00L +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x00000008 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000ffL +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x00000000 +#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000L +#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x00000010 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x00000000 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x00000001 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0x0000000b +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001cL +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x00000002 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000e0L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x00000005 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x00000008 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0x0000000e +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x00000000 +#define SPI_LB_CU_MASK__CU_MASK_MASK 0x0000ffffL +#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x00000000 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffffL +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x00000000 +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000f0L +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x00000004 +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000fL +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x00000000 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000f000L +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0x0000000c +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000f00L +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x00000008 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00f00000L +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x00000014 +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000f0000L +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x00000010 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x0000001c +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0f000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x00000018 +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0x0000ffffL +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x00000000 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0x0000000e +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003fL +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x00000000 +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x00000006 +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0x0000000d +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0x0000000c +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x00000005 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x00000006 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x00000001 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x00000002 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x00000000 +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0x0000000f +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0x0000000b +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x00000008 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x00000009 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0x0000000a +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001e000L +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0x0000000d +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x00000008 +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x00000012 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0x0000000a +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003fL +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x00000000 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x00000011 +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0x0000000d +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0x0000000c +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x00000005 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x00000006 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x00000004 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x00000007 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x00000001 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x00000002 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x00000003 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x00000000 +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0x0000000f +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0x0000000b +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x00000008 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x00000009 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0x0000000a +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0x0000000e +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000fffL +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x00000000 +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000fL +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x00000000 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000f0L +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x00000004 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000f00L +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x00000008 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000f000L +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0x0000000c +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000f0000L +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x00000010 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00f00000L +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x00000014 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0f000000L +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x00000018 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000L +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x0000001c +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000L +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x0000001b +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000L +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x0000001e +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x0000001a +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0x0e000000L +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x00000019 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x0000001c +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x07000000L +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x0000001b +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000L +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x0000001a +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000L +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x0000001d +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0x0e000000L +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x00000019 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x0000001c +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000L +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x0000001b +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x0000001e +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x0000001a +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x00000016 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x00000015 +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000ff000L +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x00000017 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000c00L +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003c0L +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x00000018 +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003fL +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x00007f00L +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x0001ff00L +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000L +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000L +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x0001ff00L +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000L +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x00000014 +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x00003f80L +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000fe00L +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x00000009 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x01ff0000L +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0x0000ff80L +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x007f0000L +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x01ff0000L +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0x0000ff80L +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0x0000ff80L +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x01ff0000L +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0x0000ff80L +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x007f0000L +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x00000010 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000ff00L +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x000fe000L +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0x0000000d +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x00000007 +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x00000000 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x00000008 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x00000009 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0x0000000a +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0x0000000b +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0x0000000c +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x00000006 +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003eL +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x00000001 +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000fL +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x00000000 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000f0L +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x00000004 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000f00L +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x00000008 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000f000L +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0x0000000c +#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0x000000ffL +#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffffL +#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x00000000 +#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffffL +#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x00000000 +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000fL +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x00000000 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x00000004L +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x00000002 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x00200000L +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x00000015 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x00000008L +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x00000003 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x00000002L +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x00000001 +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x00000001L +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x00000000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x00000200L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x00000009 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x00000400L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0x0000000a +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x00000800L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0x0000000b +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x00001000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0x0000000c +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x00002000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0x0000000d +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x00004000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0x0000000e +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x00008000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0x0000000f +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x00010000L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x00000010 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x00000020L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x00000005 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x00000040L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x00000006 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x00000080L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x00000007 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x00000100L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x00000008 +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x00000010L +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x00000004 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x00020000L +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x00000011 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x00040000L +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x00000012 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x00080000L +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x00000013 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x00100000L +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x00000014 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000ffffL +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x00000000 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000L +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x00000010 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000ffffL +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x00000000 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000L +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x00000010 +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c +#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000fffL +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x00000000 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003eL +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x00000001 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x00000006 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000ffffL +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x0000001e +#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000L +#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x00000010 +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x0000001f +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffffL +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x00000000 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x00000017 +#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x01000000L +#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x00000018 +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0x0000000f +#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L +#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x00180000L +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x00000013 +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x02000000L +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x00000019 +#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x04000000L +#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x0000001a +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x00000015 +#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000L +#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x0000001b +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0x0000000c +#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000L +#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x0000001e +#define SQC_CACHES__DATA_INVALIDATE_MASK 0x00000002L +#define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x00000001 +#define SQC_CACHES__INST_INVALIDATE_MASK 0x00000001L +#define SQC_CACHES__INST_INVALIDATE__SHIFT 0x00000000 +#define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x00000004L +#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x00000002 +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000cL +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x00000002 +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x00000007 +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x00000008 +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x00000006 +#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L +#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x00000009 +#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L +#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0x0000000a +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x00000000 +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x00000004 +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x0000000b +#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L +#define SQ_CONFIG__DEBUG_EN__SHIFT 0x00000008 +#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x00000400L +#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0x0000000a +#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x00000200L +#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x00000009 +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0x0000000f +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0x0000000d +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0x0000000e +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0x0000000c +#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x00000800L +#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0x0000000b +#define SQ_CONFIG__UNUSED_MASK 0x000000ffL +#define SQ_CONFIG__UNUSED__SHIFT 0x00000000 +#define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000L +#define SQC_SECDED_CNT__DATA_DED__SHIFT 0x00000018 +#define SQC_SECDED_CNT__DATA_SEC_MASK 0x00ff0000L +#define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x00000010 +#define SQC_SECDED_CNT__INST_DED_MASK 0x0000ff00L +#define SQC_SECDED_CNT__INST_DED__SHIFT 0x00000008 +#define SQC_SECDED_CNT__INST_SEC_MASK 0x000000ffL +#define SQC_SECDED_CNT__INST_SEC__SHIFT 0x00000000 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000ffL +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x00000000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004 +#define SQ_DED_CNT__LDS_DED_MASK 0x0000003fL +#define SQ_DED_CNT__LDS_DED__SHIFT 0x00000000 +#define SQ_DED_CNT__SGPR_DED_MASK 0x00001f00L +#define SQ_DED_CNT__SGPR_DED__SHIFT 0x00000008 +#define SQ_DED_CNT__VGPR_DED_MASK 0x01ff0000L +#define SQ_DED_CNT__VGPR_DED__SHIFT 0x00000010 +#define SQ_DED_INFO__SIMD_ID_MASK 0x00000030L +#define SQ_DED_INFO__SIMD_ID__SHIFT 0x00000004 +#define SQ_DED_INFO__SOURCE_MASK 0x000001c0L +#define SQ_DED_INFO__SOURCE__SHIFT 0x00000006 +#define SQ_DED_INFO__VM_ID_MASK 0x00001e00L +#define SQ_DED_INFO__VM_ID__SHIFT 0x00000009 +#define SQ_DED_INFO__WAVE_ID_MASK 0x0000000fL +#define SQ_DED_INFO__WAVE_ID__SHIFT 0x00000000 +#define SQ_DS_0__ENCODING_MASK 0xfc000000L +#define SQ_DS_0__ENCODING__SHIFT 0x0000001a +#define SQ_DS_0__GDS_MASK 0x00020000L +#define SQ_DS_0__GDS__SHIFT 0x00000011 +#define SQ_DS_0__OFFSET0_MASK 0x000000ffL +#define SQ_DS_0__OFFSET0__SHIFT 0x00000000 +#define SQ_DS_0__OFFSET1_MASK 0x0000ff00L +#define SQ_DS_0__OFFSET1__SHIFT 0x00000008 +#define SQ_DS_0__OP_MASK 0x03fc0000L +#define SQ_DS_0__OP__SHIFT 0x00000012 +#define SQ_DS_1__ADDR_MASK 0x000000ffL +#define SQ_DS_1__ADDR__SHIFT 0x00000000 +#define SQ_DS_1__DATA0_MASK 0x0000ff00L +#define SQ_DS_1__DATA0__SHIFT 0x00000008 +#define SQ_DS_1__DATA1_MASK 0x00ff0000L +#define SQ_DS_1__DATA1__SHIFT 0x00000010 +#define SQ_DS_1__VDST_MASK 0xff000000L +#define SQ_DS_1__VDST__SHIFT 0x00000018 +#define SQ_EXP_0__COMPR_MASK 0x00000400L +#define SQ_EXP_0__COMPR__SHIFT 0x0000000a +#define SQ_EXP_0__DONE_MASK 0x00000800L +#define SQ_EXP_0__DONE__SHIFT 0x0000000b +#define SQ_EXP_0__ENCODING_MASK 0xfc000000L +#define SQ_EXP_0__ENCODING__SHIFT 0x0000001a +#define SQ_EXP_0__EN_MASK 0x0000000fL +#define SQ_EXP_0__EN__SHIFT 0x00000000 +#define SQ_EXP_0__TGT_MASK 0x000003f0L +#define SQ_EXP_0__TGT__SHIFT 0x00000004 +#define SQ_EXP_0__VM_MASK 0x00001000L +#define SQ_EXP_0__VM__SHIFT 0x0000000c +#define SQ_EXP_1__VSRC0_MASK 0x000000ffL +#define SQ_EXP_1__VSRC0__SHIFT 0x00000000 +#define SQ_EXP_1__VSRC1_MASK 0x0000ff00L +#define SQ_EXP_1__VSRC1__SHIFT 0x00000008 +#define SQ_EXP_1__VSRC2_MASK 0x00ff0000L +#define SQ_EXP_1__VSRC2__SHIFT 0x00000010 +#define SQ_EXP_1__VSRC3_MASK 0xff000000L +#define SQ_EXP_1__VSRC3__SHIFT 0x00000018 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x00000010 +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000fL +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x00000000 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000f00L +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x00000008 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000c0000L +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x00000012 +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffffL +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000ffL +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03f00000L +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x00000014 +#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000fff00L +#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x00000008 +#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000L +#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x0000001e +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000L +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x0000001a +#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0fffc000L +#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0x0000000e +#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000L +#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x0000001f +#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L +#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x0000001c +#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003fffL +#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x08000000L +#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x0000001b +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000f000L +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0x0000000c +#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000e00L +#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x00000009 +#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L +#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001c0L +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000f0000L +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x00000010 +#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x04000000L +#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x0000001a +#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x02000000L +#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x00000019 +#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x01f00000L +#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x00000014 +#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000L +#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x0000001c +#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001fffL +#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x07ffe000L +#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0x0000000d +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001fffL +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x03ffe000L +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0x0000000d +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000ff000L +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0x0000000c +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x00000014 +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000fffL +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x00000000 +#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000L +#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x00000015 +#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffffL +#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07e00000L +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x00000015 +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x00000010 +#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L +#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L +#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x00000003 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001c0L +#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x00000006 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0x0000000c +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x0000001c +#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L +#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x0000001d +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x00000014 +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0x0000000f +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000e00L +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x00000009 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x00000013 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x0000001b +#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00fff000L +#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0x0000000c +#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000fffL +#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0f000000L +#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x00000018 +#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000L +#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x0000001c +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000L +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x0000001d +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x0000001e +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003fffL +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000fc000L +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0x0000000e +#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0c000000L +#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x0000001a +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x0000001c +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x00000014 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00c00000L +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x00000016 +#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L +#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x00000018 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000fffL +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x00000000 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000L +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x0000001e +#define SQ_IND_DATA__DATA_MASK 0xffffffffL +#define SQ_IND_DATA__DATA__SHIFT 0x00000000 +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0x0000000c +#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L +#define SQ_IND_INDEX__FORCE_READ__SHIFT 0x0000000d +#define SQ_IND_INDEX__INDEX_MASK 0xffff0000L +#define SQ_IND_INDEX__INDEX__SHIFT 0x00000010 +#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L +#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0x0000000e +#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L +#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004 +#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000fc0L +#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x00000006 +#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L +#define SQ_IND_INDEX__UNINDEXED__SHIFT 0x0000000f +#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000fL +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x00000000 +#define SQ_INST__ENCODING_MASK 0xffffffffL +#define SQ_INST__ENCODING__SHIFT 0x00000000 +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x00000010L +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x00000004 +#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0x0c000000L +#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x0000001a +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x00000020L +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x00000005 +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x00000040L +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x00000006 +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x00000080L +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x00000007 +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x00000008L +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x00000003 +#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x00000019 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x00000004L +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x00000002 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x00000001L +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x00000000 +#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x00000002L +#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x00000001 +#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0x0c000000L +#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x0000001a +#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x00000019 +#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0x00f00000L +#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x00000014 +#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0x000000ffL +#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x00000000 +#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0x0c000000L +#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x0000001a +#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x00000200L +#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x00000009 +#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x02000000L +#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x00000019 +#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x01000000L +#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x00000018 +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0x000c0000L +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x00000012 +#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x00003c00L +#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0x0000000a +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x0003c000L +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0x0000000e +#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L +#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x00000002 +#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L +#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x00000001 +#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L +#define SQ_LB_CTR_CTRL__START__SHIFT 0x00000000 +#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffffL +#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x00000000 +#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffffL +#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x00000000 +#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffffL +#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x00000000 +#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffffL +#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x00000000 +#define SQ_MIMG_0__DA_MASK 0x00004000L +#define SQ_MIMG_0__DA__SHIFT 0x0000000e +#define SQ_MIMG_0__DMASK_MASK 0x00000f00L +#define SQ_MIMG_0__DMASK__SHIFT 0x00000008 +#define SQ_MIMG_0__ENCODING_MASK 0xfc000000L +#define SQ_MIMG_0__ENCODING__SHIFT 0x0000001a +#define SQ_MIMG_0__GLC_MASK 0x00002000L +#define SQ_MIMG_0__GLC__SHIFT 0x0000000d +#define SQ_MIMG_0__LWE_MASK 0x00020000L +#define SQ_MIMG_0__LWE__SHIFT 0x00000011 +#define SQ_MIMG_0__OP_MASK 0x01fc0000L +#define SQ_MIMG_0__OP__SHIFT 0x00000012 +#define SQ_MIMG_0__R128_MASK 0x00008000L +#define SQ_MIMG_0__R128__SHIFT 0x0000000f +#define SQ_MIMG_0__SLC_MASK 0x02000000L +#define SQ_MIMG_0__SLC__SHIFT 0x00000019 +#define SQ_MIMG_0__TFE_MASK 0x00010000L +#define SQ_MIMG_0__TFE__SHIFT 0x00000010 +#define SQ_MIMG_0__UNORM_MASK 0x00001000L +#define SQ_MIMG_0__UNORM__SHIFT 0x0000000c +#define SQ_MIMG_1__SRSRC_MASK 0x001f0000L +#define SQ_MIMG_1__SRSRC__SHIFT 0x00000010 +#define SQ_MIMG_1__SSAMP_MASK 0x03e00000L +#define SQ_MIMG_1__SSAMP__SHIFT 0x00000015 +#define SQ_MIMG_1__VADDR_MASK 0x000000ffL +#define SQ_MIMG_1__VADDR__SHIFT 0x00000000 +#define SQ_MIMG_1__VDATA_MASK 0x0000ff00L +#define SQ_MIMG_1__VDATA__SHIFT 0x00000008 +#define SQ_MTBUF_0__ADDR64_MASK 0x00008000L +#define SQ_MTBUF_0__ADDR64__SHIFT 0x0000000f +#define SQ_MTBUF_0__DFMT_MASK 0x00780000L +#define SQ_MTBUF_0__DFMT__SHIFT 0x00000013 +#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000L +#define SQ_MTBUF_0__ENCODING__SHIFT 0x0000001a +#define SQ_MTBUF_0__GLC_MASK 0x00004000L +#define SQ_MTBUF_0__GLC__SHIFT 0x0000000e +#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MTBUF_0__IDXEN__SHIFT 0x0000000d +#define SQ_MTBUF_0__NFMT_MASK 0x03800000L +#define SQ_MTBUF_0__NFMT__SHIFT 0x00000017 +#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MTBUF_0__OFFEN__SHIFT 0x0000000c +#define SQ_MTBUF_0__OFFSET_MASK 0x00000fffL +#define SQ_MTBUF_0__OFFSET__SHIFT 0x00000000 +#define SQ_MTBUF_0__OP_MASK 0x00070000L +#define SQ_MTBUF_0__OP__SHIFT 0x00000010 +#define SQ_MTBUF_1__SLC_MASK 0x00400000L +#define SQ_MTBUF_1__SLC__SHIFT 0x00000016 +#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000L +#define SQ_MTBUF_1__SOFFSET__SHIFT 0x00000018 +#define SQ_MTBUF_1__SRSRC_MASK 0x001f0000L +#define SQ_MTBUF_1__SRSRC__SHIFT 0x00000010 +#define SQ_MTBUF_1__TFE_MASK 0x00800000L +#define SQ_MTBUF_1__TFE__SHIFT 0x00000017 +#define SQ_MTBUF_1__VADDR_MASK 0x000000ffL +#define SQ_MTBUF_1__VADDR__SHIFT 0x00000000 +#define SQ_MTBUF_1__VDATA_MASK 0x0000ff00L +#define SQ_MTBUF_1__VDATA__SHIFT 0x00000008 +#define SQ_MUBUF_0__ADDR64_MASK 0x00008000L +#define SQ_MUBUF_0__ADDR64__SHIFT 0x0000000f +#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000L +#define SQ_MUBUF_0__ENCODING__SHIFT 0x0000001a +#define SQ_MUBUF_0__GLC_MASK 0x00004000L +#define SQ_MUBUF_0__GLC__SHIFT 0x0000000e +#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L +#define SQ_MUBUF_0__IDXEN__SHIFT 0x0000000d +#define SQ_MUBUF_0__LDS_MASK 0x00010000L +#define SQ_MUBUF_0__LDS__SHIFT 0x00000010 +#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L +#define SQ_MUBUF_0__OFFEN__SHIFT 0x0000000c +#define SQ_MUBUF_0__OFFSET_MASK 0x00000fffL +#define SQ_MUBUF_0__OFFSET__SHIFT 0x00000000 +#define SQ_MUBUF_0__OP_MASK 0x01fc0000L +#define SQ_MUBUF_0__OP__SHIFT 0x00000012 +#define SQ_MUBUF_1__SLC_MASK 0x00400000L +#define SQ_MUBUF_1__SLC__SHIFT 0x00000016 +#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000L +#define SQ_MUBUF_1__SOFFSET__SHIFT 0x00000018 +#define SQ_MUBUF_1__SRSRC_MASK 0x001f0000L +#define SQ_MUBUF_1__SRSRC__SHIFT 0x00000010 +#define SQ_MUBUF_1__TFE_MASK 0x00800000L +#define SQ_MUBUF_1__TFE__SHIFT 0x00000017 +#define SQ_MUBUF_1__VADDR_MASK 0x000000ffL +#define SQ_MUBUF_1__VADDR__SHIFT 0x00000000 +#define SQ_MUBUF_1__VDATA_MASK 0x0000ff00L +#define SQ_MUBUF_1__VDATA__SHIFT 0x00000008 +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000L +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x0000001c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001ffL +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0f000000L +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x00000018 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00f00000L +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x00000014 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000f000L +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0x0000000c +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000f0000L +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x00000010 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x00000000 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001f00L +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x00000008 +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x00000006 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0x0000000d +#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L +#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x00000003 +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x00000002 +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x00000004 +#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L +#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x00000005 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x00000000 +#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L +#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x00000001 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x0000001b +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003fffL +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x00000000 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03ff0000L +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x00000010 +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x0000001f +#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000L +#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x00000010 +#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003fffL +#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x00000000 +#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000L +#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x0000001e +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007fL +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x00000000 +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x001ffc00L +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0x0000000a +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x00000007 +#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000f00L +#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x00000008 +#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L +#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x0000001f +#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L +#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x0000001e +#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L +#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x0000001c +#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003fL +#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x00000000 +#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L +#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x0000001d +#define SQ_SEC_CNT__LDS_SEC_MASK 0x0000003fL +#define SQ_SEC_CNT__LDS_SEC__SHIFT 0x00000000 +#define SQ_SEC_CNT__SGPR_SEC_MASK 0x00001f00L +#define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x00000008 +#define SQ_SEC_CNT__VGPR_SEC_MASK 0x01ff0000L +#define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x00000010 +#define SQ_SMRD__ENCODING_MASK 0xf8000000L +#define SQ_SMRD__ENCODING__SHIFT 0x0000001b +#define SQ_SMRD__IMM_MASK 0x00000100L +#define SQ_SMRD__IMM__SHIFT 0x00000008 +#define SQ_SMRD__OFFSET_MASK 0x000000ffL +#define SQ_SMRD__OFFSET__SHIFT 0x00000000 +#define SQ_SMRD__OP_MASK 0x07c00000L +#define SQ_SMRD__OP__SHIFT 0x00000016 +#define SQ_SMRD__SBASE_MASK 0x00007e00L +#define SQ_SMRD__SBASE__SHIFT 0x00000009 +#define SQ_SMRD__SDST_MASK 0x003f8000L +#define SQ_SMRD__SDST__SHIFT 0x0000000f +#define SQ_SOP1__ENCODING_MASK 0xff800000L +#define SQ_SOP1__ENCODING__SHIFT 0x00000017 +#define SQ_SOP1__OP_MASK 0x0000ff00L +#define SQ_SOP1__OP__SHIFT 0x00000008 +#define SQ_SOP1__SDST_MASK 0x007f0000L +#define SQ_SOP1__SDST__SHIFT 0x00000010 +#define SQ_SOP1__SSRC0_MASK 0x000000ffL +#define SQ_SOP1__SSRC0__SHIFT 0x00000000 +#define SQ_SOP2__ENCODING_MASK 0xc0000000L +#define SQ_SOP2__ENCODING__SHIFT 0x0000001e +#define SQ_SOP2__OP_MASK 0x3f800000L +#define SQ_SOP2__OP__SHIFT 0x00000017 +#define SQ_SOP2__SDST_MASK 0x007f0000L +#define SQ_SOP2__SDST__SHIFT 0x00000010 +#define SQ_SOP2__SSRC0_MASK 0x000000ffL +#define SQ_SOP2__SSRC0__SHIFT 0x00000000 +#define SQ_SOP2__SSRC1_MASK 0x0000ff00L +#define SQ_SOP2__SSRC1__SHIFT 0x00000008 +#define SQ_SOPC__ENCODING_MASK 0xff800000L +#define SQ_SOPC__ENCODING__SHIFT 0x00000017 +#define SQ_SOPC__OP_MASK 0x007f0000L +#define SQ_SOPC__OP__SHIFT 0x00000010 +#define SQ_SOPC__SSRC0_MASK 0x000000ffL +#define SQ_SOPC__SSRC0__SHIFT 0x00000000 +#define SQ_SOPC__SSRC1_MASK 0x0000ff00L +#define SQ_SOPC__SSRC1__SHIFT 0x00000008 +#define SQ_SOPK__ENCODING_MASK 0xf0000000L +#define SQ_SOPK__ENCODING__SHIFT 0x0000001c +#define SQ_SOPK__OP_MASK 0x0f800000L +#define SQ_SOPK__OP__SHIFT 0x00000017 +#define SQ_SOPK__SDST_MASK 0x007f0000L +#define SQ_SOPK__SDST__SHIFT 0x00000010 +#define SQ_SOPK__SIMM16_MASK 0x0000ffffL +#define SQ_SOPK__SIMM16__SHIFT 0x00000000 +#define SQ_SOPP__ENCODING_MASK 0xff800000L +#define SQ_SOPP__ENCODING__SHIFT 0x00000017 +#define SQ_SOPP__OP_MASK 0x007f0000L +#define SQ_SOPP__OP__SHIFT 0x00000010 +#define SQ_SOPP__SIMM16_MASK 0x0000ffffL +#define SQ_SOPP__SIMM16__SHIFT 0x00000000 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000ffffL +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x00000000 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000L +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000fL +#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x00000010L +#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffffL +#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffffL +#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x0000001f +#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L +#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001fL +#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000L +#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x00000007 +#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L +#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0x0000000f +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x00000019 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x00000017 +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x0000001e +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x0000001b +#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001c0000L +#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x00000012 +#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000e00L +#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x00000009 +#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001c0L +#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L +#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L +#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0x0000000f +#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L +#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L +#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x00000003 +#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L +#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x00000015 +#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x04000000L +#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x0000001a +#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L +#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x0000001d +#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L +#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x0000001f +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000ffffL +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000L +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003fffffL +#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x0000001e +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00070000L +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000007L +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L +#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x0000001f +#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L +#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x0000001d +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0x0000ffffL +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x00000018 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00ff0000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000ffffL +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0x0000fc00L +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x000001c0L +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0x0000f000L +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x00000009 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001e0L +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00ffffffL +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x00000600L +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x00000009 +#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x00000800L +#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0x0000000b +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003c0L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000c000L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003c00L +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0x0000ffffL +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x000001e0L +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x00000008 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000c00L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000c000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000c0000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x00000012 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x00000014 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00c00000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x00000016 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x00000018 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0c000000L +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x0000001a +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0x000000c0L +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01fff000L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0x0000000c +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x00000019 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000c00L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003c0L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003fL +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007ffc0L +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000L +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x00000013 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x00000007 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x00000009 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0x0000000f +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001c00L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffffL +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000L +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffffL +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x000003c0L +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0x0000c000L +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x00000016 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003c0L +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x00000006 +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001f0000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x00000010 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x00000005 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000c000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0x0000000e +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x0000001d +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x00000015 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003c00L +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x00000010L +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x00000004 +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x0000000fL +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x00000000 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x00003c00L +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0x0000000a +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000L +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x0000001e +#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffffL +#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x00000000 +#define SQ_TIME_HI__TIME_MASK 0xffffffffL +#define SQ_TIME_HI__TIME__SHIFT 0x00000000 +#define SQ_TIME_LO__TIME_MASK 0xffffffffL +#define SQ_TIME_LO__TIME__SHIFT 0x00000000 +#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L +#define SQ_VINTRP__ATTRCHAN__SHIFT 0x00000008 +#define SQ_VINTRP__ATTR_MASK 0x0000fc00L +#define SQ_VINTRP__ATTR__SHIFT 0x0000000a +#define SQ_VINTRP__ENCODING_MASK 0xfc000000L +#define SQ_VINTRP__ENCODING__SHIFT 0x0000001a +#define SQ_VINTRP__OP_MASK 0x00030000L +#define SQ_VINTRP__OP__SHIFT 0x00000010 +#define SQ_VINTRP__VDST_MASK 0x03fc0000L +#define SQ_VINTRP__VDST__SHIFT 0x00000012 +#define SQ_VINTRP__VSRC_MASK 0x000000ffL +#define SQ_VINTRP__VSRC__SHIFT 0x00000000 +#define SQ_VOP1__ENCODING_MASK 0xfe000000L +#define SQ_VOP1__ENCODING__SHIFT 0x00000019 +#define SQ_VOP1__OP_MASK 0x0001fe00L +#define SQ_VOP1__OP__SHIFT 0x00000009 +#define SQ_VOP1__SRC0_MASK 0x000001ffL +#define SQ_VOP1__SRC0__SHIFT 0x00000000 +#define SQ_VOP1__VDST_MASK 0x01fe0000L +#define SQ_VOP1__VDST__SHIFT 0x00000011 +#define SQ_VOP2__ENCODING_MASK 0x80000000L +#define SQ_VOP2__ENCODING__SHIFT 0x0000001f +#define SQ_VOP2__OP_MASK 0x7e000000L +#define SQ_VOP2__OP__SHIFT 0x00000019 +#define SQ_VOP2__SRC0_MASK 0x000001ffL +#define SQ_VOP2__SRC0__SHIFT 0x00000000 +#define SQ_VOP2__VDST_MASK 0x01fe0000L +#define SQ_VOP2__VDST__SHIFT 0x00000011 +#define SQ_VOP2__VSRC1_MASK 0x0001fe00L +#define SQ_VOP2__VSRC1__SHIFT 0x00000009 +#define SQ_VOP3_0__ABS_MASK 0x00000700L +#define SQ_VOP3_0__ABS__SHIFT 0x00000008 +#define SQ_VOP3_0__CLAMP_MASK 0x00000800L +#define SQ_VOP3_0__CLAMP__SHIFT 0x0000000b +#define SQ_VOP3_0__ENCODING_MASK 0xfc000000L +#define SQ_VOP3_0__ENCODING__SHIFT 0x0000001a +#define SQ_VOP3_0__OP_MASK 0x03fe0000L +#define SQ_VOP3_0__OP__SHIFT 0x00000011 +#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000L +#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x0000001a +#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03fe0000L +#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x00000011 +#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007f00L +#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x00000008 +#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000ffL +#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x00000000 +#define SQ_VOP3_0__VDST_MASK 0x000000ffL +#define SQ_VOP3_0__VDST__SHIFT 0x00000000 +#define SQ_VOP3_1__NEG_MASK 0xe0000000L +#define SQ_VOP3_1__NEG__SHIFT 0x0000001d +#define SQ_VOP3_1__OMOD_MASK 0x18000000L +#define SQ_VOP3_1__OMOD__SHIFT 0x0000001b +#define SQ_VOP3_1__SRC0_MASK 0x000001ffL +#define SQ_VOP3_1__SRC0__SHIFT 0x00000000 +#define SQ_VOP3_1__SRC1_MASK 0x0003fe00L +#define SQ_VOP3_1__SRC1__SHIFT 0x00000009 +#define SQ_VOP3_1__SRC2_MASK 0x07fc0000L +#define SQ_VOP3_1__SRC2__SHIFT 0x00000012 +#define SQ_VOPC__ENCODING_MASK 0xfe000000L +#define SQ_VOPC__ENCODING__SHIFT 0x00000019 +#define SQ_VOPC__OP_MASK 0x01fe0000L +#define SQ_VOPC__OP__SHIFT 0x00000011 +#define SQ_VOPC__SRC0_MASK 0x000001ffL +#define SQ_VOPC__SRC0__SHIFT 0x00000000 +#define SQ_VOPC__VSRC1_MASK 0x0001fe00L +#define SQ_VOPC__VSRC1__SHIFT 0x00000009 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffffL +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x00000000 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffffL +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x00000000 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003f0000L +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x00000010 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0f000000L +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x00000018 +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003fL +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x00000000 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003f00L +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x00000008 +#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000f00L +#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x00000008 +#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000L +#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x0000001e +#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000c0L +#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x00000006 +#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L +#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x00000018 +#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00002000L +#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0x0000000d +#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L +#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0x0000000c +#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L +#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x00000004 +#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L +#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x0000001b +#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000f0000L +#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x00000010 +#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00f00000L +#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x00000014 +#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000fL +#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x00000000 +#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x00c00000L +#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x00000016 +#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x06000000L +#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x00000019 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L +#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x00000008 +#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L +#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x00000000 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000c00L +#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0x0000000a +#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x00070000L +#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x00000010 +#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x01000000L +#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x00000018 +#define SQ_WAVE_IB_DBG0__KILL_MASK 0x08000000L +#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x0000001b +#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x00380000L +#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x00000013 +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000L +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x0000001c +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x00000004 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000e0L +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x00000005 +#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L +#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x00000003 +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x00000004 +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00001f00L +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x00000008 +#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x0000e000L +#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0x0000000d +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000fL +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x00000000 +#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffffL +#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x00000000 +#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffffL +#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x00000000 +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000ffL +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x00000000 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001ff000L +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0x0000000c +#define SQ_WAVE_M0__M0_MASK 0xffffffffL +#define SQ_WAVE_M0__M0__SHIFT 0x00000000 +#define SQ_WAVE_MODE__CSP_MASK 0xe0000000L +#define SQ_WAVE_MODE__CSP__SHIFT 0x0000001d +#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L +#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0x0000000b +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x00000008 +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x0007f000L +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0x0000000c +#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000f0L +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x00000004 +#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000fL +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x00000000 +#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L +#define SQ_WAVE_MODE__IEEE__SHIFT 0x00000009 +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0x0000000a +#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L +#define SQ_WAVE_MODE__VSKIP__SHIFT 0x0000001c +#define SQ_WAVE_PC_HI__PC_HI_MASK 0x000000ffL +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x00000000 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffffL +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x00000000 +#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L +#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x00000015 +#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L +#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x00000014 +#define SQ_WAVE_STATUS__DATA_ATC_MASK 0x00400000L +#define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x00000016 +#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x07000000L +#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x00000018 +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x00000011 +#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x00000009 +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x00000008 +#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L +#define SQ_WAVE_STATUS__HALT__SHIFT 0x0000000d +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0x0000000c +#define SQ_WAVE_STATUS__INST_ATC_MASK 0x00800000L +#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x00000017 +#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0x0000000b +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x0000001b +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x00000013 +#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x00000005 +#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L +#define SQ_WAVE_STATUS__SCC__SHIFT 0x00000000 +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x00000012 +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x00000001 +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x00000006 +#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L +#define SQ_WAVE_STATUS__TRAP__SHIFT 0x0000000e +#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L +#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0x0000000f +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x00000007 +#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L +#define SQ_WAVE_STATUS__VALID__SHIFT 0x00000010 +#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0x0000000a +#define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x00000018L +#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x00000003 +#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0x000000ffL +#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x00000000 +#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffffL +#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x00000000 +#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0x000000ffL +#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x00000000 +#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffffL +#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x00000000 +#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000L +#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x0000001d +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003f0000L +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x00000010 +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x0000007fL +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x00000000 +#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x00000000 +#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffffL +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x00000000 +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80L +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x00000007 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007fL +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x00000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x0000001f +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x0000001e +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x0000001d +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x0000001c +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x0000001b +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x0000001a +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x00000019 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x00000017 +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x01000000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x00000018 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x00000016 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x00000014 +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x00200000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x00000015 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x00000013 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x00000011 +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x00040000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x00000012 +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x00000010 +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0x0000000e +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x00008000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0x0000000f +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x0000000d +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0x0000000c +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x00000400L +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0x0000000a +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x00000800L +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0x0000000b +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x00000009 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x00000080L +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x00000007 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x00000100L +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x00000008 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x00000006 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x00000010L +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x00000004 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x00000020L +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x00000005 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x00000003 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x00000002L +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x00000001 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x00000004L +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x00000002 +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x00000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x0000001f +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x0000001e +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x0000001d +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x0000001c +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x0000001b +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x0000001a +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x00000019 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x00000018 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x00000017 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x00000016 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x00000015 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x00000014 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x00000013 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x00000012 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x00000011 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x00000010 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x0000000f +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x0000000e +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x0000000d +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x0000000c +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x0000000b +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x0000000a +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x00000009 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x00000008 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x00000007 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x00000006 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x00000005 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x00000004 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x00000003 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x00000002 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x00000001 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x00000000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x00000018 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x00000017 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x00000016 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x00000015 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x00000014 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x00000013 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x00000012 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x00000011 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x00000010 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x0000000f +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x0000000e +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x0000000d +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x0000000c +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x0000000b +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x0000000a +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x00000009 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x00000008 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x00000007 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x00000006 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x00000005 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x00000004 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x00000003 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x00000002 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x00000001 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x00000000 +#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000L +#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x00000019 +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x0000001f +#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L +#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x0000001e +#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x00000002 +#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L +#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x0000001b +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x00000013 +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x00000012 +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x00000011 +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x00000010 +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0x0000000f +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0x0000000e +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0x0000000d +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0x0000000c +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0x0000000b +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0x0000000a +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x00000009 +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x00000008 +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x00000007 +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x00000006 +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x00000005 +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x00000004 +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x00000000 +#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L +#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x00000014 +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x00000001 +#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x00000003 +#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L +#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x0000001d +#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L +#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x0000001c +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x0000001a +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x00000019 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x00000018 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x00000017 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x00000016 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x000001c0L +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x00000006 +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x0000003fL +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x0000001f +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x0c000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x03ff0000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x0000f000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00000e00L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x0000007fL +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0x0f000000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x00000018 +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x00007c00L +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x00800000L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x00400000L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x0000007fL +#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x007f0000L +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000180L +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x00007e00L +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x03800000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0x000000ffL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x001fc000L +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000L +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001d +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x0000001f +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x00002000L +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x00001000L +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x02000000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000019 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00800000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x01000000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x00000018 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x0000001c +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003ffL +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x00000000 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000ffc00L +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0x0000000a +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000ffc00L +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0x0000000a +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000 +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001f0000L +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x00000010 +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x00000010 +#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000e000L +#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0x0000000d +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000L +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x00000016 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffffL +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x00000000 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000ffL +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x00000000 +#define TA_DEBUG_DATA__DATA_MASK 0xffffffffL +#define TA_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define TA_DEBUG_INDEX__INDEX_MASK 0x0000001fL +#define TA_DEBUG_INDEX__INDEX__SHIFT 0x00000000 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003fc00L +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TA_SCRATCH__SCRATCH_MASK 0xffffffffL +#define TA_SCRATCH__SCRATCH__SHIFT 0x00000000 +#define TA_STATUS__AL_BUSY_MASK 0x40000000L +#define TA_STATUS__AL_BUSY__SHIFT 0x0000001e +#define TA_STATUS__BUSY_MASK 0x80000000L +#define TA_STATUS__BUSY__SHIFT 0x0000001f +#define TA_STATUS__FA_BUSY_MASK 0x20000000L +#define TA_STATUS__FA_BUSY__SHIFT 0x0000001d +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x00000015 +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x00000014 +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x00000016 +#define TA_STATUS__FG_BUSY_MASK 0x02000000L +#define TA_STATUS__FG_BUSY__SHIFT 0x00000019 +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0x0000000d +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0x0000000c +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0x0000000e +#define TA_STATUS__FL_BUSY_MASK 0x08000000L +#define TA_STATUS__FL_BUSY__SHIFT 0x0000001b +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x00000011 +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x00000010 +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x00000012 +#define TA_STATUS__IN_BUSY_MASK 0x01000000L +#define TA_STATUS__IN_BUSY__SHIFT 0x00000018 +#define TA_STATUS__LA_BUSY_MASK 0x04000000L +#define TA_STATUS__LA_BUSY__SHIFT 0x0000001a +#define TA_STATUS__TA_BUSY_MASK 0x10000000L +#define TA_STATUS__TA_BUSY__SHIFT 0x0000001c +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000fL +#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x00000000 +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL +#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L +#define TCC_CTRL__CACHE_SIZE__SHIFT 0x00000000 +#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000f0000L +#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x00000010 +#define TCC_CTRL__RATE_MASK 0x0000000cL +#define TCC_CTRL__RATE__SHIFT 0x00000002 +#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000f000L +#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0x0000000c +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x00100000L +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x00000014 +#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000f0L +#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x00000004 +#define TCC_EDC_COUNTER__DED_COUNT_MASK 0x000f0000L +#define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x00000010 +#define TCC_EDC_COUNTER__SEC_COUNT_MASK 0x0000000fL +#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x00000000 +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0f000000L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x00000018 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000L +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x0000001c +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0f000000L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x00000018 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000L +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x0000001c +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00ff0000L +#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x00000010 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000ffffL +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x00000000 +#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000L +#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x00000018 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x00000000 +#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001feL +#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x00000001 +#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L +#define TCI_STATUS__TCI_BUSY__SHIFT 0x00000000 +#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001c0L +#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x00000006 +#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L +#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x00000004 +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000fL +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x00000000 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x00000009 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x00000008 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x00000018 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x00000000 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x00000010 +#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000fL +#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x00000000 +#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000f0L +#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x00000004 +#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000f00L +#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x00000008 +#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000f000L +#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0x0000000c +#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000f0000L +#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x00000010 +#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00f00000L +#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x00000014 +#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0f000000L +#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x00000018 +#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000L +#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x0000001c +#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000fL +#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x00000000 +#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000f0L +#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x00000004 +#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000f00L +#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x00000008 +#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000f000L +#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0x0000000c +#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000f0000L +#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x00000010 +#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00f00000L +#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x00000014 +#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0f000000L +#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x00000018 +#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000L +#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x0000001c +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x0000001c +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x00000005 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x00000004 +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0fc00000L +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x00000016 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001f8000L +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0x0000000f +#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L +#define TCP_CNTL__FORCE_HIT__SHIFT 0x00000000 +#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L +#define TCP_CNTL__FORCE_MISS__SHIFT 0x00000001 +#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L +#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x0000001d +#define TCP_CNTL__L1_SIZE_MASK 0x0000000cL +#define TCP_CNTL__L1_SIZE__SHIFT 0x00000002 +#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003ffL +#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x00000000 +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007f0000L +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x00000010 +#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000L +#define TCP_CREDIT__TD_CREDIT__SHIFT 0x0000001d +#define TCP_EDC_COUNTER__DED_COUNT_MASK 0x000f0000L +#define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x00000010 +#define TCP_EDC_COUNTER__SEC_COUNT_MASK 0x0000000fL +#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x00000000 +#define TCP_INVALIDATE__START_MASK 0x00000001L +#define TCP_INVALIDATE__START__SHIFT 0x00000000 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L +#define TCP_STATUS__TCP_BUSY__SHIFT 0x00000000 +#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L +#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004 +#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000fL +#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x00000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f +#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e +#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d +#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c +#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b +#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a +#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018 +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x00000014 +#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L +#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x00000009 +#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L +#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x00000013 +#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L +#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x00000010 +#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L +#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x00000012 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L +#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0x0000000b +#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L +#define TD_CNTL__PAD_STALL_EN__SHIFT 0x00000008 +#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L +#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0x0000000f +#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L +#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x00000000 +#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L +#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x00000004 +#define TD_DEBUG_DATA__DATA_MASK 0x00ffffffL +#define TD_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define TD_DEBUG_INDEX__INDEX_MASK 0x0000001fL +#define TD_DEBUG_INDEX__INDEX__SHIFT 0x00000000 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000ffL +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003fc00L +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003fc00L +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define TD_SCRATCH__SCRATCH_MASK 0xffffffffL +#define TD_SCRATCH__SCRATCH__SHIFT 0x00000000 +#define TD_STATUS__BUSY_MASK 0x80000000L +#define TD_STATUS__BUSY__SHIFT 0x0000001f +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010 +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014 +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018 +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000c0L +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x00000006 +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x00000000 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0x0000000b +#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001f0000L +#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x00000010 +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0x0000000c +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0x0000000d +#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L +#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x00000009 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x00000008 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L +#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x00000009 +#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000005 +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000003fL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x00000040L +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x00000006 +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__cm_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__cm_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x00200000L +#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x00000015 +#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x04000000L +#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x0000001a +#define VGT_DEBUG_REG0__frmt_busy_MASK 0x00020000L +#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x00000011 +#define VGT_DEBUG_REG0__gog_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x00000010 +#define VGT_DEBUG_REG0__gs_busy_MASK 0x00001000L +#define VGT_DEBUG_REG0__gs_busy__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x08000000L +#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x0000001b +#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x00800000L +#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x00000017 +#define VGT_DEBUG_REG0__pi_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x00000400L +#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__rcm_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x01000000L +#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x00000018 +#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000L +#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x0000001d +#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000L +#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x0000001e +#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000L +#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x0000001f +#define VGT_DEBUG_REG0__SPARE10_MASK 0x00040000L +#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x00000012 +#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000L +#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x0000001c +#define VGT_DEBUG_REG0__SPARE2_MASK 0x02000000L +#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x00000019 +#define VGT_DEBUG_REG0__SPARE3_MASK 0x00100000L +#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x00000014 +#define VGT_DEBUG_REG0__SPARE4_MASK 0x00000080L +#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__SPARE5_MASK 0x00000040L +#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__SPARE6_MASK 0x00000020L +#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__SPARE7_MASK 0x00000010L +#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__SPARE8_MASK 0x00000008L +#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__SPARE9_MASK 0x00000002L +#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x00400000L +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x00000016 +#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x00080000L +#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x00000013 +#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__tm_busy_MASK 0x00004000L +#define VGT_DEBUG_REG0__tm_busy__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00000001L +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x00000020L +#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x00000040L +#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000L +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x00000017 +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x007fe000L +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0x0000000d +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x0000001fL +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x00000180L +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x00001000L +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x00000800L +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG10__SPARE2_MASK 0x00000600L +#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x00000009 +#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x00001000L +#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0x0000000c +#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x00000800L +#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0x0000000b +#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x00000400L +#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0x0000000a +#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x00000008L +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x08000000L +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x0000001b +#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x00000200L +#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x00000009 +#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000L +#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x0000001e +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x00200000L +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x00000015 +#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x00010000L +#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x00000010 +#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x00080000L +#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x00000013 +#define VGT_DEBUG_REG11__hold_eswave_MASK 0x00000100L +#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x00000008 +#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000L +#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x0000001f +#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000L +#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x0000001d +#define VGT_DEBUG_REG11__SPARE0_MASK 0x00040000L +#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x00000012 +#define VGT_DEBUG_REG11__SPARE1_MASK 0x00000020L +#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x00000005 +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x00000080L +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x00000040L +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x00000001L +#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x00000002L +#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x00000004L +#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x00020000L +#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x00000011 +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x00800000L +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x00000017 +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x00008000L +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x00004000L +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x00000010L +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000L +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x0000001c +#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x02000000L +#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x00000019 +#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x04000000L +#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x0000001a +#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x00000007L +#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x00000038L +#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x00000003 +#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x000001c0L +#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0x00000e00L +#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x00007000L +#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x00038000L +#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x001c0000L +#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0x00e00000L +#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x07000000L +#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000L +#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000L +#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x0000001e +#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000L +#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x0000001f +#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000L +#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x01000000L +#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x00800000L +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x00000017 +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x00400000L +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x00000016 +#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x00000007L +#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x00000038L +#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x00000003 +#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x000001c0L +#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0x00000e00L +#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x00007000L +#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x00038000L +#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x003c0000L +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x00000012 +#define VGT_DEBUG_REG13__SPARE0_MASK 0x04000000L +#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x0000001a +#define VGT_DEBUG_REG13__SPARE1_MASK 0x02000000L +#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x00000019 +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x00000400L +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000L +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x0000001d +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x00000020L +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x00000005 +#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x00000800L +#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0x0000000b +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x08000000L +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x0000001b +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x00200000L +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x00000015 +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x04000000L +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x0000001a +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x00000040L +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x00000006 +#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000L +#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x0000001e +#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000L +#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x0000001c +#define VGT_DEBUG_REG14__SPARE2_MASK 0x001ff000L +#define VGT_DEBUG_REG14__SPARE2__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__SPARE3_MASK 0x0000000fL +#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__SPARE8_MASK 0x00000180L +#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__SPARE_MASK 0x01c00000L +#define VGT_DEBUG_REG14__SPARE__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000L +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x0000001f +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x02000000L +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x00000019 +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x00000200L +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x00000009 +#define VGT_DEBUG_REG15__active_sm_q_MASK 0x000003e0L +#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x00000001L +#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0x000f8000L +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x00000002L +#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG15__counters_full_MASK 0x00000010L +#define VGT_DEBUG_REG15__counters_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000L +#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x0000001c +#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x00000004L +#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x00000002 +#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x00000008L +#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x00000003 +#define VGT_DEBUG_REG15__SPARE25_MASK 0x03f00000L +#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000L +#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x0000001d +#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0x0c000000L +#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG16__gog_busy_MASK 0x00000001L +#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0x0e000000L +#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x00000019 +#define VGT_DEBUG_REG16__gog_state_q_MASK 0x0000000eL +#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x00080000L +#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x00002000L +#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000L +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x0000001c +#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000L +#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x0000001f +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000L +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x00100000L +#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__r0_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__r1_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x00000040L +#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x00000200L +#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x00000100L +#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__r2_rtr_MASK 0x00000400L +#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x00000080L +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__send_event_q_MASK 0x00400000L +#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG16__SPARE24_MASK 0x01800000L +#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x00000017 +#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x00200000L +#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x00040000L +#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x01000000L +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000L +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x0000001d +#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000L +#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x00000012 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x0003f000L +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0x00000fc0L +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x0000003fL +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000L +#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x00800000L +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x00400000L +#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x00000001L +#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x08000000L +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000L +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x00000700L +#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x00040000L +#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x00002000L +#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x00020000L +#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x00004000L +#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x00010000L +#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x00008000L +#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x00100000L +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x00001000L +#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x00200000L +#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x00000040L +#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x00000080L +#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x00000007 +#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x00000002L +#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x00000004L +#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x00080000L +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x07000000L +#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__valid_indices_MASK 0x00000800L +#define VGT_DEBUG_REG18__valid_indices__SHIFT 0x0000000b +#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x00000008L +#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x00000003 +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x00080000L +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x00000013 +#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x00040000L +#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x00000012 +#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x00010000L +#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x00000010 +#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x00020000L +#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x00000011 +#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x03f00000L +#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x00000014 +#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000L +#define VGT_DEBUG_REG19__filter_event__SHIFT 0x0000001f +#define VGT_DEBUG_REG19__hold_prim_MASK 0x00000800L +#define VGT_DEBUG_REG19__hold_prim__SHIFT 0x0000000b +#define VGT_DEBUG_REG19__new_packet_q_MASK 0x00008000L +#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000L +#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x0000001e +#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000L +#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x0000001c +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x00000020L +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x00000010L +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x00000400L +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x00000004L +#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x00000002 +#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x00000008L +#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x00000003 +#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x00000001L +#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x00000002L +#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x00000100L +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x00000200L +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x00000080L +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x00000040L +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x00004000L +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x08000000L +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x04000000L +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x00001000L +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x00002000L +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000L +#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000L +#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x0000001e +#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x08000000L +#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000L +#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000L +#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x0000001f +#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x04000000L +#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x00001000L +#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x00004000L +#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x00000400L +#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00100000L +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00400000L +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x00002000L +#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__SPARE0_MASK 0x00000200L +#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__SPARE10_MASK 0x00200000L +#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__SPARE11_MASK 0x00080000L +#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__SPARE12_MASK 0x00020000L +#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__SPARE1_MASK 0x00000100L +#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__SPARE23_MASK 0x00800000L +#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__SPARE25_MASK 0x02000000L +#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__SPARE2_MASK 0x00000080L +#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__SPARE3_MASK 0x00000040L +#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__SPARE4_MASK 0x00000020L +#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__SPARE5_MASK 0x00000010L +#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__SPARE6_MASK 0x00000008L +#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__SPARE7_MASK 0x00000004L +#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__SPARE8_MASK 0x00000002L +#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__SPARE9_MASK 0x00000001L +#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00008000L +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x01000000L +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00010000L +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00040000L +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x00000800L +#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x003c0000L +#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000L +#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000L +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x0000001e +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x00010000L +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x00000010 +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0x0000ffffL +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000L +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x0000001f +#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000L +#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x0000001d +#define VGT_DEBUG_REG20__SPARE17_MASK 0x00020000L +#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x00000011 +#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x01000000L +#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000L +#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x04000000L +#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x00008000L +#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x00002000L +#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0x0000000d +#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x00000080L +#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x00010000L +#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x00000010 +#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x00100000L +#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x00200000L +#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x00000015 +#define VGT_DEBUG_REG21__null_r2_q_MASK 0x08000000L +#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x00000001L +#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x00000040L +#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x00000006 +#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000L +#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x0000001c +#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000L +#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x0000001f +#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000L +#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x0000001d +#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x00000004L +#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x00000100L +#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x00000008 +#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x00000008L +#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x00000003 +#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x00000200L +#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x00000009 +#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x00000010L +#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x00000400L +#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0x000e0000L +#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x02000000L +#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x00000020L +#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x00000800L +#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0x0000000b +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x00800000L +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x00004000L +#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG22__cm_state16_MASK 0x00000003L +#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x00000000 +#define VGT_DEBUG_REG22__cm_state17_MASK 0x0000000cL +#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x00000002 +#define VGT_DEBUG_REG22__cm_state18_MASK 0x00000030L +#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x00000004 +#define VGT_DEBUG_REG22__cm_state19_MASK 0x000000c0L +#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x00000006 +#define VGT_DEBUG_REG22__cm_state20_MASK 0x00000300L +#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x00000008 +#define VGT_DEBUG_REG22__cm_state21_MASK 0x00000c00L +#define VGT_DEBUG_REG22__cm_state21__SHIFT 0x0000000a +#define VGT_DEBUG_REG22__cm_state22_MASK 0x00003000L +#define VGT_DEBUG_REG22__cm_state22__SHIFT 0x0000000c +#define VGT_DEBUG_REG22__cm_state23_MASK 0x0000c000L +#define VGT_DEBUG_REG22__cm_state23__SHIFT 0x0000000e +#define VGT_DEBUG_REG22__cm_state24_MASK 0x00030000L +#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x00000010 +#define VGT_DEBUG_REG22__cm_state25_MASK 0x000c0000L +#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x00000012 +#define VGT_DEBUG_REG22__cm_state26_MASK 0x00300000L +#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x00000014 +#define VGT_DEBUG_REG22__cm_state27_MASK 0x00c00000L +#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x00000016 +#define VGT_DEBUG_REG22__cm_state28_MASK 0x03000000L +#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x00000018 +#define VGT_DEBUG_REG22__cm_state29_MASK 0x0c000000L +#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x0000001a +#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000L +#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x0000001c +#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000L +#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x0000001e +#define VGT_DEBUG_REG23__frmt_busy_MASK 0x00000001L +#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x00018000L +#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x00001000L +#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x00000200L +#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x00000400L +#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0x0000000a +#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x00000008L +#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x00000003 +#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0x00e00000L +#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x00000004L +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x00000002 +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x00000002L +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x00000001 +#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000L +#define VGT_DEBUG_REG23__SPARE__SHIFT 0x00000018 +#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x00004000L +#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x00002000L +#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x00000800L +#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x00000100L +#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x00000008 +#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x00000080L +#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x00000007 +#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x00000040L +#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x00000006 +#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x001e0000L +#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0x00ffffffL +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x00000000 +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x03000000L +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000L +#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x0000001a +#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000L +#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000L +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x0000001f +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000L +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x03ffffffL +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x00000000 +#define VGT_DEBUG_REG26__cm_state0_MASK 0x00000003L +#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x00000000 +#define VGT_DEBUG_REG26__cm_state10_MASK 0x00300000L +#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x00000014 +#define VGT_DEBUG_REG26__cm_state11_MASK 0x00c00000L +#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x00000016 +#define VGT_DEBUG_REG26__cm_state12_MASK 0x03000000L +#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x00000018 +#define VGT_DEBUG_REG26__cm_state13_MASK 0x0c000000L +#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x0000001a +#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000L +#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x0000001c +#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000L +#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x0000001e +#define VGT_DEBUG_REG26__cm_state1_MASK 0x0000000cL +#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x00000002 +#define VGT_DEBUG_REG26__cm_state2_MASK 0x00000030L +#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x00000004 +#define VGT_DEBUG_REG26__cm_state3_MASK 0x000000c0L +#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x00000006 +#define VGT_DEBUG_REG26__cm_state4_MASK 0x00000300L +#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x00000008 +#define VGT_DEBUG_REG26__cm_state5_MASK 0x00000c00L +#define VGT_DEBUG_REG26__cm_state5__SHIFT 0x0000000a +#define VGT_DEBUG_REG26__cm_state6_MASK 0x00003000L +#define VGT_DEBUG_REG26__cm_state6__SHIFT 0x0000000c +#define VGT_DEBUG_REG26__cm_state7_MASK 0x0000c000L +#define VGT_DEBUG_REG26__cm_state7__SHIFT 0x0000000e +#define VGT_DEBUG_REG26__cm_state8_MASK 0x00030000L +#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x00000010 +#define VGT_DEBUG_REG26__cm_state9_MASK 0x000c0000L +#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x00000012 +#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x00000800L +#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x00000400L +#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x00080000L +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x00000002L +#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x00010000L +#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x00000010 +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x00020000L +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x00008000L +#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000L +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x00004000L +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x00003000L +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x00000300L +#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x00000080L +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x00040000L +#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x00000012 +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000L +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x0000001f +#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x00000001L +#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x00000004L +#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x00000040L +#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x00000006 +#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x00000008L +#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x00000003 +#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x00800000L +#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x00000017 +#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x00400000L +#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x00000016 +#define VGT_DEBUG_REG28__con_state_q_MASK 0x0000000fL +#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x00010000L +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x00040000L +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x00100000L +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x00000014 +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x00080000L +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x00000013 +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x00020000L +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x01000000L +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x00004000L +#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x00008000L +#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x00000200L +#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x00000009 +#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x00000100L +#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x00000400L +#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0x0000000a +#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000L +#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x0000001e +#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x02000000L +#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x00000019 +#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000L +#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x0000001d +#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x00000080L +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x00000020L +#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x00000010L +#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000L +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x0000001f +#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x00800000L +#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x00000017 +#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x00400000L +#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x00000016 +#define VGT_DEBUG_REG29__con_state_q_MASK 0x0000000fL +#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x00010000L +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x00040000L +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x00100000L +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x00000014 +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x00080000L +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x00000013 +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x00020000L +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x01000000L +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x00004000L +#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x00008000L +#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x00000200L +#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x00000009 +#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x00000100L +#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x00000400L +#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0x0000000a +#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000L +#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x0000001e +#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x02000000L +#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x00000019 +#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000L +#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x0000001d +#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x00000080L +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x00000020L +#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x00000010L +#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000L +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x0000001f +#define VGT_DEBUG_REG2__grpModBusy_MASK 0x00000080L +#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x00000007 +#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x00001000L +#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0x0000000c +#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x00040000L +#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x00000012 +#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x00000002L +#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x00000040L +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x00000006 +#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x00002000L +#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0x0000000d +#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x00080000L +#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x00000013 +#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x00000400L +#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0x0000000a +#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x00010000L +#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x00000010 +#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x00000800L +#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0x0000000b +#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x00020000L +#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x00000011 +#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x08000000L +#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x0000001b +#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x04000000L +#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x0000001a +#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x00000100L +#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x00000008 +#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x00004000L +#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0x0000000e +#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x00000008L +#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x00000003 +#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x00000200L +#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x00000009 +#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x00008000L +#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0x0000000f +#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x00000020L +#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x00000005 +#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000L +#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x0000001c +#define VGT_DEBUG_REG2__p0_dr_MASK 0x00400000L +#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x00000016 +#define VGT_DEBUG_REG2__p0_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG2__p0_rts_MASK 0x01000000L +#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x00000018 +#define VGT_DEBUG_REG2__p1_dr_MASK 0x00800000L +#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x00000017 +#define VGT_DEBUG_REG2__p1_rtr_MASK 0x00200000L +#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x00000015 +#define VGT_DEBUG_REG2__p1_rts_MASK 0x02000000L +#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x00000019 +#define VGT_DEBUG_REG2__SPARE_MASK 0xffffffffL +#define VGT_DEBUG_REG2__SPARE__SHIFT 0x00000000 +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x00000004L +#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x00000002 +#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x01000000L +#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x00000008L +#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x00000003 +#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x08000000L +#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x04000000L +#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x02000000L +#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x00000019 +#define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x00080000L +#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x00000013 +#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x00000001L +#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x00000002L +#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x00000020L +#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x00000005 +#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x00000040L +#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x00000006 +#define VGT_DEBUG_REG30__pipe2_dr_MASK 0x00000004L +#define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x00000080L +#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x00000007 +#define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000L +#define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x0000001e +#define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000L +#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x0000001f +#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x00070000L +#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0x00f00000L +#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000L +#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x0000001c +#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x00000200L +#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x00000100L +#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x00000400L +#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0x0000000a +#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x00000800L +#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0x0000000b +#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x00001000L +#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0x0000000c +#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x00002000L +#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0x0000000d +#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x00004000L +#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0x0000000e +#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x00008000L +#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0x0000000f +#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000L +#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x0000001f +#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000L +#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x00400000L +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x00000016 +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x00800000L +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x00000017 +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x00100000L +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x00000014 +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x00200000L +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x00000015 +#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x02000000L +#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x00000019 +#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000L +#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x0000001c +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x04000000L +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x0000001a +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000L +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x0000001d +#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x01000000L +#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x08000000L +#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x0000001b +#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x00000001L +#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x00000002L +#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x00000001 +#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x00000008L +#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x00000003 +#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x00000004L +#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x00000020L +#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x00000005 +#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x00000010L +#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x00000004 +#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x00000080L +#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x00000007 +#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x00008000L +#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0x0000000f +#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x00000040L +#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x00000006 +#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x00004000L +#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0x0000000e +#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x00000200L +#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x00000009 +#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x00020000L +#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x00000011 +#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x00000100L +#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x00010000L +#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x00000010 +#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x00000800L +#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0x0000000b +#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x00080000L +#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x00000013 +#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x00000400L +#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0x0000000a +#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x00040000L +#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x00000012 +#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x00000100L +#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x00000080L +#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x00000400L +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x00000200L +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x00000001L +#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x00000000 +#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x02000000L +#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x00000019 +#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x00000010L +#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x00000004 +#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x00000004L +#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x00000002 +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x00000040L +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x00000800L +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x00000020L +#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x00000005 +#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x00000008L +#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x00000003 +#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x00000002L +#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x00000001 +#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x00020000L +#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x00000011 +#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x00010000L +#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x00000010 +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x00100000L +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x00000014 +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x00040000L +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x00000012 +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x00400000L +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x00000016 +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x00200000L +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x00080000L +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x00000013 +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x00800000L +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x00000017 +#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x00008000L +#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0x0000000f +#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x00004000L +#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0x0000000e +#define VGT_DEBUG_REG32__SPARE_MASK 0x80000000L +#define VGT_DEBUG_REG32__SPARE__SHIFT 0x0000001f +#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x00003000L +#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x00040000L +#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x00010000L +#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x00000010 +#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000L +#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x0000001f +#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000L +#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x0000001e +#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000L +#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x0000001d +#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x00080000L +#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x00000013 +#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x00020000L +#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x00000011 +#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x00008000L +#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x00100000L +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x00000001L +#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x00000004L +#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x00000008L +#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x00000003 +#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x00000080L +#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x00000007 +#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x00000100L +#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x00000200L +#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x00000009 +#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x00000800L +#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x00000040L +#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x00000006 +#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x00800000L +#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x00000017 +#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x00000400L +#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x00000020L +#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x00000005 +#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x00400000L +#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x00000016 +#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x00002000L +#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x00000002L +#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x00200000L +#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x00000015 +#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000L +#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x0000001c +#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0x0c000000L +#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x03000000L +#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x00004000L +#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0x0000000e +#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x00800000L +#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x00000017 +#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x00400000L +#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x00000016 +#define VGT_DEBUG_REG34__con_state_q_MASK 0x0000000fL +#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x00010000L +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x00040000L +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x00100000L +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x00000014 +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x00080000L +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x00000013 +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x00020000L +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x01000000L +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x00200000L +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x00000015 +#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x00004000L +#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x00008000L +#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x00000200L +#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x00000009 +#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x00000100L +#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x00000008 +#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x00000400L +#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0x0000000a +#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000L +#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x0000001e +#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x02000000L +#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x00000019 +#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000L +#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x0000001d +#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x00000040L +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x00000080L +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x00000020L +#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x00000010L +#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000L +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x0000001f +#define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x00040000L +#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000L +#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x0000001c +#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x00000800L +#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0x0000000b +#define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x00080000L +#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG35__pipe0_dr_MASK 0x00000001L +#define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x00000000 +#define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x00000004L +#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x00000002 +#define VGT_DEBUG_REG35__pipe1_dr_MASK 0x00000002L +#define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x00000001 +#define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x00000008L +#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x00000003 +#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x08000000L +#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x0003f000L +#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000L +#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x0000001f +#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x00000040L +#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x07f00000L +#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x00000080L +#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x00000010L +#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x00000004 +#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x00000020L +#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x00000005 +#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x00000100L +#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x00000008 +#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x00000200L +#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x00000009 +#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000L +#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x0000001e +#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x00000400L +#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000L +#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x0000001d +#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000L +#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x0000001a +#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x03fc0000L +#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x00000012 +#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0x00000fffL +#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x0003f000L +#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0x0000000c +#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000L +#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x00000018 +#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000L +#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x0000001e +#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0x000000ffL +#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x00000000 +#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0x00ffff00L +#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x00000008 +#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000L +#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x0000001d +#define VGT_DEBUG_REG4__SPARE_MASK 0xffffffffL +#define VGT_DEBUG_REG4__SPARE__SHIFT 0x00000000 +#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0x0000f800L +#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0x0000000b +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0x000000f8L +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x00000003 +#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000L +#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x0000001b +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0x00f80000L +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x00000013 +#define VGT_DEBUG_REG5__SPARE1_MASK 0x07000000L +#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x00000018 +#define VGT_DEBUG_REG5__SPARE2_MASK 0x00070000L +#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x00000010 +#define VGT_DEBUG_REG5__SPARE3_MASK 0x00000700L +#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x00000008 +#define VGT_DEBUG_REG5__SPARE4_MASK 0x00000007L +#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__debug_BASE_MASK 0x0000ffffL +#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000L +#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x00000001L +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x00000002L +#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x00000001 +#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x00000004L +#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x00000002 +#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x00000008L +#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x00000003 +#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x00000010L +#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x00000004 +#define VGT_DEBUG_REG7__SPARE_MASK 0x0000ffe0L +#define VGT_DEBUG_REG7__SPARE__SHIFT 0x00000005 +#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000L +#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x00000010 +#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x00004000L +#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0x0000000e +#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x02000000L +#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x00000019 +#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x00008000L +#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0x0000000f +#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x04000000L +#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x0000001a +#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x08000000L +#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x00020000L +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x00000020L +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x01000000L +#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x00000018 +#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x00040000L +#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG8__r0_rtr_MASK 0x00000400L +#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0x0000000a +#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x00000004L +#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__r1_rtr_MASK 0x00000800L +#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0x0000000b +#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x00001000L +#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x00800000L +#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x00000017 +#define VGT_DEBUG_REG8__r2_rtr_MASK 0x00002000L +#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0x0000000d +#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x00000001L +#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x00000002L +#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x00000010L +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x00000008L +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x00000003 +#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000L +#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x0000001c +#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000L +#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x0000001d +#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000L +#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x0000001e +#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000L +#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x0000001f +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x00200000L +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x00000015 +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x00010000L +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x00000010 +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x00000040L +#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x00000080L +#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__valid_r2_MASK 0x00000100L +#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x00000200L +#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x00000008 +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x00400000L +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x00080000L +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x00000010L +#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x00000004 +#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x00000020L +#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x00000040L +#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x00000006 +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x02000000L +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x00000080L +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x00000007 +#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x00000008L +#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x00000003 +#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x01000000L +#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x00400000L +#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x04000000L +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x0000001a +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x00040000L +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x00000400L +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x0003f800L +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x00380000L +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x00000003L +#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x00800000L +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x00000017 +#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000L +#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x0000001f +#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x00000200L +#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x00000009 +#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x00000100L +#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x00000008 +#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000L +#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x0000001e +#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x00000004L +#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x00000002 +#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000L +#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x0000001d +#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000L +#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x0000001c +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x000000ffL +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x00000000 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001ffL +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x00000000 +#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L +#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x00000008 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x00000004 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x00000009 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000c0L +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x00000006 +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0x0000000a +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000cL +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x00000002 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffffL +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x00000000 +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003fL +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x00000000 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffffL +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x00000000 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003fL +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000cL +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x00000002 +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x00000005 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x00000004 +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x00000006 +#define VGT_ENHANCE__MISC_MASK 0xffffffffL +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 +#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL +#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 +#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007ffL +#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x00000000 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0fffffffL +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x00000000 +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07fc0000L +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x00000012 +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x0000001b +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003fff00L +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x00000008 +#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L +#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x00000007 +#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0xffc00000L +#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x00000016 +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007fL +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x00000000 +#define VGT_GROUP_DECR__DECR_MASK 0x0000000fL +#define VGT_GROUP_DECR__DECR__SHIFT 0x00000000 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000fL +#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x00000000 +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x00000010 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001fL +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0x0000000e +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0x0000000f +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x00000003 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x00000000 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x00000001 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x00000002 +#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00ff0000L +#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x00000010 +#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000ff00L +#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x00000008 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0f000000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x00000018 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000L +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000fL +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x00000000 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000f0L +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000f00L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x00000008 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000f0000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x00000010 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x00000003 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x00000000 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x00000001 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x00000002 +#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00ff0000L +#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x00000010 +#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000ff00L +#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x00000008 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0f000000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x00000018 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000L +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x0000001c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000fL +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x00000000 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000f0L +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x00000004 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000f00L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x00000008 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000f000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0x0000000c +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000f0000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x00000010 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00f00000L +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x00000014 +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001fcL +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x00000002 +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x00000000 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007ffL +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x00000000 +#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x00004000L +#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0x0000000e +#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L +#define VGT_GS_MODE__CUT_MODE__SHIFT 0x00000004 +#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x00010000L +#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x00000010 +#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L +#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0x0000000d +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x00000013 +#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x00008000L +#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0x0000000f +#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L +#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0x0000000b +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x00000014 +#define VGT_GS_MODE__MODE_MASK 0x00000007L +#define VGT_GS_MODE__MODE__SHIFT 0x00000000 +#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L +#define VGT_GS_MODE__ONCHIP__SHIFT 0x00000015 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x00000011 +#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L +#define VGT_GS_MODE__RESERVED_0__SHIFT 0x00000003 +#define VGT_GS_MODE__RESERVED_1_MASK 0x000007c0L +#define VGT_GS_MODE__RESERVED_1__SHIFT 0x00000006 +#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L +#define VGT_GS_MODE__RESERVED_2__SHIFT 0x0000000c +#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L +#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x00000012 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003f00L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x00000008 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003f0000L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x00000010 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0fc00000L +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x00000016 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003fL +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x00000000 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x0000001f +#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007ffL +#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x00000000 +#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000fL +#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x00000000 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001fL +#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x00000000 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007fffL +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007fffL +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007fffL +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007fffL +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x00000000 +#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007fffL +#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x00000000 +#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007fffL +#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x00000000 +#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007fffL +#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x00000000 +#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffffL +#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x00000000 +#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L +#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x00000000 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffffL +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x00000000 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffffL +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x00000000 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000ffL +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x00000000 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x0000007fL +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x00000000 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x00000009 +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x00000000 +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffffL +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffffL +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x00000000 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffffL +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003f00L +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x00000008 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000fc000L +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0x0000000e +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000ffL +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x00000000 +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffffL +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x00000003L +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x00000000 +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffffL +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x00000000 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffffL +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffffL +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x00000000 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffffL +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x00000000 +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007fL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x00000000 +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000ffL +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x00000000 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x00000001 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x00000000 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffffL +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x00000000 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003fL +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x00000000 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x00000008 +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x00000003 +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x00000005 +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x00000002 +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x00000000 +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000c0L +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x00000006 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000fL +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000f0L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x00000004 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000f00L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x00000008 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000f000L +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0x0000000c +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000f00L +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x00000008 +#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x00000004 +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x00000000 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x00000001 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x00000002 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x00000003 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x0000001f +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffffL +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x00000000 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffffL +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x00000000 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001ffL +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x00000000 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003ffL +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x00000000 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003ffL +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x00000000 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003ffL +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x00000000 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003ffL +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x00000000 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x00000007 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x00000000 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007eL +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x00000001 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffffL +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x00000000 +#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L +#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x00000009 +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0x0000000e +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003c00L +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0x0000000a +#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001cL +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x00000002 +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0x0000000f +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x00000008 +#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000e0L +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x00000005 +#define VGT_TF_PARAM__TYPE_MASK 0x00000003L +#define VGT_TF_PARAM__TYPE__SHIFT 0x00000000 +#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000ffffL +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x00000000 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000ffL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 +#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L +#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x00000000 +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003ffL +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 +#define WD_DEBUG_DATA__DATA_MASK 0xffffffffL +#define WD_DEBUG_DATA__DATA__SHIFT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h new file mode 100644 index 000000000000..dc4e5b93801d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_d.h @@ -0,0 +1,1274 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_6_0_D_H +#define GMC_6_0_D_H + +#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE +#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE +#define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE +#define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE +#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE +#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE +#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E +#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E +#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E +#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E +#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x01AE +#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x01BE +#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x012E +#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x013E +#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x016E +#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x017E +#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0x00CD +#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0x00DD +#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0x00AD +#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0x00BD +#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x010D +#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x011D +#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x018D +#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x019D +#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x01AD +#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x01BD +#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x012D +#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x013D +#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x016D +#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x017D +#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0x00CC +#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0x00DC +#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0x00AC +#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0x00BC +#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x010C +#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x011C +#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x018C +#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x019C +#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x01AC +#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x01BC +#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x012C +#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x013C +#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x016C +#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x017C +#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0x00CB +#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0x00DB +#define ixMC_IO_DEBUG_CK_MISC_D0 0x00AB +#define ixMC_IO_DEBUG_CK_MISC_D1 0x00BB +#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x010B +#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x011B +#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x018B +#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x019B +#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x01AB +#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x01BB +#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x012B +#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x013B +#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x016B +#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x017B +#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0x00CF +#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0x00DF +#define ixMC_IO_DEBUG_CMD_MISC_D0 0x00AF +#define ixMC_IO_DEBUG_CMD_MISC_D1 0x00BF +#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0x00EF +#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0x00FF +#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x01CF +#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x01DF +#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x010F +#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x011F +#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x018F +#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x019F +#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x01AF +#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x01BF +#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x012F +#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x013F +#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x016F +#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x017F +#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x014F +#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x015F +#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0x00C8 +#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0x00D8 +#define ixMC_IO_DEBUG_DBI_MISC_D0 0x00A8 +#define ixMC_IO_DEBUG_DBI_MISC_D1 0x00B8 +#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0x00E8 +#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0x00F8 +#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x01C8 +#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x01D8 +#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x0108 +#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x0118 +#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x0148 +#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x0158 +#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x0188 +#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x0198 +#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x01A8 +#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x01B8 +#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x0128 +#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x0138 +#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x0168 +#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x0178 +#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x01CD +#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x01DD +#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x01CB +#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x01DB +#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x01CE +#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x01DE +#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x01CC +#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x01DC +#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x014B +#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x015B +#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0x00C1 +#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0x00D1 +#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0x00A1 +#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0x00B1 +#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0x00E1 +#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0x00F1 +#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x01C1 +#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x01D1 +#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x0101 +#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x0111 +#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x0141 +#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x0151 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x0181 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x0191 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x01A1 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x01B1 +#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x0121 +#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x0131 +#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x0161 +#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x0171 +#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0x00C0 +#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0x00D0 +#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0x00A0 +#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0x00B0 +#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0x00E0 +#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0x00F0 +#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x01C0 +#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x01D0 +#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x0100 +#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x0110 +#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x0140 +#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x0150 +#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x0180 +#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x0190 +#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x01A0 +#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x01B0 +#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x0120 +#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x0130 +#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x0160 +#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x0170 +#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x014C +#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x015C +#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0x00C3 +#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0x00D3 +#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0x00A3 +#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0x00B3 +#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0x00E3 +#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0x00F3 +#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x01C3 +#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x01D3 +#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x0103 +#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x0113 +#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x0143 +#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x0153 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x0183 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x0193 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x01A3 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x01B3 +#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x0123 +#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x0133 +#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x0163 +#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x0173 +#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0x00C2 +#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0x00D2 +#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0x00A2 +#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0x00B2 +#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0x00E2 +#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0x00F2 +#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x01C2 +#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x01D2 +#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x0102 +#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x0112 +#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x0142 +#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x0152 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x0182 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x0192 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x01A2 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x01B2 +#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x0122 +#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x0132 +#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x0162 +#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x0172 +#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x014D +#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x015D +#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0x00C5 +#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0x00D5 +#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0x00A5 +#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0x00B5 +#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0x00E5 +#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0x00F5 +#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x01C5 +#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x01D5 +#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x0105 +#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x0115 +#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x0145 +#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x0155 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x0185 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x0195 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x01A5 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x01B5 +#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x0125 +#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x0135 +#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x0165 +#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x0175 +#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0x00C4 +#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0x00D4 +#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0x00A4 +#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0x00B4 +#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0x00E4 +#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0x00F4 +#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x01C4 +#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x01D4 +#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x0104 +#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x0114 +#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x0144 +#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x0154 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x0184 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x0194 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x01A4 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x01B4 +#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x0124 +#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x0134 +#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x0164 +#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x0174 +#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x014E +#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x015E +#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0x00C7 +#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0x00D7 +#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0x00A7 +#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0x00B7 +#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0x00E7 +#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0x00F7 +#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x01C7 +#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x01D7 +#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x0107 +#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x0117 +#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x0147 +#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x0157 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x0187 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x0197 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x01A7 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x01B7 +#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x0127 +#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x0137 +#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x0167 +#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x0177 +#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0x00C6 +#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0x00D6 +#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0x00A6 +#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0x00B6 +#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0x00E6 +#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0x00F6 +#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x01C6 +#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x01D6 +#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x0106 +#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x0116 +#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x0146 +#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x0156 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x0186 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x0196 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x01A6 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x01B6 +#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x0126 +#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x0136 +#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x0166 +#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x0176 +#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0x00ED +#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0x00FD +#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0x00C9 +#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0x00D9 +#define ixMC_IO_DEBUG_EDC_MISC_D0 0x00A9 +#define ixMC_IO_DEBUG_EDC_MISC_D1 0x00B9 +#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0x00E9 +#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0x00F9 +#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0x00EC +#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0x00FC +#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x01C9 +#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x01D9 +#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0x00EB +#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0x00FB +#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x0109 +#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x0119 +#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x0149 +#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x0159 +#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x0189 +#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x0199 +#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x01A9 +#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x01B9 +#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x0129 +#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x0139 +#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x0169 +#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x0179 +#define ixMC_IO_DEBUG_UP_0 0x0000 +#define ixMC_IO_DEBUG_UP_100 0x0064 +#define ixMC_IO_DEBUG_UP_10 0x000A +#define ixMC_IO_DEBUG_UP_101 0x0065 +#define ixMC_IO_DEBUG_UP_102 0x0066 +#define ixMC_IO_DEBUG_UP_103 0x0067 +#define ixMC_IO_DEBUG_UP_104 0x0068 +#define ixMC_IO_DEBUG_UP_105 0x0069 +#define ixMC_IO_DEBUG_UP_106 0x006A +#define ixMC_IO_DEBUG_UP_107 0x006B +#define ixMC_IO_DEBUG_UP_108 0x006C +#define ixMC_IO_DEBUG_UP_109 0x006D +#define ixMC_IO_DEBUG_UP_1 0x0001 +#define ixMC_IO_DEBUG_UP_110 0x006E +#define ixMC_IO_DEBUG_UP_11 0x000B +#define ixMC_IO_DEBUG_UP_111 0x006F +#define ixMC_IO_DEBUG_UP_112 0x0070 +#define ixMC_IO_DEBUG_UP_113 0x0071 +#define ixMC_IO_DEBUG_UP_114 0x0072 +#define ixMC_IO_DEBUG_UP_115 0x0073 +#define ixMC_IO_DEBUG_UP_116 0x0074 +#define ixMC_IO_DEBUG_UP_117 0x0075 +#define ixMC_IO_DEBUG_UP_118 0x0076 +#define ixMC_IO_DEBUG_UP_119 0x0077 +#define ixMC_IO_DEBUG_UP_120 0x0078 +#define ixMC_IO_DEBUG_UP_12 0x000C +#define ixMC_IO_DEBUG_UP_121 0x0079 +#define ixMC_IO_DEBUG_UP_122 0x007A +#define ixMC_IO_DEBUG_UP_123 0x007B +#define ixMC_IO_DEBUG_UP_124 0x007C +#define ixMC_IO_DEBUG_UP_125 0x007D +#define ixMC_IO_DEBUG_UP_126 0x007E +#define ixMC_IO_DEBUG_UP_127 0x007F +#define ixMC_IO_DEBUG_UP_128 0x0080 +#define ixMC_IO_DEBUG_UP_129 0x0081 +#define ixMC_IO_DEBUG_UP_130 0x0082 +#define ixMC_IO_DEBUG_UP_13 0x000D +#define ixMC_IO_DEBUG_UP_131 0x0083 +#define ixMC_IO_DEBUG_UP_132 0x0084 +#define ixMC_IO_DEBUG_UP_133 0x0085 +#define ixMC_IO_DEBUG_UP_134 0x0086 +#define ixMC_IO_DEBUG_UP_135 0x0087 +#define ixMC_IO_DEBUG_UP_136 0x0088 +#define ixMC_IO_DEBUG_UP_137 0x0089 +#define ixMC_IO_DEBUG_UP_138 0x008A +#define ixMC_IO_DEBUG_UP_139 0x008B +#define ixMC_IO_DEBUG_UP_140 0x008C +#define ixMC_IO_DEBUG_UP_14 0x000E +#define ixMC_IO_DEBUG_UP_141 0x008D +#define ixMC_IO_DEBUG_UP_142 0x008E +#define ixMC_IO_DEBUG_UP_143 0x008F +#define ixMC_IO_DEBUG_UP_144 0x0090 +#define ixMC_IO_DEBUG_UP_145 0x0091 +#define ixMC_IO_DEBUG_UP_146 0x0092 +#define ixMC_IO_DEBUG_UP_147 0x0093 +#define ixMC_IO_DEBUG_UP_148 0x0094 +#define ixMC_IO_DEBUG_UP_149 0x0095 +#define ixMC_IO_DEBUG_UP_150 0x0096 +#define ixMC_IO_DEBUG_UP_15 0x000F +#define ixMC_IO_DEBUG_UP_151 0x0097 +#define ixMC_IO_DEBUG_UP_152 0x0098 +#define ixMC_IO_DEBUG_UP_153 0x0099 +#define ixMC_IO_DEBUG_UP_154 0x009A +#define ixMC_IO_DEBUG_UP_155 0x009B +#define ixMC_IO_DEBUG_UP_156 0x009C +#define ixMC_IO_DEBUG_UP_157 0x009D +#define ixMC_IO_DEBUG_UP_158 0x009E +#define ixMC_IO_DEBUG_UP_159 0x009F +#define ixMC_IO_DEBUG_UP_16 0x0010 +#define ixMC_IO_DEBUG_UP_17 0x0011 +#define ixMC_IO_DEBUG_UP_18 0x0012 +#define ixMC_IO_DEBUG_UP_19 0x0013 +#define ixMC_IO_DEBUG_UP_20 0x0014 +#define ixMC_IO_DEBUG_UP_2 0x0002 +#define ixMC_IO_DEBUG_UP_21 0x0015 +#define ixMC_IO_DEBUG_UP_22 0x0016 +#define ixMC_IO_DEBUG_UP_23 0x0017 +#define ixMC_IO_DEBUG_UP_24 0x0018 +#define ixMC_IO_DEBUG_UP_25 0x0019 +#define ixMC_IO_DEBUG_UP_26 0x001A +#define ixMC_IO_DEBUG_UP_27 0x001B +#define ixMC_IO_DEBUG_UP_28 0x001C +#define ixMC_IO_DEBUG_UP_29 0x001D +#define ixMC_IO_DEBUG_UP_30 0x001E +#define ixMC_IO_DEBUG_UP_3 0x0003 +#define ixMC_IO_DEBUG_UP_31 0x001F +#define ixMC_IO_DEBUG_UP_32 0x0020 +#define ixMC_IO_DEBUG_UP_33 0x0021 +#define ixMC_IO_DEBUG_UP_34 0x0022 +#define ixMC_IO_DEBUG_UP_35 0x0023 +#define ixMC_IO_DEBUG_UP_36 0x0024 +#define ixMC_IO_DEBUG_UP_37 0x0025 +#define ixMC_IO_DEBUG_UP_38 0x0026 +#define ixMC_IO_DEBUG_UP_39 0x0027 +#define ixMC_IO_DEBUG_UP_40 0x0028 +#define ixMC_IO_DEBUG_UP_4 0x0004 +#define ixMC_IO_DEBUG_UP_41 0x0029 +#define ixMC_IO_DEBUG_UP_42 0x002A +#define ixMC_IO_DEBUG_UP_43 0x002B +#define ixMC_IO_DEBUG_UP_44 0x002C +#define ixMC_IO_DEBUG_UP_45 0x002D +#define ixMC_IO_DEBUG_UP_46 0x002E +#define ixMC_IO_DEBUG_UP_47 0x002F +#define ixMC_IO_DEBUG_UP_48 0x0030 +#define ixMC_IO_DEBUG_UP_49 0x0031 +#define ixMC_IO_DEBUG_UP_50 0x0032 +#define ixMC_IO_DEBUG_UP_5 0x0005 +#define ixMC_IO_DEBUG_UP_51 0x0033 +#define ixMC_IO_DEBUG_UP_52 0x0034 +#define ixMC_IO_DEBUG_UP_53 0x0035 +#define ixMC_IO_DEBUG_UP_54 0x0036 +#define ixMC_IO_DEBUG_UP_55 0x0037 +#define ixMC_IO_DEBUG_UP_56 0x0038 +#define ixMC_IO_DEBUG_UP_57 0x0039 +#define ixMC_IO_DEBUG_UP_58 0x003A +#define ixMC_IO_DEBUG_UP_59 0x003B +#define ixMC_IO_DEBUG_UP_60 0x003C +#define ixMC_IO_DEBUG_UP_6 0x0006 +#define ixMC_IO_DEBUG_UP_61 0x003D +#define ixMC_IO_DEBUG_UP_62 0x003E +#define ixMC_IO_DEBUG_UP_63 0x003F +#define ixMC_IO_DEBUG_UP_64 0x0040 +#define ixMC_IO_DEBUG_UP_65 0x0041 +#define ixMC_IO_DEBUG_UP_66 0x0042 +#define ixMC_IO_DEBUG_UP_67 0x0043 +#define ixMC_IO_DEBUG_UP_68 0x0044 +#define ixMC_IO_DEBUG_UP_69 0x0045 +#define ixMC_IO_DEBUG_UP_70 0x0046 +#define ixMC_IO_DEBUG_UP_7 0x0007 +#define ixMC_IO_DEBUG_UP_71 0x0047 +#define ixMC_IO_DEBUG_UP_72 0x0048 +#define ixMC_IO_DEBUG_UP_73 0x0049 +#define ixMC_IO_DEBUG_UP_74 0x004A +#define ixMC_IO_DEBUG_UP_75 0x004B +#define ixMC_IO_DEBUG_UP_76 0x004C +#define ixMC_IO_DEBUG_UP_77 0x004D +#define ixMC_IO_DEBUG_UP_78 0x004E +#define ixMC_IO_DEBUG_UP_79 0x004F +#define ixMC_IO_DEBUG_UP_80 0x0050 +#define ixMC_IO_DEBUG_UP_8 0x0008 +#define ixMC_IO_DEBUG_UP_81 0x0051 +#define ixMC_IO_DEBUG_UP_82 0x0052 +#define ixMC_IO_DEBUG_UP_83 0x0053 +#define ixMC_IO_DEBUG_UP_84 0x0054 +#define ixMC_IO_DEBUG_UP_85 0x0055 +#define ixMC_IO_DEBUG_UP_86 0x0056 +#define ixMC_IO_DEBUG_UP_87 0x0057 +#define ixMC_IO_DEBUG_UP_88 0x0058 +#define ixMC_IO_DEBUG_UP_89 0x0059 +#define ixMC_IO_DEBUG_UP_90 0x005A +#define ixMC_IO_DEBUG_UP_9 0x0009 +#define ixMC_IO_DEBUG_UP_91 0x005B +#define ixMC_IO_DEBUG_UP_92 0x005C +#define ixMC_IO_DEBUG_UP_93 0x005D +#define ixMC_IO_DEBUG_UP_94 0x005E +#define ixMC_IO_DEBUG_UP_95 0x005F +#define ixMC_IO_DEBUG_UP_96 0x0060 +#define ixMC_IO_DEBUG_UP_97 0x0061 +#define ixMC_IO_DEBUG_UP_98 0x0062 +#define ixMC_IO_DEBUG_UP_99 0x0063 +#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x01EA +#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x01FA +#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x01E1 +#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x01F1 +#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x01E0 +#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x01F0 +#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x01E2 +#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x01F2 +#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x01EC +#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x01FC +#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x01E9 +#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x01F9 +#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x01EB +#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x01FB +#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x01E3 +#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x01F3 +#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x01E5 +#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x01F5 +#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x01E7 +#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x01F7 +#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x01E8 +#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x01F8 +#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x01E4 +#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x01F4 +#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x01E6 +#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x01F6 +#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0x00CA +#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0x00DA +#define ixMC_IO_DEBUG_WCK_MISC_D0 0x00AA +#define ixMC_IO_DEBUG_WCK_MISC_D1 0x00BA +#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0x00EA +#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0x00FA +#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x01CA +#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x01DA +#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x010A +#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x011A +#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x014A +#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x015A +#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x018A +#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x019A +#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x01AA +#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x01BA +#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x012A +#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x013A +#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x016A +#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x017A +#define ixMC_TSM_DEBUG_BCNT0 0x0003 +#define ixMC_TSM_DEBUG_BCNT10 0x000D +#define ixMC_TSM_DEBUG_BCNT1 0x0004 +#define ixMC_TSM_DEBUG_BCNT2 0x0005 +#define ixMC_TSM_DEBUG_BCNT3 0x0006 +#define ixMC_TSM_DEBUG_BCNT4 0x0007 +#define ixMC_TSM_DEBUG_BCNT5 0x0008 +#define ixMC_TSM_DEBUG_BCNT6 0x0009 +#define ixMC_TSM_DEBUG_BCNT7 0x000A +#define ixMC_TSM_DEBUG_BCNT8 0x000B +#define ixMC_TSM_DEBUG_BCNT9 0x000C +#define ixMC_TSM_DEBUG_BKPT 0x0013 +#define ixMC_TSM_DEBUG_FLAG 0x0001 +#define ixMC_TSM_DEBUG_GCNT 0x0000 +#define ixMC_TSM_DEBUG_MISC 0x0002 +#define ixMC_TSM_DEBUG_ST01 0x0010 +#define ixMC_TSM_DEBUG_ST23 0x0011 +#define ixMC_TSM_DEBUG_ST45 0x0012 +#define mmATC_ATS_CNTL 0x0CC9 +#define mmATC_ATS_DEBUG 0x0CCA +#define mmATC_ATS_DEFAULT_PAGE_CNTL 0x0CD1 +#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0CD0 +#define mmATC_ATS_FAULT_CNTL 0x0CCD +#define mmATC_ATS_FAULT_DEBUG 0x0CCB +#define mmATC_ATS_FAULT_STATUS_ADDR 0x0CCF +#define mmATC_ATS_FAULT_STATUS_INFO 0x0CCE +#define mmATC_ATS_STATUS 0x0CCC +#define mmATC_L1_ADDRESS_OFFSET 0x0CDD +#define mmATC_L1_CNTL 0x0CDC +#define mmATC_L1RD_DEBUG_TLB 0x0CDE +#define mmATC_L1RD_STATUS 0x0CE0 +#define mmATC_L1WR_DEBUG_TLB 0x0CDF +#define mmATC_L1WR_STATUS 0x0CE1 +#define mmATC_L2_CNTL 0x0CD5 +#define mmATC_L2_DEBUG 0x0CD7 +#define mmATC_MISC_CG 0x0CD4 +#define mmATC_VM_APERTURE0_CNTL 0x0CC4 +#define mmATC_VM_APERTURE0_CNTL2 0x0CC6 +#define mmATC_VM_APERTURE0_HIGH_ADDR 0x0CC2 +#define mmATC_VM_APERTURE0_LOW_ADDR 0x0CC0 +#define mmATC_VM_APERTURE1_CNTL 0x0CC5 +#define mmATC_VM_APERTURE1_CNTL2 0x0CC7 +#define mmATC_VM_APERTURE1_HIGH_ADDR 0x0CC3 +#define mmATC_VM_APERTURE1_LOW_ADDR 0x0CC1 +#define mmATC_VMID0_PASID_MAPPING 0x0CE7 +#define mmATC_VMID10_PASID_MAPPING 0x0CF1 +#define mmATC_VMID11_PASID_MAPPING 0x0CF2 +#define mmATC_VMID12_PASID_MAPPING 0x0CF3 +#define mmATC_VMID13_PASID_MAPPING 0x0CF4 +#define mmATC_VMID14_PASID_MAPPING 0x0CF5 +#define mmATC_VMID15_PASID_MAPPING 0x0CF6 +#define mmATC_VMID1_PASID_MAPPING 0x0CE8 +#define mmATC_VMID2_PASID_MAPPING 0x0CE9 +#define mmATC_VMID3_PASID_MAPPING 0x0CEA +#define mmATC_VMID4_PASID_MAPPING 0x0CEB +#define mmATC_VMID5_PASID_MAPPING 0x0CEC +#define mmATC_VMID6_PASID_MAPPING 0x0CED +#define mmATC_VMID7_PASID_MAPPING 0x0CEE +#define mmATC_VMID8_PASID_MAPPING 0x0CEF +#define mmATC_VMID9_PASID_MAPPING 0x0CF0 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x0CE6 +#define mmCC_MC_MAX_CHANNEL 0x096E +#define mmDLL_CNTL 0x0AE9 +#define mmGMCON_DEBUG 0x0D5F +#define mmGMCON_MISC 0x0D43 +#define mmGMCON_MISC2 0x0D44 +#define mmGMCON_MISC3 0x0D51 +#define mmGMCON_PERF_MON_CNTL0 0x0D4A +#define mmGMCON_PERF_MON_CNTL1 0x0D4B +#define mmGMCON_PERF_MON_RSLT0 0x0D4C +#define mmGMCON_PERF_MON_RSLT1 0x0D4D +#define mmGMCON_PGFSM_CONFIG 0x0D4E +#define mmGMCON_PGFSM_READ 0x0D50 +#define mmGMCON_PGFSM_WRITE 0x0D4F +#define mmGMCON_RENG_EXECUTE 0x0D42 +#define mmGMCON_RENG_RAM_DATA 0x0D41 +#define mmGMCON_RENG_RAM_INDEX 0x0D40 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0D48 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0D49 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0x0D45 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0x0D46 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0x0D47 +#define mmMC_ARB_ADDR_HASH 0x09DC +#define mmMC_ARB_AGE_RD 0x09E9 +#define mmMC_ARB_AGE_WR 0x09EA +#define mmMC_ARB_BANKMAP 0x09D7 +#define mmMC_ARB_BURST_TIME 0x0A02 +#define mmMC_ARB_CAC_CNTL 0x09D4 +#define mmMC_ARB_CG 0x09FA +#define mmMC_ARB_DRAM_TIMING 0x09DD +#define mmMC_ARB_DRAM_TIMING_1 0x09FC +#define mmMC_ARB_DRAM_TIMING2 0x09DE +#define mmMC_ARB_DRAM_TIMING2_1 0x09FF +#define mmMC_ARB_FED_CNTL 0x09C1 +#define mmMC_ARB_GDEC_RD_CNTL 0x09EE +#define mmMC_ARB_GDEC_WR_CNTL 0x09EF +#define mmMC_ARB_GECC2 0x09C9 +#define mmMC_ARB_GECC2_CLI 0x09CA +#define mmMC_ARB_GECC2_DEBUG 0x09C4 +#define mmMC_ARB_GECC2_DEBUG2 0x09C5 +#define mmMC_ARB_GECC2_MISC 0x09C3 +#define mmMC_ARB_GECC2_STATUS 0x09C2 +#define mmMC_ARB_LAZY0_RD 0x09E5 +#define mmMC_ARB_LAZY0_WR 0x09E6 +#define mmMC_ARB_LAZY1_RD 0x09E7 +#define mmMC_ARB_LAZY1_WR 0x09E8 +#define mmMC_ARB_LM_RD 0x09F0 +#define mmMC_ARB_LM_WR 0x09F1 +#define mmMC_ARB_MINCLKS 0x09DA +#define mmMC_ARB_MISC 0x09D6 +#define mmMC_ARB_MISC2 0x09D5 +#define mmMC_ARB_PM_CNTL 0x09ED +#define mmMC_ARB_POP 0x09D9 +#define mmMC_ARB_RAMCFG 0x09D8 +#define mmMC_ARB_REMREQ 0x09F2 +#define mmMC_ARB_REPLAY 0x09F3 +#define mmMC_ARB_RET_CREDITS_RD 0x09F4 +#define mmMC_ARB_RET_CREDITS_WR 0x09F5 +#define mmMC_ARB_RFSH_CNTL 0x09EB +#define mmMC_ARB_RFSH_RATE 0x09EC +#define mmMC_ARB_RTT_CNTL0 0x09D0 +#define mmMC_ARB_RTT_CNTL1 0x09D1 +#define mmMC_ARB_RTT_CNTL2 0x09D2 +#define mmMC_ARB_RTT_DATA 0x09CF +#define mmMC_ARB_RTT_DEBUG 0x09D3 +#define mmMC_ARB_SQM_CNTL 0x09DB +#define mmMC_ARB_TM_CNTL_RD 0x09E3 +#define mmMC_ARB_TM_CNTL_WR 0x09E4 +#define mmMC_ARB_WCDR 0x09FB +#define mmMC_ARB_WCDR_2 0x09CE +#define mmMC_ARB_WTM_CNTL_RD 0x09DF +#define mmMC_ARB_WTM_CNTL_WR 0x09E0 +#define mmMC_ARB_WTM_GRPWT_RD 0x09E1 +#define mmMC_ARB_WTM_GRPWT_WR 0x09E2 +#define mmMC_BIST_AUTO_CNTL 0x0A06 +#define mmMC_BIST_CMD_CNTL 0x0A8E +#define mmMC_BIST_CMP_CNTL 0x0A8D +#define mmMC_BIST_CMP_CNTL_2 0x0AB6 +#define mmMC_BIST_CNTL 0x0A05 +#define mmMC_BIST_DATA_MASK 0x0A12 +#define mmMC_BIST_DATA_WORD0 0x0A0A +#define mmMC_BIST_DATA_WORD1 0x0A0B +#define mmMC_BIST_DATA_WORD2 0x0A0C +#define mmMC_BIST_DATA_WORD3 0x0A0D +#define mmMC_BIST_DATA_WORD4 0x0A0E +#define mmMC_BIST_DATA_WORD5 0x0A0F +#define mmMC_BIST_DATA_WORD6 0x0A10 +#define mmMC_BIST_DATA_WORD7 0x0A11 +#define mmMC_BIST_DIR_CNTL 0x0A07 +#define mmMC_BIST_EADDR 0x0A09 +#define mmMC_BIST_MISMATCH_ADDR 0x0A13 +#define mmMC_BIST_RDATA_EDC 0x0A1D +#define mmMC_BIST_RDATA_MASK 0x0A1C +#define mmMC_BIST_RDATA_WORD0 0x0A14 +#define mmMC_BIST_RDATA_WORD1 0x0A15 +#define mmMC_BIST_RDATA_WORD2 0x0A16 +#define mmMC_BIST_RDATA_WORD3 0x0A17 +#define mmMC_BIST_RDATA_WORD4 0x0A18 +#define mmMC_BIST_RDATA_WORD5 0x0A19 +#define mmMC_BIST_RDATA_WORD6 0x0A1A +#define mmMC_BIST_RDATA_WORD7 0x0A1B +#define mmMC_BIST_SADDR 0x0A08 +#define mmMC_CG_CONFIG 0x096F +#define mmMC_CG_CONFIG_MCD 0x0829 +#define mmMC_CG_DATAPORT 0x0A21 +#define mmMC_CITF_CNTL 0x0970 +#define mmMC_CITF_CREDITS_ARB_RD 0x0972 +#define mmMC_CITF_CREDITS_ARB_WR 0x0973 +#define mmMC_CITF_CREDITS_VM 0x0971 +#define mmMC_CITF_CREDITS_XBAR 0x0989 +#define mmMC_CITF_DAGB_CNTL 0x0974 +#define mmMC_CITF_DAGB_DLY 0x0977 +#define mmMC_CITF_INT_CREDITS 0x0975 +#define mmMC_CITF_INT_CREDITS_WR 0x097D +#define mmMC_CITF_MISC_RD_CG 0x0992 +#define mmMC_CITF_MISC_VM_CG 0x0994 +#define mmMC_CITF_MISC_WR_CG 0x0993 +#define mmMC_CITF_PERF_MON_CNTL2 0x098E +#define mmMC_CITF_PERF_MON_RSLT2 0x0991 +#define mmMC_CITF_REMREQ 0x097A +#define mmMC_CITF_RET_MODE 0x0976 +#define mmMC_CITF_WTM_RD_CNTL 0x097F +#define mmMC_CITF_WTM_WR_CNTL 0x0980 +#define mmMC_CITF_XTRA_ENABLE 0x096D +#define mmMC_CONFIG 0x0800 +#define mmMC_CONFIG_MCD 0x0828 +#define mmMC_HUB_MISC_DBG 0x0831 +#define mmMC_HUB_MISC_FRAMING 0x0834 +#define mmMC_HUB_MISC_HUB_CG 0x082E +#define mmMC_HUB_MISC_IDLE_STATUS 0x0847 +#define mmMC_HUB_MISC_OVERRIDE 0x0833 +#define mmMC_HUB_MISC_POWER 0x082D +#define mmMC_HUB_MISC_SIP_CG 0x0830 +#define mmMC_HUB_MISC_STATUS 0x0832 +#define mmMC_HUB_MISC_VM_CG 0x082F +#define mmMC_HUB_RDREQ_CNTL 0x083B +#define mmMC_HUB_RDREQ_CREDITS 0x0844 +#define mmMC_HUB_RDREQ_CREDITS2 0x0845 +#define mmMC_HUB_RDREQ_DMIF 0x0863 +#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x0848 +#define mmMC_HUB_RDREQ_GBL0 0x0856 +#define mmMC_HUB_RDREQ_GBL1 0x0857 +#define mmMC_HUB_RDREQ_HDP 0x085B +#define mmMC_HUB_RDREQ_MCDW 0x0851 +#define mmMC_HUB_RDREQ_MCDX 0x0852 +#define mmMC_HUB_RDREQ_MCDY 0x0853 +#define mmMC_HUB_RDREQ_MCDZ 0x0854 +#define mmMC_HUB_RDREQ_MCIF 0x0864 +#define mmMC_HUB_RDREQ_RLC 0x085D +#define mmMC_HUB_RDREQ_SEM 0x085E +#define mmMC_HUB_RDREQ_SIP 0x0855 +#define mmMC_HUB_RDREQ_SMU 0x0858 +#define mmMC_HUB_RDREQ_STATUS 0x0839 +#define mmMC_HUB_RDREQ_UMC 0x0860 +#define mmMC_HUB_RDREQ_UVD 0x0861 +#define mmMC_HUB_RDREQ_VCE 0x085F +#define mmMC_HUB_RDREQ_VCEU 0x0866 +#define mmMC_HUB_RDREQ_VMC 0x0865 +#define mmMC_HUB_RDREQ_WTM_CNTL 0x083D +#define mmMC_HUB_RDREQ_XDMAM 0x0882 +#define mmMC_HUB_SHARED_DAGB_DLY 0x0846 +#define mmMC_HUB_WDP_BP 0x0837 +#define mmMC_HUB_WDP_CNTL 0x0835 +#define mmMC_HUB_WDP_CREDITS 0x083F +#define mmMC_HUB_WDP_ERR 0x0836 +#define mmMC_HUB_WDP_GBL0 0x0841 +#define mmMC_HUB_WDP_GBL1 0x0842 +#define mmMC_HUB_WDP_HDP 0x0879 +#define mmMC_HUB_WDP_IH 0x0872 +#define mmMC_HUB_WDP_MCDW 0x0867 +#define mmMC_HUB_WDP_MCDX 0x0868 +#define mmMC_HUB_WDP_MCDY 0x0869 +#define mmMC_HUB_WDP_MCDZ 0x086A +#define mmMC_HUB_WDP_MCIF 0x086F +#define mmMC_HUB_WDP_MGPU 0x0843 +#define mmMC_HUB_WDP_MGPU2 0x0840 +#define mmMC_HUB_WDP_RLC 0x0873 +#define mmMC_HUB_WDP_SEM 0x0874 +#define mmMC_HUB_WDP_SH0 0x086E +#define mmMC_HUB_WDP_SH1 0x0876 +#define mmMC_HUB_WDP_SIP 0x086B +#define mmMC_HUB_WDP_SMU 0x0875 +#define mmMC_HUB_WDP_STATUS 0x0838 +#define mmMC_HUB_WDP_UMC 0x0877 +#define mmMC_HUB_WDP_UVD 0x0878 +#define mmMC_HUB_WDP_VCE 0x0870 +#define mmMC_HUB_WDP_VCEU 0x087F +#define mmMC_HUB_WDP_WTM_CNTL 0x083E +#define mmMC_HUB_WDP_XDMA 0x0881 +#define mmMC_HUB_WDP_XDMAM 0x0880 +#define mmMC_HUB_WDP_XDP 0x0871 +#define mmMC_HUB_WRRET_CNTL 0x083C +#define mmMC_HUB_WRRET_MCDW 0x087B +#define mmMC_HUB_WRRET_MCDX 0x087C +#define mmMC_HUB_WRRET_MCDY 0x087D +#define mmMC_HUB_WRRET_MCDZ 0x087E +#define mmMC_HUB_WRRET_STATUS 0x083A +#define mmMC_IMP_CNTL 0x0A36 +#define mmMC_IMP_DEBUG 0x0A37 +#define mmMC_IMP_DQ_STATUS 0x0ABC +#define mmMC_IMP_STATUS 0x0A38 +#define mmMC_IO_APHY_STR_CNTL_D0 0x0A97 +#define mmMC_IO_APHY_STR_CNTL_D1 0x0A98 +#define mmMC_IO_CDRCNTL1_D0 0x0ADD +#define mmMC_IO_CDRCNTL1_D1 0x0ADE +#define mmMC_IO_CDRCNTL2_D0 0x0AE4 +#define mmMC_IO_CDRCNTL2_D1 0x0AE5 +#define mmMC_IO_CDRCNTL_D0 0x0A55 +#define mmMC_IO_CDRCNTL_D1 0x0A56 +#define mmMC_IO_DPHY_STR_CNTL_D0 0x0A4E +#define mmMC_IO_DPHY_STR_CNTL_D1 0x0A54 +#define mmMC_IO_PAD_CNTL 0x0A73 +#define mmMC_IO_PAD_CNTL_D0 0x0A74 +#define mmMC_IO_PAD_CNTL_D1 0x0A75 +#define mmMC_IO_RXCNTL1_DPHY0_D0 0x0ADF +#define mmMC_IO_RXCNTL1_DPHY0_D1 0x0AE1 +#define mmMC_IO_RXCNTL1_DPHY1_D0 0x0AE0 +#define mmMC_IO_RXCNTL1_DPHY1_D1 0x0AE2 +#define mmMC_IO_RXCNTL_DPHY0_D0 0x0A4C +#define mmMC_IO_RXCNTL_DPHY0_D1 0x0A52 +#define mmMC_IO_RXCNTL_DPHY1_D0 0x0A4D +#define mmMC_IO_RXCNTL_DPHY1_D1 0x0A53 +#define mmMC_IO_TXCNTL_APHY_D0 0x0A4B +#define mmMC_IO_TXCNTL_APHY_D1 0x0A51 +#define mmMC_IO_TXCNTL_DPHY0_D0 0x0A49 +#define mmMC_IO_TXCNTL_DPHY0_D1 0x0A4F +#define mmMC_IO_TXCNTL_DPHY1_D0 0x0A4A +#define mmMC_IO_TXCNTL_DPHY1_D1 0x0A50 +#define mmMCLK_PWRMGT_CNTL 0x0AE8 +#define mmMC_MEM_POWER_LS 0x082A +#define mmMC_NPL_STATUS 0x0A76 +#define mmMC_PHY_TIMING_2 0x0ACE +#define mmMC_PHY_TIMING_D0 0x0ACC +#define mmMC_PHY_TIMING_D1 0x0ACD +#define mmMC_PMG_AUTO_CFG 0x0A35 +#define mmMC_PMG_AUTO_CMD 0x0A34 +#define mmMC_PMG_CFG 0x0A84 +#define mmMC_PMG_CMD_EMRS 0x0A83 +#define mmMC_PMG_CMD_MRS 0x0AAB +#define mmMC_PMG_CMD_MRS1 0x0AD1 +#define mmMC_PMG_CMD_MRS2 0x0AD7 +#define mmMC_RD_CB 0x0981 +#define mmMC_RD_DB 0x0982 +#define mmMC_RD_GRP_EXT 0x0978 +#define mmMC_RD_GRP_GFX 0x0803 +#define mmMC_RD_GRP_LCL 0x098A +#define mmMC_RD_GRP_OTH 0x0807 +#define mmMC_RD_GRP_SYS 0x0805 +#define mmMC_RD_HUB 0x0985 +#define mmMC_RD_TC0 0x0983 +#define mmMC_RD_TC1 0x0984 +#define mmMC_RPB_ARB_CNTL 0x0951 +#define mmMC_RPB_BIF_CNTL 0x0952 +#define mmMC_RPB_CID_QUEUE_EX 0x095A +#define mmMC_RPB_CID_QUEUE_EX_DATA 0x095B +#define mmMC_RPB_CID_QUEUE_RD 0x0957 +#define mmMC_RPB_CID_QUEUE_WR 0x0956 +#define mmMC_RPB_CONF 0x094D +#define mmMC_RPB_DBG1 0x094F +#define mmMC_RPB_EFF_CNTL 0x0950 +#define mmMC_RPB_IF_CONF 0x094E +#define mmMC_RPB_PERF_COUNTER_CNTL 0x0958 +#define mmMC_RPB_PERF_COUNTER_STATUS 0x0959 +#define mmMC_RPB_RD_SWITCH_CNTL 0x0955 +#define mmMC_RPB_WR_COMBINE_CNTL 0x0954 +#define mmMC_RPB_WR_SWITCH_CNTL 0x0953 +#define mmMC_SEQ_BIT_REMAP_B0_D0 0x0AA3 +#define mmMC_SEQ_BIT_REMAP_B0_D1 0x0AA7 +#define mmMC_SEQ_BIT_REMAP_B1_D0 0x0AA4 +#define mmMC_SEQ_BIT_REMAP_B1_D1 0x0AA8 +#define mmMC_SEQ_BIT_REMAP_B2_D0 0x0AA5 +#define mmMC_SEQ_BIT_REMAP_B2_D1 0x0AA9 +#define mmMC_SEQ_BIT_REMAP_B3_D0 0x0AA6 +#define mmMC_SEQ_BIT_REMAP_B3_D1 0x0AAA +#define mmMC_SEQ_BYTE_REMAP_D0 0x0A93 +#define mmMC_SEQ_BYTE_REMAP_D1 0x0A94 +#define mmMC_SEQ_CAS_TIMING 0x0A29 +#define mmMC_SEQ_CAS_TIMING_LP 0x0A9C +#define mmMC_SEQ_CG 0x0A9A +#define mmMC_SEQ_CMD 0x0A31 +#define mmMC_SEQ_CNTL 0x0A25 +#define mmMC_SEQ_CNTL_2 0x0AD4 +#define mmMC_SEQ_DRAM 0x0A26 +#define mmMC_SEQ_DRAM_2 0x0A27 +#define mmMC_SEQ_DRAM_ERROR_INSERTION 0x0ACB +#define mmMC_SEQ_FIFO_CTL 0x0A57 +#define mmMC_SEQ_IO_DEBUG_DATA 0x0A92 +#define mmMC_SEQ_IO_DEBUG_INDEX 0x0A91 +#define mmMC_SEQ_IO_RDBI 0x0AB4 +#define mmMC_SEQ_IO_REDC 0x0AB5 +#define mmMC_SEQ_IO_RESERVE_D0 0x0AB7 +#define mmMC_SEQ_IO_RESERVE_D1 0x0AB8 +#define mmMC_SEQ_IO_RWORD0 0x0AAC +#define mmMC_SEQ_IO_RWORD1 0x0AAD +#define mmMC_SEQ_IO_RWORD2 0x0AAE +#define mmMC_SEQ_IO_RWORD3 0x0AAF +#define mmMC_SEQ_IO_RWORD4 0x0AB0 +#define mmMC_SEQ_IO_RWORD5 0x0AB1 +#define mmMC_SEQ_IO_RWORD6 0x0AB2 +#define mmMC_SEQ_IO_RWORD7 0x0AB3 +#define mmMC_SEQ_MISC0 0x0A80 +#define mmMC_SEQ_MISC1 0x0A81 +#define mmMC_SEQ_MISC3 0x0A8B +#define mmMC_SEQ_MISC4 0x0A8C +#define mmMC_SEQ_MISC5 0x0A95 +#define mmMC_SEQ_MISC6 0x0A96 +#define mmMC_SEQ_MISC7 0x0A99 +#define mmMC_SEQ_MISC8 0x0A5F +#define mmMC_SEQ_MISC9 0x0AE7 +#define mmMC_SEQ_MISC_TIMING 0x0A2A +#define mmMC_SEQ_MISC_TIMING2 0x0A2B +#define mmMC_SEQ_MISC_TIMING2_LP 0x0A9E +#define mmMC_SEQ_MISC_TIMING_LP 0x0A9D +#define mmMC_SEQ_MPLL_OVERRIDE 0x0A22 +#define mmMC_SEQ_PERF_CNTL 0x0A77 +#define mmMC_SEQ_PERF_CNTL_1 0x0AFD +#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0x0A79 +#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0x0A7A +#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0x0A7B +#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0x0A7C +#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0x0AD9 +#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0x0ADA +#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0x0ADB +#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0x0ADC +#define mmMC_SEQ_PERF_SEQ_CTL 0x0A78 +#define mmMC_SEQ_PMG_CMD_EMRS_LP 0x0AA1 +#define mmMC_SEQ_PMG_CMD_MRS1_LP 0x0AD2 +#define mmMC_SEQ_PMG_CMD_MRS2_LP 0x0AD8 +#define mmMC_SEQ_PMG_CMD_MRS_LP 0x0AA2 +#define mmMC_SEQ_PMG_PG_HWCNTL 0x0AB9 +#define mmMC_SEQ_PMG_PG_SWCNTL_0 0x0ABA +#define mmMC_SEQ_PMG_PG_SWCNTL_1 0x0ABB +#define mmMC_SEQ_PMG_TIMING 0x0A2C +#define mmMC_SEQ_PMG_TIMING_LP 0x0AD3 +#define mmMC_SEQ_RAS_TIMING 0x0A28 +#define mmMC_SEQ_RAS_TIMING_LP 0x0A9B +#define mmMC_SEQ_RD_CTL_D0 0x0A2D +#define mmMC_SEQ_RD_CTL_D0_LP 0x0AC7 +#define mmMC_SEQ_RD_CTL_D1 0x0A2E +#define mmMC_SEQ_RD_CTL_D1_LP 0x0AC8 +#define mmMC_SEQ_RESERVE_0_S 0x0A1E +#define mmMC_SEQ_RESERVE_1_S 0x0A1F +#define mmMC_SEQ_RESERVE_M 0x0A82 +#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0x0A67 +#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0x0A6D +#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0x0A68 +#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0x0A6E +#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0x0A69 +#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0x0A6F +#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0x0A6A +#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0x0A70 +#define mmMC_SEQ_RXFRAMING_DBI_D0 0x0A6B +#define mmMC_SEQ_RXFRAMING_DBI_D1 0x0A71 +#define mmMC_SEQ_RXFRAMING_EDC_D0 0x0A6C +#define mmMC_SEQ_RXFRAMING_EDC_D1 0x0A72 +#define mmMC_SEQ_STATUS_M 0x0A7D +#define mmMC_SEQ_STATUS_S 0x0A20 +#define mmMC_SEQ_SUP_CNTL 0x0A32 +#define mmMC_SEQ_SUP_DEC_STAT 0x0A88 +#define mmMC_SEQ_SUP_GP0_STAT 0x0A8F +#define mmMC_SEQ_SUP_GP1_STAT 0x0A90 +#define mmMC_SEQ_SUP_GP2_STAT 0x0A85 +#define mmMC_SEQ_SUP_GP3_STAT 0x0A86 +#define mmMC_SEQ_SUP_IR_STAT 0x0A87 +#define mmMC_SEQ_SUP_PGM 0x0A33 +#define mmMC_SEQ_SUP_PGM_STAT 0x0A89 +#define mmMC_SEQ_SUP_R_PGM 0x0A8A +#define mmMC_SEQ_TCG_CNTL 0x0ABD +#define mmMC_SEQ_TIMER_RD 0x0ACA +#define mmMC_SEQ_TIMER_WR 0x0AC9 +#define mmMC_SEQ_TRAIN_CAPTURE 0x0A3E +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0x0A3B +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0x0AFE +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0x0AFF +#define mmMC_SEQ_TRAIN_TIMING 0x0A40 +#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0x0A3F +#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0x0A3A +#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0x0A3C +#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0x0A3D +#define mmMC_SEQ_TSM_BCNT 0x0AC2 +#define mmMC_SEQ_TSM_CTRL 0x0ABE +#define mmMC_SEQ_TSM_DBI 0x0AC6 +#define mmMC_SEQ_TSM_DEBUG_DATA 0x0AD0 +#define mmMC_SEQ_TSM_DEBUG_INDEX 0x0ACF +#define mmMC_SEQ_TSM_EDC 0x0AC5 +#define mmMC_SEQ_TSM_FLAG 0x0AC3 +#define mmMC_SEQ_TSM_GCNT 0x0ABF +#define mmMC_SEQ_TSM_MISC 0x0AE6 +#define mmMC_SEQ_TSM_NCNT 0x0AC1 +#define mmMC_SEQ_TSM_OCNT 0x0AC0 +#define mmMC_SEQ_TSM_UPDATE 0x0AC4 +#define mmMC_SEQ_TSM_WCDR 0x0AE3 +#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0x0A58 +#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0x0A60 +#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0x0A59 +#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0x0A61 +#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0x0A5A +#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0x0A62 +#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0x0A5B +#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0x0A63 +#define mmMC_SEQ_TXFRAMING_DBI_D0 0x0A5C +#define mmMC_SEQ_TXFRAMING_DBI_D1 0x0A64 +#define mmMC_SEQ_TXFRAMING_EDC_D0 0x0A5D +#define mmMC_SEQ_TXFRAMING_EDC_D1 0x0A65 +#define mmMC_SEQ_TXFRAMING_FCK_D0 0x0A5E +#define mmMC_SEQ_TXFRAMING_FCK_D1 0x0A66 +#define mmMC_SEQ_VENDOR_ID_I0 0x0A7E +#define mmMC_SEQ_VENDOR_ID_I1 0x0A7F +#define mmMC_SEQ_WCDR_CTRL 0x0A39 +#define mmMC_SEQ_WR_CTL_2 0x0AD5 +#define mmMC_SEQ_WR_CTL_2_LP 0x0AD6 +#define mmMC_SEQ_WR_CTL_D0 0x0A2F +#define mmMC_SEQ_WR_CTL_D0_LP 0x0A9F +#define mmMC_SEQ_WR_CTL_D1 0x0A30 +#define mmMC_SEQ_WR_CTL_D1_LP 0x0AA0 +#define mmMC_SHARED_BLACKOUT_CNTL 0x082B +#define mmMC_SHARED_CHMAP 0x0801 +#define mmMC_SHARED_CHREMAP 0x0802 +#define mmMC_TRAIN_EDCCDR_R_D0 0x0A41 +#define mmMC_TRAIN_EDCCDR_R_D1 0x0A42 +#define mmMC_TRAIN_EDC_STATUS_D0 0x0A45 +#define mmMC_TRAIN_EDC_STATUS_D1 0x0A48 +#define mmMC_TRAIN_PRBSERR_0_D0 0x0A43 +#define mmMC_TRAIN_PRBSERR_0_D1 0x0A46 +#define mmMC_TRAIN_PRBSERR_1_D0 0x0A44 +#define mmMC_TRAIN_PRBSERR_1_D1 0x0A47 +#define mmMC_TRAIN_PRBSERR_2_D0 0x0AFB +#define mmMC_TRAIN_PRBSERR_2_D1 0x0AFC +#define mmMC_VM_AGP_BASE 0x080C +#define mmMC_VM_AGP_BOT 0x080B +#define mmMC_VM_AGP_TOP 0x080A +#define mmMC_VM_DC_WRITE_CNTL 0x0810 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x0815 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x0811 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x0816 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x0812 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x0817 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x0813 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x0818 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x0814 +#define mmMC_VM_FB_LOCATION 0x0809 +#define mmMC_VM_FB_OFFSET 0x081A +#define mmMC_VM_MB_L1_TLB0_DEBUG 0x0891 +#define mmMC_VM_MB_L1_TLB0_STATUS 0x0895 +#define mmMC_VM_MB_L1_TLB1_STATUS 0x0896 +#define mmMC_VM_MB_L1_TLB2_DEBUG 0x0893 +#define mmMC_VM_MB_L1_TLB2_STATUS 0x0897 +#define mmMC_VM_MB_L1_TLB3_DEBUG 0x08A5 +#define mmMC_VM_MB_L1_TLB3_STATUS 0x08A6 +#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x08A1 +#define mmMC_VM_MD_L1_TLB0_DEBUG 0x0998 +#define mmMC_VM_MD_L1_TLB0_STATUS 0x099B +#define mmMC_VM_MD_L1_TLB1_DEBUG 0x0999 +#define mmMC_VM_MD_L1_TLB1_STATUS 0x099C +#define mmMC_VM_MD_L1_TLB2_DEBUG 0x099A +#define mmMC_VM_MD_L1_TLB2_STATUS 0x099D +#define mmMC_VM_MD_L1_TLB3_DEBUG 0x09A7 +#define mmMC_VM_MD_L1_TLB3_STATUS 0x09A8 +#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x09A4 +#define mmMC_VM_MX_L1_TLB_CNTL 0x0819 +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x080F +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x080E +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x080D +#define mmMC_WR_CB 0x0986 +#define mmMC_WR_DB 0x0987 +#define mmMC_WR_GRP_EXT 0x0979 +#define mmMC_WR_GRP_GFX 0x0804 +#define mmMC_WR_GRP_LCL 0x098B +#define mmMC_WR_GRP_OTH 0x0808 +#define mmMC_WR_GRP_SYS 0x0806 +#define mmMC_WR_HUB 0x0988 +#define mmMC_WR_TC0 0x097B +#define mmMC_WR_TC1 0x097C +#define mmMC_XBAR_ADDR_DEC 0x0C80 +#define mmMC_XBAR_ARB 0x0C8D +#define mmMC_XBAR_ARB_MAX_BURST 0x0C8E +#define mmMC_XBAR_CHTRIREMAP 0x0C8B +#define mmMC_XBAR_PERF_MON_CNTL0 0x0C8F +#define mmMC_XBAR_PERF_MON_CNTL1 0x0C90 +#define mmMC_XBAR_PERF_MON_CNTL2 0x0C91 +#define mmMC_XBAR_PERF_MON_MAX_THSH 0x0C96 +#define mmMC_XBAR_PERF_MON_RSLT0 0x0C92 +#define mmMC_XBAR_PERF_MON_RSLT1 0x0C93 +#define mmMC_XBAR_PERF_MON_RSLT2 0x0C94 +#define mmMC_XBAR_PERF_MON_RSLT3 0x0C95 +#define mmMC_XBAR_RDREQ_CREDIT 0x0C83 +#define mmMC_XBAR_RDREQ_PRI_CREDIT 0x0C84 +#define mmMC_XBAR_RDRET_CREDIT1 0x0C87 +#define mmMC_XBAR_RDRET_CREDIT2 0x0C88 +#define mmMC_XBAR_RDRET_PRI_CREDIT1 0x0C89 +#define mmMC_XBAR_RDRET_PRI_CREDIT2 0x0C8A +#define mmMC_XBAR_REMOTE 0x0C81 +#define mmMC_XBAR_SPARE0 0x0C97 +#define mmMC_XBAR_SPARE1 0x0C98 +#define mmMC_XBAR_TWOCHAN 0x0C8C +#define mmMC_XBAR_WRREQ_CREDIT 0x0C82 +#define mmMC_XBAR_WRRET_CREDIT1 0x0C85 +#define mmMC_XBAR_WRRET_CREDIT2 0x0C86 +#define mmMC_XPB_CLG_CFG0 0x08E9 +#define mmMC_XPB_CLG_CFG10 0x08F3 +#define mmMC_XPB_CLG_CFG1 0x08EA +#define mmMC_XPB_CLG_CFG11 0x08F4 +#define mmMC_XPB_CLG_CFG12 0x08F5 +#define mmMC_XPB_CLG_CFG13 0x08F6 +#define mmMC_XPB_CLG_CFG14 0x08F7 +#define mmMC_XPB_CLG_CFG15 0x08F8 +#define mmMC_XPB_CLG_CFG16 0x08F9 +#define mmMC_XPB_CLG_CFG17 0x08FA +#define mmMC_XPB_CLG_CFG18 0x08FB +#define mmMC_XPB_CLG_CFG19 0x08FC +#define mmMC_XPB_CLG_CFG20 0x0928 +#define mmMC_XPB_CLG_CFG2 0x08EB +#define mmMC_XPB_CLG_CFG21 0x0929 +#define mmMC_XPB_CLG_CFG22 0x092A +#define mmMC_XPB_CLG_CFG23 0x092B +#define mmMC_XPB_CLG_CFG24 0x092C +#define mmMC_XPB_CLG_CFG25 0x092D +#define mmMC_XPB_CLG_CFG26 0x092E +#define mmMC_XPB_CLG_CFG27 0x092F +#define mmMC_XPB_CLG_CFG28 0x0930 +#define mmMC_XPB_CLG_CFG29 0x0931 +#define mmMC_XPB_CLG_CFG30 0x0932 +#define mmMC_XPB_CLG_CFG3 0x08EC +#define mmMC_XPB_CLG_CFG31 0x0933 +#define mmMC_XPB_CLG_CFG32 0x0936 +#define mmMC_XPB_CLG_CFG33 0x0937 +#define mmMC_XPB_CLG_CFG34 0x0938 +#define mmMC_XPB_CLG_CFG35 0x0939 +#define mmMC_XPB_CLG_CFG36 0x093A +#define mmMC_XPB_CLG_CFG4 0x08ED +#define mmMC_XPB_CLG_CFG5 0x08EE +#define mmMC_XPB_CLG_CFG6 0x08EF +#define mmMC_XPB_CLG_CFG7 0x08F0 +#define mmMC_XPB_CLG_CFG8 0x08F1 +#define mmMC_XPB_CLG_CFG9 0x08F2 +#define mmMC_XPB_CLG_EXTRA 0x08FD +#define mmMC_XPB_CLG_EXTRA_RD 0x0935 +#define mmMC_XPB_CLK_GAT 0x091E +#define mmMC_XPB_INTF_CFG 0x091F +#define mmMC_XPB_INTF_CFG2 0x0934 +#define mmMC_XPB_INTF_STS 0x0920 +#define mmMC_XPB_LB_ADDR 0x08FE +#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x0923 +#define mmMC_XPB_MISC_CFG 0x0927 +#define mmMC_XPB_P2P_BAR0 0x0904 +#define mmMC_XPB_P2P_BAR1 0x0905 +#define mmMC_XPB_P2P_BAR2 0x0906 +#define mmMC_XPB_P2P_BAR3 0x0907 +#define mmMC_XPB_P2P_BAR4 0x0908 +#define mmMC_XPB_P2P_BAR5 0x0909 +#define mmMC_XPB_P2P_BAR6 0x090A +#define mmMC_XPB_P2P_BAR7 0x090B +#define mmMC_XPB_P2P_BAR_CFG 0x0903 +#define mmMC_XPB_P2P_BAR_DEBUG 0x090D +#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x090E +#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x090F +#define mmMC_XPB_P2P_BAR_SETUP 0x090C +#define mmMC_XPB_PEER_SYS_BAR0 0x0910 +#define mmMC_XPB_PEER_SYS_BAR1 0x0911 +#define mmMC_XPB_PEER_SYS_BAR2 0x0912 +#define mmMC_XPB_PEER_SYS_BAR3 0x0913 +#define mmMC_XPB_PEER_SYS_BAR4 0x0914 +#define mmMC_XPB_PEER_SYS_BAR5 0x0915 +#define mmMC_XPB_PEER_SYS_BAR6 0x0916 +#define mmMC_XPB_PEER_SYS_BAR7 0x0917 +#define mmMC_XPB_PEER_SYS_BAR8 0x0918 +#define mmMC_XPB_PEER_SYS_BAR9 0x0919 +#define mmMC_XPB_PERF_KNOBS 0x0924 +#define mmMC_XPB_PIPE_STS 0x0921 +#define mmMC_XPB_RTR_DEST_MAP0 0x08DB +#define mmMC_XPB_RTR_DEST_MAP1 0x08DC +#define mmMC_XPB_RTR_DEST_MAP2 0x08DD +#define mmMC_XPB_RTR_DEST_MAP3 0x08DE +#define mmMC_XPB_RTR_DEST_MAP4 0x08DF +#define mmMC_XPB_RTR_DEST_MAP5 0x08E0 +#define mmMC_XPB_RTR_DEST_MAP6 0x08E1 +#define mmMC_XPB_RTR_DEST_MAP7 0x08E2 +#define mmMC_XPB_RTR_DEST_MAP8 0x08E3 +#define mmMC_XPB_RTR_DEST_MAP9 0x08E4 +#define mmMC_XPB_RTR_SRC_APRTR0 0x08CD +#define mmMC_XPB_RTR_SRC_APRTR1 0x08CE +#define mmMC_XPB_RTR_SRC_APRTR2 0x08CF +#define mmMC_XPB_RTR_SRC_APRTR3 0x08D0 +#define mmMC_XPB_RTR_SRC_APRTR4 0x08D1 +#define mmMC_XPB_RTR_SRC_APRTR5 0x08D2 +#define mmMC_XPB_RTR_SRC_APRTR6 0x08D3 +#define mmMC_XPB_RTR_SRC_APRTR7 0x08D4 +#define mmMC_XPB_RTR_SRC_APRTR8 0x08D5 +#define mmMC_XPB_RTR_SRC_APRTR9 0x08D6 +#define mmMC_XPB_STICKY 0x0925 +#define mmMC_XPB_STICKY_W1C 0x0926 +#define mmMC_XPB_SUB_CTRL 0x0922 +#define mmMC_XPB_UNC_THRESH_HST 0x08FF +#define mmMC_XPB_UNC_THRESH_SID 0x0900 +#define mmMC_XPB_WCB_CFG 0x0902 +#define mmMC_XPB_WCB_STS 0x0901 +#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x091A +#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x091B +#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x091C +#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x091D +#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x08E5 +#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x08E6 +#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x08E7 +#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x08E8 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x08D7 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x08D8 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x08D9 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x08DA +#define mmMPLL_AD_FUNC_CNTL 0x0AF0 +#define mmMPLL_AD_STATUS 0x0AF6 +#define mmMPLL_CNTL_MODE 0x0AEC +#define mmMPLL_CONTROL 0x0AF5 +#define mmMPLL_DQ_0_0_STATUS 0x0AF7 +#define mmMPLL_DQ_0_1_STATUS 0x0AF8 +#define mmMPLL_DQ_1_0_STATUS 0x0AF9 +#define mmMPLL_DQ_1_1_STATUS 0x0AFA +#define mmMPLL_DQ_FUNC_CNTL 0x0AF1 +#define mmMPLL_FUNC_CNTL 0x0AED +#define mmMPLL_FUNC_CNTL_1 0x0AEE +#define mmMPLL_FUNC_CNTL_2 0x0AEF +#define mmMPLL_SEQ_UCODE_1 0x0AEA +#define mmMPLL_SEQ_UCODE_2 0x0AEB +#define mmMPLL_SS1 0x0AF3 +#define mmMPLL_SS2 0x0AF4 +#define mmMPLL_TIME 0x0AF2 +#define mmVM_CONTEXT0_CNTL 0x0504 +#define mmVM_CONTEXT0_CNTL2 0x050C +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x054F +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x055F +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x0557 +#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x053E +#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x0546 +#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x0536 +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x0510 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x0511 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x0512 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x0513 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x0514 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x0515 +#define mmVM_CONTEXT1_CNTL 0x0505 +#define mmVM_CONTEXT1_CNTL2 0x050D +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x0550 +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x0560 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x0558 +#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x053F +#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x0547 +#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x0537 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x0551 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x0552 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x0553 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x0554 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x0555 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x0556 +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x050E +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x050F +#define mmVM_CONTEXTS_DISABLE 0x0535 +#define mmVM_DEBUG 0x056F +#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x0507 +#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0506 +#define mmVM_FAULT_CLIENT_ID 0x054E +#define mmVM_INVALIDATE_REQUEST 0x051E +#define mmVM_INVALIDATE_RESPONSE 0x051F +#define mmVM_L2_BANK_SELECT_MASKA 0x0572 +#define mmVM_L2_BANK_SELECT_MASKB 0x0573 +#define mmVM_L2_CG 0x0570 +#define mmVM_L2_CNTL 0x0500 +#define mmVM_L2_CNTL2 0x0501 +#define mmVM_L2_CNTL3 0x0502 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x0576 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x0575 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x0577 +#define mmVM_L2_STATUS 0x0503 +#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x0530 +#define mmVM_PRT_APERTURE0_LOW_ADDR 0x052C +#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x0531 +#define mmVM_PRT_APERTURE1_LOW_ADDR 0x052D +#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x0532 +#define mmVM_PRT_APERTURE2_LOW_ADDR 0x052E +#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x0533 +#define mmVM_PRT_APERTURE3_LOW_ADDR 0x052F +#define mmVM_PRT_CNTL 0x0534 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h new file mode 100644 index 000000000000..0f6c6c8d089b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h @@ -0,0 +1,11895 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_6_0_SH_MASK_H +#define GMC_6_0_SH_MASK_H + +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 +#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L +#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x00000004L +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x00000002 +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x00004000L +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0x0000000e +#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x00000080L +#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x00000007 +#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x00000002L +#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x00000001 +#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x00008000L +#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0x0000000f +#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x00000001L +#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x00000000 +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x00010000L +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x00000010 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x00003c00L +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0x0000000a +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x00000100L +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x00000008 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x00000020L +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x00000005 +#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x00000040L +#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x00000006 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x00000200L +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x00000009 +#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x0000003cL +#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x00000002 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x00000001L +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x00000000 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffffL +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x00000000 +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x03f00000L +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x00000014 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0000fc00L +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0x0000000a +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x0000003fL +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x00000000 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000100L +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000008 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x00010000L +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x00000010 +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x0000001fL +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x00000000 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffffL +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x00000000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x00000010 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0x0000000f +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x0000003fL +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x00000000 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x00000011 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0f000000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x00000018 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x00000012 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00f80000L +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x00000013 +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007c00L +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0x0000000a +#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L +#define ATC_ATS_STATUS__BUSY__SHIFT 0x00000000 +#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x00000001 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000002 +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffffL +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x00000000 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x00000003L +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x00000000 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x00000004L +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x00000002 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x00000010L +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x00000004 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008 +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e +#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x00000100L +#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x00000008 +#define ATC_L1RD_STATUS__BUSY_MASK 0x00000001L +#define ATC_L1RD_STATUS__BUSY__SHIFT 0x00000000 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008 +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e +#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x00000100L +#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x00000008 +#define ATC_L1WR_STATUS__BUSY_MASK 0x00000001L +#define ATC_L1WR_STATUS__BUSY__SHIFT 0x00000000 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x00000000 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000a +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000030L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x00000004 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000b +#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x0000003fL +#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x00000000 +#define ATC_MISC_CG__ENABLE_MASK 0x00040000L +#define ATC_MISC_CG__ENABLE__SHIFT 0x00000012 +#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define ATC_MISC_CG__OFFDLY_MASK 0x00000fc0L +#define ATC_MISC_CG__OFFDLY__SHIFT 0x00000006 +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000 +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000 +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000 +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000ffffL +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x00000000 +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x0000001f +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x00000000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0x0000000a +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0x0000000b +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0x0000000c +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0x0000000d +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0x0000000e +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0x0000000f +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x00000001 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x00000002 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x00000003 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x00000004 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x00000005 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x00000006 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x00000007 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x00000008 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x00000009 +#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x0000001eL +#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x00000001 +#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x003ff000L +#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0x0000000c +#define DLL_CNTL__DLL_RESET_TIME_MASK 0x000003ffL +#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x00000000 +#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x01000000L +#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x00000018 +#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x02000000L +#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x00000019 +#define DLL_CNTL__PWR2_MODE_MASK 0x04000000L +#define DLL_CNTL__PWR2_MODE__SHIFT 0x0000001a +#define GMCON_DEBUG__GFX_CLEAR_MASK 0x00000002L +#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x00000001 +#define GMCON_DEBUG__GFX_STALL_MASK 0x00000001L +#define GMCON_DEBUG__GFX_STALL__SHIFT 0x00000000 +#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffcL +#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x00000002 +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x00000007L +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x00000000 +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x00000038L +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x00000003 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x0000fc00L +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0x0000000a +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x20000000L +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x0000001d +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x10000000L +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x0000001c +#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x0fff0000L +#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x00000010 +#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x0000003fL +#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x00000000 +#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0x00000fc0L +#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x00000006 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00fff000L +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x0000000c +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x30000000L +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0000001c +#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x08000000L +#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x0000001b +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x00000400L +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0x0000000a +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00000800L +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x0000000b +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0x0000f000L +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0x0000000c +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x02000000L +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x00000019 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x04000000L +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x0000001a +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x40000000L +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x0000001e +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x00060000L +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x00000011 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x00400000L +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x00000016 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x00200000L +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x00000015 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x01000000L +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x00000018 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x00800000L +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x00000017 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x00180000L +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x00000013 +#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x00010000L +#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x00000010 +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c +#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L +#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018 +#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL +#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000 +#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L +#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a +#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L +#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c +#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x00fc0000L +#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x00000012 +#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000L +#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x00000018 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x00000fc0L +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000006 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x0003f000L +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x0000000c +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x0000003fL +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000 +#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL +#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000 +#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL +#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000 +#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000ffL +#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x00000000 +#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L +#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0x0000000a +#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L +#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0x0000000b +#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L +#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x00000008 +#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L +#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x00000009 +#define GMCON_PGFSM_CONFIG__READ_MASK 0x00002000L +#define GMCON_PGFSM_CONFIG__READ__SHIFT 0x0000000d +#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000L +#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x0000001c +#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x07ffc000L +#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0x0000000e +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x0000001b +#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x00001000L +#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0x0000000c +#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0x0f000000L +#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x00000018 +#define GMCON_PGFSM_READ__READ_VALUE_MASK 0x00ffffffL +#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x00000000 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000L +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x0000001c +#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffffL +#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x00000000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x003ff000L +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0x0000000c +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000L +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x00000016 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x00000001 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000ffcL +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x00000002 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x00000000 +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffffL +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x00000000 +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003ffL +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x00000010 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x00000010 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x00000010 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x00000010 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0x0000ffffL +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x00000000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000L +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x00000010 +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0x0000000fL +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x00000000 +#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0x00000ff0L +#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x00000004 +#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0x0ffff000L +#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0x0000000c +#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x01000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x00000018 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x02000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x00000019 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x04000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x0000001a +#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x08000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x0000001b +#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x0000001c +#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x0000001d +#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x0000001e +#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000L +#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x0000001f +#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x00010000L +#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x00000010 +#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x00020000L +#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x00000011 +#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x00040000L +#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x00000012 +#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x00080000L +#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x00000013 +#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x00100000L +#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x00000014 +#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x00200000L +#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x00000015 +#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x00400000L +#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x00000016 +#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x00800000L +#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x00000017 +#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x00000003L +#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x00000000 +#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0x0000000cL +#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x00000002 +#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x00000030L +#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x00000004 +#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0x000000c0L +#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x00000006 +#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x00000300L +#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x00000008 +#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0x00000c00L +#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0x0000000a +#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x00003000L +#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0x0000000c +#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0x0000c000L +#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0x0000000e +#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x01000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x00000018 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x02000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x00000019 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x04000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x0000001a +#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x08000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x0000001b +#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x0000001c +#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x0000001d +#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x0000001e +#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000L +#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x0000001f +#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x00010000L +#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x00000010 +#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x00020000L +#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x00000011 +#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x00040000L +#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x00000012 +#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x00080000L +#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x00000013 +#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x00100000L +#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x00000014 +#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x00200000L +#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x00000015 +#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x00400000L +#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x00000016 +#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x00800000L +#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x00000017 +#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x00000003L +#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x00000000 +#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0x0000000cL +#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x00000002 +#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x00000030L +#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x00000004 +#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0x000000c0L +#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x00000006 +#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x00000300L +#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x00000008 +#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0x00000c00L +#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0x0000000a +#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x00003000L +#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0x0000000c +#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0x0000c000L +#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0x0000000e +#define MC_ARB_BANKMAP__BANK0_MASK 0x0000000fL +#define MC_ARB_BANKMAP__BANK0__SHIFT 0x00000000 +#define MC_ARB_BANKMAP__BANK1_MASK 0x000000f0L +#define MC_ARB_BANKMAP__BANK1__SHIFT 0x00000004 +#define MC_ARB_BANKMAP__BANK2_MASK 0x00000f00L +#define MC_ARB_BANKMAP__BANK2__SHIFT 0x00000008 +#define MC_ARB_BANKMAP__BANK3_MASK 0x0000f000L +#define MC_ARB_BANKMAP__BANK3__SHIFT 0x0000000c +#define MC_ARB_BANKMAP__RANK_MASK 0x000f0000L +#define MC_ARB_BANKMAP__RANK__SHIFT 0x00000010 +#define MC_ARB_BURST_TIME__STATE0_MASK 0x0000001fL +#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x00000000 +#define MC_ARB_BURST_TIME__STATE1_MASK 0x000003e0L +#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x00000005 +#define MC_ARB_BURST_TIME__STATE2_MASK 0x00007c00L +#define MC_ARB_BURST_TIME__STATE2__SHIFT 0x0000000a +#define MC_ARB_BURST_TIME__STATE3_MASK 0x000f8000L +#define MC_ARB_BURST_TIME__STATE3__SHIFT 0x0000000f +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x00002000L +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0x0000000d +#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x00000001L +#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x00000000 +#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x0000007eL +#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x00000001 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x00001f80L +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x00000007 +#define MC_ARB_CG__CG_ARB_REQ_MASK 0x000000ffL +#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x00000000 +#define MC_ARB_CG__CG_ARB_RESP_MASK 0x0000ff00L +#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0x000000ffL +#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x00000000 +#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0x0000ff00L +#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0x00ff0000L +#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x00000010 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000L +#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x00000018 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000L +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x00000018 +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0x000000ffL +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x00000000 +#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0x0000ff00L +#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0x00ff0000L +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x00000010 +#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000L +#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x00000018 +#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0x000000ffL +#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x00000000 +#define MC_ARB_DRAM_TIMING2__RP_MASK 0x0000ff00L +#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0x00ff0000L +#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x00000010 +#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0x000000ffL +#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x00000000 +#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0x0000ff00L +#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x00000008 +#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0x00ff0000L +#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x00000010 +#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000L +#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x00000018 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x00000010L +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x00000004 +#define MC_ARB_FED_CNTL__MODE_MASK 0x00000003L +#define MC_ARB_FED_CNTL__MODE__SHIFT 0x00000000 +#define MC_ARB_FED_CNTL__WR_ERR_MASK 0x0000000cL +#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x00000002 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0x0000000fL +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x00000000 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0x000000f0L +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x00000004 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a +#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x00000100L +#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x00000008 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x00000200L +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x00000009 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0x0000000fL +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x00000000 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0x000000f0L +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x00000004 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a +#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x00000100L +#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x00000008 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x00000200L +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x00000009 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0x000000ffL +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x00000000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0x0000ff00L +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x00000008 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0x00ff0000L +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x00000010 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000L +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x00000018 +#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x00004000L +#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0x0000000e +#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x001f8000L +#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0x0000000f +#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0x0000ff00L +#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x00000008 +#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0x00ff0000L +#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x00000010 +#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000L +#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x00000018 +#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0x000000ffL +#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x00000000 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x00000018L +#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x00000003 +#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x00000004L +#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x00000002 +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x00000003L +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x00000000 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x00000020L +#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x00000005 +#define MC_ARB_GECC2__ECC_MODE_MASK 0x00000006L +#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x00000001 +#define MC_ARB_GECC2__ENABLE_MASK 0x00000001L +#define MC_ARB_GECC2__ENABLE__SHIFT 0x00000000 +#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x00000060L +#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x00000005 +#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0x0000000fL +#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x00000000 +#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x00000780L +#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x00000007 +#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x00000018L +#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x00000003 +#define MC_ARB_GECC2__READ_ERR_MASK 0x00003800L +#define MC_ARB_GECC2__READ_ERR__SHIFT 0x0000000b +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x00000100L +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x00000008 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x00001000L +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0x0000000c +#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x00000001L +#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x00000000 +#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x00000010L +#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x00000004 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x00000400L +#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0x0000000a +#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x00004000L +#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0x0000000e +#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x00000004L +#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x00000002 +#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x00000040L +#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x00000006 +#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x00000008L +#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x00000003 +#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x00000080L +#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x00000007 +#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x00000800L +#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0x0000000b +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x00000200L +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x00000009 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x00002000L +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0x0000000d +#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x00000002L +#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x00000001 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x00000020L +#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x00000005 +#define MC_ARB_LAZY0_RD__GROUP0_MASK 0x000000ffL +#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x00000000 +#define MC_ARB_LAZY0_RD__GROUP1_MASK 0x0000ff00L +#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x00000008 +#define MC_ARB_LAZY0_RD__GROUP2_MASK 0x00ff0000L +#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x00000010 +#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000L +#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x00000018 +#define MC_ARB_LAZY0_WR__GROUP0_MASK 0x000000ffL +#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x00000000 +#define MC_ARB_LAZY0_WR__GROUP1_MASK 0x0000ff00L +#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x00000008 +#define MC_ARB_LAZY0_WR__GROUP2_MASK 0x00ff0000L +#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x00000010 +#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000L +#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x00000018 +#define MC_ARB_LAZY1_RD__GROUP4_MASK 0x000000ffL +#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x00000000 +#define MC_ARB_LAZY1_RD__GROUP5_MASK 0x0000ff00L +#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x00000008 +#define MC_ARB_LAZY1_RD__GROUP6_MASK 0x00ff0000L +#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x00000010 +#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000L +#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x00000018 +#define MC_ARB_LAZY1_WR__GROUP4_MASK 0x000000ffL +#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x00000000 +#define MC_ARB_LAZY1_WR__GROUP5_MASK 0x0000ff00L +#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x00000008 +#define MC_ARB_LAZY1_WR__GROUP6_MASK 0x00ff0000L +#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x00000010 +#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000L +#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x00000018 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0x00e00000L +#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x00000015 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x00040000L +#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x00000012 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x00080000L +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x00000013 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x00100000L +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x00000014 +#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x00010000L +#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x00000010 +#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0x000000ffL +#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x00000000 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0x0000ff00L +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x00000008 +#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x00020000L +#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x00000011 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0x00e00000L +#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x00000015 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x00040000L +#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x00000012 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x00080000L +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x00000013 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x00100000L +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x00000014 +#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x00010000L +#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x00000010 +#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0x000000ffL +#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x00000000 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0x0000ff00L +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x00000008 +#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x00020000L +#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x00000011 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x00010000L +#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x00000010 +#define MC_ARB_MINCLKS__READ_CLKS_MASK 0x000000ffL +#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x00000000 +#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0x0000ff00L +#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x00000008 +#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000L +#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x0000001d +#define MC_ARB_MISC2__GECC_MASK 0x00040000L +#define MC_ARB_MISC2__GECC_RST_MASK 0x00080000L +#define MC_ARB_MISC2__GECC_RST__SHIFT 0x00000013 +#define MC_ARB_MISC2__GECC__SHIFT 0x00000012 +#define MC_ARB_MISC2__GECC_STATUS_MASK 0x00100000L +#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x00000014 +#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x00000800L +#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0x0000000b +#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x00002000L +#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0x0000000d +#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x00001000L +#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0x0000000c +#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x0003c000L +#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0x0000000e +#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000L +#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x0000001c +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000L +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x0000001e +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x01e00000L +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x00000015 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x00000040L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x00000006 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x00000080L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x00000007 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x00000100L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x00000008 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x00000200L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x00000009 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x00000400L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0x0000000a +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x00000020L +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x00000005 +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000L +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x0000001f +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0x0e000000L +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x00000019 +#define MC_ARB_MISC__CALI_ENABLE_MASK 0x00100000L +#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x00000014 +#define MC_ARB_MISC__CALI_RATES_MASK 0x00600000L +#define MC_ARB_MISC__CALI_RATES__SHIFT 0x00000015 +#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x000007f8L +#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x00000003 +#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x01000000L +#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x00000018 +#define MC_ARB_MISC__DISPURG_STALL_MASK 0x02000000L +#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x00000019 +#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000L +#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x0000001a +#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x00800000L +#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x00000017 +#define MC_ARB_MISC__HARSHNESS_MASK 0x0007f800L +#define MC_ARB_MISC__HARSHNESS__SHIFT 0x0000000b +#define MC_ARB_MISC__IDLE_RFSH_MASK 0x00000002L +#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x00000001 +#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x00080000L +#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x00000013 +#define MC_ARB_MISC__STICKY_RFSH_MASK 0x00000001L +#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x00000000 +#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x00000004L +#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x00000002 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x00000020L +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x00000005 +#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0x00f00000L +#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x00000014 +#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x00000040L +#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x00000006 +#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x00040000L +#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x00000012 +#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x00080000L +#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x00000013 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x00000003L +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x00000000 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x00000004L +#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x00000002 +#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x00000008L +#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x00000003 +#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x00000080L +#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x00000007 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x00000300L +#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x00000008 +#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x00000400L +#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0x0000000a +#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x00000800L +#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0x0000000b +#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x00004000L +#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0x0000000e +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x00008000L +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0x0000000f +#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x00001000L +#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0x0000000c +#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x00002000L +#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0x0000000d +#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x00000010L +#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x00000004 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x00080000L +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x00000013 +#define MC_ARB_POP__ENABLE_ARB_MASK 0x00000001L +#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x00000000 +#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x00040000L +#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x00000012 +#define MC_ARB_POP__POP_DEPTH_MASK 0x0000003cL +#define MC_ARB_POP__POP_DEPTH__SHIFT 0x00000002 +#define MC_ARB_POP__QUICK_STOP_MASK 0x00020000L +#define MC_ARB_POP__QUICK_STOP__SHIFT 0x00000011 +#define MC_ARB_POP__SKID_DEPTH_MASK 0x00007000L +#define MC_ARB_POP__SKID_DEPTH__SHIFT 0x0000000c +#define MC_ARB_POP__SPEC_OPEN_MASK 0x00000002L +#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x00000001 +#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x00018000L +#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0x0000000f +#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0x00000fc0L +#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x00000006 +#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x00000100L +#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x00000008 +#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x00000003L +#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x00000000 +#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0x000000c0L +#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x00000006 +#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x00001000L +#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0x0000000c +#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x00000004L +#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x00000002 +#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x00000038L +#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x00000003 +#define MC_ARB_REMREQ__RD_WATER_MASK 0x000000ffL +#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x00000000 +#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0x00f00000L +#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x00000014 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0x000f0000L +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x00000010 +#define MC_ARB_REMREQ__WR_WATER_MASK 0x0000ff00L +#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x00000008 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x00000080L +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x00000007 +#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x00007f00L +#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x00000008 +#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x00000040L +#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x00000006 +#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x00000001L +#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x00000000 +#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x00000002L +#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x00000001 +#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x00000020L +#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x00000005 +#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x00000010L +#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x00000004 +#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x00000008L +#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x00000003 +#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x00000004L +#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x00000002 +#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0x00ff0000L +#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x00000010 +#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0x0000ff00L +#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x00000008 +#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0x000000ffL +#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x00000000 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000L +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x00000018 +#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0x0000ff00L +#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x00000008 +#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0x000000ffL +#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x00000000 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0x00ff0000L +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x00000010 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0x0f000000L +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x00000018 +#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x00000800L +#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0x0000000b +#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x00000001L +#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x00000000 +#define MC_ARB_RFSH_CNTL__URG0_MASK 0x0000003eL +#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x00000001 +#define MC_ARB_RFSH_CNTL__URG1_MASK 0x000007c0L +#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x00000006 +#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0x000000ffL +#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x00000000 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x00000100L +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x00000008 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x00000200L +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x00000009 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x00000400L +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0x0000000a +#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x01000000L +#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x00000018 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x00008000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0x0000000f +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x00010000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x00000010 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x00020000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x00000011 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x00040000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x00000012 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x00080000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x00000013 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x00100000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x00000014 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x00200000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x00000015 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x00400000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x00000016 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x00800000L +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x00000017 +#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x00000001L +#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x00000000 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x00000010L +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x00000004 +#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x00000020L +#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x00000005 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x02000000L +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x00000019 +#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x00000002L +#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x00000001 +#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0x0000000cL +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x00004000L +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0x0000000e +#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x00000002 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x00000040L +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x00000006 +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x00003800L +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0x0000000b +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x00000080L +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x00000007 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0x000fe000L +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0x0000000d +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x00001fc0L +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x00000006 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x0000001fL +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x01f00000L +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x00000014 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000L +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x00000019 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x00000000 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000L +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x0000001e +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x00000020L +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x00000005 +#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x00002000L +#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0x0000000d +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x00001000L +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0x0000000c +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0x00000fc0L +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x00000006 +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x0000003fL +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x00000000 +#define MC_ARB_RTT_DATA__PATTERN_MASK 0x000000ffL +#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x00000000 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x00000003L +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x00000000 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0x0000000cL +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x00000002 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0x00000ff0L +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x00000004 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x01fe0000L +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x00000011 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x0001f000L +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0x0000000c +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000L +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x00000019 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x00000100L +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x00000008 +#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0x000000ffL +#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x00000000 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000L +#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x00000018 +#define MC_ARB_SQM_CNTL__RATIO_MASK 0x00ff0000L +#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x00000010 +#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0x0000fe00L +#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0x00000009 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x00000006L +#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x00000001 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x00000001L +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x00000000 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x00000010L +#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x00000004 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x00000008L +#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x00000003 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x00000006L +#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x00000001 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x00000001L +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x00000000 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x00000010L +#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x00000004 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x00000008L +#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x00000003 +#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x00000200L +#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x00000009 +#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x00000400L +#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0x0000000a +#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x00000800L +#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0x0000000b +#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x00001000L +#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0x0000000c +#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x00002000L +#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0x0000000d +#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x00004000L +#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0x0000000e +#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0x0000000fL +#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x00000000 +#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x000001f0L +#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x00000004 +#define MC_ARB_WCDR__IDLE_BURST_MASK 0x00001f80L +#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x00002000L +#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0x0000000d +#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x00000007 +#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x00010000L +#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x00000010 +#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x00000001L +#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x00000000 +#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x0000007cL +#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x00000002 +#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0x0000c000L +#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0x0000000e +#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x00000002L +#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x00000001 +#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x00020000L +#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x00000011 +#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x02000000L +#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x00000019 +#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x08000000L +#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x0000001b +#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x04000000L +#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x0000001a +#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x01c00000L +#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x00000016 +#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x003c0000L +#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x00000012 +#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000L +#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x0000001c +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x00000008L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x00000003 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x00000010L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x00000004 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x00000020L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x00000005 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x00000040L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x00000006 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x00000080L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x00000007 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x00000100L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x00000008 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x00000200L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x00000009 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x00000400L +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x00000004L +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x00000002 +#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x00000003L +#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x00000000 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x00000008L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x00000003 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x00000010L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x00000004 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x00000020L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x00000005 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x00000040L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x00000006 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x00000080L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x00000007 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x00000100L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x00000008 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x00000200L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x00000009 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x00000400L +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x00000004L +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x00000002 +#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x00000003L +#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x00000000 +#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x00000003L +#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x00000000 +#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0x0000000cL +#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x00000002 +#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x00000030L +#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x00000004 +#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0x000000c0L +#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x00000006 +#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x00000300L +#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x00000008 +#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0x00000c00L +#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0x0000000a +#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x00003000L +#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0x0000000c +#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0x0000c000L +#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0x0000000e +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0x00ff0000L +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x00000010 +#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x00000003L +#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x00000000 +#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0x0000000cL +#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x00000002 +#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x00000030L +#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x00000004 +#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0x000000c0L +#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x00000006 +#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x00000300L +#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x00000008 +#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0x00000c00L +#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0x0000000a +#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x00003000L +#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0x0000000c +#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0x0000c000L +#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0x0000000e +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0x00ff0000L +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x00000010 +#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0x000000f0L +#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x00000004 +#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x02000000L +#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x00000019 +#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0x00ffff00L +#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x00000008 +#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x01000000L +#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x00000018 +#define MC_BIST_AUTO_CNTL__MOP_MASK 0x00000003L +#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x00000000 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x00000004L +#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x00000002 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x00000002L +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x00000001 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x00010000L +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x00000010 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x00020000L +#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x00000011 +#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000L +#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x0000001f +#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000L +#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x0000001c +#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000L +#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x0000001d +#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0x0000fff0L +#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x00000004 +#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0x0ffc0000L +#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x00000012 +#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x00000008L +#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x00000003 +#define MC_BIST_CMD_CNTL__RESET_MASK 0x00000001L +#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x00000000 +#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000L +#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x0000001e +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x0000001fL +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x00000100L +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x00000008 +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x00000000 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x0001f000L +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x00100000L +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x00000014 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0x0000000c +#define MC_BIST_CMP_CNTL__CMP_MASK 0x00030000L +#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0x00000ff0L +#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x00000004 +#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0x0000000fL +#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x00000000 +#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x00000010 +#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x00300000L +#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x00000014 +#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x00002000L +#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0x0000000d +#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x00040000L +#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x00000012 +#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x00080000L +#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x00000013 +#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x00004000L +#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0x0000000e +#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x00008000L +#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0x0000000f +#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x00001000L +#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0x0000000c +#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000L +#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x00000016 +#define MC_BIST_CNTL__ADR_MODE_MASK 0x00000020L +#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x00000005 +#define MC_BIST_CNTL__DAT_MODE_MASK 0x00000040L +#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x00000006 +#define MC_BIST_CNTL__DONE_MASK 0x40000000L +#define MC_BIST_CNTL__DONE__SHIFT 0x0000001e +#define MC_BIST_CNTL__ENABLE_D0_MASK 0x00001000L +#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0x0000000c +#define MC_BIST_CNTL__ENABLE_D1_MASK 0x00002000L +#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0x0000000d +#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x00004000L +#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0x0000000e +#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000L +#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x0000001f +#define MC_BIST_CNTL__LOOP_CNT_MASK 0x0fff0000L +#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x00000010 +#define MC_BIST_CNTL__LOOP_MASK 0x00000c00L +#define MC_BIST_CNTL__LOOP__SHIFT 0x0000000a +#define MC_BIST_CNTL__MOP_MODE_MASK 0x00000010L +#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x00000004 +#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x00000004L +#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x00000002 +#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x00000008L +#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x00000003 +#define MC_BIST_CNTL__RESET_MASK 0x00000001L +#define MC_BIST_CNTL__RESET__SHIFT 0x00000000 +#define MC_BIST_CNTL__RUN_MASK 0x00000002L +#define MC_BIST_CNTL__RUN__SHIFT 0x00000001 +#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffffL +#define MC_BIST_DATA_MASK__MASK__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x00000000 +#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffffL +#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x00000000 +#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x00000040L +#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x00000006 +#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x00000100L +#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x00000008 +#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x00000020L +#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x00000005 +#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x00000080L +#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x00000007 +#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x00000200L +#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x00000009 +#define MC_BIST_DIR_CNTL__EOB_MASK 0x00000008L +#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x00000003 +#define MC_BIST_DIR_CNTL__MOP3_MASK 0x00000400L +#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0x0000000a +#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x00000010L +#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x00000004 +#define MC_BIST_DIR_CNTL__MOP_MASK 0x00000007L +#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x00000000 +#define MC_BIST_EADDR__BANK_MASK 0x0f000000L +#define MC_BIST_EADDR__BANK__SHIFT 0x00000018 +#define MC_BIST_EADDR__COLH_MASK 0x20000000L +#define MC_BIST_EADDR__COLH__SHIFT 0x0000001d +#define MC_BIST_EADDR__COL_MASK 0x000003ffL +#define MC_BIST_EADDR__COL__SHIFT 0x00000000 +#define MC_BIST_EADDR__RANK_MASK 0x10000000L +#define MC_BIST_EADDR__RANK__SHIFT 0x0000001c +#define MC_BIST_EADDR__ROWH_MASK 0xc0000000L +#define MC_BIST_EADDR__ROWH__SHIFT 0x0000001e +#define MC_BIST_EADDR__ROW_MASK 0x00fffc00L +#define MC_BIST_EADDR__ROW__SHIFT 0x0000000a +#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0x0f000000L +#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x00000018 +#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000L +#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x0000001d +#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x000003ffL +#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x00000000 +#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000L +#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x0000001c +#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000L +#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x0000001e +#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0x00fffc00L +#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0x0000000a +#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffffL +#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x00000000 +#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffffL +#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x00000000 +#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffffL +#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x00000000 +#define MC_BIST_SADDR__BANK_MASK 0x0f000000L +#define MC_BIST_SADDR__BANK__SHIFT 0x00000018 +#define MC_BIST_SADDR__COLH_MASK 0x20000000L +#define MC_BIST_SADDR__COLH__SHIFT 0x0000001d +#define MC_BIST_SADDR__COL_MASK 0x000003ffL +#define MC_BIST_SADDR__COL__SHIFT 0x00000000 +#define MC_BIST_SADDR__RANK_MASK 0x10000000L +#define MC_BIST_SADDR__RANK__SHIFT 0x0000001c +#define MC_BIST_SADDR__ROWH_MASK 0xc0000000L +#define MC_BIST_SADDR__ROWH__SHIFT 0x0000001e +#define MC_BIST_SADDR__ROW_MASK 0x00fffc00L +#define MC_BIST_SADDR__ROW__SHIFT 0x0000000a +#define MC_CG_CONFIG__INDEX_MASK 0x003fffc0L +#define MC_CG_CONFIG__INDEX__SHIFT 0x00000006 +#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000L +#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0x0000000d +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008 +#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L +#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000 +#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L +#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001 +#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L +#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L +#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003 +#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x00000030L +#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004 +#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffffL +#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x00000000 +#define MC_CITF_CNTL__EXEMPTPM_MASK 0x00000008L +#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x00000003 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x00000030L +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x00000004 +#define MC_CITF_CNTL__IGNOREPM_MASK 0x00000004L +#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x00000002 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x00000040L +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x00000006 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x02000000L +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x00000019 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x01000000L +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x00000018 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0x0000ff00L +#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x00000008 +#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0x000000ffL +#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x00000000 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0x00ff0000L +#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x00000010 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x00010000L +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x00000010 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x00020000L +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x00000011 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0x0000ff00L +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x00000008 +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0x000000ffL +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x00000000 +#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x0000003fL +#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x00000000 +#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0x00000fc0L +#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x00000006 +#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0x000000ffL +#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x00000000 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0x0000ff00L +#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x00000008 +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x0000001eL +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x00000001 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x000003c0L +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x00000006 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x00000020L +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x00000005 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x00000001L +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x00000000 +#define MC_CITF_DAGB_DLY__CLI_MASK 0x001f0000L +#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x00000010 +#define MC_CITF_DAGB_DLY__DLY_MASK 0x0000001fL +#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x00000000 +#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000L +#define MC_CITF_DAGB_DLY__POS__SHIFT 0x00000018 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0x00fc0000L +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x00000012 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x0003f000L +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0x0000000c +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000L +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x00000018 +#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x0000003fL +#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x00000000 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x0000003fL +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x00000000 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0x00000fc0L +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x00000006 +#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x00040000L +#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x00000012 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0x00000fc0L +#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x00000006 +#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x0000003fL +#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x00000000 +#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x0003f000L +#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0x0000000c +#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x00040000L +#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x00000012 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L +#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x00000006 +#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x0000003fL +#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x00000000 +#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x0003f000L +#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c +#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x00040000L +#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x00000012 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0x00000fc0L +#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x00000006 +#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x0000003fL +#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x00000000 +#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x0003f000L +#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0x0000000c +#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0x000001ffL +#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x00000000 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x00000040L +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x00000006 +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x00001000L +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x0000000c +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x00000080L +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x00000007 +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x00002000L +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x0000000d +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x00004000L +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x0000000e +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x00000100L +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x00000008 +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x00010000L +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x00000010 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x00000400L +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x0000000a +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x00020000L +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x00000011 +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x00008000L +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0x0000000f +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x00040000L +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x00000012 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x00000200L +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x00000009 +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x00000800L +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x0000000b +#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x00004000L +#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0x0000000e +#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x0000007fL +#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x00000000 +#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x00003f80L +#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x00000007 +#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x00000001L +#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x00000000 +#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x00000002L +#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x00000001 +#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x00000010L +#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x00000004 +#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x00000020L +#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x00000005 +#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x00000004L +#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x00000002 +#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x00000008L +#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x00000003 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x01000000L +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x00000018 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x00000007L +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x00000038L +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x00007000L +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x00038000L +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x01000000L +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x00000018 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x00000007L +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x00000038L +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x00007000L +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x00038000L +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 +#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0x00000f00L +#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x00000008 +#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x00000001L +#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x00000000 +#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x00000002L +#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x00000001 +#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x00000004L +#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x00000002 +#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x00000008L +#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x00000003 +#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x00000010L +#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x00000004 +#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x00001000L +#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0x0000000c +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000L +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x0000001f +#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L +#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L +#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L +#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L +#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L +#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L +#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005 +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000L +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x0000001f +#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L +#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008 +#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L +#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000 +#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L +#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001 +#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L +#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002 +#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L +#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003 +#define MC_CONFIG__MC_RD_ENABLE_MASK 0x00000030L +#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004 +#define MC_HUB_MISC_DBG__SELECT0_MASK 0x0000000fL +#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x00000000 +#define MC_HUB_MISC_DBG__SELECT1_MASK 0x000000f0L +#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x00000004 +#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffffL +#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x00000000 +#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x00040000L +#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x00000012 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0x00000fc0L +#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x00000006 +#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x0000003fL +#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x00000000 +#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x0003f000L +#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0x0000000c +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x00000001L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x00000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x00000002L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x00000001 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x00000400L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x0000000a +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x00000800L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x0000000b +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x00000004L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x00000002 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x00000008L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x00000003 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x00010000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0x00000010 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x00020000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0x00000011 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x00040000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x00000012 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x00080000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x00000013 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x00000040L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x00000006 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x00000080L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x00000007 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x00004000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0x0000000e +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x00008000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0x0000000f +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x00001000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0x0000000c +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x00002000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0x0000000d +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x01000000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x00000018 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x02000000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x00000019 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x00100000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x00000014 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x00200000L +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x00000015 +#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x00000003L +#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x00000000 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x00000018L +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x00000003 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x00000004L +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x00000002 +#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x00040000L +#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x00000012 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0x00000fc0L +#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x00000006 +#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x0000003fL +#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x00000000 +#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x0003f000L +#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0x0000000c +#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x00002000L +#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x0000000d +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x00000004L +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x00000002 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x00000008L +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x00000003 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x00000010L +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x00000004 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x00000020L +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x00000005 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x00000100L +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x00000008 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x00000200L +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x00000009 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x00000001L +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x00000000 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x00000040L +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x00000006 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x00000080L +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x00000007 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x00000002L +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x00000001 +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x00001000L +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x0000000c +#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x00000400L +#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0x0000000a +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x00000800L +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x0000000b +#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x00040000L +#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x00000012 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L +#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x00000006 +#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x0000003fL +#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x00000000 +#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x0003f000L +#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x00000200L +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x00000009 +#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x0001fc00L +#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0x0000000a +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00020000L +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x00000011 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00040000L +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x00000012 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x00000004L +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000002 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x00000008L +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000003 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x00000020L +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x00000005 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x00000040L +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x00000080L +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x00000007 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x00000100L +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x00000008 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x00080000L +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x00000013 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x00000001L +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x00000000 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0x000000ffL +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x00000000 +#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0x00ff0000L +#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x00000010 +#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000L +#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x00000018 +#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0x000000ffL +#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x00000000 +#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0x0000ff00L +#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x00000008 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x00000003L +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x0000007cL +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x00000002 +#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0x000000ffL +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x00000000 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0x000000ffL +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x00000000 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x0003f800L +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x00000004L +#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x00000002 +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x01fc0000L +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x00000012 +#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x00000780L +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x00000078L +#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000L +#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x00000019 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x0003f800L +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x00000004L +#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x00000002 +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x01fc0000L +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x00000012 +#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x00000780L +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x00000078L +#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000L +#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x00000019 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x0003f800L +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x00000004L +#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x00000002 +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x01fc0000L +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x00000012 +#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x00000780L +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x00000078L +#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000L +#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x00000019 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x0003f800L +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x00000004L +#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x00000002 +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x01fc0000L +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x00000012 +#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x00000780L +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x00000078L +#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000L +#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x00000019 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x0000007fL +#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x00000000 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x00007f00L +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x00000008 +#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x00000080L +#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x00000007 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x00000040L +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x00000020L +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x00000005 +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x00000200L +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009 +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x00000100L +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x00000008 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004 +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x00000800L +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0x0000000b +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x00000001L +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x00000000 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x00010000L +#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x00000010 +#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x00000001L +#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x00000000 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x00000780L +#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x00000006L +#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x00000030L +#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x001f0000L +#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x00000010 +#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x0000003fL +#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x00000000 +#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000L +#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x00000018 +#define MC_HUB_WDP_BP__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_BP__RDRET_MASK 0x0003fffeL +#define MC_HUB_WDP_BP__RDRET__SHIFT 0x00000001 +#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000L +#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x00000012 +#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x00001fe0L +#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x00000005 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00002000L +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x0000000d +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00004000L +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x0000000e +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x00008000L +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0x0000000f +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x00040000L +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x00000012 +#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x00010000L +#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x00000010 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x00000002L +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000001 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x00000004L +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000002 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x00000008L +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x00000003 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x00020000L +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x00000011 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x00080000L +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x00000013 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x00100000L +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x00000014 +#define MC_HUB_WDP_CREDITS__STOR0_MASK 0x00ff0000L +#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x00000010 +#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000L +#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x00000018 +#define MC_HUB_WDP_CREDITS__VM0_MASK 0x000000ffL +#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x00000000 +#define MC_HUB_WDP_CREDITS__VM1_MASK 0x0000ff00L +#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x00000008 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x00000001L +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x00000000 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x00000002L +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x00000001 +#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0x000000f0L +#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x00000004 +#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0x0000000fL +#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x00000000 +#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x00010000L +#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x00000010 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0x0000ff00L +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x00000008 +#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0x000000f0L +#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x00000004 +#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0x0000000fL +#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x00000000 +#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x00010000L +#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x00000010 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0x0000ff00L +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x00000008 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_HDP__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_IH__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_IH__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_IH__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x00001f80L +#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x00000007 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000L +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x00000018 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x0001e000L +#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0x0000000d +#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x00000078L +#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x00000004L +#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x00000002 +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0x00fe0000L +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x00000011 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x00001f80L +#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x00000007 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000L +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x00000018 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x0001e000L +#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0x0000000d +#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x00000078L +#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x00000004L +#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x00000002 +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0x00fe0000L +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x00000011 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x00001f80L +#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x00000007 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000L +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x00000018 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x0001e000L +#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0x0000000d +#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x00000078L +#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x00000004L +#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x00000002 +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0x00fe0000L +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x00000011 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x00001f80L +#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x00000007 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000L +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x00000018 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001 +#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x0001e000L +#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0x0000000d +#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x00000078L +#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x00000003 +#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x00000004L +#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x00000002 +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0x00fe0000L +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x00000011 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_MGPU2__CID2_MASK 0x000000ffL +#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x00000000 +#define MC_HUB_WDP_MGPU__CID_MASK 0x0000ff00L +#define MC_HUB_WDP_MGPU__CID__SHIFT 0x00000008 +#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x00800000L +#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x00000017 +#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x007f0000L +#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x00000010 +#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000L +#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x00000018 +#define MC_HUB_WDP_MGPU__STOR_MASK 0x000000ffL +#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x00000000 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_RLC__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_SEM__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_SH0__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_SH1__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x000001fcL +#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x00000002 +#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x00000003L +#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_SMU__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x00000040L +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x00000020L +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x00000005 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x00000200L +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x00000100L +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x00000008 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001 +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x00000800L +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x0000000b +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002 +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x00001000L +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0x0000000c +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003 +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x00002000L +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0x0000000d +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004 +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x00004000L +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0x0000000e +#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x00000001L +#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x00000000 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_UMC__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_UVD__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x00010000L +#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x00000010 +#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_VCE__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010 +#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010 +#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_HUB_WDP_XDP__ENABLE_MASK 0x00000001L +#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x00000000 +#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x00007800L +#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0x0000000b +#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x00000780L +#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x00000007 +#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x00000006L +#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x00000001 +#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x00000030L +#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x00000004 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x00000040L +#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x00200000L +#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x00000015 +#define MC_HUB_WRRET_CNTL__BP_MASK 0x001ffffeL +#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x00000001 +#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000L +#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x00000016 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000L +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x0000001e +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000L +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x0000001f +#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x00000001L +#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x00000000 +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0x000000feL +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x00000001 +#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x00000001L +#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0x000000feL +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x00000001 +#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x00000001L +#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0x000000feL +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x00000001 +#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x00000001L +#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0x000000feL +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x00000001 +#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x00000001L +#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x00000000 +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x00000001L +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x00000000 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x00000002L +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x00000001 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x00000004L +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x00000002 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x00000008L +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x00000003 +#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000L +#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x0000001f +#define MC_IMP_CNTL__CAL_VREF_MASK 0x007f0000L +#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x00000040L +#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x00000006 +#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x00000020L +#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x00000005 +#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x00000010 +#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000L +#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x0000001d +#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000L +#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x0000001e +#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x00000200L +#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x00000009 +#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0x0000e000L +#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0x0000000d +#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x0000001fL +#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x00000000 +#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x00000100L +#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x00000008 +#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000L +#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x0000001f +#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000L +#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x0000001c +#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000L +#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x0000001e +#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000L +#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x0000001d +#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0x0fff0000L +#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x00000010 +#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0x0000ff00L +#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x00000008 +#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0x000000ffL +#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x00000000 +#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0x0000ff00L +#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x00000008 +#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0x000000ffL +#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x00000000 +#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000L +#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x00000018 +#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0x00ff0000L +#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x00000010 +#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000L +#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x00000018 +#define MC_IMP_STATUS__NSTR_CAL_MASK 0x00ff0000L +#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x00000010 +#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0x0000ff00L +#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x00000008 +#define MC_IMP_STATUS__PSTR_CAL_MASK 0x000000ffL +#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x00000000 +#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L +#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a +#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000L +#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x0000001c +#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000L +#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x0000001d +#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0x00000fc0L +#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x00000006 +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x0000003fL +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x00000000 +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x0003f000L +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0x0000000c +#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x01000000L +#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x00000018 +#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x02000000L +#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x00000019 +#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L +#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a +#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000L +#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x0000001c +#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000L +#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x0000001d +#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0x00000fc0L +#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x00000006 +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x0000003fL +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x00000000 +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x0003f000L +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0x0000000c +#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x01000000L +#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x00000018 +#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x02000000L +#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x00000019 +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0x000000ffL +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x00000000 +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0x0000ff00L +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x00000008 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0x00ff0000L +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x00000010 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000L +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x00000018 +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0x000000ffL +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x00000000 +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0x0000ff00L +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x00000008 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0x00ff0000L +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x00000010 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000L +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x00000018 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x00000001L +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x00000000 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x00000002L +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x00000001 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x00000004L +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x00000002 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x00000008L +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x00000003 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x00000010L +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x00000004 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x00000020L +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x00000005 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x00000040L +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x00000006 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x00000080L +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x00000007 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x00000001L +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x00000000 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x00000002L +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x00000001 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x00000004L +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x00000002 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x00000008L +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x00000003 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x00000010L +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x00000004 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x00000020L +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x00000005 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x00000040L +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x00000006 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x00000080L +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x00000007 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x00400000L +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x00000016 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x00800000L +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x00000017 +#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000L +#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x0000001c +#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000L +#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x0000001d +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x00100000L +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x00000014 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x00200000L +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x00000015 +#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000L +#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x0000001e +#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000L +#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x0000001f +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x00000400L +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0x0000000a +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x00000800L +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0x0000000b +#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x00000100L +#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x00000008 +#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x00000200L +#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x00000009 +#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0x0000f000L +#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0x0000000c +#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0x000f0000L +#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x00000010 +#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0x0000000fL +#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x00000000 +#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0x000000f0L +#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x00000004 +#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x04000000L +#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x0000001a +#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x08000000L +#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x0000001b +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x01000000L +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x00000018 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x02000000L +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x00000019 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x00400000L +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x00000016 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x00800000L +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x00000017 +#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000L +#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x0000001c +#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000L +#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x0000001d +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x00100000L +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x00000014 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x00200000L +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x00000015 +#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000L +#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x0000001e +#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000L +#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x0000001f +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x00000400L +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0x0000000a +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x00000800L +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0x0000000b +#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x00000100L +#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x00000008 +#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x00000200L +#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x00000009 +#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0x0000f000L +#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0x0000000c +#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0x000f0000L +#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x00000010 +#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0x0000000fL +#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x00000000 +#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0x000000f0L +#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x00000004 +#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x04000000L +#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x0000001a +#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x08000000L +#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x0000001b +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x01000000L +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x00000018 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x02000000L +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x00000019 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x00000018 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0x000000ffL +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x00000000 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0x0000ff00L +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x00000008 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0x00ff0000L +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x00000010 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000L +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x00000018 +#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L +#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000L +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x0000001c +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000L +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x0000001d +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0x00000fc0L +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x00000006 +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0x00fc0000L +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x00000012 +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x0000003fL +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x00000000 +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x0003f000L +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0x0000000c +#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x01000000L +#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x00000018 +#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x02000000L +#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x00000019 +#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L +#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000L +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x0000001c +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000L +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x0000001d +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0x00000fc0L +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x00000006 +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0x00fc0000L +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x00000012 +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x0000003fL +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x00000000 +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x0003f000L +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0x0000000c +#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x01000000L +#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x00000018 +#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x02000000L +#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x00000019 +#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000L +#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x00000018 +#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000L +#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x0000001f +#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000L +#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x0000001e +#define MC_IO_PAD_CNTL__ATBSEL_MASK 0x00f00000L +#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x00000014 +#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x00100000L +#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x00000014 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0x00c00000L +#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x00000016 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x03000000L +#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x00000018 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x00200000L +#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x00000015 +#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x00000010L +#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x00000004 +#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x00000004L +#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x00000002 +#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x00000008L +#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x00000003 +#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000L +#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x0000001d +#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x00002000L +#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0x0000000d +#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x00001000L +#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0x0000000c +#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x00000800L +#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0x0000000b +#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x00000400L +#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0x0000000a +#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000L +#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x0000001e +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x00000200L +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x00000009 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x00000080L +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x00000007 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x00000100L +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x00000008 +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x08000000L +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x0000001b +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000L +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x0000001f +#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000L +#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x0000001c +#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x00004000L +#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0x0000000e +#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0x000f8000L +#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0x0000000f +#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x00100000L +#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x00000014 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0x00c00000L +#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x00000016 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x03000000L +#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x00000018 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x00200000L +#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x00000015 +#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x00000010L +#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x00000004 +#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x00000004L +#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x00000002 +#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x00000008L +#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x00000003 +#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x00000001L +#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x00000000 +#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x00000002L +#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x00000001 +#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000L +#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x0000001d +#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x00002000L +#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0x0000000d +#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x00001000L +#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0x0000000c +#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x00000800L +#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0x0000000b +#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x00000400L +#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0x0000000a +#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000L +#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x0000001e +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x00000200L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x00000009 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x00000080L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x00000007 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x00000100L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x00000008 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x00000020L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x00000005 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x00000040L +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x00000006 +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x08000000L +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x0000001b +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000L +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x0000001f +#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000L +#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x0000001c +#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x00004000L +#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0x0000000e +#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0x000f8000L +#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0x0000000f +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0x0000ff00L +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x00000008 +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0x000000ffL +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x00000000 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x00040000L +#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x00000012 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x00080000L +#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x00000013 +#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x00020000L +#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x00000011 +#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x00010000L +#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000L +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x0000001c +#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0x0e000000L +#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x00000019 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0x0000000fL +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x00000000 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0x000000f0L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x00000004 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0x0000ff00L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x00000008 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x00040000L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x00000012 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x00010000L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x00020000L +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x00000011 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000L +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x0000001c +#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0x0e000000L +#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x00000019 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0x0000000fL +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x00000000 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0x000000f0L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x00000004 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0x0000ff00L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x00000008 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x00040000L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x00000012 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x00010000L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x00020000L +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x00000011 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000L +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x0000001c +#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0x0e000000L +#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x00000019 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0x0000000fL +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x00000000 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0x000000f0L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x00000004 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0x0000ff00L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x00000008 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x00040000L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x00000012 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x00010000L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x00020000L +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x00000011 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000L +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x0000001c +#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0x0e000000L +#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x00000019 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0x0000000fL +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x00000000 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0x000000f0L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x00000004 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0x0000ff00L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x00000008 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x00040000L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x00000012 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x00010000L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x00000010 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x00020000L +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x00000011 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x00700000L +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x00000014 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x07000000L +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x00000018 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000L +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x0000001c +#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000L +#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x0000001e +#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x00000004L +#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x00000002 +#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000L +#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x0000001d +#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x00000003L +#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x00000000 +#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x00000030L +#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x00000004 +#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x00000080L +#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x00000007 +#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x00000040L +#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x00000006 +#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0x000c0000L +#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x00000012 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0x00000f00L +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x00000008 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0x0000f000L +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0x0000000c +#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x00000008L +#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x00000003 +#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x00010000L +#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x00000010 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x00700000L +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x00000014 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x07000000L +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x00000018 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000L +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x0000001c +#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000L +#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x0000001e +#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x00000004L +#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x00000002 +#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000L +#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x0000001d +#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x00000003L +#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x00000000 +#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x00000030L +#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x00000004 +#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x00000080L +#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x00000007 +#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x00000040L +#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x00000006 +#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0x000c0000L +#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x00000012 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0x00000f00L +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x00000008 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0x0000f000L +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0x0000000c +#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x00000008L +#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x00000003 +#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x00010000L +#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x00000010 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x00700000L +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x00000014 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x07000000L +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x00000018 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000L +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x0000001c +#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000L +#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x0000001e +#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x00000004L +#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x00000002 +#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000L +#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x0000001d +#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x00000003L +#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x00000000 +#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x00000030L +#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x00000004 +#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x00000080L +#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x00000007 +#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x00000040L +#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x00000006 +#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0x000c0000L +#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x00000012 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0x00000f00L +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x00000008 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0x0000f000L +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0x0000000c +#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x00000008L +#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x00000003 +#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x00010000L +#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x00000010 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x00700000L +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x00000014 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x07000000L +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x00000018 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000L +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x0000001c +#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000L +#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x0000001e +#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x00000004L +#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x00000002 +#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000L +#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x0000001d +#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x00000003L +#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x00000000 +#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x00000030L +#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x00000004 +#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x00000080L +#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x00000007 +#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x00000040L +#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x00000006 +#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0x000c0000L +#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x00000012 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0x00000f00L +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x00000008 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0x0000f000L +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0x0000000c +#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x00000008L +#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x00000003 +#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x00010000L +#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x00000010 +#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000L +#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x0000001e +#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000L +#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x0000001f +#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x00700000L +#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0x0000e000L +#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0x0000000d +#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x00001000L +#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0x0000000c +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000L +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x0000001b +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x02000000L +#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x00000019 +#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x00800000L +#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x00000017 +#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000L +#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x0000001e +#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000L +#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x0000001f +#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x00700000L +#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0x0000e000L +#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0x0000000d +#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x00001000L +#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0x0000000c +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000L +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x0000001b +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x02000000L +#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x00000019 +#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x00800000L +#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x00000017 +#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x02000000L +#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x00000019 +#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0x00f00000L +#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0x0000f000L +#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0x0000000c +#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x08000000L +#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x0000001b +#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000L +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x0000001c +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x02000000L +#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x00000019 +#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0x00f00000L +#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0x0000f000L +#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0x0000000c +#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x08000000L +#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x0000001b +#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000L +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x0000001c +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x02000000L +#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x00000019 +#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0x00f00000L +#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0x0000f000L +#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0x0000000c +#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x08000000L +#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x0000001b +#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000L +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x0000001c +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x00000007 +#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x00000003L +#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x00000000 +#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0x0000000cL +#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x00000002 +#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x02000000L +#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x00000019 +#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x00000040L +#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x00000006 +#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x00000010L +#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x00000004 +#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0x00f00000L +#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x00000014 +#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0x0000f000L +#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0x0000000c +#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0x000f0000L +#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x00000010 +#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x08000000L +#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x0000001b +#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0x00000f00L +#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x00000008 +#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x00000020L +#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x00000005 +#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x01000000L +#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x00000018 +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000L +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x0000001c +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x04000000L +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x0000001a +#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x00000080L +#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x00000007 +#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x00000040L +#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x01000000L +#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x00000018 +#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000006 +#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x0000001fL +#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x00000000 +#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00000080L +#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000007 +#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x00000100L +#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x00000008 +#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x00010000L +#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x00000010 +#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x00000200L +#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x00000009 +#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x00020000L +#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x00000011 +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000fc0L +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000006 +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003fL +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000000 +#define MC_NPL_STATUS__D0_NDELAY_MASK 0x0000000cL +#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x00000002 +#define MC_NPL_STATUS__D0_NEARLY_MASK 0x00000020L +#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x00000005 +#define MC_NPL_STATUS__D0_PDELAY_MASK 0x00000003L +#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x00000000 +#define MC_NPL_STATUS__D0_PEARLY_MASK 0x00000010L +#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x00000004 +#define MC_NPL_STATUS__D1_NDELAY_MASK 0x00000300L +#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x00000008 +#define MC_NPL_STATUS__D1_NEARLY_MASK 0x00000800L +#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0x0000000b +#define MC_NPL_STATUS__D1_PDELAY_MASK 0x000000c0L +#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x00000006 +#define MC_NPL_STATUS__D1_PEARLY_MASK 0x00000400L +#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0x0000000a +#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x00040000L +#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x00000012 +#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x00080000L +#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x00000013 +#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x0000007fL +#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x00000000 +#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x00001000L +#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0x0000000c +#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x00000100L +#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x00000008 +#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x00002000L +#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0x0000000d +#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x00000200L +#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x00000009 +#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x00004000L +#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0x0000000e +#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x00000400L +#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0x0000000a +#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x00008000L +#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0x0000000f +#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x00000800L +#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0x0000000b +#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x00010000L +#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x00000010 +#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x00020000L +#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x00000011 +#define MC_PHY_TIMING_2__WR_DLY_MASK 0x00f00000L +#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x00000014 +#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0x0000000fL +#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x00000000 +#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0x000000f0L +#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x00000004 +#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0x00000f00L +#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x00000008 +#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0x0000f000L +#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0x0000000c +#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x00070000L +#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x00000010 +#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0x00f00000L +#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x00000014 +#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x07000000L +#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x00000018 +#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000L +#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x0000001c +#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0x0000000fL +#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x00000000 +#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0x000000f0L +#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x00000004 +#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0x00000f00L +#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x00000008 +#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0x0000f000L +#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0x0000000c +#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x00070000L +#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x00000010 +#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0x00f00000L +#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x00000014 +#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x07000000L +#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x00000018 +#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000L +#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x0000001c +#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000L +#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x00000018 +#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x00000800L +#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0x0000000b +#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0x000f0000L +#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x00000010 +#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x00002000L +#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0x0000000d +#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x00001000L +#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0x0000000c +#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x00000002L +#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x00000001 +#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x00400000L +#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x00000016 +#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x00000400L +#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0x0000000a +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x00008000L +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0x0000000f +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x00800000L +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x00000017 +#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x00000100L +#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x00000008 +#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x00000200L +#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x00000009 +#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x00004000L +#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0x0000000e +#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x00000001L +#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x00000000 +#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x00000004L +#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x00000002 +#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x00100000L +#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x00000014 +#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0x000000f0L +#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x00000004 +#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x00200000L +#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x00000015 +#define MC_PMG_AUTO_CMD__ADR_MASK 0x0001ffffL +#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x00000000 +#define MC_PMG_CFG__DPM_WAKE_MASK 0x00000400L +#define MC_PMG_CFG__DPM_WAKE__SHIFT 0x0000000a +#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x00400000L +#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x00000016 +#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0x000f0000L +#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x00000010 +#define MC_PMG_CFG__PREA_SRX_MASK 0x00002000L +#define MC_PMG_CFG__PREA_SRX__SHIFT 0x0000000d +#define MC_PMG_CFG__RFS_SRX_MASK 0x00001000L +#define MC_PMG_CFG__RFS_SRX__SHIFT 0x0000000c +#define MC_PMG_CFG__RST_EMRS_MASK 0x00000004L +#define MC_PMG_CFG__RST_EMRS__SHIFT 0x00000002 +#define MC_PMG_CFG__RST_MRS1_MASK 0x00000100L +#define MC_PMG_CFG__RST_MRS1__SHIFT 0x00000008 +#define MC_PMG_CFG__RST_MRS2_MASK 0x00000200L +#define MC_PMG_CFG__RST_MRS2__SHIFT 0x00000009 +#define MC_PMG_CFG__RST_MRS_MASK 0x00000002L +#define MC_PMG_CFG__RST_MRS__SHIFT 0x00000001 +#define MC_PMG_CFG__RXPDNB_MASK 0x02000000L +#define MC_PMG_CFG__RXPDNB__SHIFT 0x00000019 +#define MC_PMG_CFG__SYC_CLK_MASK 0x00000001L +#define MC_PMG_CFG__SYC_CLK__SHIFT 0x00000000 +#define MC_PMG_CFG__TRI_MIO_MASK 0x00000008L +#define MC_PMG_CFG__TRI_MIO__SHIFT 0x00000003 +#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x00100000L +#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x00000014 +#define MC_PMG_CFG__XSR_TMR_MASK 0x000000f0L +#define MC_PMG_CFG__XSR_TMR__SHIFT 0x00000004 +#define MC_PMG_CFG__YCLK_ON_MASK 0x00200000L +#define MC_PMG_CFG__YCLK_ON__SHIFT 0x00000015 +#define MC_PMG_CFG__ZQCL_SEND_MASK 0x0c000000L +#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x0000001a +#define MC_PMG_CMD_EMRS__ADR_MASK 0x0000ffffL +#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x00000000 +#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x00080000L +#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x00000013 +#define MC_PMG_CMD_EMRS__CSB_MASK 0x00600000L +#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x00000015 +#define MC_PMG_CMD_EMRS__END_MASK 0x00100000L +#define MC_PMG_CMD_EMRS__END__SHIFT 0x00000014 +#define MC_PMG_CMD_EMRS__MOP_MASK 0x00070000L +#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x00000010 +#define MC_PMG_CMD_MRS1__ADR_MASK 0x0000ffffL +#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x00000000 +#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x00080000L +#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x00000013 +#define MC_PMG_CMD_MRS1__CSB_MASK 0x00600000L +#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x00000015 +#define MC_PMG_CMD_MRS1__END_MASK 0x00100000L +#define MC_PMG_CMD_MRS1__END__SHIFT 0x00000014 +#define MC_PMG_CMD_MRS1__MOP_MASK 0x00070000L +#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x00000010 +#define MC_PMG_CMD_MRS2__ADR_MASK 0x0000ffffL +#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x00000000 +#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x00080000L +#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x00000013 +#define MC_PMG_CMD_MRS2__CSB_MASK 0x00600000L +#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x00000015 +#define MC_PMG_CMD_MRS2__END_MASK 0x00100000L +#define MC_PMG_CMD_MRS2__END__SHIFT 0x00000014 +#define MC_PMG_CMD_MRS2__MOP_MASK 0x00070000L +#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x00000010 +#define MC_PMG_CMD_MRS__ADR_MASK 0x0000ffffL +#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000L +#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x0000001d +#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000L +#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x0000001c +#define MC_PMG_CMD_MRS__ADR__SHIFT 0x00000000 +#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x00080000L +#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x00000013 +#define MC_PMG_CMD_MRS__CSB_MASK 0x00600000L +#define MC_PMG_CMD_MRS__CSB__SHIFT 0x00000015 +#define MC_PMG_CMD_MRS__END_MASK 0x00100000L +#define MC_PMG_CMD_MRS__END__SHIFT 0x00000014 +#define MC_PMG_CMD_MRS__MOP_MASK 0x00070000L +#define MC_PMG_CMD_MRS__MOP__SHIFT 0x00000010 +#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_CB__ENABLE_MASK 0x00000001L +#define MC_RD_CB__ENABLE__SHIFT 0x00000000 +#define MC_RD_CB__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_CB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_CB__MAX_BURST_MASK 0x00000780L +#define MC_RD_CB__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_CB__PRESCALE_MASK 0x00000006L +#define MC_RD_CB__PRESCALE__SHIFT 0x00000001 +#define MC_RD_CB__STALL_MODE_MASK 0x00000030L +#define MC_RD_CB__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_CB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_DB__ENABLE_MASK 0x00000001L +#define MC_RD_DB__ENABLE__SHIFT 0x00000000 +#define MC_RD_DB__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_DB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_DB__MAX_BURST_MASK 0x00000780L +#define MC_RD_DB__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_DB__PRESCALE_MASK 0x00000006L +#define MC_RD_DB__PRESCALE__SHIFT 0x00000001 +#define MC_RD_DB__STALL_MODE_MASK 0x00000030L +#define MC_RD_DB__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_DB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RD_GRP_EXT__DBSTEN0_MASK 0x0000000fL +#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x00000000 +#define MC_RD_GRP_EXT__TC0_MASK 0x000000f0L +#define MC_RD_GRP_EXT__TC0__SHIFT 0x00000004 +#define MC_RD_GRP_GFX__CP_MASK 0x0000000fL +#define MC_RD_GRP_GFX__CP__SHIFT 0x00000000 +#define MC_RD_GRP_GFX__XDMAM_MASK 0x000f0000L +#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x00000010 +#define MC_RD_GRP_LCL__CB0_MASK 0x0000f000L +#define MC_RD_GRP_LCL__CB0__SHIFT 0x0000000c +#define MC_RD_GRP_LCL__CBCMASK0_MASK 0x000f0000L +#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x00000010 +#define MC_RD_GRP_LCL__CBFMASK0_MASK 0x00f00000L +#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x00000014 +#define MC_RD_GRP_LCL__DB0_MASK 0x0f000000L +#define MC_RD_GRP_LCL__DB0__SHIFT 0x00000018 +#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000L +#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x0000001c +#define MC_RD_GRP_OTH__HDP_MASK 0x00000f00L +#define MC_RD_GRP_OTH__HDP__SHIFT 0x00000008 +#define MC_RD_GRP_OTH__SEM_MASK 0x0000f000L +#define MC_RD_GRP_OTH__SEM__SHIFT 0x0000000c +#define MC_RD_GRP_OTH__UMC_MASK 0x000f0000L +#define MC_RD_GRP_OTH__UMC__SHIFT 0x00000010 +#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0x0000000fL +#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x00000000 +#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0x0f000000L +#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x00000018 +#define MC_RD_GRP_OTH__UVD_MASK 0x00f00000L +#define MC_RD_GRP_OTH__UVD__SHIFT 0x00000014 +#define MC_RD_GRP_SYS__DMIF_MASK 0x0000f000L +#define MC_RD_GRP_SYS__DMIF__SHIFT 0x0000000c +#define MC_RD_GRP_SYS__MCIF_MASK 0x000f0000L +#define MC_RD_GRP_SYS__MCIF__SHIFT 0x00000010 +#define MC_RD_GRP_SYS__RLC_MASK 0x0000000fL +#define MC_RD_GRP_SYS__RLC__SHIFT 0x00000000 +#define MC_RD_GRP_SYS__SMU_MASK 0x00f00000L +#define MC_RD_GRP_SYS__SMU__SHIFT 0x00000014 +#define MC_RD_GRP_SYS__VCE_MASK 0x0f000000L +#define MC_RD_GRP_SYS__VCE__SHIFT 0x00000018 +#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000L +#define MC_RD_GRP_SYS__VCEU__SHIFT 0x0000001c +#define MC_RD_GRP_SYS__VMC_MASK 0x000000f0L +#define MC_RD_GRP_SYS__VMC__SHIFT 0x00000004 +#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_HUB__ENABLE_MASK 0x00000001L +#define MC_RD_HUB__ENABLE__SHIFT 0x00000000 +#define MC_RD_HUB__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_HUB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_HUB__MAX_BURST_MASK 0x00000780L +#define MC_RD_HUB__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_HUB__PRESCALE_MASK 0x00000006L +#define MC_RD_HUB__PRESCALE__SHIFT 0x00000001 +#define MC_RD_HUB__STALL_MODE_MASK 0x00000030L +#define MC_RD_HUB__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_TC0__ENABLE_MASK 0x00000001L +#define MC_RD_TC0__ENABLE__SHIFT 0x00000000 +#define MC_RD_TC0__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_TC0__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_TC0__MAX_BURST_MASK 0x00000780L +#define MC_RD_TC0__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_TC0__PRESCALE_MASK 0x00000006L +#define MC_RD_TC0__PRESCALE__SHIFT 0x00000001 +#define MC_RD_TC0__STALL_MODE_MASK 0x00000030L +#define MC_RD_TC0__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_RD_TC1__ENABLE_MASK 0x00000001L +#define MC_RD_TC1__ENABLE__SHIFT 0x00000000 +#define MC_RD_TC1__LAZY_TIMER_MASK 0x00007800L +#define MC_RD_TC1__LAZY_TIMER__SHIFT 0x0000000b +#define MC_RD_TC1__MAX_BURST_MASK 0x00000780L +#define MC_RD_TC1__MAX_BURST__SHIFT 0x00000007 +#define MC_RD_TC1__PRESCALE_MASK 0x00000006L +#define MC_RD_TC1__PRESCALE__SHIFT 0x00000001 +#define MC_RD_TC1__STALL_MODE_MASK 0x00000030L +#define MC_RD_TC1__STALL_MODE__SHIFT 0x00000004 +#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x00000040L +#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0x00ff0000L +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x00000010 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x0000ff00L +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x00000008 +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x000000ffL +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x00000000 +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0x000000ffL +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x00000000 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0x0000ff00L +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x00000008 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000L +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x00000010 +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000ffffL +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x00000000 +#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x0000003eL +#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x00000001 +#define MC_RPB_CID_QUEUE_EX__START_MASK 0x00000001L +#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x00000000 +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0x000000ffL +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x00000000 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x00000c00L +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0x0000000a +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00000300L +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x00000008 +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0x000000ffL +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x00000000 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00001800L +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0x0000000b +#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x00002000L +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000100L +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x00000008 +#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x0000000d +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00000600L +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x00000009 +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x00010000L +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x00000010 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x00020000L +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x00000011 +#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x00008000L +#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0x0000000f +#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000L +#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x00000014 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0x000fff00L +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x00000008 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0x000000ffL +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x00000000 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000ff00L +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x00000008 +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000ffL +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x00000000 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0x0000ff00L +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x00000008 +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0x000000ffL +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x00000000 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x00000003 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x00000002 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001e0L +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x00000005 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003e00L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x00000009 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007c000L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0x0000000e +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00f80000L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x00000013 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x00000018 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x00000004 +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffffL +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x00000000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x00000080L +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x00000007 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x00000001L +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x00000000 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x00000078L +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x00000003 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x00000006L +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x00000001 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x000000ffL +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x00000000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x0000ff00L +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x00000008 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x00ff0000L +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x00000010 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000L +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x00000018 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x00000007L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x00000000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x00000038L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x00000003 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x000001c0L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x00000006 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0x00000e00L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x00000009 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x00007000L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0x0000000c +#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x00038000L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0x0000000f +#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x001c0000L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x00000012 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0x00e00000L +#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x00000015 +#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x00000003L +#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x00000000 +#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0x0000000cL +#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x00000002 +#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x00000030L +#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x00000004 +#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0x000000c0L +#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x00000006 +#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x00000003L +#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x00000000 +#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0x0000000cL +#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x00000002 +#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x00000030L +#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x00000004 +#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0x000000c0L +#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x00000006 +#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0x00000e00L +#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x00000009 +#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000L +#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x00000018 +#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0x0000000cL +#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x00000002 +#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x00000003L +#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x00000000 +#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0x0000f000L +#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0x0000000c +#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x000001f0L +#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x00000004 +#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x001f0000L +#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x00000010 +#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0x00000e00L +#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x00000009 +#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000L +#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x00000018 +#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0x0000000cL +#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x00000002 +#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x00000003L +#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x00000000 +#define MC_SEQ_CAS_TIMING__TR2R_MASK 0x0000f000L +#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0x0000000c +#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x000001f0L +#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x00000004 +#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x001f0000L +#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x00000010 +#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0x000000ffL +#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x00000000 +#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0x0000ff00L +#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x00000008 +#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0x00ff0000L +#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x00000010 +#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000L +#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x00000018 +#define MC_SEQ_CMD__ADR_MASK 0x0000ffffL +#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_CMD__ADR__SHIFT 0x00000000 +#define MC_SEQ_CMD__CHAN0_MASK 0x01000000L +#define MC_SEQ_CMD__CHAN0__SHIFT 0x00000018 +#define MC_SEQ_CMD__CHAN1_MASK 0x02000000L +#define MC_SEQ_CMD__CHAN1__SHIFT 0x00000019 +#define MC_SEQ_CMD__CSB_MASK 0x00600000L +#define MC_SEQ_CMD__CSB__SHIFT 0x00000015 +#define MC_SEQ_CMD__END_MASK 0x00100000L +#define MC_SEQ_CMD__END__SHIFT 0x00000014 +#define MC_SEQ_CMD__MOP_MASK 0x000f0000L +#define MC_SEQ_CMD__MOP__SHIFT 0x00000010 +#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x00000300L +#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x00000008 +#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0x0000fc00L +#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0x0000000a +#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x003f0000L +#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x00000010 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0x0f000000L +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x00000018 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000L +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x0000001c +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x00400000L +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x00000016 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x00800000L +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x00000017 +#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0x00f00000L +#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x00000014 +#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0x0f000000L +#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x00000018 +#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000L +#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x0000001c +#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x00040000L +#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x00000012 +#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x00020000L +#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x00000011 +#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x00000300L +#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x00000008 +#define MC_SEQ_CNTL__DAT_INV_MASK 0x00000040L +#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x00000006 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0x0000000cL +#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x00000002 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x00000003L +#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x00000000 +#define MC_SEQ_CNTL__MSK_DF1_MASK 0x00000080L +#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x00000007 +#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x00008000L +#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0x0000000f +#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x00004000L +#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0x0000000e +#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x00010000L +#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x00000010 +#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x00080000L +#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x00000013 +#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x00000030L +#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x00000004 +#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x04000000L +#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x0000001a +#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x02000000L +#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x00000019 +#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x00000004L +#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x00000002 +#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x00000002L +#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x00000001 +#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x00000001L +#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x00000000 +#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x00002000L +#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0x0000000d +#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x00000008L +#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x00000003 +#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000L +#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x0000001f +#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x00000010L +#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x00000004 +#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000L +#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x0000001c +#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x08000000L +#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x0000001b +#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000L +#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x0000001d +#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x00004000L +#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0x0000000e +#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x00001000L +#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0x0000000c +#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x00000080L +#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x00000007 +#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x01000000L +#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x00000018 +#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x00000800L +#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0x0000000b +#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0x00ff0000L +#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x00000010 +#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x00000400L +#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0x0000000a +#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x00000040L +#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x00000006 +#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x00000100L +#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x00000008 +#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000L +#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x0000001e +#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x00008000L +#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0x0000000f +#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x00000020L +#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x00000005 +#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x00000200L +#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x00000009 +#define MC_SEQ_DRAM__ADR_2CK_MASK 0x00000001L +#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x00000000 +#define MC_SEQ_DRAM__ADR_DF1_MASK 0x00000004L +#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x00000002 +#define MC_SEQ_DRAM__ADR_MUX_MASK 0x00000002L +#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x00000001 +#define MC_SEQ_DRAM__AP8_MASK 0x00000008L +#define MC_SEQ_DRAM__AP8__SHIFT 0x00000003 +#define MC_SEQ_DRAM__BO4_MASK 0x00004000L +#define MC_SEQ_DRAM__BO4__SHIFT 0x0000000e +#define MC_SEQ_DRAM__CKE_ACT_MASK 0x00002000L +#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0x0000000d +#define MC_SEQ_DRAM__CKE_DYN_MASK 0x00001000L +#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0x0000000c +#define MC_SEQ_DRAM__DAT_DF1_MASK 0x00000010L +#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x00000004 +#define MC_SEQ_DRAM__DAT_INV_MASK 0x01000000L +#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x00000018 +#define MC_SEQ_DRAM__DLL_CLR_MASK 0x00008000L +#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0x0000000f +#define MC_SEQ_DRAM__DLL_CNT_MASK 0x00ff0000L +#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x00000010 +#define MC_SEQ_DRAM__DQM_ACT_MASK 0x00000080L +#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x00000007 +#define MC_SEQ_DRAM__DQM_DF1_MASK 0x00000040L +#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x00000006 +#define MC_SEQ_DRAM__DQS_DF1_MASK 0x00000020L +#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x00000005 +#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000L +#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x00000010 +#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0x0000ffffL +#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x00000000 +#define MC_SEQ_DRAM__INV_ACM_MASK 0x02000000L +#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x00000019 +#define MC_SEQ_DRAM__ODT_ACT_MASK 0x08000000L +#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x0000001b +#define MC_SEQ_DRAM__ODT_ENB_MASK 0x04000000L +#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x0000001a +#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000L +#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x0000001c +#define MC_SEQ_DRAM__STB_CNT_MASK 0x00000f00L +#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x00000008 +#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000L +#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x0000001e +#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000L +#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x0000001d +#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x00000100L +#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x00000008 +#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x00000200L +#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x00000009 +#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x00000030L +#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x00000004 +#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0x000000c0L +#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x00000006 +#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x00007000L +#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0x0000000c +#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x00030000L +#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x00000010 +#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0x000c0000L +#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x00000012 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x00000003L +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x00000000 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0x00000c00L +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0x0000000a +#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0x0000000cL +#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x00000002 +#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffffL +#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x00000000 +#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x000001ffL +#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x00000000 +#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffffL +#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x00000000 +#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffffL +#define MC_SEQ_IO_REDC__EDC__SHIFT 0x00000000 +#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000L +#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x00000018 +#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0x00000fffL +#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x00000000 +#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0x00fff000L +#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0x0000000c +#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000L +#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x00000018 +#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0x00000fffL +#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x00000000 +#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0x00fff000L +#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0x0000000c +#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x00000000 +#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffffL +#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x00000000 +#define MC_SEQ_MISC0__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC1__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC3__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC3__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC4__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC4__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC5__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC5__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC6__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC6__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC7__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC7__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC8__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC8__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC9__VALUE_MASK 0xffffffffL +#define MC_SEQ_MISC9__VALUE__SHIFT 0x00000000 +#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x00001f00L +#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x00000008 +#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x00001f00L +#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x00000008 +#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x00000007L +#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x00000000 +#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x00000070L +#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x00000004 +#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0x00e00000L +#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x00000015 +#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0x0f000000L +#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x00000018 +#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0x0000e000L +#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0x0000000d +#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000L +#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x0000001c +#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x001f0000L +#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x00000010 +#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x00000007L +#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x00000000 +#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x00000070L +#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x00000004 +#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x01e00000L +#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x00000015 +#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0x0000e000L +#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0x0000000d +#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000L +#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x0000001c +#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x001f0000L +#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x00000010 +#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000L +#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x00000014 +#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0x000f8000L +#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x00003f00L +#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x00000008 +#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0x0000000f +#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x0000003fL +#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x00000000 +#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000L +#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x00000014 +#define MC_SEQ_MISC_TIMING__TRP_MASK 0x000f8000L +#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x00003f00L +#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x00000008 +#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0x0000000f +#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x0000003fL +#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x00000000 +#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x00000001L +#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x00000000 +#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x00000020L +#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x00000005 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x00000002L +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x00000001 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x00000004L +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x00000002 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x00000008L +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x00000003 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x00000010L +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x00000004 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x00000040L +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x00000006 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x00000080L +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x00000007 +#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x00000001L +#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x00000000 +#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x00000100L +#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x00000008 +#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x00000200L +#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x00000009 +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x00000400L +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0x0000000a +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x00000800L +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0x0000000b +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x00001000L +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0x0000000c +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x00002000L +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0x0000000d +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x00004000L +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0x0000000e +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x00008000L +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0x0000000f +#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000L +#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x0000001e +#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffffL +#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0x0000000fL +#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x00000000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0x000000f0L +#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x00000004 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0x00000f00L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x00000008 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0x0000f000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0x0000000c +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0x000f0000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x00000010 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0x00f00000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x00000014 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0x0f000000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x00000018 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000L +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0x0000ffffL +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x00000000 +#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x00080000L +#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x00000013 +#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x00600000L +#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x00000015 +#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x00100000L +#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x00000014 +#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x00070000L +#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x00000010 +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0x0000ffffL +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x00000000 +#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x00080000L +#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x00000013 +#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x00600000L +#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x00000015 +#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x00100000L +#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x00000014 +#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x00070000L +#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x00000010 +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0x0000ffffL +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x00000000 +#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x00080000L +#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x00000013 +#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x00600000L +#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x00000015 +#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x00100000L +#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x00000014 +#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x00070000L +#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x00000010 +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0x0000ffffL +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000L +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x0000001d +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000L +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x0000001c +#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x00000000 +#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x00080000L +#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x00000013 +#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x00600000L +#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x00000015 +#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x00100000L +#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x00000014 +#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x00070000L +#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x00000010 +#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x00040000L +#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x00000012 +#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x00000300L +#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x00000008 +#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0x000000c0L +#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x00000006 +#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x00003c00L +#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0x0000000a +#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x00000001L +#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x00000000 +#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x00020000L +#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x00000011 +#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x00000002L +#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x00000001 +#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x0000003cL +#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x00000002 +#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x00010000L +#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x00000010 +#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000L +#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x0000001f +#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x00010000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x00000010 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x00000020L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x00000005 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x00000002L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x00000001 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x00000010L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x00000004 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x00000001L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x00000000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x00000040L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x00000006 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x00000004L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x00000002 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x00000080L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x00000007 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x00000008L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x00000003 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x00002000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0x0000000d +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x00000200L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x00000009 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x00001000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0x0000000c +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x00000100L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x00000008 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x00004000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0x0000000e +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x00000400L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0x0000000a +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x00008000L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0x0000000f +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x00000800L +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0x0000000b +#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000L +#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x0000001f +#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x00010000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x00000010 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x00000020L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x00000005 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x00000002L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x00000001 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x00000010L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x00000004 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x00000001L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x00000000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x00000040L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x00000006 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x00000004L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x00000002 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x00000080L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x00000007 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x00000008L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x00000003 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x00002000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0x0000000d +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x00000200L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x00000009 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x00001000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0x0000000c +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x00000100L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x00000008 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x00004000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0x0000000e +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x00000400L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0x0000000a +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x00008000L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0x0000000f +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x00000800L +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0x0000000b +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x001c0000L +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x00000012 +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000L +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x00000018 +#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x0003f000L +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0x00000f00L +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x00800000L +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x00000017 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x00000008 +#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0x0000000c +#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x00000007L +#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x00000000 +#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x00000070L +#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x00000004 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x001c0000L +#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x00000012 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000L +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x00000018 +#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x0003f000L +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0x00000f00L +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x00800000L +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x00000017 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x00000008 +#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0x0000000c +#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x00000007L +#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x00000000 +#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x00000070L +#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x00000004 +#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0x000f8000L +#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0x0000000f +#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x00007c00L +#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0x0000000a +#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x000003e0L +#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x00000005 +#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x0000001fL +#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x00000000 +#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000L +#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x00000018 +#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0x00f00000L +#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x00000014 +#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0x000f8000L +#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0x0000000f +#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x00007c00L +#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0x0000000a +#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x000003e0L +#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x00000005 +#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x0000001fL +#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x00000000 +#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000L +#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x00000018 +#define MC_SEQ_RAS_TIMING__TRRD_MASK 0x00f00000L +#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x01f00000L +#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000L +#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x00000019 +#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x00000007L +#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x00000000 +#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0x000000f8L +#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x00000003 +#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0x0000f000L +#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0x0000000c +#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x00000300L +#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x00000008 +#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0x00000c00L +#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0x0000000a +#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x00010000L +#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x00000010 +#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x00020000L +#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x00000011 +#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x01f00000L +#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000L +#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x00000019 +#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x00000007L +#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x00000000 +#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0x000000f8L +#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x00000003 +#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0x0000f000L +#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0x0000000c +#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x00000300L +#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x00000008 +#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0x00000c00L +#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0x0000000a +#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x00010000L +#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x00000010 +#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x00020000L +#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x00000011 +#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x01f00000L +#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000L +#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x00000019 +#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x00000007L +#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x00000000 +#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0x000000f8L +#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x00000003 +#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0x0000f000L +#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0x0000000c +#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x00000300L +#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x00000008 +#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0x00000c00L +#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0x0000000a +#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x00010000L +#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x00000010 +#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x00020000L +#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x00000011 +#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x01f00000L +#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x00000014 +#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000L +#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x00000019 +#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x00000007L +#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x00000000 +#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0x000000f8L +#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x00000003 +#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0x0000f000L +#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0x0000000c +#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x00000300L +#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x00000008 +#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0x00000c00L +#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0x0000000a +#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x00010000L +#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x00000010 +#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x00020000L +#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x00000011 +#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xffffffffL +#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x00000000 +#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffffL +#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x00000000 +#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffffL +#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x0000001c +#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0x0000000fL +#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x00000000 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0x000000f0L +#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x00000004 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0x00000f00L +#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x00000008 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0x0000f000L +#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0x0000000c +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0x000f0000L +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x00000010 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0x00f00000L +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x00000014 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0x0f000000L +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x00000018 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000L +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x0000001c +#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x00000004L +#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x00000002 +#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x00000008L +#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x00000003 +#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x01f00000L +#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x00000014 +#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x00010000L +#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x00000010 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x00000001L +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x00000000 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x00000002L +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x00000001 +#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x00000100L +#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x00000008 +#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x02000000L +#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x00000019 +#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x00004000L +#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0x0000000e +#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x00001000L +#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0x0000000c +#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x00000200L +#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x00000009 +#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x04000000L +#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x0000001a +#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x00008000L +#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0x0000000f +#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x00002000L +#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0x0000000d +#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x00000010L +#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x00000004 +#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x00000020L +#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x00000005 +#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x00000040L +#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x00000006 +#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x00000080L +#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x00000007 +#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x00000010L +#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x00000004 +#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x00000001L +#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x00000000 +#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x00000100L +#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x00000008 +#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x00000020L +#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x00000005 +#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x00000002L +#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x00000001 +#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x00000200L +#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x00000009 +#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x00000080L +#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x00000007 +#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x00000040L +#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x00000006 +#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000L +#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x00000017 +#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x00000020L +#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x00000005 +#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x00000010L +#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x00000004 +#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x00000008L +#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x00000003 +#define MC_SEQ_SUP_CNTL__RUN_MASK 0x00000001L +#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x00000000 +#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x00000002L +#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x00000001 +#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x00000004L +#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x00000002 +#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffffL +#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x00000000 +#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffffL +#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x00000000 +#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffffL +#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x00000000 +#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x04000000L +#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x0000001a +#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x02000000L +#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x00000019 +#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x00380000L +#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x00000013 +#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0x0000f000L +#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0x0000000c +#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000L +#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x0000001f +#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x00000002L +#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x00000001 +#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x00000004L +#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x00000002 +#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x00040000L +#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x00000012 +#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x00000080L +#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x00000007 +#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x00400000L +#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x00000016 +#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x00010000L +#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x00000010 +#define MC_SEQ_TCG_CNTL__MOP_MASK 0x00000f00L +#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x00000008 +#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x00000070L +#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x00000004 +#define MC_SEQ_TCG_CNTL__RESET_MASK 0x00000001L +#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x00000000 +#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x00020000L +#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x00000011 +#define MC_SEQ_TCG_CNTL__START_MASK 0x00000008L +#define MC_SEQ_TCG_CNTL__START__SHIFT 0x00000003 +#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x00800000L +#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x00000017 +#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x01000000L +#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x00000018 +#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffffL +#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x00000000 +#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffffL +#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x00040000L +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x00080000L +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x00000001L +#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L +#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L +#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x01000000L +#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x00000004L +#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x00000010L +#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x00000002L +#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L +#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L +#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x02000000L +#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x00000008L +#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x00000020L +#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x00800000L +#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x00000017 +#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x00100000L +#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L +#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x04000000L +#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x00002000L +#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L +#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L +#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x00020000L +#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x00008000L +#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x00004000L +#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0x0000000e +#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffffL +#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x00000100L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x00000001L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x00000200L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x00000002L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x00000004L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x00000030L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x00000008L +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000L +#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x00000010 +#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0x0000ffffL +#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x000003e0L +#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0x000f8000L +#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x00007c00L +#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x0000001fL +#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x00040000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x00080000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x00010000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x00000010 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x00000001L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x01000000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x00000004L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x00000010L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x00000002L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x02000000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x00000008L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x00000020L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x00800000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x00000017 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x00100000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x04000000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x00002000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x00020000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x00008000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x00004000L +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0x0000000e +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x00000100L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x00000400L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x00100000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x00000200L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x00000800L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x01000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x04000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x02000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x08000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x0000001b +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x00000001L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x00000004L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x00000002L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x00000008L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x0000001d +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x00010000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x00000010 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x00040000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x00020000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x00080000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x00000010L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x00000040L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x00000020L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x00000080L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x00200000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x00400000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x0000001c +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x0000001e +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x0000001f +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x00001000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x00004000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0x0000000e +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x00002000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x00008000L +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x00040000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x00080000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x00000001L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x01000000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x00000004L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x00000010L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x00000002L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x02000000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x00000008L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x00000020L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x00800000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x00000017 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x00100000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x04000000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x00002000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x00020000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x00008000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x00004000L +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0x0000000e +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x00040000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x00000012 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x00080000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x00000013 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x00200000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x00000015 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x00400000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x00000016 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x00000001L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x00000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x00000100L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000008 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x00000400L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000a +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x01000000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x00000018 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x00000004L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x00000002 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x00000010L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x00000004 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x00000002L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x00000001 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x00000200L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x00000009 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x00000800L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0x0000000b +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x02000000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x00000019 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x00000008L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x00000003 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x00000020L +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x00000005 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x00800000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x00000017 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x00100000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x00000014 +#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x00000040L +#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x00000006 +#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x04000000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x0000001a +#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x00002000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0x0000000d +#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x00000080L +#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x00000007 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x00001000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0x0000000c +#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x00020000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x00000011 +#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x00008000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0x0000000f +#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x00004000L +#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0x0000000e +#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0x00ff0000L +#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x00000010 +#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000L +#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x00000018 +#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x00000002L +#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x00000001 +#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x00000020L +#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x00000005 +#define MC_SEQ_TSM_CTRL__DONE_MASK 0x00000004L +#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x00000002 +#define MC_SEQ_TSM_CTRL__ERR_MASK 0x00000008L +#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x00000003 +#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x00000040L +#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x00000006 +#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x00000080L +#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x00000007 +#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000L +#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x00000010 +#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x00000400L +#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0x0000000a +#define MC_SEQ_TSM_CTRL__START_MASK 0x00000001L +#define MC_SEQ_TSM_CTRL__START__SHIFT 0x00000000 +#define MC_SEQ_TSM_CTRL__STEP_MASK 0x00000010L +#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x00000004 +#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x00000300L +#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x00000008 +#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffffL +#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x00000000 +#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffffL +#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x00000000 +#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x0000001fL +#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x00000000 +#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffffL +#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x00000000 +#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000L +#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x00000018 +#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0x000f0000L +#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x00000010 +#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000L +#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x00000010 +#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_GCNT__TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0x000f0000L +#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x00000010 +#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0x0000ffffL +#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x00000000 +#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0x0f000000L +#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x00000018 +#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0x00f00000L +#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x00000014 +#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0x000f0000L +#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x00000010 +#define MC_SEQ_TSM_NCNT__TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000L +#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x00000010 +#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_OCNT__TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0x00ff0000L +#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x00000010 +#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000L +#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x00000018 +#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0x000000f0L +#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x00000004 +#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0x0000000fL +#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x00000000 +#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0x0000ff00L +#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x00000008 +#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffffL +#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0x000f0000L +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x00000010 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0x00f00000L +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x00000014 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0x0f000000L +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x00000018 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000L +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x0000001c +#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0x0000000c +#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0x0000000fL +#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x00000000 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0x000000f0L +#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x00000004 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0x00000f00L +#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x00000008 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0x0000f000L +#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0x0000000c +#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffffL +#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x00000000 +#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffffL +#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x00000000 +#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x00004000L +#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0x0000000e +#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x00100000L +#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x00000014 +#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x00200000L +#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x00000015 +#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0x0f000000L +#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x00000018 +#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000L +#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x0000001c +#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x00002000L +#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0x0000000d +#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x00008000L +#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0x0000000f +#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0x000f0000L +#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x00000010 +#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0x000000ffL +#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x00000000 +#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0x00000f00L +#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x00000008 +#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x00001000L +#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x00000001L +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x00000008L +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x00000003 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x00000002L +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x00000001 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x00000010L +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x00000001L +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x00000008L +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x00000003 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x00000002L +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x00000001 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x00000010L +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x00000004L +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x00000002 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x00000020L +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x00000005 +#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x00000040L +#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x00000006 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x00000004L +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x00000002 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x00000020L +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x00000005 +#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x00000040L +#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x00000006 +#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x00000400L +#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0x0000000a +#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000L +#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x0000001d +#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x00000800L +#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0x0000000b +#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000L +#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x0000001e +#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x00000200L +#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x00000009 +#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0x0000000fL +#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0x000000f0L +#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x00000100L +#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x00000008 +#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x00000400L +#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0x0000000a +#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000L +#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x0000001d +#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x00000800L +#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0x0000000b +#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000L +#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x0000001e +#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x00000200L +#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x00000009 +#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0x0000000fL +#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0x000000f0L +#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x00000100L +#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x00000008 +#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0x0f000000L +#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x00000018 +#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000L +#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x0000001c +#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0x0000f000L +#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0x000f0000L +#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x00000010 +#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x00300000L +#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x00000014 +#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0x0f000000L +#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x00000018 +#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000L +#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x0000001c +#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0x0000f000L +#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0x000f0000L +#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x00000010 +#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x00300000L +#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x00000014 +#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x00000400L +#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0x0000000a +#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000L +#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x0000001d +#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x00000800L +#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0x0000000b +#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000L +#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x0000001e +#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x00000200L +#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x00000009 +#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0x0000000fL +#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0x000000f0L +#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x00000100L +#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x00000008 +#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x00000400L +#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0x0000000a +#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000L +#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x0000001d +#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x00000800L +#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0x0000000b +#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000L +#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x0000001e +#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x00000200L +#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x00000009 +#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0x0000000fL +#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x00000000 +#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0x000000f0L +#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x00000004 +#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x00000100L +#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x00000008 +#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0x0f000000L +#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x00000018 +#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000L +#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x0000001c +#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0x0000f000L +#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0x000f0000L +#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x00000010 +#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x00300000L +#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x00000014 +#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0x0f000000L +#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x00000018 +#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000L +#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x0000001c +#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0x0000f000L +#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0x0000000c +#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0x000f0000L +#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x00000010 +#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x00300000L +#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x00000014 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x00000007L +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x00000000 +#define MC_SHARED_CHMAP__CHAN0_MASK 0x0000000fL +#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x00000000 +#define MC_SHARED_CHMAP__CHAN1_MASK 0x000000f0L +#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x00000004 +#define MC_SHARED_CHMAP__CHAN2_MASK 0x00000f00L +#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x00000008 +#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0x0000f000L +#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0x0000000c +#define MC_SHARED_CHREMAP__CHAN0_MASK 0x00000007L +#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x00000000 +#define MC_SHARED_CHREMAP__CHAN1_MASK 0x00000038L +#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x00000003 +#define MC_SHARED_CHREMAP__CHAN2_MASK 0x000001c0L +#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x00000006 +#define MC_SHARED_CHREMAP__CHAN3_MASK 0x00000e00L +#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0x00000009 +#define MC_SHARED_CHREMAP__CHAN4_MASK 0x00007000L +#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x0000000c +#define MC_SHARED_CHREMAP__CHAN5_MASK 0x00038000L +#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x0000000f +#define MC_SHARED_CHREMAP__CHAN6_MASK 0x001c0000L +#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x00000012 +#define MC_SHARED_CHREMAP__CHAN7_MASK 0x00e00000L +#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x00000015 +#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0x000000ffL +#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x00000000 +#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0x0000ff00L +#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x00000008 +#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0x00ff0000L +#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x00000010 +#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000L +#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x00000018 +#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0x000000ffL +#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x00000000 +#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0x0000ff00L +#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x00000008 +#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0x00ff0000L +#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x00000010 +#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000L +#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x00000018 +#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000L +#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x00000010 +#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0x0000ffffL +#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x00000000 +#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000L +#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x00000010 +#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0x0000ffffL +#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffffL +#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffffL +#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0x0000000fL +#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0x000000f0L +#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x00000004 +#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000L +#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x0000001c +#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000L +#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x0000001d +#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000L +#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x0000001e +#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0x0000f000L +#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0x0000000c +#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0x00000f00L +#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x00000008 +#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0x0000000fL +#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0x000000f0L +#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x00000004 +#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000L +#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x0000001c +#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000L +#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x0000001d +#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000L +#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x0000001e +#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0x0000f000L +#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0x0000000c +#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0x00000f00L +#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x00000008 +#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000L +#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x0000001c +#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x03ff0000L +#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x00000010 +#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x00000400L +#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0x0000000a +#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x00000002L +#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x00000001 +#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x00000100L +#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x00000008 +#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x00000001L +#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x00000030L +#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x00000004 +#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x00000200L +#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x00000009 +#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x00000800L +#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0x0000000b +#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000L +#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x0000001c +#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x03ff0000L +#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x00000010 +#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x00000400L +#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0x0000000a +#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x00000002L +#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x00000001 +#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x00000100L +#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x00000008 +#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x00000001L +#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x00000000 +#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x00000030L +#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x00000004 +#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x00000200L +#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x00000009 +#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x00000800L +#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0x0000000b +#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0x000000ffL +#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x00000000 +#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0x0000ff00L +#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x00000008 +#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0x00ff0000L +#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x00000010 +#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000L +#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x00000018 +#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_MISC__FLAG_MASK 0x000000ffL +#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x00000000 +#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0x00000f00L +#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x00000008 +#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0x0000f000L +#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0x0000000c +#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x00000000 +#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffffL +#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x00000000 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x0003ffffL +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x00000000 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x0003ffffL +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x00000000 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x0003ffffL +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x00000100L +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x00000008 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x00000200L +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x00000009 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x00000003L +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0x0000000cL +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x00000002 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x00000030L +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x00000004 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0x000000c0L +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x00000006 +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0x0fffffffL +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x00000000 +#define MC_VM_FB_LOCATION__FB_BASE_MASK 0x0000ffffL +#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x00000000 +#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000L +#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x00000010 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x0003ffffL +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00007000L +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0x0000000c +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0x00000e00L +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x00000009 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x00000001L +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x00078000L +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0x0000000f +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x00000100L +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x00000008 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x00000000 +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x0000003fL +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x00000000 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x00000007 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x00000006 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x00000002L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x00000001 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x00000000 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x00000003 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x00000005 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_CB__ENABLE_MASK 0x00000001L +#define MC_WR_CB__ENABLE__SHIFT 0x00000000 +#define MC_WR_CB__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_CB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_CB__MAX_BURST_MASK 0x00000780L +#define MC_WR_CB__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_CB__PRESCALE_MASK 0x00000006L +#define MC_WR_CB__PRESCALE__SHIFT 0x00000001 +#define MC_WR_CB__STALL_MODE_MASK 0x00000030L +#define MC_WR_CB__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_CB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_DB__ENABLE_MASK 0x00000001L +#define MC_WR_DB__ENABLE__SHIFT 0x00000000 +#define MC_WR_DB__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_DB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_DB__MAX_BURST_MASK 0x00000780L +#define MC_WR_DB__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_DB__PRESCALE_MASK 0x00000006L +#define MC_WR_DB__PRESCALE__SHIFT 0x00000001 +#define MC_WR_DB__STALL_MODE_MASK 0x00000030L +#define MC_WR_DB__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_DB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_WR_GRP_EXT__DBSTEN0_MASK 0x0000000fL +#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x00000000 +#define MC_WR_GRP_EXT__TC0_MASK 0x000000f0L +#define MC_WR_GRP_EXT__TC0__SHIFT 0x00000004 +#define MC_WR_GRP_GFX__CP_MASK 0x0000000fL +#define MC_WR_GRP_GFX__CP__SHIFT 0x00000000 +#define MC_WR_GRP_GFX__XDMA_MASK 0x0000f000L +#define MC_WR_GRP_GFX__XDMAM_MASK 0x000f0000L +#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x00000010 +#define MC_WR_GRP_GFX__XDMA__SHIFT 0x0000000c +#define MC_WR_GRP_LCL__CB0_MASK 0x0000000fL +#define MC_WR_GRP_LCL__CB0__SHIFT 0x00000000 +#define MC_WR_GRP_LCL__CBCMASK0_MASK 0x000000f0L +#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x00000004 +#define MC_WR_GRP_LCL__CBFMASK0_MASK 0x00000f00L +#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x00000008 +#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000L +#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x0000001c +#define MC_WR_GRP_LCL__DB0_MASK 0x0000f000L +#define MC_WR_GRP_LCL__DB0__SHIFT 0x0000000c +#define MC_WR_GRP_LCL__DBHTILE0_MASK 0x000f0000L +#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x00000010 +#define MC_WR_GRP_LCL__SX0_MASK 0x00f00000L +#define MC_WR_GRP_LCL__SX0__SHIFT 0x00000014 +#define MC_WR_GRP_OTH__HDP_MASK 0x00000f00L +#define MC_WR_GRP_OTH__HDP__SHIFT 0x00000008 +#define MC_WR_GRP_OTH__SEM_MASK 0x0000f000L +#define MC_WR_GRP_OTH__SEM__SHIFT 0x0000000c +#define MC_WR_GRP_OTH__UMC_MASK 0x000f0000L +#define MC_WR_GRP_OTH__UMC__SHIFT 0x00000010 +#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0x0000000fL +#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x00000000 +#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000L +#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x0000001c +#define MC_WR_GRP_OTH__UVD_MASK 0x00f00000L +#define MC_WR_GRP_OTH__UVD__SHIFT 0x00000014 +#define MC_WR_GRP_OTH__XDP_MASK 0x0f000000L +#define MC_WR_GRP_OTH__XDP__SHIFT 0x00000018 +#define MC_WR_GRP_SYS__IH_MASK 0x0000000fL +#define MC_WR_GRP_SYS__IH__SHIFT 0x00000000 +#define MC_WR_GRP_SYS__MCIF_MASK 0x000000f0L +#define MC_WR_GRP_SYS__MCIF__SHIFT 0x00000004 +#define MC_WR_GRP_SYS__RLC_MASK 0x00000f00L +#define MC_WR_GRP_SYS__RLC__SHIFT 0x00000008 +#define MC_WR_GRP_SYS__SMU_MASK 0x00f00000L +#define MC_WR_GRP_SYS__SMU__SHIFT 0x00000014 +#define MC_WR_GRP_SYS__VCE_MASK 0x0f000000L +#define MC_WR_GRP_SYS__VCE__SHIFT 0x00000018 +#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000L +#define MC_WR_GRP_SYS__VCEU__SHIFT 0x0000001c +#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_HUB__ENABLE_MASK 0x00000001L +#define MC_WR_HUB__ENABLE__SHIFT 0x00000000 +#define MC_WR_HUB__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_HUB__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_HUB__MAX_BURST_MASK 0x00000780L +#define MC_WR_HUB__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_HUB__PRESCALE_MASK 0x00000006L +#define MC_WR_HUB__PRESCALE__SHIFT 0x00000001 +#define MC_WR_HUB__STALL_MODE_MASK 0x00000030L +#define MC_WR_HUB__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_TC0__ENABLE_MASK 0x00000001L +#define MC_WR_TC0__ENABLE__SHIFT 0x00000000 +#define MC_WR_TC0__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_TC0__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_TC0__MAX_BURST_MASK 0x00000780L +#define MC_WR_TC0__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_TC0__PRESCALE_MASK 0x00000006L +#define MC_WR_TC0__PRESCALE__SHIFT 0x00000001 +#define MC_WR_TC0__STALL_MODE_MASK 0x00000030L +#define MC_WR_TC0__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x00000008L +#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x00000003 +#define MC_WR_TC1__ENABLE_MASK 0x00000001L +#define MC_WR_TC1__ENABLE__SHIFT 0x00000000 +#define MC_WR_TC1__LAZY_TIMER_MASK 0x00007800L +#define MC_WR_TC1__LAZY_TIMER__SHIFT 0x0000000b +#define MC_WR_TC1__MAX_BURST_MASK 0x00000780L +#define MC_WR_TC1__MAX_BURST__SHIFT 0x00000007 +#define MC_WR_TC1__PRESCALE_MASK 0x00000006L +#define MC_WR_TC1__PRESCALE__SHIFT 0x00000001 +#define MC_WR_TC1__STALL_MODE_MASK 0x00000030L +#define MC_WR_TC1__STALL_MODE__SHIFT 0x00000004 +#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x00000040L +#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x00000006 +#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x00008000L +#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f +#define MC_XBAR_ADDR_DEC__GECC_MASK 0x00000002L +#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x00000001 +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x00000001L +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x00000000 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x00000008L +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x00000003 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x00000004L +#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x00000002 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x00000004L +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x00000002 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x00000002L +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x00000001 +#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x00000001L +#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x00000000 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0x0000000fL +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x00000000 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0x000000f0L +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x00000004 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0x00000f00L +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x00000008 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0x0000f000L +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0x0000000c +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0x000f0000L +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x00000010 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0x00f00000L +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x00000014 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0x0f000000L +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x00000018 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000L +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x0000001c +#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x00000003L +#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x00000000 +#define MC_XBAR_CHTRIREMAP__CH1_MASK 0x0000000cL +#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x00000002 +#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x00000030L +#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x00000004 +#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L +#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c +#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L +#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018 +#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL +#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L +#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a +#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L +#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c +#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x0000ff00L +#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000008 +#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x00ff0000L +#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x00000010 +#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x000000ffL +#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0x000000ffL +#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0x0000ff00L +#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x00000008 +#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0x00ff0000L +#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x00000010 +#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000L +#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x00000018 +#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0x000000ffL +#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0x0000ff00L +#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x00000008 +#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0x00ff0000L +#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x00000010 +#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000L +#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x00000018 +#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL +#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL +#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffffL +#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x00000000 +#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffffL +#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x00000000 +#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0x000000ffL +#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x00000000 +#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0x0000ff00L +#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x00000008 +#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0x00ff0000L +#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x00000010 +#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000L +#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x00000018 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0x000000ffL +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x00000000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0x0000ff00L +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x00000008 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0x00ff0000L +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x00000010 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000L +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x00000018 +#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0x000000ffL +#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x00000000 +#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0x0000ff00L +#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x00000008 +#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0x00ff0000L +#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x00000010 +#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000L +#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x00000018 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0x00ff0000L +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x00000010 +#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0x000000ffL +#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x00000000 +#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0x0000ff00L +#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x00000008 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0x000000ffL +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x00000000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0x0000ff00L +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x00000008 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0x00ff0000L +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x00000010 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000L +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x00000018 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0x000000ffL +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x00000000 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0x0000ff00L +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x00000008 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x00000002L +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x00000001 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x00000001L +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x00000000 +#define MC_XBAR_SPARE0__BIT_MASK 0xffffffffL +#define MC_XBAR_SPARE0__BIT__SHIFT 0x00000000 +#define MC_XBAR_SPARE1__BIT_MASK 0xffffffffL +#define MC_XBAR_SPARE1__BIT__SHIFT 0x00000000 +#define MC_XBAR_TWOCHAN__CH0_MASK 0x00000006L +#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x00000001 +#define MC_XBAR_TWOCHAN__CH1_MASK 0x00000018L +#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x00000003 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x00000001L +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x00000000 +#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0x000000ffL +#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x00000000 +#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0x0000ff00L +#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x00000008 +#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0x00ff0000L +#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x00000010 +#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000L +#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x00000018 +#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0x000000ffL +#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x00000000 +#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0x0000ff00L +#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x00000008 +#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0x00ff0000L +#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x00000010 +#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000L +#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x00000018 +#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0x000000ffL +#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x00000000 +#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0x0000ff00L +#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x00000008 +#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x00003c00L +#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0x0000000a +#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x00000070L +#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x00000004 +#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x00000380L +#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x00000007 +#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x0003c000L +#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0x0000000e +#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0x0000000fL +#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x00000000 +#define MC_XPB_CLG_EXTRA__CMP0_MASK 0x000000ffL +#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x00000000 +#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x01fe0000L +#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x00000011 +#define MC_XPB_CLG_EXTRA__MSK0_MASK 0x0000ff00L +#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x00000008 +#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0x000000ffL +#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x00000000 +#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x01fe0000L +#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x00000011 +#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0x0000ff00L +#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x00000008 +#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x00010000L +#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x00000010 +#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x02000000L +#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x00000019 +#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x00010000L +#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x00000010 +#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x02000000L +#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x00000019 +#define MC_XPB_CLK_GAT__ENABLE_MASK 0x00040000L +#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x00000012 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x00000013 +#define MC_XPB_CLK_GAT__OFFDLY_MASK 0x00000fc0L +#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x00000006 +#define MC_XPB_CLK_GAT__ONDLY_MASK 0x0000003fL +#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x00000000 +#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x0003f000L +#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0x0000000c +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000ffL +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x00000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x00000019 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x0000001a +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x00000017 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x00000018 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000ff00L +#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x00000008 +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000ffL +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x00000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x0000001e +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x0000001f +#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007f0000L +#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x00000010 +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x0000001b +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x0000001d +#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L +#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x00000012 +#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L +#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x00000011 +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x00000010 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0x0000000f +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07f80000L +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x00000013 +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000ffL +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x00000000 +#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007f00L +#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x00000008 +#define MC_XPB_LB_ADDR__CMP0_MASK 0x000003ffL +#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x00000000 +#define MC_XPB_LB_ADDR__CMP1_MASK 0x03f00000L +#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x00000014 +#define MC_XPB_LB_ADDR__MASK0_MASK 0x000ffc00L +#define MC_XPB_LB_ADDR__MASK0__SHIFT 0x0000000a +#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000L +#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x0000001a +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000ffffL +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x00000000 +#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0x000000ffL +#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x00000000 +#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0x0000ff00L +#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x00000008 +#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0x00ff0000L +#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x00000010 +#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000L +#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x00000018 +#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L +#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x0000001f +#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR0__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR0__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR1__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR1__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR2__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR2__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR3__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR3__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR4__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR4__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR5__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR5__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR6__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR6__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000fL +#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000f0L +#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR7__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR7__VALID__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000fL +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L +#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0x0000000b +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0x0000000a +#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L +#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x00000004 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L +#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x00000007 +#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L +#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x00000006 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x00000009 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0x00000f00L +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0x0000f000L +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0x0000000c +#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0x000000ffL +#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0fffff00L +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000ffL +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0fffff00L +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000ffL +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000L +#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x00000010 +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0x0000000e +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000f00L +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x00000008 +#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L +#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0x0000000f +#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0x000000ffL +#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x00000000 +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0x0000000d +#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L +#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0x0000000c +#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x00000000 +#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x07fffffcL +#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x00000002 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x00000002L +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L +#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x00000000 +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003fL +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x00000000 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000fc0L +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x00000006 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003f000L +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0x0000000c +#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L +#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x00000017 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x00000000 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000feL +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000001 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x00000015 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0x0000000f +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x00000011 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x00000013 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007f00L +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000008 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x00000016 +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x00000010 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x00000012 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x00000014 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000L +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L +#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x00000000 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_STICKY__BITS_MASK 0xffffffffL +#define MC_XPB_STICKY__BITS__SHIFT 0x00000000 +#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffffL +#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x00000000 +#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L +#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x00000013 +#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L +#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0x0000000a +#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L +#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x00000010 +#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L +#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0x0000000f +#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L +#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0x0000000d +#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L +#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0x0000000c +#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L +#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0x0000000b +#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L +#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x00000011 +#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L +#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x00000012 +#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L +#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0x0000000e +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x00000001 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x00000008 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x00000004 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x00000006 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x00000003 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x00000002 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x00000007 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x00000005 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x00000009 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x00000000 +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x0000003fL +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x00000000 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0x00000fc0L +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x00000006 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x0003f000L +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0x0000000c +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x0000003fL +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x00000000 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0x00000fc0L +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x00000006 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x0003f000L +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0x0000000c +#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x00030000L +#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x00000010 +#define MC_XPB_WCB_CFG__SID_MAX_MASK 0x000c0000L +#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x00000012 +#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0x0000ffffL +#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x00000000 +#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0x0000ffffL +#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x00000000 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007f0000L +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x00000010 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000L +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x00000017 +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x07fffffcL +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x00000002 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x00000002L +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x00000000 +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x07fffffcL +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x00000002 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x00000002L +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x00000000 +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x07fffffcL +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x00000002 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x00000002L +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x00000000 +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x07fffffcL +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x00000002 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x00000002L +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x00000001 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000L +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x0000001a +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000ffffeL +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x00000001 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00f00000L +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x00000018 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x00000014 +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x00000019 +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x00000000 +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x01ffffffL +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x00000000 +#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8L +#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x00000003 +#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x00000007L +#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x00000000 +#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_AD_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_AD_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x00600000L +#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x00000015 +#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x00100000L +#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x00000014 +#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x00020000L +#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x00000011 +#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000L +#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x0000001f +#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0x000000ffL +#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x00000000 +#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x00010000L +#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x00000010 +#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x00004000L +#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0x0000000e +#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x00000800L +#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0x0000000b +#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x00000100L +#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x00000008 +#define MPLL_CNTL_MODE__QDR_MASK 0x00002000L +#define MPLL_CNTL_MODE__QDR__SHIFT 0x0000000d +#define MPLL_CNTL_MODE__SPARE_1_MASK 0x00001000L +#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0x0000000c +#define MPLL_CNTL_MODE__SPARE_2_MASK 0x00800000L +#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x00000017 +#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000L +#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x0000001c +#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x04000000L +#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x0000001a +#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x03000000L +#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x00000018 +#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x08000000L +#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x0000001b +#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x00001000L +#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0x0000000c +#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x00002000L +#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0x0000000d +#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x00004000L +#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0x0000000e +#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x00010000L +#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x00000010 +#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x00020000L +#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x00000011 +#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x00040000L +#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x00000012 +#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x00100000L +#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x00000014 +#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x00200000L +#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x00000015 +#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x00400000L +#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x00000016 +#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x01000000L +#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x00000018 +#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x02000000L +#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x00000019 +#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x04000000L +#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x0000001a +#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000L +#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x0000001c +#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000L +#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x0000001d +#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000L +#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x0000001e +#define MPLL_CONTROL__GDDR_PWRON_MASK 0x00000001L +#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x00000000 +#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x00000004L +#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x00000002 +#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x00000002L +#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x00000001 +#define MPLL_CONTROL__SPARE_AD_0_MASK 0x00008000L +#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0x0000000f +#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x00080000L +#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x00000013 +#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x00800000L +#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x00000017 +#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x08000000L +#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x0000001b +#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000L +#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x0000001f +#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x00040000L +#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x00000012 +#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x00080000L +#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x00000013 +#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x00020000L +#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x00000011 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x00000070L +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x00000004 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x0001ff80L +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x00000007 +#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x00000007L +#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x00000000 +#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x00000008L +#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x00000003 +#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0L +#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x00000005 +#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x00000007L +#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x00000000 +#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x00000010L +#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x00000004 +#define MPLL_FUNC_CNTL_1__CLKF_MASK 0x0fff0000L +#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0x0000fff0L +#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x00000004 +#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x00000010 +#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0x0000000cL +#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x00000002 +#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000L +#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x0000001c +#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x00000003L +#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x00000000 +#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0x000e0000L +#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x00000011 +#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000L +#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x0000001b +#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x07f00000L +#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x00000014 +#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x00000080L +#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x00000007 +#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x00003000L +#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0x0000000c +#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x00000004L +#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x00000002 +#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0x00000c00L +#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0x0000000a +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x00000008L +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x00000003 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x00000010L +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x00000004 +#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x00000040L +#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x00000006 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x00000020L +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000005 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x00000200L +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x00000009 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x00000100L +#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x00000008 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x00000002L +#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x00000001 +#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x00000001L +#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x00000000 +#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0x00000f00L +#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x00000008 +#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0x000f0000L +#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x00000010 +#define MPLL_FUNC_CNTL__BWCTRL_MASK 0x0ff00000L +#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x00000014 +#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000L +#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x0000001e +#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x00000020L +#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x00000005 +#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0x0000000fL +#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x00000000 +#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0x000000f0L +#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x00000004 +#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0x00000f00L +#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x00000008 +#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0x0000f000L +#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0x0000000c +#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0x000f0000L +#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x00000010 +#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0x00f00000L +#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x00000014 +#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0x0f000000L +#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x00000018 +#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000L +#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x0000001c +#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0x00000f00L +#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x00000008 +#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0x0000f000L +#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0x0000000c +#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0x000f0000L +#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x00000010 +#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0x00f00000L +#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x00000014 +#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0x0f000000L +#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x00000018 +#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000L +#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x0000001c +#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0x0000000fL +#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x00000000 +#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0x000000f0L +#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x00000004 +#define MPLL_SS1__CLKV_MASK 0x03ffffffL +#define MPLL_SS1__CLKV__SHIFT 0x00000000 +#define MPLL_SS1__SPARE_MASK 0xfc000000L +#define MPLL_SS1__SPARE__SHIFT 0x0000001a +#define MPLL_SS2__CLKS_MASK 0x00000fffL +#define MPLL_SS2__CLKS__SHIFT 0x00000000 +#define MPLL_SS2__SPARE_MASK 0xfffff000L +#define MPLL_SS2__SPARE__SHIFT 0x0000000c +#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0x0000ffffL +#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x00000000 +#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000L +#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x00000010 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x00000001 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x00000002 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000017 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x000ff000L +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000003 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x00000001 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x00000002 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x00000004 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000007 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000006 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x00000000 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0f000000L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x00000018 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x00000001 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000a +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000009 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000b +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000016 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000015 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000017 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000004 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000003 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000010 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000f +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000011 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x0000000d +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x0000000c +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x0000000e +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x00000013 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x00000012 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x00000014 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0x0fffffffL +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0x0fffffffL +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x00000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x000ff000L +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0x0000000c +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x01000000L +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x00000018 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0x000000ffL +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x00000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000L +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x00000019 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x00000000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0x0000000a +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0x0000000b +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0x0000000c +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0x0000000d +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0x0000000e +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0x0000000f +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x00000001 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x00000002 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x00000003 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x00000004 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x00000005 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x00000006 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x00000007 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x00000008 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x00000009 +#define VM_DEBUG__FLAGS_MASK 0xffffffffL +#define VM_DEBUG__FLAGS__SHIFT 0x00000000 +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0x0fffffffL +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x00000000 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x00000001 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0x0000000cL +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x00000002 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x00000000 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x000001ffL +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x0003fe00L +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x00000009 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x00000000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x00000001L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x00000000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x00000400L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0x0000000a +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x00000800L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0x0000000b +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x00001000L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0x0000000c +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x00002000L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0x0000000d +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x00004000L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0x0000000e +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x00008000L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0x0000000f +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x00000002L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x00000001 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x00000004L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x00000002 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x00000008L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x00000003 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x00000010L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x00000004 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x00000020L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x00000005 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x00000040L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x00000006 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x00000080L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x00000007 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x00000100L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x00000008 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x00000200L +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x00000009 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x00000001L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x00000000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x00000400L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0x0000000a +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x00000800L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0x0000000b +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x00001000L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0x0000000c +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x00002000L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0x0000000d +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x00004000L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0x0000000e +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x00008000L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0x0000000f +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x00000002L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x00000001 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x00000004L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x00000002 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x00000008L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x00000003 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x00000010L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x00000004 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x00000020L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x00000005 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x00000040L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x00000006 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x00000080L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x00000007 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x00000100L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x00000008 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x00000200L +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x00000009 +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0x0fffffffL +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x00000000 +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x000000ffL +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x00000000 +#define VM_L2_CG__ENABLE_MASK 0x00040000L +#define VM_L2_CG__ENABLE__SHIFT 0x00000012 +#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x00080000L +#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x00000013 +#define VM_L2_CG__OFFDLY_MASK 0x00000fc0L +#define VM_L2_CG__OFFDLY__SHIFT 0x00000006 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x00000016 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x00000015 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x00000000 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0c000000L +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x0000001a +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x00000001 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x00000017 +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003fL +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x00000000 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00e00000L +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x00000015 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x0000001c +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x00000014 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0f000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x00000018 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x0000001d +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000f8000L +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x0000000f +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000c0L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x00000006 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001f00L +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x00000008 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x00000013 +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0x0000000f +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x00000000 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x00000001 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x0000000a +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x00000009 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03e00000L +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x00000015 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0c000000L +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001a +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x0000001c +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x00000004 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000cL +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x00000002 +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0x0000000c +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x00000008 +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x00000012 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0x0fffffffL +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x00000000 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001fffeL +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x00000001 +#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x00000000 +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0x0fffffffL +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x00000000 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x00000008L +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x00000003 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x00000004L +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x00000002 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h new file mode 100644 index 000000000000..edc8a793a95d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h @@ -0,0 +1,275 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_1_0_D_H +#define OSS_1_0_D_H + +#define ixCLIENT0_BM 0x0220 +#define ixCLIENT0_CD0 0x0210 +#define ixCLIENT0_CD1 0x0214 +#define ixCLIENT0_CD2 0x0218 +#define ixCLIENT0_CD3 0x021C +#define ixCLIENT0_CK0 0x0200 +#define ixCLIENT0_CK1 0x0204 +#define ixCLIENT0_CK2 0x0208 +#define ixCLIENT0_CK3 0x020C +#define ixCLIENT0_K0 0x01F0 +#define ixCLIENT0_K1 0x01F4 +#define ixCLIENT0_K2 0x01F8 +#define ixCLIENT0_K3 0x01FC +#define ixCLIENT0_OFFSET 0x0224 +#define ixCLIENT0_OFFSET_HI 0x0290 +#define ixCLIENT0_STATUS 0x0228 +#define ixCLIENT1_BM 0x025C +#define ixCLIENT1_CD0 0x024C +#define ixCLIENT1_CD1 0x0250 +#define ixCLIENT1_CD2 0x0254 +#define ixCLIENT1_CD3 0x0258 +#define ixCLIENT1_CK0 0x023C +#define ixCLIENT1_CK1 0x0240 +#define ixCLIENT1_CK2 0x0244 +#define ixCLIENT1_CK3 0x0248 +#define ixCLIENT1_K0 0x022C +#define ixCLIENT1_K1 0x0230 +#define ixCLIENT1_K2 0x0234 +#define ixCLIENT1_K3 0x0238 +#define ixCLIENT1_OFFSET 0x0260 +#define ixCLIENT1_OFFSET_HI 0x0294 +#define ixCLIENT1_PORT_STATUS 0x0264 +#define ixCLIENT2_BM 0x01E4 +#define ixCLIENT2_CD0 0x01D4 +#define ixCLIENT2_CD1 0x01D8 +#define ixCLIENT2_CD2 0x01DC +#define ixCLIENT2_CD3 0x01E0 +#define ixCLIENT2_CK0 0x01C4 +#define ixCLIENT2_CK1 0x01C8 +#define ixCLIENT2_CK2 0x01CC +#define ixCLIENT2_CK3 0x01D0 +#define ixCLIENT2_K0 0x01B4 +#define ixCLIENT2_K1 0x01B8 +#define ixCLIENT2_K2 0x01BC +#define ixCLIENT2_K3 0x01C0 +#define ixCLIENT2_OFFSET 0x01E8 +#define ixCLIENT2_OFFSET_HI 0x0298 +#define ixCLIENT2_STATUS 0x01EC +#define ixCLIENT3_BM 0x02D4 +#define ixCLIENT3_CD0 0x02C4 +#define ixCLIENT3_CD1 0x02C8 +#define ixCLIENT3_CD2 0x02CC +#define ixCLIENT3_CD3 0x02D0 +#define ixCLIENT3_CK0 0x02B4 +#define ixCLIENT3_CK1 0x02B8 +#define ixCLIENT3_CK2 0x02BC +#define ixCLIENT3_CK3 0x02C0 +#define ixCLIENT3_K0 0x02A4 +#define ixCLIENT3_K1 0x02A8 +#define ixCLIENT3_K2 0x02AC +#define ixCLIENT3_K3 0x02B0 +#define ixCLIENT3_OFFSET 0x02D8 +#define ixCLIENT3_OFFSET_HI 0x02A0 +#define ixCLIENT3_STATUS 0x02DC +#define ixDH_TEST 0x0000 +#define ixEXP0 0x0034 +#define ixEXP1 0x0038 +#define ixEXP2 0x003C +#define ixEXP3 0x0040 +#define ixEXP4 0x0044 +#define ixEXP5 0x0048 +#define ixEXP6 0x004C +#define ixEXP7 0x0050 +#define ixHFS_SEED0 0x0278 +#define ixHFS_SEED1 0x027C +#define ixHFS_SEED2 0x0280 +#define ixHFS_SEED3 0x0284 +#define ixKEFUSE0 0x0268 +#define ixKEFUSE1 0x026C +#define ixKEFUSE2 0x0270 +#define ixKEFUSE3 0x0274 +#define ixKHFS0 0x0004 +#define ixKHFS1 0x0008 +#define ixKHFS2 0x000C +#define ixKHFS3 0x0010 +#define ixKSESSION0 0x0014 +#define ixKSESSION1 0x0018 +#define ixKSESSION2 0x001C +#define ixKSESSION3 0x0020 +#define ixKSIG0 0x0024 +#define ixKSIG1 0x0028 +#define ixKSIG2 0x002C +#define ixKSIG3 0x0030 +#define ixLX0 0x0054 +#define ixLX1 0x0058 +#define ixLX2 0x005C +#define ixLX3 0x0060 +#define ixRINGOSC_MASK 0x0288 +#define ixSPU_PORT_STATUS 0x029C +#define mmCC_DRM_ID_STRAPS 0x1559 +#define mmCC_SYS_RB_BACKEND_DISABLE 0x03A0 +#define mmCC_SYS_RB_REDUNDANCY 0x039F +#define mmCGTT_DRM_CLK_CTRL0 0x1579 +#define mmCP_CONFIG 0x0F92 +#define mmDC_TEST_DEBUG_DATA 0x157D +#define mmDC_TEST_DEBUG_INDEX 0x157C +#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x03A1 +#define mmHDP_ADDR_CONFIG 0x0BD2 +#define mmHDP_DEBUG0 0x0BCC +#define mmHDP_DEBUG1 0x0BCD +#define mmHDP_HOST_PATH_CNTL 0x0B00 +#define mmHDP_LAST_SURFACE_HIT 0x0BCE +#define mmHDP_MEMIO_ADDR 0x0BF7 +#define mmHDP_MEMIO_CNTL 0x0BF6 +#define mmHDP_MEMIO_RD_DATA 0x0BFA +#define mmHDP_MEMIO_STATUS 0x0BF8 +#define mmHDP_MEMIO_WR_DATA 0x0BF9 +#define mmHDP_MEM_POWER_LS 0x0BD4 +#define mmHDP_MISC_CNTL 0x0BD3 +#define mmHDP_NONSURFACE_BASE 0x0B01 +#define mmHDP_NONSURFACE_INFO 0x0B02 +#define mmHDP_NONSURFACE_PREFETCH 0x0BD5 +#define mmHDP_NONSURFACE_SIZE 0x0B03 +#define mmHDP_NONSURF_FLAGS 0x0BC9 +#define mmHDP_NONSURF_FLAGS_CLR 0x0BCA +#define mmHDP_OUTSTANDING_REQ 0x0BD1 +#define mmHDP_SC_MULTI_CHIP_CNTL 0x0BD0 +#define mmHDP_SW_SEMAPHORE 0x0BCB +#define mmHDP_TILING_CONFIG 0x0BCF +#define mmHDP_XDP_BARS_ADDR_39_36 0x0C44 +#define mmHDP_XDP_BUSY_STS 0x0C3E +#define mmHDP_XDP_CGTT_BLK_CTRL 0x0C33 +#define mmHDP_XDP_CHKN 0x0C40 +#define mmHDP_XDP_D2H_BAR_UPDATE 0x0C02 +#define mmHDP_XDP_D2H_FLUSH 0x0C01 +#define mmHDP_XDP_D2H_RSVD_10 0x0C0A +#define mmHDP_XDP_D2H_RSVD_11 0x0C0B +#define mmHDP_XDP_D2H_RSVD_12 0x0C0C +#define mmHDP_XDP_D2H_RSVD_13 0x0C0D +#define mmHDP_XDP_D2H_RSVD_14 0x0C0E +#define mmHDP_XDP_D2H_RSVD_15 0x0C0F +#define mmHDP_XDP_D2H_RSVD_16 0x0C10 +#define mmHDP_XDP_D2H_RSVD_17 0x0C11 +#define mmHDP_XDP_D2H_RSVD_18 0x0C12 +#define mmHDP_XDP_D2H_RSVD_19 0x0C13 +#define mmHDP_XDP_D2H_RSVD_20 0x0C14 +#define mmHDP_XDP_D2H_RSVD_21 0x0C15 +#define mmHDP_XDP_D2H_RSVD_22 0x0C16 +#define mmHDP_XDP_D2H_RSVD_23 0x0C17 +#define mmHDP_XDP_D2H_RSVD_24 0x0C18 +#define mmHDP_XDP_D2H_RSVD_25 0x0C19 +#define mmHDP_XDP_D2H_RSVD_26 0x0C1A +#define mmHDP_XDP_D2H_RSVD_27 0x0C1B +#define mmHDP_XDP_D2H_RSVD_28 0x0C1C +#define mmHDP_XDP_D2H_RSVD_29 0x0C1D +#define mmHDP_XDP_D2H_RSVD_30 0x0C1E +#define mmHDP_XDP_D2H_RSVD_3 0x0C03 +#define mmHDP_XDP_D2H_RSVD_31 0x0C1F +#define mmHDP_XDP_D2H_RSVD_32 0x0C20 +#define mmHDP_XDP_D2H_RSVD_33 0x0C21 +#define mmHDP_XDP_D2H_RSVD_34 0x0C22 +#define mmHDP_XDP_D2H_RSVD_4 0x0C04 +#define mmHDP_XDP_D2H_RSVD_5 0x0C05 +#define mmHDP_XDP_D2H_RSVD_6 0x0C06 +#define mmHDP_XDP_D2H_RSVD_7 0x0C07 +#define mmHDP_XDP_D2H_RSVD_8 0x0C08 +#define mmHDP_XDP_D2H_RSVD_9 0x0C09 +#define mmHDP_XDP_DBG_ADDR 0x0C41 +#define mmHDP_XDP_DBG_DATA 0x0C42 +#define mmHDP_XDP_DBG_MASK 0x0C43 +#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0C00 +#define mmHDP_XDP_DIRECT2HDP_LAST 0x0C23 +#define mmHDP_XDP_FLUSH_ARMED_STS 0x0C3C +#define mmHDP_XDP_FLUSH_CNTR0_STS 0x0C3D +#define mmHDP_XDP_HDP_IPH_CFG 0x0C31 +#define mmHDP_XDP_HDP_MBX_MC_CFG 0x0C2D +#define mmHDP_XDP_HDP_MC_CFG 0x0C2E +#define mmHDP_XDP_HST_CFG 0x0C2F +#define mmHDP_XDP_P2P_BAR0 0x0C34 +#define mmHDP_XDP_P2P_BAR1 0x0C35 +#define mmHDP_XDP_P2P_BAR2 0x0C36 +#define mmHDP_XDP_P2P_BAR3 0x0C37 +#define mmHDP_XDP_P2P_BAR4 0x0C38 +#define mmHDP_XDP_P2P_BAR5 0x0C39 +#define mmHDP_XDP_P2P_BAR6 0x0C3A +#define mmHDP_XDP_P2P_BAR7 0x0C3B +#define mmHDP_XDP_P2P_BAR_CFG 0x0C24 +#define mmHDP_XDP_P2P_MBX_ADDR0 0x0C26 +#define mmHDP_XDP_P2P_MBX_ADDR1 0x0C27 +#define mmHDP_XDP_P2P_MBX_ADDR2 0x0C28 +#define mmHDP_XDP_P2P_MBX_ADDR3 0x0C29 +#define mmHDP_XDP_P2P_MBX_ADDR4 0x0C2A +#define mmHDP_XDP_P2P_MBX_ADDR5 0x0C2B +#define mmHDP_XDP_P2P_MBX_ADDR6 0x0C2C +#define mmHDP_XDP_P2P_MBX_OFFSET 0x0C25 +#define mmHDP_XDP_SID_CFG 0x0C30 +#define mmHDP_XDP_SRBM_CFG 0x0C32 +#define mmHDP_XDP_STICKY 0x0C3F +#define mmIH_ADVFAULT_CNTL 0x0F8C +#define mmIH_CNTL 0x0F86 +#define mmIH_LEVEL_STATUS 0x0F87 +#define mmIH_PERFCOUNTER0_RESULT 0x0F8A +#define mmIH_PERFCOUNTER1_RESULT 0x0F8B +#define mmIH_PERFMON_CNTL 0x0F89 +#define mmIH_RB_BASE 0x0F81 +#define mmIH_RB_CNTL 0x0F80 +#define mmIH_RB_RPTR 0x0F82 +#define mmIH_RB_WPTR 0x0F83 +#define mmIH_RB_WPTR_ADDR_HI 0x0F84 +#define mmIH_RB_WPTR_ADDR_LO 0x0F85 +#define mmIH_STATUS 0x0F88 +#define mmSEM_MAILBOX 0x0F9B +#define mmSEM_MAILBOX_CLIENTCONFIG 0x0F9A +#define mmSEM_MAILBOX_CONTROL 0x0F9C +#define mmSEM_MCIF_CONFIG 0x0F90 +#define mmSRBM_CAM_DATA 0x0397 +#define mmSRBM_CAM_INDEX 0x0396 +#define mmSRBM_CHIP_REVISION 0x039B +#define mmSRBM_CNTL 0x0390 +#define mmSRBM_DEBUG 0x03A4 +#define mmSRBM_DEBUG_CNTL 0x0399 +#define mmSRBM_DEBUG_DATA 0x039A +#define mmSRBM_DEBUG_SNAPSHOT 0x03A5 +#define mmSRBM_GFX_CNTL 0x0391 +#define mmSRBM_INT_ACK 0x03AA +#define mmSRBM_INT_CNTL 0x03A8 +#define mmSRBM_INT_STATUS 0x03A9 +#define mmSRBM_MC_CLKEN_CNTL 0x03B3 +#define mmSRBM_PERFCOUNTER0_HI 0x0704 +#define mmSRBM_PERFCOUNTER0_LO 0x0703 +#define mmSRBM_PERFCOUNTER0_SELECT 0x0701 +#define mmSRBM_PERFCOUNTER1_HI 0x0706 +#define mmSRBM_PERFCOUNTER1_LO 0x0705 +#define mmSRBM_PERFCOUNTER1_SELECT 0x0702 +#define mmSRBM_PERFMON_CNTL 0x0700 +#define mmSRBM_READ_ERROR 0x03A6 +#define mmSRBM_SOFT_RESET 0x0398 +#define mmSRBM_STATUS 0x0394 +#define mmSRBM_STATUS2 0x0393 +#define mmSRBM_SYS_CLKEN_CNTL 0x03B4 +#define mmSRBM_UVD_CLKEN_CNTL 0x03B6 +#define mmSRBM_VCE_CLKEN_CNTL 0x03B5 +#define mmUVD_CONFIG 0x0F98 +#define mmVCE_CONFIG 0x0F94 +#define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x03F8 + +/* from the old sid.h */ +#define mmDMA_TILING_CONFIG 0x342E + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h new file mode 100644 index 000000000000..1c540fe136cb --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h @@ -0,0 +1,1079 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_1_0_SH_MASK_H +#define OSS_1_0_SH_MASK_H + +#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L +#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c +#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L +#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004 +#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L +#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014 +#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L +#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 +#define CLIENT0_BM__RESERVED_MASK 0xffffffffL +#define CLIENT0_BM__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CD0__RESERVED_MASK 0xffffffffL +#define CLIENT0_CD0__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CD1__RESERVED_MASK 0xffffffffL +#define CLIENT0_CD1__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CD2__RESERVED_MASK 0xffffffffL +#define CLIENT0_CD2__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CD3__RESERVED_MASK 0xffffffffL +#define CLIENT0_CD3__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CK0__RESERVED_MASK 0xffffffffL +#define CLIENT0_CK0__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CK1__RESERVED_MASK 0xffffffffL +#define CLIENT0_CK1__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CK2__RESERVED_MASK 0xffffffffL +#define CLIENT0_CK2__RESERVED__SHIFT 0x00000000 +#define CLIENT0_CK3__RESERVED_MASK 0xffffffffL +#define CLIENT0_CK3__RESERVED__SHIFT 0x00000000 +#define CLIENT0_K0__RESERVED_MASK 0xffffffffL +#define CLIENT0_K0__RESERVED__SHIFT 0x00000000 +#define CLIENT0_K1__RESERVED_MASK 0xffffffffL +#define CLIENT0_K1__RESERVED__SHIFT 0x00000000 +#define CLIENT0_K2__RESERVED_MASK 0xffffffffL +#define CLIENT0_K2__RESERVED__SHIFT 0x00000000 +#define CLIENT0_K3__RESERVED_MASK 0xffffffffL +#define CLIENT0_K3__RESERVED__SHIFT 0x00000000 +#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffffL +#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x00000000 +#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffffL +#define CLIENT0_OFFSET__RESERVED__SHIFT 0x00000000 +#define CLIENT0_STATUS__RESERVED_MASK 0xffffffffL +#define CLIENT0_STATUS__RESERVED__SHIFT 0x00000000 +#define CLIENT1_BM__RESERVED_MASK 0xffffffffL +#define CLIENT1_BM__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CD0__RESERVED_MASK 0xffffffffL +#define CLIENT1_CD0__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CD1__RESERVED_MASK 0xffffffffL +#define CLIENT1_CD1__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CD2__RESERVED_MASK 0xffffffffL +#define CLIENT1_CD2__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CD3__RESERVED_MASK 0xffffffffL +#define CLIENT1_CD3__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CK0__RESERVED_MASK 0xffffffffL +#define CLIENT1_CK0__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CK1__RESERVED_MASK 0xffffffffL +#define CLIENT1_CK1__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CK2__RESERVED_MASK 0xffffffffL +#define CLIENT1_CK2__RESERVED__SHIFT 0x00000000 +#define CLIENT1_CK3__RESERVED_MASK 0xffffffffL +#define CLIENT1_CK3__RESERVED__SHIFT 0x00000000 +#define CLIENT1_K0__RESERVED_MASK 0xffffffffL +#define CLIENT1_K0__RESERVED__SHIFT 0x00000000 +#define CLIENT1_K1__RESERVED_MASK 0xffffffffL +#define CLIENT1_K1__RESERVED__SHIFT 0x00000000 +#define CLIENT1_K2__RESERVED_MASK 0xffffffffL +#define CLIENT1_K2__RESERVED__SHIFT 0x00000000 +#define CLIENT1_K3__RESERVED_MASK 0xffffffffL +#define CLIENT1_K3__RESERVED__SHIFT 0x00000000 +#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffffL +#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x00000000 +#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffffL +#define CLIENT1_OFFSET__RESERVED__SHIFT 0x00000000 +#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffffL +#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x00000000 +#define CLIENT2_BM__RESERVED_MASK 0xffffffffL +#define CLIENT2_BM__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CD0__RESERVED_MASK 0xffffffffL +#define CLIENT2_CD0__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CD1__RESERVED_MASK 0xffffffffL +#define CLIENT2_CD1__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CD2__RESERVED_MASK 0xffffffffL +#define CLIENT2_CD2__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CD3__RESERVED_MASK 0xffffffffL +#define CLIENT2_CD3__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CK0__RESERVED_MASK 0xffffffffL +#define CLIENT2_CK0__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CK1__RESERVED_MASK 0xffffffffL +#define CLIENT2_CK1__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CK2__RESERVED_MASK 0xffffffffL +#define CLIENT2_CK2__RESERVED__SHIFT 0x00000000 +#define CLIENT2_CK3__RESERVED_MASK 0xffffffffL +#define CLIENT2_CK3__RESERVED__SHIFT 0x00000000 +#define CLIENT2_K0__RESERVED_MASK 0xffffffffL +#define CLIENT2_K0__RESERVED__SHIFT 0x00000000 +#define CLIENT2_K1__RESERVED_MASK 0xffffffffL +#define CLIENT2_K1__RESERVED__SHIFT 0x00000000 +#define CLIENT2_K2__RESERVED_MASK 0xffffffffL +#define CLIENT2_K2__RESERVED__SHIFT 0x00000000 +#define CLIENT2_K3__RESERVED_MASK 0xffffffffL +#define CLIENT2_K3__RESERVED__SHIFT 0x00000000 +#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffffL +#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x00000000 +#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffffL +#define CLIENT2_OFFSET__RESERVED__SHIFT 0x00000000 +#define CLIENT2_STATUS__RESERVED_MASK 0xffffffffL +#define CLIENT2_STATUS__RESERVED__SHIFT 0x00000000 +#define CLIENT3_BM__RESERVED_MASK 0xffffffffL +#define CLIENT3_BM__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CD0__RESERVED_MASK 0xffffffffL +#define CLIENT3_CD0__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CD1__RESERVED_MASK 0xffffffffL +#define CLIENT3_CD1__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CD2__RESERVED_MASK 0xffffffffL +#define CLIENT3_CD2__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CD3__RESERVED_MASK 0xffffffffL +#define CLIENT3_CD3__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CK0__RESERVED_MASK 0xffffffffL +#define CLIENT3_CK0__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CK1__RESERVED_MASK 0xffffffffL +#define CLIENT3_CK1__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CK2__RESERVED_MASK 0xffffffffL +#define CLIENT3_CK2__RESERVED__SHIFT 0x00000000 +#define CLIENT3_CK3__RESERVED_MASK 0xffffffffL +#define CLIENT3_CK3__RESERVED__SHIFT 0x00000000 +#define CLIENT3_K0__RESERVED_MASK 0xffffffffL +#define CLIENT3_K0__RESERVED__SHIFT 0x00000000 +#define CLIENT3_K1__RESERVED_MASK 0xffffffffL +#define CLIENT3_K1__RESERVED__SHIFT 0x00000000 +#define CLIENT3_K2__RESERVED_MASK 0xffffffffL +#define CLIENT3_K2__RESERVED__SHIFT 0x00000000 +#define CLIENT3_K3__RESERVED_MASK 0xffffffffL +#define CLIENT3_K3__RESERVED__SHIFT 0x00000000 +#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffffL +#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x00000000 +#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffffL +#define CLIENT3_OFFSET__RESERVED__SHIFT 0x00000000 +#define CLIENT3_STATUS__RESERVED_MASK 0xffffffffL +#define CLIENT3_STATUS__RESERVED__SHIFT 0x00000000 +#define CP_CONFIG__CP_RDREQ_URG_MASK 0x00000f00L +#define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x00000008 +#define CP_CONFIG__CP_REQ_TRAN_MASK 0x00010000L +#define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x00000010 +#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffffL +#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x00000000 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0x000000ffL +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 +#define DH_TEST__DH_TEST_MASK 0x00000001L +#define DH_TEST__DH_TEST__SHIFT 0x00000000 +#define EXP0__RESERVED_MASK 0xffffffffL +#define EXP0__RESERVED__SHIFT 0x00000000 +#define EXP1__RESERVED_MASK 0xffffffffL +#define EXP1__RESERVED__SHIFT 0x00000000 +#define EXP2__RESERVED_MASK 0xffffffffL +#define EXP2__RESERVED__SHIFT 0x00000000 +#define EXP3__RESERVED_MASK 0xffffffffL +#define EXP3__RESERVED__SHIFT 0x00000000 +#define EXP4__RESERVED_MASK 0xffffffffL +#define EXP4__RESERVED__SHIFT 0x00000000 +#define EXP5__RESERVED_MASK 0xffffffffL +#define EXP5__RESERVED__SHIFT 0x00000000 +#define EXP6__RESERVED_MASK 0xffffffffL +#define EXP6__RESERVED__SHIFT 0x00000000 +#define EXP7__RESERVED_MASK 0xffffffffL +#define EXP7__RESERVED__SHIFT 0x00000000 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x00000000 +#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x00000000 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x0000001d +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x00000007L +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x00000000 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x00400000L +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x00000016 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x00800000L +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x00000017 +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x0000001f +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x000001f8L +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000003 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0x0000000b +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0f000000L +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x00000018 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x00000015 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x00000013 +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x0000001e +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x00000009 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x0000003fL +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x00000000 +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffffL +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x00000000 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003f00L +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x00000008 +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003cL +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x00000002 +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0x0000000f +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0x0000000e +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x00000001 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x00000007 +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x00000000 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x00000006 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffffL +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x00000000 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x00000003 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x00000001 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x00000002 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x00000000 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffffL +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x00000000 +#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L +#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x00000000 +#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001f80L +#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000007 +#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x0000007eL +#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000001 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x00100000L +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x00000014 +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x00000015 +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x00000000 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x00000780L +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x00000007 +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000L +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d +#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L +#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x00000006 +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x00001000L +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0x0000000c +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x00000005 +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x00080000L +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x00000013 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0x0000000b +#define HDP_MISC_CNTL__VM_ID_MASK 0x0000001eL +#define HDP_MISC_CNTL__VM_ID__SHIFT 0x00000001 +#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffffL +#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x00000000 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x00000001L +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x00000000 +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x0000001eL +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x00000001 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x03000000L +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x00000018 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0x00c00000L +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x00000016 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x00000060L +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x00000005 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0x0c000000L +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x0000001a +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x30000000L +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x0000001c +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x00300000L +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x00000014 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x00000380L +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x00000007 +#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x00008000L +#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0x0000000f +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x00001c00L +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0x0000000a +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x00006000L +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0x0000000d +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x40000000L +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x0000001e +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x00010000L +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x00000010 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0x000e0000L +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x00000011 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x0000001b +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x00000038L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x00000003 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0x000ffe00L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x00000009 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x000001c0L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x00000006 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x00000007L +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x00000000 +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x000007ffL +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x00000000 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800L +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0x0000000b +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x00000001 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x00000000 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x00000001 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x00000000 +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000ff00L +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x00000008 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000ffL +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x00000000 +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x00000007L +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x00000000 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x00000018L +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x00000003 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffffL +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x00000000 +#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x00003800L +#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0x0000000b +#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x00000030L +#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x00000004 +#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0x000000c0L +#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x00000006 +#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0x0000000eL +#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x00000001 +#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x00000700L +#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x00000008 +#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0x0000c000L +#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0x0000000e +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000fL +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x00000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000f0L +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x00000004 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000f00L +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x00000008 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000f000L +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0x0000000c +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000f0000L +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x00000010 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00f00000L +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x00000014 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0f000000L +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x00000018 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000L +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x0000001c +#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003ffffL +#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x00000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0x0000000fL +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x00000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0x00000ff0L +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x00000004 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000L +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0x0000000c +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000L +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x0000001e +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000L +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x0000001f +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000ffL +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x00000000 +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000ff00L +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x00000008 +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00ff0000L +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x00000010 +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000L +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x00000018 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000ffffL +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x00000000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x00000014 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000f0000L +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x00000010 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x00000012 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000fL +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x00000000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x00000008 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000f0L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x00000004 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x00000013 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x00000014 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x00000010 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x00020000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x00000011 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000f800L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0x0000000b +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffffL +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000L +#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x00000010 +#define HDP_XDP_DBG_ADDR__STS_MASK 0x0000ffffL +#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x00000000 +#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000L +#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x00000010 +#define HDP_XDP_DBG_DATA__STS_MASK 0x0000ffffL +#define HDP_XDP_DBG_DATA__STS__SHIFT 0x00000000 +#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000L +#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x00000010 +#define HDP_XDP_DBG_MASK__STS_MASK 0x0000ffffL +#define HDP_XDP_DBG_MASK__STS__SHIFT 0x00000000 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffffL +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffffL +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x00000000 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffffL +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x00000000 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03ffffffL +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x00000000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0x0000000c +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0x0000000d +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003fL +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000fc0L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000006 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x00000001L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x00000000 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000006L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x00000001 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x00000008L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x00000003 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x000000f0L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x00000004 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x00000001L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x00000000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x00000006L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x00000001 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x00000008L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x00000003 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x07800000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x00000017 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x00700000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x00000014 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x00000010L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x00000004 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x00000060L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x00000005 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x00000080L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x00000007 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x0000001b +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000fc000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0x0000000e +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x00003f00L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x00000008 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x00000000 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001 +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000ffffL +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000f0000L +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x00000010 +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x00000014 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000fL +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x00000000 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x00000004 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x01e00000L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x00000015 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x001ffffeL +#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x00000001 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x00000000 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x00003fffL +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x00000000 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x00000018L +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x00000003 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x00000001L +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x00000000 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x00000006L +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x0000003fL +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x00000000 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x00000040L +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x00000006 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x00000080L +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x00000007 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000ffffL +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x00000000 +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000L +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x00000010 +#define HFS_SEED0__RESERVED_MASK 0xffffffffL +#define HFS_SEED0__RESERVED__SHIFT 0x00000000 +#define HFS_SEED1__RESERVED_MASK 0xffffffffL +#define HFS_SEED1__RESERVED__SHIFT 0x00000000 +#define HFS_SEED2__RESERVED_MASK 0xffffffffL +#define HFS_SEED2__RESERVED__SHIFT 0x00000000 +#define HFS_SEED3__RESERVED_MASK 0xffffffffL +#define HFS_SEED3__RESERVED__SHIFT 0x00000000 +#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0x0000ff00L +#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x00000008 +#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000L +#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x00000010 +#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x00000008L +#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x00000003 +#define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x00000007L +#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x00000010L +#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x00000004 +#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x00000000 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x00000300L +#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x00000008 +#define IH_CNTL__ENABLE_INTR_MASK 0x00000001L +#define IH_CNTL__ENABLE_INTR__SHIFT 0x00000000 +#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x00007c00L +#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0x0000000a +#define IH_CNTL__MC_SWAP_MASK 0x00000006L +#define IH_CNTL__MC_SWAP__SHIFT 0x00000001 +#define IH_CNTL__MC_TRAN_MASK 0x00000008L +#define IH_CNTL__MC_TRAN__SHIFT 0x00000003 +#define IH_CNTL__MC_VMID_MASK 0x1e000000L +#define IH_CNTL__MC_VMID__SHIFT 0x00000019 +#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01f00000L +#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x00000014 +#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0x000f8000L +#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x0000000f +#define IH_CNTL__RPTR_REARM_MASK 0x00000010L +#define IH_CNTL__RPTR_REARM__SHIFT 0x00000004 +#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x00000010L +#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x00000004 +#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x00000001L +#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x00000000 +#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x00000004L +#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x00000002 +#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x00000008L +#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x00000003 +#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x00000020L +#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x00000005 +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000 +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000 +#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L +#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x00000001 +#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00000200L +#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x00000009 +#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L +#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x00000000 +#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00000100L +#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x00000008 +#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000000fcL +#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002 +#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0000fc00L +#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000a +#define IH_RB_BASE__ADDR_MASK 0xffffffffL +#define IH_RB_BASE__ADDR__SHIFT 0x00000000 +#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000040L +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000006 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L +#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x00000007 +#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003eL +#define IH_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008 +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000009 +#define IH_RB_RPTR__OFFSET_MASK 0x0003fffcL +#define IH_RB_RPTR__OFFSET__SHIFT 0x00000002 +#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000ffL +#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000 +#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL +#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002 +#define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL +#define IH_RB_WPTR__OFFSET__SHIFT 0x00000002 +#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L +#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x00000000 +#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L +#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0x0000000a +#define IH_STATUS__IDLE_MASK 0x00000001L +#define IH_STATUS__IDLE__SHIFT 0x00000000 +#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L +#define IH_STATUS__INPUT_IDLE__SHIFT 0x00000001 +#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L +#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x00000008 +#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L +#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x00000009 +#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L +#define IH_STATUS__MC_WR_IDLE__SHIFT 0x00000006 +#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L +#define IH_STATUS__MC_WR_STALL__SHIFT 0x00000007 +#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L +#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x00000004 +#define IH_STATUS__RB_FULL_MASK 0x00000008L +#define IH_STATUS__RB_FULL__SHIFT 0x00000003 +#define IH_STATUS__RB_IDLE_MASK 0x00000004L +#define IH_STATUS__RB_IDLE__SHIFT 0x00000002 +#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L +#define IH_STATUS__RB_OVERFLOW__SHIFT 0x00000005 +#define KEFUSE0__RESERVED_MASK 0xffffffffL +#define KEFUSE0__RESERVED__SHIFT 0x00000000 +#define KEFUSE1__RESERVED_MASK 0xffffffffL +#define KEFUSE1__RESERVED__SHIFT 0x00000000 +#define KEFUSE2__RESERVED_MASK 0xffffffffL +#define KEFUSE2__RESERVED__SHIFT 0x00000000 +#define KEFUSE3__RESERVED_MASK 0xffffffffL +#define KEFUSE3__RESERVED__SHIFT 0x00000000 +#define KHFS0__RESERVED_MASK 0xffffffffL +#define KHFS0__RESERVED__SHIFT 0x00000000 +#define KHFS1__RESERVED_MASK 0xffffffffL +#define KHFS1__RESERVED__SHIFT 0x00000000 +#define KHFS2__RESERVED_MASK 0xffffffffL +#define KHFS2__RESERVED__SHIFT 0x00000000 +#define KHFS3__RESERVED_MASK 0xffffffffL +#define KHFS3__RESERVED__SHIFT 0x00000000 +#define KSESSION0__RESERVED_MASK 0xffffffffL +#define KSESSION0__RESERVED__SHIFT 0x00000000 +#define KSESSION1__RESERVED_MASK 0xffffffffL +#define KSESSION1__RESERVED__SHIFT 0x00000000 +#define KSESSION2__RESERVED_MASK 0xffffffffL +#define KSESSION2__RESERVED__SHIFT 0x00000000 +#define KSESSION3__RESERVED_MASK 0xffffffffL +#define KSESSION3__RESERVED__SHIFT 0x00000000 +#define KSIG0__RESERVED_MASK 0xffffffffL +#define KSIG0__RESERVED__SHIFT 0x00000000 +#define KSIG1__RESERVED_MASK 0xffffffffL +#define KSIG1__RESERVED__SHIFT 0x00000000 +#define KSIG2__RESERVED_MASK 0xffffffffL +#define KSIG2__RESERVED__SHIFT 0x00000000 +#define KSIG3__RESERVED_MASK 0xffffffffL +#define KSIG3__RESERVED__SHIFT 0x00000000 +#define LX0__RESERVED_MASK 0xffffffffL +#define LX0__RESERVED__SHIFT 0x00000000 +#define LX1__RESERVED_MASK 0xffffffffL +#define LX1__RESERVED__SHIFT 0x00000000 +#define LX2__RESERVED_MASK 0xffffffffL +#define LX2__RESERVED__SHIFT 0x00000000 +#define LX3__RESERVED_MASK 0xffffffffL +#define LX3__RESERVED__SHIFT 0x00000000 +#define RINGOSC_MASK__MASK_MASK 0x0000ffffL +#define RINGOSC_MASK__MASK__SHIFT 0x00000000 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x00000000 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x00000003 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001c0L +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x00000006 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000e00L +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x00000009 +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0x0000000f +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00e00000L +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x00000015 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000ff00L +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000008 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0x000000ffL +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x00000000 +#define SEM_MAILBOX__HOSTPORT_MASK 0x0000ff00L +#define SEM_MAILBOX__HOSTPORT__SHIFT 0x00000008 +#define SEM_MAILBOX__SIDEPORT_MASK 0x000000ffL +#define SEM_MAILBOX__SIDEPORT__SHIFT 0x00000000 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L +#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x00000000 +#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffffL +#define SPU_PORT_STATUS__RESERVED__SHIFT 0x00000000 +#define SRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL +#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000 +#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L +#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010 +#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L +#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000 +#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000ffL +#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x00000000 +#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x00020000L +#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x00000011 +#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x00010000L +#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x00000010 +#define SRBM_CNTL__READ_TIMEOUT_MASK 0x000003ffL +#define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x0000003fL +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x00000000 +#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffffL +#define SRBM_DEBUG_DATA__DATA__SHIFT 0x00000000 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000002L +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000001 +#define SRBM_DEBUG__IGNORE_RDY_MASK 0x00000001L +#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000000 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000100L +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000008 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x00000080L +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x00000007 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x00000040L +#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x00000006 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000004L +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000002 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x00000020L +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x00000005 +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x00000001L +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x00000000 +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000L +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x0000001c +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x08000000L +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x0000001b +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x04000000L +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x0000001a +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x02000000L +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x00000019 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x01000000L +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x00000018 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x00800000L +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x00000017 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x00400000L +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x00000016 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x00200000L +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x00000015 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x00100000L +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x00000014 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x00080000L +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x00000013 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x00040000L +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x00000012 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x00020000L +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x00000011 +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x00010000L +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x00000010 +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x00008000L +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0x0000000f +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x00004000L +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0x0000000e +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x00002000L +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0x0000000d +#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x00001000L +#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0x0000000c +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x00000800L +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0x0000000b +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x00000200L +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x00000009 +#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000L +#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x0000001d +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x00000100L +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x00000008 +#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x00000400L +#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0x0000000a +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000010L +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000004 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000040L +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000006 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000020L +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000005 +#define SRBM_GFX_CNTL__VMID_MASK 0x000000f0L +#define SRBM_GFX_CNTL__VMID__SHIFT 0x00000004 +#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffffL +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffffL +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffffL +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a +#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL +#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x02000000L +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x00000019 +#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x01000000L +#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x00000018 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x04000000L +#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x0000001a +#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x00400000L +#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x00000016 +#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000L +#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x0000001d +#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x00100000L +#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x00000014 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x00000002L +#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x00000001 +#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x00000020L +#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x00000005 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x00000100L +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x00000008 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x00000200L +#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x00000009 +#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x00000400L +#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0x0000000a +#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x00000800L +#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0x0000000b +#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x00800000L +#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x00000017 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x00400000L +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x00000016 +#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x00004000L +#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0x0000000e +#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x00008000L +#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0x0000000f +#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x00200000L +#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x00000015 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x00040000L +#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x00000012 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x01000000L +#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x00000018 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x00020000L +#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x00000011 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x02000000L +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x00000019 +#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x00080000L +#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x00000013 +#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x00000002L +#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x00000001 +#define SRBM_STATUS2__VCE_BUSY_MASK 0x00000080L +#define SRBM_STATUS2__VCE_BUSY__SHIFT 0x00000007 +#define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x00000008L +#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x00000003 +#define SRBM_STATUS2__XDMA_BUSY_MASK 0x00000100L +#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x00000008 +#define SRBM_STATUS2__XSP_BUSY_MASK 0x00000010L +#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x00000004 +#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000L +#define SRBM_STATUS__BIF_BUSY__SHIFT 0x0000001d +#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x00000020L +#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x00000005 +#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x00000040L +#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x00000006 +#define SRBM_STATUS__IH_BUSY_MASK 0x00020000L +#define SRBM_STATUS__IH_BUSY__SHIFT 0x00000011 +#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x00000080L +#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x00000007 +#define SRBM_STATUS__MCB_BUSY_MASK 0x00000200L +#define SRBM_STATUS__MCB_BUSY__SHIFT 0x00000009 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x00000400L +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0x0000000a +#define SRBM_STATUS__MCC_BUSY_MASK 0x00000800L +#define SRBM_STATUS__MCC_BUSY__SHIFT 0x0000000b +#define SRBM_STATUS__MCD_BUSY_MASK 0x00001000L +#define SRBM_STATUS__MCD_BUSY__SHIFT 0x0000000c +#define SRBM_STATUS__SEM_BUSY_MASK 0x00004000L +#define SRBM_STATUS__SEM_BUSY__SHIFT 0x0000000e +#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x00000010L +#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x00000004 +#define SRBM_STATUS__UVD_BUSY_MASK 0x00080000L +#define SRBM_STATUS__UVD_BUSY__SHIFT 0x00000013 +#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x00000002L +#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x00000001 +#define SRBM_STATUS__VMC_BUSY_MASK 0x00000100L +#define SRBM_STATUS__VMC_BUSY__SHIFT 0x00000008 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008 +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000 +#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0x00000f00L +#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x00000008 +#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x00010000L +#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x00000010 +#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0x00000f00L +#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x00000008 +#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x00010000L +#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x00000010 +#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x00080000L +#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x00000013 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000L +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x0000001f +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0x0000ffffL +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x00000000 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000L +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x00000010 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h new file mode 100644 index 000000000000..6b10be61efc3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h @@ -0,0 +1,148 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_6_0_D_H +#define SMU_6_0_D_H + +#define ixLCAC_MC0_CNTL 0x011C +#define ixLCAC_MC0_OVR_SEL 0x011D +#define ixLCAC_MC0_OVR_VAL 0x011E +#define ixLCAC_MC1_CNTL 0x011F +#define ixLCAC_MC1_OVR_SEL 0x0120 +#define ixLCAC_MC1_OVR_VAL 0x0121 +#define ixLCAC_MC2_CNTL 0x0122 +#define ixLCAC_MC2_OVR_SEL 0x0123 +#define ixLCAC_MC2_OVR_VAL 0x0124 +#define ixLCAC_MC3_CNTL 0x0125 +#define ixLCAC_MC3_OVR_SEL 0x0126 +#define ixLCAC_MC3_OVR_VAL 0x0127 +#define ixLCAC_MC4_CNTL 0x0128 +#define ixLCAC_MC4_OVR_SEL 0x0129 +#define ixLCAC_MC4_OVR_VAL 0x012A +#define ixLCAC_MC5_CNTL 0x012B +#define ixLCAC_MC5_OVR_SEL 0x012C +#define ixLCAC_MC5_OVR_VAL 0x012D +#define ixSMC_PC_C 0x80000370 +#define ixTHM_TMON0_DEBUG 0x03F0 +#define ixTHM_TMON0_INT_DATA 0x0380 +#define ixTHM_TMON0_RDIL0_DATA 0x0300 +#define ixTHM_TMON0_RDIL10_DATA 0x030A +#define ixTHM_TMON0_RDIL11_DATA 0x030B +#define ixTHM_TMON0_RDIL12_DATA 0x030C +#define ixTHM_TMON0_RDIL13_DATA 0x030D +#define ixTHM_TMON0_RDIL14_DATA 0x030E +#define ixTHM_TMON0_RDIL15_DATA 0x030F +#define ixTHM_TMON0_RDIL1_DATA 0x0301 +#define ixTHM_TMON0_RDIL2_DATA 0x0302 +#define ixTHM_TMON0_RDIL3_DATA 0x0303 +#define ixTHM_TMON0_RDIL4_DATA 0x0304 +#define ixTHM_TMON0_RDIL5_DATA 0x0305 +#define ixTHM_TMON0_RDIL6_DATA 0x0306 +#define ixTHM_TMON0_RDIL7_DATA 0x0307 +#define ixTHM_TMON0_RDIL8_DATA 0x0308 +#define ixTHM_TMON0_RDIL9_DATA 0x0309 +#define ixTHM_TMON0_RDIR0_DATA 0x0310 +#define ixTHM_TMON0_RDIR10_DATA 0x031A +#define ixTHM_TMON0_RDIR11_DATA 0x031B +#define ixTHM_TMON0_RDIR12_DATA 0x031C +#define ixTHM_TMON0_RDIR13_DATA 0x031D +#define ixTHM_TMON0_RDIR14_DATA 0x031E +#define ixTHM_TMON0_RDIR15_DATA 0x031F +#define ixTHM_TMON0_RDIR1_DATA 0x0311 +#define ixTHM_TMON0_RDIR2_DATA 0x0312 +#define ixTHM_TMON0_RDIR3_DATA 0x0313 +#define ixTHM_TMON0_RDIR4_DATA 0x0314 +#define ixTHM_TMON0_RDIR5_DATA 0x0315 +#define ixTHM_TMON0_RDIR6_DATA 0x0316 +#define ixTHM_TMON0_RDIR7_DATA 0x0317 +#define ixTHM_TMON0_RDIR8_DATA 0x0318 +#define ixTHM_TMON0_RDIR9_DATA 0x0319 +#define ixTHM_TMON1_DEBUG 0x03F1 +#define ixTHM_TMON1_INT_DATA 0x0381 +#define ixTHM_TMON1_RDIL0_DATA 0x0320 +#define ixTHM_TMON1_RDIL10_DATA 0x032A +#define ixTHM_TMON1_RDIL11_DATA 0x032B +#define ixTHM_TMON1_RDIL12_DATA 0x032C +#define ixTHM_TMON1_RDIL13_DATA 0x032D +#define ixTHM_TMON1_RDIL14_DATA 0x032E +#define ixTHM_TMON1_RDIL15_DATA 0x032F +#define ixTHM_TMON1_RDIL1_DATA 0x0321 +#define ixTHM_TMON1_RDIL2_DATA 0x0322 +#define ixTHM_TMON1_RDIL3_DATA 0x0323 +#define ixTHM_TMON1_RDIL4_DATA 0x0324 +#define ixTHM_TMON1_RDIL5_DATA 0x0325 +#define ixTHM_TMON1_RDIL6_DATA 0x0326 +#define ixTHM_TMON1_RDIL7_DATA 0x0327 +#define ixTHM_TMON1_RDIL8_DATA 0x0328 +#define ixTHM_TMON1_RDIL9_DATA 0x0329 +#define ixTHM_TMON1_RDIR0_DATA 0x0330 +#define ixTHM_TMON1_RDIR10_DATA 0x033A +#define ixTHM_TMON1_RDIR11_DATA 0x033B +#define ixTHM_TMON1_RDIR12_DATA 0x033C +#define ixTHM_TMON1_RDIR13_DATA 0x033D +#define ixTHM_TMON1_RDIR14_DATA 0x033E +#define ixTHM_TMON1_RDIR15_DATA 0x033F +#define ixTHM_TMON1_RDIR1_DATA 0x0331 +#define ixTHM_TMON1_RDIR2_DATA 0x0332 +#define ixTHM_TMON1_RDIR3_DATA 0x0333 +#define ixTHM_TMON1_RDIR4_DATA 0x0334 +#define ixTHM_TMON1_RDIR5_DATA 0x0335 +#define ixTHM_TMON1_RDIR6_DATA 0x0336 +#define ixTHM_TMON1_RDIR7_DATA 0x0337 +#define ixTHM_TMON1_RDIR8_DATA 0x0338 +#define ixTHM_TMON1_RDIR9_DATA 0x0339 +#define mmGPIOPAD_A 0x05E7 +#define mmGPIOPAD_EN 0x05E8 +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x05F1 +#define mmGPIOPAD_INT_EN 0x05EE +#define mmGPIOPAD_INT_POLARITY 0x05F0 +#define mmGPIOPAD_INT_STAT 0x05EC +#define mmGPIOPAD_INT_STAT_AK 0x05ED +#define mmGPIOPAD_INT_STAT_EN 0x05EB +#define mmGPIOPAD_INT_TYPE 0x05EF +#define mmGPIOPAD_MASK 0x05E6 +#define mmGPIOPAD_PD_EN 0x05F4 +#define mmGPIOPAD_PINSTRAPS 0x05EA +#define mmGPIOPAD_PU_EN 0x05F3 +#define mmGPIOPAD_RCVR_SEL 0x05F2 +#define mmGPIOPAD_STRENGTH 0x05E5 +#define mmGPIOPAD_SW_INT_STAT 0x05E4 +#define mmGPIOPAD_Y 0x05E9 +#define mmSMC_IND_ACCESS_CNTL 0x008A +#define mmSMC_IND_DATA_0 0x0081 +#define mmSMC_IND_DATA 0x0081 +#define mmSMC_IND_DATA_1 0x0083 +#define mmSMC_IND_DATA_2 0x0085 +#define mmSMC_IND_DATA_3 0x0087 +#define mmSMC_IND_INDEX_0 0x0080 +#define mmSMC_IND_INDEX 0x0080 +#define mmSMC_IND_INDEX_1 0x0082 +#define mmSMC_IND_INDEX_2 0x0084 +#define mmSMC_IND_INDEX_3 0x0086 +#define mmSMC_MESSAGE_0 0x008B +#define mmSMC_MESSAGE_1 0x008D +#define mmSMC_MESSAGE_2 0x008F +#define mmSMC_RESP_0 0x008C +#define mmSMC_RESP_1 0x008E +#define mmSMC_RESP_2 0x0090 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h new file mode 100644 index 000000000000..7d3925b7266e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h @@ -0,0 +1,715 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_6_0_SH_MASK_H +#define SMU_6_0_SH_MASK_H + +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL +#define GPIOPAD_A__GPIO_A__SHIFT 0x00000000 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x00000040L +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x00000006 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x0000001fL +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x00000000 +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffffL +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x00000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x0000001f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffffL +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x00000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x0000001f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x00000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0x0000000a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0x0000000b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0x0000000c +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0x0000000d +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0x0000000e +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0x0000000f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x00000010 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x00000011 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x00000012 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x00000013 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x00000001 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x00000014 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x00000015 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x00000016 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x00000017 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x00000018 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x00000019 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x0000001a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x0000001b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x0000001c +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x00000002 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x00000003 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x00000004 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x00000005 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x00000006 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x00000007 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x00000008 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x00000009 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x0000001f +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffffL +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x00000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x0000001f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffffL +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x00000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x0000001f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffffL +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x00000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x0000001f +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffffL +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x00000000 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffffL +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x00000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x00000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0x0000000a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0x0000000b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0x0000000c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0x0000000d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0x0000000e +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0x0000000f +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x00000010 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x00000011 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x00000012 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x00000013 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x00000001 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x00000014 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x00000015 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x00000016 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x00000017 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x00000018 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x00000019 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x0000001a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x0000001b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x0000001c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x0000001d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x00000002 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x0000001e +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x00000003 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x00000004 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x00000005 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x00000006 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x00000007 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x00000008 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x00000009 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffffL +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x00000000 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffffL +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x00000000 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0x0000000fL +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x00000000 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0x000000f0L +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x00000004 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x00000000 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffffL +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x00000000 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x00000001L +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x00000000 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x00000001L +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x00000000 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x00000001L +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x00000000 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x00000001L +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x00000000 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC4_CNTL__MC4_ENABLE_MASK 0x00000001L +#define LCAC_MC4_CNTL__MC4_ENABLE__SHIFT 0x00000000 +#define LCAC_MC4_CNTL__MC4_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC4_CNTL__MC4_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL__SHIFT 0x00000000 +#define LCAC_MC5_CNTL__MC5_ENABLE_MASK 0x00000001L +#define LCAC_MC5_CNTL__MC5_ENABLE__SHIFT 0x00000000 +#define LCAC_MC5_CNTL__MC5_THRESHOLD_MASK 0x0001fffeL +#define LCAC_MC5_CNTL__MC5_THRESHOLD__SHIFT 0x00000001 +#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL_MASK 0xffffffffL +#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL__SHIFT 0x00000000 +#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL_MASK 0xffffffffL +#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL__SHIFT 0x00000000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x00000001L +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x00000000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x00000100L +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x00000008 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x00010000L +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x00000010 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x01000000L +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x00000018 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffffL +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x00000000 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffffL +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x00000000 +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffffffffL +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x00000000 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffffffffL +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x00000000 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffffffffL +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x00000000 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffffL +#define SMC_PC_C__smc_pc_c__SHIFT 0x00000000 +#define SMC_RESP_0__SMC_RESP_MASK 0xffffffffL +#define SMC_RESP_0__SMC_RESP__SHIFT 0x00000000 +#define SMC_RESP_1__SMC_RESP_MASK 0xffffffffL +#define SMC_RESP_1__SMC_RESP__SHIFT 0x00000000 +#define SMC_RESP_2__SMC_RESP_MASK 0xffffffffL +#define SMC_RESP_2__SMC_RESP__SHIFT 0x00000000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0x000ff000L +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0x0000000c +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x00000010L +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x00000004 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x00000008L +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x00000003 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x00000002L +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x00000001 +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000L +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x0000001c +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x00000000 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0x00000c00L +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0x0000000a +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x00000004L +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x00000002 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000L +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x0000001d +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0x0f000000L +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x00000018 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000L +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x0000001c +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001fL +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x00000000 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000ffe0L +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x00000005 +#define THM_TMON0_INT_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_INT_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_INT_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_INT_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x00000000 +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007ffL +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001fL +#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x00000000 +#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000ffe0L +#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x00000005 +#define THM_TMON1_INT_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_INT_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_INT_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_INT_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_INT_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x00000000 +#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00fff000L +#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0x0000000c +#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L +#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0x0000000b +#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007ffL +#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h index 3014d4a58c43..a9ef1562f43b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h @@ -176,6 +176,8 @@ #define mmSMU1_SMU_SMC_IND_DATA 0x83 #define mmSMU2_SMU_SMC_IND_DATA 0x85 #define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_11 0x1AC +#define mmSMC_IND_DATA_11 0x1AD #define ixRCU_UC_EVENTS 0xc0000004 #define ixRCU_MISC_CTRL 0xc0000010 #define ixCC_RCU_FUSES 0xc00c0000 diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h index 933917479985..22dd4c2b7290 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h @@ -87,6 +87,8 @@ #define mmSMC_IND_DATA_6 0x8d #define mmSMC_IND_INDEX_7 0x8e #define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_INDEX_11 0x1AC +#define mmSMC_IND_DATA_11 0x1AD #define mmSMC_IND_ACCESS_CNTL 0x92 #define mmSMC_MESSAGE_0 0x94 #define mmSMC_RESP_0 0x95 diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h index 44b1855cb8df..eca2b851f25f 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h @@ -90,6 +90,8 @@ #define mmSMC_IND_DATA_6 0x8d #define mmSMC_IND_INDEX_7 0x8e #define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_INDEX_11 0x1AC +#define mmSMC_IND_DATA_11 0x1AD #define mmSMC_IND_ACCESS_CNTL 0x92 #define mmSMC_MESSAGE_0 0x94 #define mmSMC_RESP_0 0x95 diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h new file mode 100644 index 000000000000..5c0e3f3332e5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_d.h @@ -0,0 +1,96 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_4_0_D_H +#define UVD_4_0_D_H + +#define ixUVD_CGC_CTRL2 0x00C1 +#define ixUVD_CGC_MEM_CTRL 0x00C0 +#define ixUVD_LMI_ADDR_EXT2 0x00AB +#define ixUVD_LMI_CACHE_CTRL 0x009B +#define ixUVD_LMI_SWAP_CNTL2 0x00AA +#define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048 +#define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114 +#define ixUVD_MIF_REF_ADDR_CONFIG 0x004C +#define mmUVD_CGC_CTRL 0x3D2C +#define mmUVD_CGC_GATE 0x3D2A +#define mmUVD_CGC_STATUS 0x3D2B +#define mmUVD_CGC_UDEC_STATUS 0x3D2D +#define mmUVD_CONTEXT_ID 0x3DBD +#define mmUVD_CTX_DATA 0x3D29 +#define mmUVD_CTX_INDEX 0x3D28 +#define mmUVD_ENGINE_CNTL 0x3BC6 +#define mmUVD_GPCOM_VCPU_CMD 0x3BC3 +#define mmUVD_GPCOM_VCPU_DATA0 0x3BC4 +#define mmUVD_GPCOM_VCPU_DATA1 0x3BC5 +#define mmUVD_GP_SCRATCH4 0x3D38 +#define mmUVD_LMI_ADDR_EXT 0x3D65 +#define mmUVD_LMI_CTRL 0x3D66 +#define mmUVD_LMI_CTRL2 0x3D3D +#define mmUVD_LMI_EXT40_ADDR 0x3D26 +#define mmUVD_LMI_STATUS 0x3D67 +#define mmUVD_LMI_SWAP_CNTL 0x3D6D +#define mmUVD_MASTINT_EN 0x3D40 +#define mmUVD_MPC_CNTL 0x3D77 +#define mmUVD_MPC_SET_ALU 0x3D7E +#define mmUVD_MPC_SET_MUX 0x3D7D +#define mmUVD_MPC_SET_MUXA0 0x3D79 +#define mmUVD_MPC_SET_MUXA1 0x3D7A +#define mmUVD_MPC_SET_MUXB0 0x3D7B +#define mmUVD_MPC_SET_MUXB1 0x3D7C +#define mmUVD_MP_SWAP_CNTL 0x3D6F +#define mmUVD_NO_OP 0x3BFF +#define mmUVD_PGFSM_CONFIG 0x38F8 +#define mmUVD_PGFSM_READ_TILE1 0x38FA +#define mmUVD_PGFSM_READ_TILE2 0x38FB +#define mmUVD_POWER_STATUS 0x38FC +#define mmUVD_RBC_IB_BASE 0x3DA1 +#define mmUVD_RBC_IB_SIZE 0x3DA2 +#define mmUVD_RBC_IB_SIZE_UPDATE 0x3DF1 +#define mmUVD_RBC_RB_BASE 0x3DA3 +#define mmUVD_RBC_RB_CNTL 0x3DA9 +#define mmUVD_RBC_RB_RPTR 0x3DA4 +#define mmUVD_RBC_RB_RPTR_ADDR 0x3DAA +#define mmUVD_RBC_RB_WPTR 0x3DA5 +#define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6 +#define mmUVD_SEMA_ADDR_HIGH 0x3BC1 +#define mmUVD_SEMA_ADDR_LOW 0x3BC0 +#define mmUVD_SEMA_CMD 0x3BC2 +#define mmUVD_SEMA_CNTL 0x3D00 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3DB3 +#define mmUVD_SEMA_TIMEOUT_STATUS 0x3DB0 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3DB2 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3DB1 +#define mmUVD_SOFT_RESET 0x3DA0 +#define mmUVD_STATUS 0x3DAF +#define mmUVD_UDEC_ADDR_CONFIG 0x3BD3 +#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3BD4 +#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3BD5 +#define mmUVD_VCPU_CACHE_OFFSET0 0x3D36 +#define mmUVD_VCPU_CACHE_OFFSET1 0x3D38 +#define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A +#define mmUVD_VCPU_CACHE_SIZE0 0x3D37 +#define mmUVD_VCPU_CACHE_SIZE1 0x3D39 +#define mmUVD_VCPU_CACHE_SIZE2 0x3D3B +#define mmUVD_VCPU_CNTL 0x3D98 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h new file mode 100644 index 000000000000..8ee3149df5b7 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h @@ -0,0 +1,795 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_4_0_SH_MASK_H +#define UVD_4_0_SH_MASK_H + +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001 +#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL +#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002 +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006 +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000 +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x00000017 +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x0000001a +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x00000015 +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x00000016 +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x0000001b +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x00000019 +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x00000012 +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x00000018 +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x00000014 +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x00000013 +#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L +#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x0000001e +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x00000010 +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0x0000000c +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0x0000000e +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0x0000000d +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x00000011 +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0x0000000f +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0x0000000b +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x0000001d +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x0000001c +#define UVD_CGC_GATE__IDCT_MASK 0x00000080L +#define UVD_CGC_GATE__IDCT__SHIFT 0x00000007 +#define UVD_CGC_GATE__LBSI_MASK 0x00000400L +#define UVD_CGC_GATE__LBSI__SHIFT 0x0000000a +#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x00000005 +#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x00000006 +#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L +#define UVD_CGC_GATE__LRBBM__SHIFT 0x0000000b +#define UVD_CGC_GATE__MPC_MASK 0x00000200L +#define UVD_CGC_GATE__MPC__SHIFT 0x00000009 +#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L +#define UVD_CGC_GATE__MPEG2__SHIFT 0x00000002 +#define UVD_CGC_GATE__MPRD_MASK 0x00000100L +#define UVD_CGC_GATE__MPRD__SHIFT 0x00000008 +#define UVD_CGC_GATE__RBC_MASK 0x00000010L +#define UVD_CGC_GATE__RBC__SHIFT 0x00000004 +#define UVD_CGC_GATE__REGS_MASK 0x00000008L +#define UVD_CGC_GATE__REGS__SHIFT 0x00000003 +#define UVD_CGC_GATE__SCPU_MASK 0x00080000L +#define UVD_CGC_GATE__SCPU__SHIFT 0x00000013 +#define UVD_CGC_GATE__SYS_MASK 0x00000001L +#define UVD_CGC_GATE__SYS__SHIFT 0x00000000 +#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0x0000000d +#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0x0000000f +#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0x0000000e +#define UVD_CGC_GATE__UDEC_MASK 0x00000002L +#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x00000010 +#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0x0000000c +#define UVD_CGC_GATE__UDEC__SHIFT 0x00000001 +#define UVD_CGC_GATE__VCPU_MASK 0x00040000L +#define UVD_CGC_GATE__VCPU__SHIFT 0x00000012 +#define UVD_CGC_GATE__WCB_MASK 0x00020000L +#define UVD_CGC_GATE__WCB__SHIFT 0x00000011 +#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L +#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0x0000000d +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x00000000 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00f00000L +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x00000014 +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000f0000L +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x00000010 +#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L +#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0x0000000c +#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L +#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x00000001 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x00000002 +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x00000800L +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0x0000000b +#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L +#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x00000009 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x00000005 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x00000007 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x00000006 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x00000008 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x00000004 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0x0000000a +#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L +#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x00000003 +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0x0000000e +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0x0000000f +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x00000015 +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x00000016 +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0x0000000c +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0x0000000d +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x00000017 +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x00000014 +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x00000013 +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x00000007 +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x00000006 +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x00000008 +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x00000011 +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x00000010 +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x00000012 +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0x0000000b +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x00000009 +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0x0000000a +#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x08000000L +#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x0000001b +#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000L +#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x0000001c +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x00000001 +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x00000000 +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x00000002 +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x00000004 +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x00000003 +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x00000005 +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x00000019 +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x0000001a +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x00000018 +#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L +#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x00000004 +#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L +#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x00000003 +#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L +#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x00000005 +#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L +#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0x0000000a +#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L +#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x00000009 +#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L +#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0x0000000b +#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L +#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x00000007 +#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L +#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x00000006 +#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L +#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x00000008 +#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L +#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0x0000000d +#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L +#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0x0000000c +#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L +#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0x0000000e +#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L +#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x00000001 +#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L +#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x00000000 +#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L +#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x00000002 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffffL +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x00000000 +#define UVD_CTX_DATA__DATA_MASK 0xffffffffL +#define UVD_CTX_DATA__DATA__SHIFT 0x00000000 +#define UVD_CTX_INDEX__INDEX_MASK 0x000001ffL +#define UVD_CTX_INDEX__INDEX__SHIFT 0x00000000 +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x00000001 +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x00000000 +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffeL +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x00000000 +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x00000001 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x0000001f +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffffL +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x00000000 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffffL +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x00000000 +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0x0000000fL +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x00000000 +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0x00000f00L +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x00000008 +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0x0000f000L +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0x0000000c +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0x000000f0L +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x00000004 +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0x000000f0L +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x00000004 +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0x00000f00L +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x00000008 +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0x00f00000L +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x00000014 +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0x000f0000L +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x00000010 +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0x0000000fL +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x00000000 +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0x0f000000L +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x00000018 +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000L +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x0000001c +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0x0000f000L +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0x0000000c +#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x00000004L +#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x00000002 +#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x00000008L +#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x00000003 +#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x00000001L +#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x00000000 +#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x00000002L +#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x00000001 +#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000010L +#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000004 +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000020L +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x00000005 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x00000002 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x00000007 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x00000003 +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x00000070L +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x00000004 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x00000009 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0x0000000b +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x00000000 +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0x0000000f +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x00000001 +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008 +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0x0000000d +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0x0000000e +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x0000000b +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x00000016 +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0x0000000e +#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000f8000L +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0x0000000f +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0x0000000d +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x00000017 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x00000018 +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x00000014 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x00000019 +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0x0000000c +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x0000001a +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x00000009 +#define UVD_LMI_CTRL__RFU_MASK 0xf8000000L +#define UVD_LMI_CTRL__RFU_MASK 0xfc000000L +#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001a +#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001b +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x00000008 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000ffL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x00000000 +#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0x000000ffL +#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x00000000 +#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x001f0000L +#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x00000010 +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000L +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x0000001f +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0x0000000c +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0x0000000d +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x00000007 +#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L +#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L +#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x00000008 +#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x00000000 +#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L +#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0x0000000b +#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x00000009 +#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x00000004 +#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L +#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0x0000000a +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x00000006 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x00000005 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x00000003 +#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x00000002 +#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x00000001 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x00000000 +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000cL +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x00000002 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000c00L +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0x0000000a +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000c0000L +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x00000012 +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000c000L +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0x0000000e +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x00000010 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x00000018 +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000cL +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x00000002 +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0x0000000c +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000L +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x0000001e +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00c00000L +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x00000016 +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x00000000 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x00000004 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0c000000L +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x0000001a +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x0000001c +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000c0L +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x00000006 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000008 +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007ffff0L +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x00000004 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x00000000 +#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x00000002 +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x00000001 +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L +#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x00000010 +#define UVD_MPC_CNTL__DBG_MUX_MASK 0x00000700L +#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x00000008 +#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L +#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x00000006 +#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L +#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x00000003 +#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L +#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x00000012 +#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L +#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x00000000 +#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000ff0L +#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x00000004 +#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003fL +#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x00000000 +#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000fc0L +#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006 +#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003f000L +#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c +#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00fc0000L +#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012 +#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000L +#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018 +#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003fL +#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x00000000 +#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000fc0L +#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x00000006 +#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003f000L +#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c +#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003fL +#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x00000000 +#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000fc0L +#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x00000006 +#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003f000L +#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c +#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00fc0000L +#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012 +#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000L +#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018 +#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003fL +#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x00000000 +#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000fc0L +#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x00000006 +#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003f000L +#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0x0000000c +#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L +#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000 +#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L +#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003 +#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001c0L +#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006 +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x00000000 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x00000014 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00c00000L +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x00000016 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x00000018 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0c000000L +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x0000001a +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x0000001c +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000L +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x0000001e +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000cL +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x00000002 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x00000004 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000c0L +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x00000006 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x00000008 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000c00L +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0x0000000a +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0x0000000c +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000c000L +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0x0000000e +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x00000010 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000c0000L +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x00000012 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0x000000ffL +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x00000000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x00000400L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0x0000000a +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x00000800L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0x0000000b +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x00000100L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x00000008 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x00000200L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x00000009 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x00002000L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0x0000000d +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x0000001c +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x00001000L +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0x0000000c +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0x00ffffffL +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x00000000 +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0x00ffffffL +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x00000000 +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x00000000 +#define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0L +#define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x00000006 +#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007ffff0L +#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x00000004 +#define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0L +#define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x00000006 +#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001f00L +#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001fL +#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L +#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x00000010 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x00000018 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x0000001c +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x00000014 +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffffL +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000000 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007ffff0L +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x00000004 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007ffff0L +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x00000004 +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0x000fffffL +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x00000000 +#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0x000fffffL +#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x00000000 +#define UVD_SEMA_CMD__MODE_MASK 0x00000040L +#define UVD_SEMA_CMD__MODE__SHIFT 0x00000006 +#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000fL +#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x00000000 +#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L +#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x00000007 +#define UVD_SEMA_CMD__VMID_MASK 0x00000f00L +#define UVD_SEMA_CMD__VMID__SHIFT 0x00000008 +#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L +#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x00000004 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x00000001 +#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L +#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x00000000 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001ffffeL +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x00000001 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x00000000 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000002 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x00000003 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x00000001 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x00000000 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001ffffeL +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x00000001 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x00000000 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x00000018 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001ffffeL +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x00000001 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x00000000 +#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L +#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x00000005 +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x00000006 +#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x00000200L +#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x00000009 +#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L +#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0x0000000c +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0x0000000a +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x00000001 +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x00000010 +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x00000002 +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x0000000d +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x0000000f +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x00000008 +#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L +#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0x0000000b +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x00000000 +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0x0000000e +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x00000007 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x00000004 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x00000003 +#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L +#define UVD_STATUS__RBC_BUSY__SHIFT 0x00000000 +#define UVD_STATUS__VCPU_REPORT_MASK 0x000000feL +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01ffffffL +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01ffffffL +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x01ffffffL +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001fffffL +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001fffffL +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x00000000 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001fffffL +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x00000000 +#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L +#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x00000008 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000010L +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x00000004 +#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000L +#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x0000001c +#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x00020000L +#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x00000011 +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x00000009 +#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000e000L +#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0x0000000d +#define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000L +#define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x0000001d +#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000fL +#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x00000000 +#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L +#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x00000010 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L +#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x00000005 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L +#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x00000006 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0ff00000L +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x00000014 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000007 +#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L +#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x00000012 +#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L +#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0x0000000a +#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L +#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0x0000000b +#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000L +#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x0000001e + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h new file mode 100644 index 000000000000..2176548e9203 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h @@ -0,0 +1,64 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_1_0_D_H +#define VCE_1_0_D_H + +#define mmVCE_CLOCK_GATING_A 0x80BE +#define mmVCE_CLOCK_GATING_B 0x80BF +#define mmVCE_LMI_CACHE_CTRL 0x83BD +#define mmVCE_LMI_CTRL 0x83A6 +#define mmVCE_LMI_CTRL2 0x839D +#define mmVCE_LMI_MISC_CTRL 0x83B5 +#define mmVCE_LMI_STATUS 0x83A7 +#define mmVCE_LMI_SWAP_CNTL 0x83AD +#define mmVCE_LMI_SWAP_CNTL1 0x83AE +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8397 +#define mmVCE_LMI_VM_CTRL 0x83A8 +#define mmVCE_RB_ARB_CTRL 0x809F +#define mmVCE_RB_BASE_HI 0x8061 +#define mmVCE_RB_BASE_HI2 0x805C +#define mmVCE_RB_BASE_LO 0x8060 +#define mmVCE_RB_BASE_LO2 0x805B +#define mmVCE_RB_RPTR 0x8063 +#define mmVCE_RB_RPTR2 0x805E +#define mmVCE_RB_SIZE 0x8062 +#define mmVCE_RB_SIZE2 0x805D +#define mmVCE_RB_WPTR 0x8064 +#define mmVCE_RB_WPTR2 0x805F +#define mmVCE_SOFT_RESET 0x8048 +#define mmVCE_STATUS 0x8001 +#define mmVCE_SYS_INT_ACK 0x8341 +#define mmVCE_SYS_INT_EN 0x8340 +#define mmVCE_SYS_INT_STATUS 0x8341 +#define mmVCE_UENC_CLOCK_GATING 0x816F +#define mmVCE_UENC_DMA_DCLK_CTRL 0x8250 +#define mmVCE_UENC_REG_CLOCK_GATING 0x8170 +#define mmVCE_VCPU_CACHE_OFFSET0 0x8009 +#define mmVCE_VCPU_CACHE_OFFSET1 0x800B +#define mmVCE_VCPU_CACHE_OFFSET2 0x800D +#define mmVCE_VCPU_CACHE_SIZE0 0x800A +#define mmVCE_VCPU_CACHE_SIZE1 0x800C +#define mmVCE_VCPU_CACHE_SIZE2 0x800E +#define mmVCE_VCPU_CNTL 0x8005 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h new file mode 100644 index 000000000000..ea5b26b11cb1 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h @@ -0,0 +1,99 @@ +/* + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_1_0_SH_MASK_H +#define VCE_1_0_SH_MASK_H + +#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L +#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000000 +#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L +#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008 +#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L +#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015 +#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003ffcL +#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x00000002 +#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L +#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x00000000 +#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L +#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000000 +#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003ffcL +#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x00000002 +#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffffL +#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x00000000 +#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffffL +#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x00000000 +#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffffL +#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x00000000 +#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0L +#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x00000006 +#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0L +#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x00000006 +#define VCE_RB_RPTR2__RB_RPTR_MASK 0x007ffff0L +#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x00000004 +#define VCE_RB_RPTR__RB_RPTR_MASK 0x007ffff0L +#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x00000004 +#define VCE_RB_SIZE2__RB_SIZE_MASK 0x007ffff0L +#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x00000004 +#define VCE_RB_SIZE__RB_SIZE_MASK 0x007ffff0L +#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x00000004 +#define VCE_RB_WPTR2__RB_WPTR_MASK 0x007ffff0L +#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x00000004 +#define VCE_RB_WPTR__RB_WPTR_MASK 0x007ffff0L +#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x00000004 +#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L +#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x00000000 +#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L +#define VCE_STATUS__JOB_BUSY__SHIFT 0x00000000 +#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L +#define VCE_STATUS__UENC_BUSY__SHIFT 0x00000008 +#define VCE_STATUS__VCPU_REPORT_MASK 0x000000feL +#define VCE_STATUS__VCPU_REPORT__SHIFT 0x00000001 +#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L +#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x00000003 +#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L +#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x00000003 +#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L +#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x00000003 +#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x00000002L +#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x00000001 +#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x00000004L +#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x00000002 +#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x00000001L +#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0fffffffL +#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0fffffffL +#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0fffffffL +#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00ffffffL +#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00ffffffL +#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x00000000 +#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00ffffffL +#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x00000000 +#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L +#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x00000000 +#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L +#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000012 + +#endif diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h index df7c18b6a02a..e4a1697ec1d3 100755..100644 --- a/drivers/gpu/drm/amd/include/cgs_common.h +++ b/drivers/gpu/drm/amd/include/cgs_common.h @@ -106,6 +106,7 @@ enum cgs_ucode_id { CGS_UCODE_ID_CP_MEC_JT2, CGS_UCODE_ID_GMCON_RENG, CGS_UCODE_ID_RLC_G, + CGS_UCODE_ID_STORAGE, CGS_UCODE_ID_MAXIMUM, }; @@ -619,6 +620,8 @@ typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device, typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, struct cgs_system_info *sys_info); +typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device); + struct cgs_ops { /* memory management calls (similar to KFD interface) */ cgs_gpu_mem_info_t gpu_mem_info; @@ -670,6 +673,7 @@ struct cgs_ops { cgs_call_acpi_method call_acpi_method; /* get system info */ cgs_query_system_info query_system_info; + cgs_is_virtualization_enabled_t is_virtualization_enabled; }; struct cgs_os_ops; /* To be define in OS-specific CGS header */ @@ -773,4 +777,6 @@ struct cgs_device CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ resource_base) +#define cgs_is_virtualization_enabled(cgs_device) \ + CGS_CALL(is_virtualization_enabled, cgs_device) #endif /* _CGS_COMMON_H */ diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 7174f7a68266..c81cf1412728 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -41,7 +41,7 @@ #define PP_CHECK_HW(hwmgr) \ do { \ if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \ - return -EINVAL; \ + return 0; \ } while (0) static int pp_early_init(void *handle) @@ -115,6 +115,7 @@ static int pp_hw_init(void *handle) struct pp_instance *pp_handle; struct pp_smumgr *smumgr; struct pp_eventmgr *eventmgr; + struct pp_hwmgr *hwmgr; int ret = 0; if (handle == NULL) @@ -122,6 +123,7 @@ static int pp_hw_init(void *handle) pp_handle = (struct pp_instance *)handle; smumgr = pp_handle->smu_mgr; + hwmgr = pp_handle->hwmgr; if (smumgr == NULL || smumgr->smumgr_funcs == NULL || smumgr->smumgr_funcs->smu_init == NULL || @@ -141,9 +143,11 @@ static int pp_hw_init(void *handle) return ret; } - hw_init_power_state_table(pp_handle->hwmgr); - eventmgr = pp_handle->eventmgr; + PP_CHECK_HW(hwmgr); + + hw_init_power_state_table(hwmgr); + eventmgr = pp_handle->eventmgr; if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) return -EINVAL; @@ -243,7 +247,9 @@ static int pp_suspend(void *handle) pp_handle = (struct pp_instance *)handle; eventmgr = pp_handle->eventmgr; - pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); + + if (eventmgr != NULL) + pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); return 0; } @@ -273,7 +279,8 @@ static int pp_resume(void *handle) } eventmgr = pp_handle->eventmgr; - pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); + if (eventmgr != NULL) + pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); return 0; } @@ -340,8 +347,7 @@ static enum amd_dpm_forced_level pp_dpm_get_performance_level( hwmgr = ((struct pp_instance *)handle)->hwmgr; - if (hwmgr == NULL) - return -EINVAL; + PP_CHECK_HW(hwmgr); return (((struct pp_instance *)handle)->hwmgr->dpm_level); } @@ -436,7 +442,8 @@ static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) } } -int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output) +static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, + void *input, void *output) { int ret = 0; struct pp_instance *pp_handle; @@ -447,6 +454,9 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, if (pp_handle == NULL) return -EINVAL; + if (pp_handle->eventmgr == NULL) + return 0; + switch (event_id) { case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); @@ -475,7 +485,7 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, return ret; } -enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) +static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) { struct pp_hwmgr *hwmgr; struct pp_power_state *state; @@ -581,6 +591,23 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed) return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed); } +static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) +{ + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) + return -EINVAL; + + return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); +} + static int pp_dpm_get_temperature(void *handle) { struct pp_hwmgr *hwmgr; @@ -820,6 +847,21 @@ static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value) return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value); } +static struct amd_vce_state* +pp_dpm_get_vce_clock_state(void *handle, unsigned idx) +{ + struct pp_hwmgr *hwmgr; + + if (handle) { + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr && idx < hwmgr->num_vce_state_tables) + return &hwmgr->vce_states[idx]; + } + + return NULL; +} + const struct amd_powerplay_funcs pp_dpm_funcs = { .get_temperature = pp_dpm_get_temperature, .load_firmware = pp_dpm_load_fw, @@ -836,6 +878,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = { .get_fan_control_mode = pp_dpm_get_fan_control_mode, .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, + .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, .get_pp_num_states = pp_dpm_get_pp_num_states, .get_pp_table = pp_dpm_get_pp_table, .set_pp_table = pp_dpm_set_pp_table, @@ -846,6 +889,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = { .get_mclk_od = pp_dpm_get_mclk_od, .set_mclk_od = pp_dpm_set_mclk_od, .read_sensor = pp_dpm_read_sensor, + .get_vce_clock_state = pp_dpm_get_vce_clock_state, }; static int amd_pp_instance_init(struct amd_pp_init *pp_init, @@ -864,6 +908,13 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init, if (ret) goto fail_smum; + + amd_pp->pp_handle = handle; + + if ((amdgpu_dpm == 0) + || cgs_is_virtualization_enabled(pp_init->device)) + return 0; + ret = hwmgr_init(pp_init, handle); if (ret) goto fail_hwmgr; @@ -872,7 +923,6 @@ static int amd_pp_instance_init(struct amd_pp_init *pp_init, if (ret) goto fail_eventmgr; - amd_pp->pp_handle = handle; return 0; fail_eventmgr: @@ -891,12 +941,13 @@ static int amd_pp_instance_fini(void *handle) if (instance == NULL) return -EINVAL; - eventmgr_fini(instance->eventmgr); - - hwmgr_fini(instance->hwmgr); + if ((amdgpu_dpm != 0) + && !cgs_is_virtualization_enabled(instance->smu_mgr->device)) { + eventmgr_fini(instance->eventmgr); + hwmgr_fini(instance->hwmgr); + } smum_fini(instance->smu_mgr); - kfree(handle); return 0; } @@ -953,6 +1004,10 @@ int amd_powerplay_reset(void *handle) if (ret) return ret; + if ((amdgpu_dpm == 0) + || cgs_is_virtualization_enabled(instance->smu_mgr->device)) + return 0; + hw_init_power_state_table(instance->hwmgr); if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) @@ -976,6 +1031,8 @@ int amd_powerplay_display_configuration_change(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + phm_store_dal_configuration_data(hwmgr, display_config); return 0; @@ -993,6 +1050,8 @@ int amd_powerplay_get_display_power_level(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + return phm_get_dal_power_level(hwmgr, output); } @@ -1010,6 +1069,8 @@ int amd_powerplay_get_current_clocks(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + phm_get_dal_power_level(hwmgr, &simple_clocks); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { @@ -1054,6 +1115,8 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + result = phm_get_clock_by_type(hwmgr, type, clocks); return result; @@ -1072,6 +1135,8 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle, hwmgr = ((struct pp_instance *)handle)->hwmgr; + PP_CHECK_HW(hwmgr); + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) result = phm_get_max_high_clocks(hwmgr, clocks); diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c index b6f45fd01fa6..ec36c0e28388 100644 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c @@ -154,7 +154,7 @@ int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_ int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) { - /* TODO */ + phm_disable_clock_power_gatings(eventmgr->hwmgr); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c index 2028980f1ed4..b0c63c5f54c9 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c @@ -169,7 +169,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) if (bgate) { cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_CG_STATE_GATE); cgs_set_powergating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, AMD_PG_STATE_GATE); @@ -182,7 +182,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) AMD_CG_STATE_UNGATE); cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_PG_STATE_GATE); + AMD_PG_STATE_UNGATE); cz_dpm_update_uvd_dpm(hwmgr, false); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c index 960424913496..4b14f259a147 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c @@ -66,7 +66,7 @@ static const struct cz_power_state *cast_const_PhwCzPowerState( return (struct cz_power_state *)hw_ps; } -uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr, +static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr, uint32_t clock, uint32_t msg) { int i = 0; @@ -1017,7 +1017,7 @@ static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input, return 0; } -int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input, +static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); @@ -1225,7 +1225,7 @@ static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) return 0; } -int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) +static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); @@ -1239,7 +1239,7 @@ int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) return 0; } -int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) +static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); struct phm_clock_voltage_dependency_table *table = @@ -1277,7 +1277,7 @@ int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) return 0; } -int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) +static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); @@ -1533,7 +1533,7 @@ static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, return result; } -int cz_get_power_state_size(struct pp_hwmgr *hwmgr) +static int cz_get_power_state_size(struct pp_hwmgr *hwmgr) { return sizeof(struct cz_power_state); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c index a6abe81bc843..71822ae73a12 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c @@ -35,7 +35,7 @@ static int phm_run_table(struct pp_hwmgr *hwmgr, phm_table_function *function; if (rt_table->function_list == NULL) { - printk(KERN_INFO "[ powerplay ] this function not implement!\n"); + pr_debug("[ powerplay ] this function not implement!\n"); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c index 14f8c1f4da3d..c355a0f51663 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c @@ -209,6 +209,19 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr) return 0; } +int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr) +{ + PHM_FUNC_CHECK(hwmgr); + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TablelessHardwareInterface)) { + if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) + return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); + } + return 0; +} + + int phm_display_configuration_changed(struct pp_hwmgr *hwmgr) { PHM_FUNC_CHECK(hwmgr); @@ -272,7 +285,7 @@ bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hw PHM_FUNC_CHECK(hwmgr); if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL) - return -EINVAL; + return false; return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 2ba7937d2545..dc6700aee18f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -80,20 +80,17 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) switch (hwmgr->chip_id) { case CHIP_TOPAZ: topaz_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK | + hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | PP_ENABLE_GFX_CG_THRU_SMU); hwmgr->pp_table_version = PP_TABLE_V0; break; case CHIP_TONGA: tonga_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK); + hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; break; case CHIP_FIJI: fiji_set_asic_special_caps(hwmgr); - hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK | - PP_VBI_TIME_SUPPORT_MASK | + hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | PP_ENABLE_GFX_CG_THRU_SMU); break; case CHIP_POLARIS11: @@ -685,20 +682,24 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) { - if (amdgpu_sclk_deep_sleep_en) + if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); else phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); - if (amdgpu_powercontainment) + if (amdgpu_pp_feature_mask & PP_POWER_CONTAINMENT_MASK) { phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment); - else + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC); + } else { phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment); - + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_CAC); + } hwmgr->feature_mask = amdgpu_pp_feature_mask; return 0; @@ -710,8 +711,10 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t vol; int ret = 0; - if (hwmgr->chip_id < CHIP_POLARIS10) { - atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); + if (hwmgr->chip_id < CHIP_TONGA) { + ret = atomctrl_get_voltage_evv(hwmgr, id, voltage); + } else if (hwmgr->chip_id < CHIP_POLARIS10) { + ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); if (*voltage >= 2000 || *voltage == 0) *voltage = 1150; } else { @@ -734,9 +737,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_TCPRamping); phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot); phm_cap_set(hwmgr->platform_descriptor.platformCaps, @@ -765,8 +765,6 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); return 0; } @@ -789,9 +787,6 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - return 0; } @@ -808,8 +803,6 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TablelessHardwareInterface); phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC); - phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c index 1944d289f846..f5e8fda964f7 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c @@ -25,6 +25,7 @@ #include "linux/delay.h" #include "hwmgr.h" #include "amd_acpi.h" +#include "pp_acpi.h" bool acpi_atcs_functions_supported(void *device, uint32_t index) { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c index 4477c55a58e3..c45bd2560468 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c @@ -131,7 +131,7 @@ static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) /** * Private Function to get the PowerPlay Table Address. */ -const void *get_powerplay_table(struct pp_hwmgr *hwmgr) +static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) { int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); @@ -1049,7 +1049,7 @@ static int check_powerplay_tables( return 0; } -int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr) +static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr) { int result = 0; const ATOM_Tonga_POWERPLAYTABLE *powerplay_table; @@ -1100,7 +1100,7 @@ int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr) return result; } -int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr) +static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr) { struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -1214,7 +1214,7 @@ static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr) } static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i, - struct pp_vce_state *vce_state, void **clock_info, uint32_t *flag) + struct amd_vce_state *vce_state, void **clock_info, uint32_t *flag) { const ATOM_Tonga_VCE_State_Record *vce_state_record; ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record; @@ -1318,7 +1318,7 @@ int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr, hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr); - if ((i != 0) && (i <= PP_MAX_VCE_LEVELS)) { + if ((i != 0) && (i <= AMD_MAX_VCE_LEVELS)) { for (j = 0; j < i; j++) ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c index ccf7ebeaf892..a4e9cf429e62 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c @@ -1507,7 +1507,7 @@ static int init_phase_shedding_table(struct pp_hwmgr *hwmgr, return 0; } -int get_number_of_vce_state_table_entries( +static int get_number_of_vce_state_table_entries( struct pp_hwmgr *hwmgr) { const ATOM_PPLIB_POWERPLAYTABLE *table = @@ -1521,9 +1521,9 @@ int get_number_of_vce_state_table_entries( return 0; } -int get_vce_state_table_entry(struct pp_hwmgr *hwmgr, +static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr, unsigned long i, - struct pp_vce_state *vce_state, + struct amd_vce_state *vce_state, void **clock_info, unsigned long *flag) { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c index 6eb6db199250..a1fc4fcac1e0 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c @@ -75,7 +75,7 @@ int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr) return 0; } -int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) +static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) { if (phm_cf_want_uvd_power_gating(hwmgr)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -91,7 +91,7 @@ int smu7_powerup_uvd(struct pp_hwmgr *hwmgr) return 0; } -int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) +static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) { if (phm_cf_want_vce_power_gating(hwmgr)) return smum_send_msg_to_smc(hwmgr->smumgr, @@ -99,7 +99,7 @@ int smu7_powerdown_vce(struct pp_hwmgr *hwmgr) return 0; } -int smu7_powerup_vce(struct pp_hwmgr *hwmgr) +static int smu7_powerup_vce(struct pp_hwmgr *hwmgr) { if (phm_cf_want_vce_power_gating(hwmgr)) return smum_send_msg_to_smc(hwmgr->smumgr, @@ -107,7 +107,7 @@ int smu7_powerup_vce(struct pp_hwmgr *hwmgr) return 0; } -int smu7_powerdown_samu(struct pp_hwmgr *hwmgr) +static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SamuPowerGating)) @@ -116,7 +116,7 @@ int smu7_powerdown_samu(struct pp_hwmgr *hwmgr) return 0; } -int smu7_powerup_samu(struct pp_hwmgr *hwmgr) +static int smu7_powerup_samu(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SamuPowerGating)) @@ -150,14 +150,20 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, AMD_CG_STATE_GATE); + cgs_set_powergating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_GATE); smu7_update_uvd_dpm(hwmgr, true); smu7_powerdown_uvd(hwmgr); } else { smu7_powerup_uvd(hwmgr); - smu7_update_uvd_dpm(hwmgr, false); + cgs_set_powergating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_UNGATE); cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, AMD_CG_STATE_UNGATE); + smu7_update_uvd_dpm(hwmgr, false); } return 0; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 75854021f403..a74f60a575ae 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -89,7 +89,7 @@ enum DPM_EVENT_SRC { static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic); -struct smu7_power_state *cast_phw_smu7_power_state( +static struct smu7_power_state *cast_phw_smu7_power_state( struct pp_hw_power_state *hw_ps) { PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), @@ -99,7 +99,7 @@ struct smu7_power_state *cast_phw_smu7_power_state( return (struct smu7_power_state *)hw_ps; } -const struct smu7_power_state *cast_const_phw_smu7_power_state( +static const struct smu7_power_state *cast_const_phw_smu7_power_state( const struct pp_hw_power_state *hw_ps) { PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), @@ -115,7 +115,7 @@ const struct smu7_power_state *cast_const_phw_smu7_power_state( * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr) +static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) { cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); @@ -124,7 +124,7 @@ int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr) return 0; } -uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) +static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) { uint32_t speedCntl = 0; @@ -135,7 +135,7 @@ uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); } -int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) +static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) { uint32_t link_width; @@ -155,7 +155,7 @@ int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) * @param pHwMgr the address of the powerplay hardware manager. * @return always PP_Result_OK */ -int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) +static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) { if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable); @@ -802,7 +802,7 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr) return 0; } -int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) +static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -993,13 +993,6 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0); - PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_Voltage_Cntl_Enable)), - "Failed to enable voltage DPM during DPM Start Function!", - return -EINVAL); - - if (smu7_enable_sclk_mclk_dpm(hwmgr)) { printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); return -EINVAL; @@ -1153,7 +1146,7 @@ static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); } -int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) +static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); data->pcie_performance_request = true; @@ -1161,7 +1154,7 @@ int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) return 0; } -int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) +static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) { int tmp_result = 0; int result = 0; @@ -1352,6 +1345,8 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct cgs_system_info sys_info = {0}; + int result; data->dll_default_on = false; data->mclk_dpm0_activity_target = 0xa; @@ -1426,7 +1421,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ControlVDDCI); - if ((hwmgr->pp_table_version != PP_TABLE_V0) + if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) && (table_info->cac_dtp_table->usClockStretchAmount != 0)) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ClockStretcher); @@ -1439,6 +1434,18 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) data->pcie_lane_performance.min = 16; data->pcie_lane_power_saving.max = 0; data->pcie_lane_power_saving.min = 16; + + sys_info.size = sizeof(struct cgs_system_info); + sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; + result = cgs_query_system_info(hwmgr->device, &sys_info); + if (!result) { + if (sys_info.value & AMD_PG_SUPPORT_UVD) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_UVDPowerGating); + if (sys_info.value & AMD_PG_SUPPORT_VCE) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_VCEPowerGating); + } } /** @@ -1460,19 +1467,17 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; - if (table_info == NULL) - return -EINVAL; - - sclk_table = table_info->vdd_dep_on_sclk; - for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { - if (0 == phm_get_sclk_for_voltage_evv(hwmgr, + if ((hwmgr->pp_table_version == PP_TABLE_V1) + && !phm_get_sclk_for_voltage_evv(hwmgr, table_info->vddgfx_lookup_table, vv_id, &sclk)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ClockStretcher)) { + sclk_table = table_info->vdd_dep_on_sclk; + for (j = 1; j < sclk_table->count; j++) { if (sclk_table->entries[j].clk == sclk && sclk_table->entries[j].cks_enable == 0) { @@ -1498,12 +1503,15 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) } } } else { - if ((hwmgr->pp_table_version == PP_TABLE_V0) || !phm_get_sclk_for_voltage_evv(hwmgr, table_info->vddc_lookup_table, vv_id, &sclk)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ClockStretcher)) { + if (table_info == NULL) + return -EINVAL; + sclk_table = table_info->vdd_dep_on_sclk; + for (j = 1; j < sclk_table->count; j++) { if (sclk_table->entries[j].clk == sclk && sclk_table->entries[j].cks_enable == 0) { @@ -1864,7 +1872,7 @@ static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr) return 0; } -int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) +static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) { struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -1993,8 +2001,9 @@ static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = table_info->cac_dtp_table->usTargetOperatingTemp; - phm_cap_set(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ODFuzzyFanControlSupport); + if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_ODFuzzyFanControlSupport); } return 0; @@ -2133,9 +2142,11 @@ static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); if (tab) { + vddc = tab->vddc; smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage); tab->vddc = vddc; + vddci = tab->vddci; smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, &data->vddci_leakage); tab->vddci = vddci; @@ -2256,7 +2267,7 @@ static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) return 0; } -int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) +static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data; int result; @@ -2981,19 +2992,19 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk) data->highest_mclk = memory_clock; - performance_level = &(ps->performance_levels - [ps->performance_level_count++]); - PP_ASSERT_WITH_CODE( (ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)), "Performance levels exceeds SMC limit!", return -EINVAL); PP_ASSERT_WITH_CODE( - (ps->performance_level_count <= + (ps->performance_level_count < hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), - "Performance levels exceeds Driver limit!", - return -EINVAL); + "Performance levels exceeds Driver limit, Skip!", + return 0); + + performance_level = &(ps->performance_levels + [ps->performance_level_count++]); /* Performance levels are arranged from low to high. */ performance_level->memory_clock = memory_clock; @@ -3675,14 +3686,16 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); } -int smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) +static int +smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) { PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; } -int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) +static int +smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) { uint32_t num_active_displays = 0; struct cgs_display_info info = {0}; @@ -3704,7 +3717,7 @@ int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always OK */ -int smu7_program_display_gap(struct pp_hwmgr *hwmgr) +static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); uint32_t num_active_displays = 0; @@ -3754,7 +3767,7 @@ int smu7_program_display_gap(struct pp_hwmgr *hwmgr) return 0; } -int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) +static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { return smu7_program_display_gap(hwmgr); } @@ -3778,13 +3791,14 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); } -int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, +static int smu7_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *thermal_interrupt_info) { return 0; } -bool smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) +static bool +smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); bool is_update_required = false; @@ -3813,7 +3827,9 @@ static inline bool smu7_are_power_levels_equal(const struct smu7_performance_lev (pl1->pcie_lane == pl2->pcie_lane)); } -int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) +static int smu7_check_states_equal(struct pp_hwmgr *hwmgr, + const struct pp_hw_power_state *pstate1, + const struct pp_hw_power_state *pstate2, bool *equal) { const struct smu7_power_state *psa; const struct smu7_power_state *psb; @@ -3846,7 +3862,7 @@ int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_sta return 0; } -int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr) +static int smu7_upload_mc_firmware(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -3975,7 +3991,7 @@ static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr) return 0; } -int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) +static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) { int tmp_result, result = 0; @@ -4228,18 +4244,26 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) { struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)hwmgr->pptable; - struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; + struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; + struct phm_clock_voltage_dependency_table *sclk_table; int i; - if (table_info == NULL) - return -EINVAL; - - dep_sclk_table = table_info->vdd_dep_on_sclk; - - for (i = 0; i < dep_sclk_table->count; i++) { - clocks->clock[i] = dep_sclk_table->entries[i].clk; - clocks->count++; + if (hwmgr->pp_table_version == PP_TABLE_V1) { + if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) + return -EINVAL; + dep_sclk_table = table_info->vdd_dep_on_sclk; + for (i = 0; i < dep_sclk_table->count; i++) { + clocks->clock[i] = dep_sclk_table->entries[i].clk; + clocks->count++; + } + } else if (hwmgr->pp_table_version == PP_TABLE_V0) { + sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; + for (i = 0; i < sclk_table->count; i++) { + clocks->clock[i] = sclk_table->entries[i].clk; + clocks->count++; + } } + return 0; } @@ -4261,17 +4285,24 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) (struct phm_ppt_v1_information *)hwmgr->pptable; struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; int i; + struct phm_clock_voltage_dependency_table *mclk_table; - if (table_info == NULL) - return -EINVAL; - - dep_mclk_table = table_info->vdd_dep_on_mclk; - - for (i = 0; i < dep_mclk_table->count; i++) { - clocks->clock[i] = dep_mclk_table->entries[i].clk; - clocks->latency[i] = smu7_get_mem_latency(hwmgr, + if (hwmgr->pp_table_version == PP_TABLE_V1) { + if (table_info == NULL) + return -EINVAL; + dep_mclk_table = table_info->vdd_dep_on_mclk; + for (i = 0; i < dep_mclk_table->count; i++) { + clocks->clock[i] = dep_mclk_table->entries[i].clk; + clocks->latency[i] = smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk); - clocks->count++; + clocks->count++; + } + } else if (hwmgr->pp_table_version == PP_TABLE_V0) { + mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; + for (i = 0; i < mclk_table->count; i++) { + clocks->clock[i] = mclk_table->entries[i].clk; + clocks->count++; + } } return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c index 41b634ffa5b0..26477f0f09dc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c @@ -603,9 +603,10 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) return 0; } -static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) +static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr, + uint32_t target_tdp) { - return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c index fb6c6f6106d5..29d0319b22e6 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c @@ -30,7 +30,7 @@ int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info) { if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; + return -ENODEV; fan_speed_info->supports_percent_read = true; fan_speed_info->supports_percent_write = true; @@ -60,7 +60,7 @@ int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint64_t tmp64; if (hwmgr->thermal_controller.fanInfo.bNoFan) - return 0; + return -ENODEV; duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100); @@ -89,7 +89,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) if (hwmgr->thermal_controller.fanInfo.bNoFan || (hwmgr->thermal_controller.fanInfo. ucTachometerPulsesPerRevolution == 0)) - return 0; + return -ENODEV; tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_TACH_STATUS, TACH_PERIOD); diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 3fb5e57a378b..3a883e6c601a 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -29,6 +29,8 @@ #include "amd_shared.h" #include "cgs_common.h" +extern int amdgpu_dpm; + enum amd_pp_sensors { AMDGPU_PP_SENSOR_GFX_SCLK = 0, AMDGPU_PP_SENSOR_VDDNB, @@ -349,6 +351,7 @@ struct amd_powerplay_funcs { int (*get_fan_control_mode)(void *handle); int (*set_fan_speed_percent)(void *handle, uint32_t percent); int (*get_fan_speed_percent)(void *handle, uint32_t *speed); + int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); int (*get_pp_num_states)(void *handle, struct pp_states_info *data); int (*get_pp_table)(void *handle, char **table); int (*set_pp_table)(void *handle, const char *buf, size_t size); @@ -359,6 +362,7 @@ struct amd_powerplay_funcs { int (*get_mclk_od)(void *handle); int (*set_mclk_od)(void *handle, uint32_t value); int (*read_sensor)(void *handle, int idx, int32_t *value); + struct amd_vce_state* (*get_vce_clock_state)(void *handle, unsigned idx); }; struct amd_powerplay { diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h index d4495839c64c..26129972f686 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h @@ -334,6 +334,7 @@ struct phm_clocks { uint32_t clock[MAX_NUM_CLOCKS]; }; +extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr); extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr); extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate); extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate); diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 4f0fedd1e9d3..6cdb7cbf515e 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -38,8 +38,6 @@ struct pp_hwmgr; struct phm_fan_speed_info; struct pp_atomctrl_voltage_table; -extern int amdgpu_powercontainment; -extern int amdgpu_sclk_deep_sleep_en; extern unsigned amdgpu_pp_feature_mask; #define VOLTAGE_SCALE 4 @@ -85,7 +83,9 @@ enum PP_FEATURE_MASK { PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, PP_VBI_TIME_SUPPORT_MASK = 0x80, PP_ULV_MASK = 0x100, - PP_ENABLE_GFX_CG_THRU_SMU = 0x200 + PP_ENABLE_GFX_CG_THRU_SMU = 0x200, + PP_CLOCK_STRETCH_MASK = 0x400, + PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800 }; enum PHM_BackEnd_Magic { @@ -367,7 +367,7 @@ struct pp_table_func { int (*pptable_get_vce_state_table_entry)( struct pp_hwmgr *hwmgr, unsigned long i, - struct pp_vce_state *vce_state, + struct amd_vce_state *vce_state, void **clock_info, unsigned long *flag); }; @@ -586,18 +586,6 @@ struct phm_microcode_version_info { uint32_t NB; }; -#define PP_MAX_VCE_LEVELS 6 - -enum PP_VCE_LEVEL { - PP_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ - PP_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ - PP_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ - PP_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ - PP_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ - PP_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ -}; - - enum PP_TABLE_VERSION { PP_TABLE_V0 = 0, PP_TABLE_V1, @@ -620,7 +608,7 @@ struct pp_hwmgr { void *hardcode_pp_table; bool need_pp_table_upload; - struct pp_vce_state vce_states[PP_MAX_VCE_LEVELS]; + struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; uint32_t num_vce_state_tables; enum amd_dpm_forced_level dpm_level; diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h b/drivers/gpu/drm/amd/powerplay/inc/power_state.h index 9ceaed9ac52a..827860fffe78 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/power_state.h +++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h @@ -156,15 +156,6 @@ struct pp_power_state { struct pp_hw_power_state hardware; }; - -/*Structure to hold a VCE state entry*/ -struct pp_vce_state { - uint32_t evclk; - uint32_t ecclk; - uint32_t sclk; - uint32_t mclk; -}; - enum PP_MMProfilingState { PP_MMProfilingState_NA = 0, PP_MMProfilingState_Started, diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h index 3df5de2cdab0..8fe8ba9434ff 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_acpi.h @@ -21,9 +21,6 @@ * */ -extern bool acpi_atcs_functions_supported(void *device, - uint32_t index); -extern int acpi_pcie_perf_request(void *device, - uint8_t perf_req, - bool advertise); -extern bool acpi_atcs_notify_pcie_device_ready(void *device); +bool acpi_atcs_functions_supported(void *device, uint32_t index); +int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise); +bool acpi_atcs_notify_pcie_device_ready(void *device); diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c index 76310ac7ef0d..6aeb1d20cc3b 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c @@ -1958,6 +1958,12 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) int res; uint64_t tmp64; + if (hwmgr->thermal_controller.fanInfo.bNoFan) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + if (smu_data->smu7_data.fan_table_start == 0) { phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); @@ -2049,7 +2055,7 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) return 0; } -int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) +static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -2125,7 +2131,7 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member) return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold); } } - printk("cant't get the offset of type %x member %x \n", type, member); + printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member); return 0; } @@ -2150,7 +2156,7 @@ uint32_t fiji_get_mac_definition(uint32_t value) return SMU73_MAX_LEVELS_MVDD; } - printk("cant't get the mac of %x \n", value); + printk(KERN_WARNING "can't get the mac of %x\n", value); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c index 02fe1df855a9..26eff56b4a99 100755..100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c @@ -159,7 +159,7 @@ static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) return result; } -int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) +static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr) { int i, result = -1; uint32_t reg, data; @@ -224,7 +224,7 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr) return result; } -int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr) +static int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr) { int result = 0; uint32_t table_start; @@ -260,7 +260,7 @@ int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr) return result; } -int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) +static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) { int32_t vr_config; uint32_t table_start; @@ -299,7 +299,7 @@ int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr) } /* Work in Progress */ -int fiji_restore_vft_table(struct pp_smumgr *smumgr) +static int fiji_restore_vft_table(struct pp_smumgr *smumgr) { struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); @@ -311,7 +311,7 @@ int fiji_restore_vft_table(struct pp_smumgr *smumgr) } /* Work in Progress */ -int fiji_save_vft_table(struct pp_smumgr *smumgr) +static int fiji_save_vft_table(struct pp_smumgr *smumgr) { struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); @@ -322,7 +322,7 @@ int fiji_save_vft_table(struct pp_smumgr *smumgr) return -EINVAL; } -int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) +static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started) { struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); @@ -396,7 +396,8 @@ static int fiji_start_smu(struct pp_smumgr *smumgr) struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend); /* Only start SMC if SMC RAM is not running */ - if (!smu7_is_smc_ram_running(smumgr)) { + if (!(smu7_is_smc_ram_running(smumgr) + || cgs_is_virtualization_enabled(smumgr->device))) { fiji_avfs_event_mgr(smumgr, false); /* Check if SMU is running in protected mode */ @@ -443,6 +444,9 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr) uint32_t efuse = 0; uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; + if (cgs_is_virtualization_enabled(smumgr->device)) + return 0; + if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB, mask, &efuse)) { if (efuse) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c index 8c889caba420..a24971a33bfd 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c @@ -2006,6 +2006,12 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) return 0; + if (hwmgr->thermal_controller.fanInfo.bNoFan) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + if (0 == smu7_data->fan_table_start) { phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); return 0; @@ -2140,7 +2146,7 @@ uint32_t iceland_get_offsetof(uint32_t type, uint32_t member) return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold); } } - printk("cant't get the offset of type %x member %x \n", type, member); + printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member); return 0; } @@ -2163,7 +2169,7 @@ uint32_t iceland_get_mac_definition(uint32_t value) return SMU71_MAX_LEVELS_MVDD; } - printk("cant't get the mac of %x \n", value); + printk(KERN_WARNING "can't get the mac of %x\n", value); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c index 4ccc0b72324d..5190e821200c 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c @@ -1885,6 +1885,12 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) int res; uint64_t tmp64; + if (hwmgr->thermal_controller.fanInfo.bNoFan) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + if (smu_data->smu7_data.fan_table_start == 0) { phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); @@ -2174,7 +2180,7 @@ uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member) return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold); } } - printk("cant't get the offset of type %x member %x \n", type, member); + printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member); return 0; } @@ -2201,7 +2207,7 @@ uint32_t polaris10_get_mac_definition(uint32_t value) return SMU7_UVD_MCLK_HANDSHAKE_DISABLE; } - printk("cant't get the mac of %x \n", value); + printk(KERN_WARNING "can't get the mac of %x\n", value); return 0; } @@ -2214,6 +2220,7 @@ uint32_t polaris10_get_mac_definition(uint32_t value) int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) { struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); uint32_t tmp; int result; bool error = false; @@ -2233,8 +2240,10 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) offsetof(SMU74_Firmware_Header, SoftRegisters), &tmp, SMC_RAM_END); - if (!result) + if (!result) { + data->soft_regs_start = tmp; smu_data->smu7_data.soft_regs_start = tmp; + } error |= (0 != result); diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c index 5c3598ab7dae..f38a68747df0 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -118,7 +118,7 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr) } -int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) +static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) { uint32_t vr_config; uint32_t dpm_table_start; @@ -172,7 +172,8 @@ int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) return 0; } -int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) +static int +polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) { struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c index 6af744f42ec9..f49b5487b951 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c @@ -278,6 +278,9 @@ enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type) case UCODE_ID_RLC_G: result = CGS_UCODE_ID_RLC_G; break; + case UCODE_ID_MEC_STORAGE: + result = CGS_UCODE_ID_STORAGE; + break; default: break; } @@ -363,12 +366,16 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr, &info); if (!result) { - entry->version = info.version; + entry->version = info.fw_version; entry->id = (uint16_t)fw_type; entry->image_addr_high = smu_upper_32_bits(info.mc_addr); entry->image_addr_low = smu_lower_32_bits(info.mc_addr); entry->meta_data_addr_high = 0; entry->meta_data_addr_low = 0; + + /* digest need be excluded out */ + if (cgs_is_virtualization_enabled(smumgr->device)) + info.image_size -= 20; entry->data_size_byte = info.image_size; entry->num_register_entries = 0; } @@ -400,8 +407,14 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr) 0x0); if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */ - smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); - smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); + if (!cgs_is_virtualization_enabled(smumgr->device)) { + smu7_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SMU_DRAM_ADDR_HI, + smu_data->smu_buffer.mc_addr_high); + smu7_send_msg_to_smc_with_parameter(smumgr, + PPSMC_MSG_SMU_DRAM_ADDR_LO, + smu_data->smu_buffer.mc_addr_low); + } fw_to_load = UCODE_ID_RLC_G_MASK + UCODE_ID_SDMA0_MASK + UCODE_ID_SDMA1_MASK @@ -452,6 +465,10 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr) PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -EINVAL); + if (cgs_is_virtualization_enabled(smumgr->device)) + PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr, + UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]), + "Failed to Get Firmware Entry.", return -EINVAL); smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); @@ -532,7 +549,6 @@ int smu7_init(struct pp_smumgr *smumgr) smu_data = (struct smu7_smumgr *)(smumgr->backend); smu_data->header_buffer.data_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; - smu_data->smu_buffer.data_size = 200*4096; /* Allocate FW image data structure and header buffer and * send the header buffer address to SMU */ @@ -555,6 +571,10 @@ int smu7_init(struct pp_smumgr *smumgr) (cgs_handle_t)smu_data->header_buffer.handle); return -EINVAL); + if (cgs_is_virtualization_enabled(smumgr->device)) + return 0; + + smu_data->smu_buffer.data_size = 200*4096; smu_allocate_memory(smumgr->device, smu_data->smu_buffer.data_size, CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h index 76352f2423ae..919be435b49c 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h @@ -28,8 +28,6 @@ #include <pp_endian.h> #define SMC_RAM_END 0x40000 -#define mmSMC_IND_INDEX_11 0x01AC -#define mmSMC_IND_DATA_11 0x01AD struct smu7_buffer_entry { uint32_t data_size; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c index de2a24d85f48..2e1493ce1bb5 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c @@ -2496,6 +2496,12 @@ int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_MicrocodeFanControl)) return 0; + if (hwmgr->thermal_controller.fanInfo.bNoFan) { + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_MicrocodeFanControl); + return 0; + } + if (0 == smu_data->smu7_data.fan_table_start) { phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); @@ -2651,7 +2657,7 @@ uint32_t tonga_get_offsetof(uint32_t type, uint32_t member) return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold); } } - printk("cant't get the offset of type %x member %x\n", type, member); + printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member); return 0; } @@ -2675,7 +2681,7 @@ uint32_t tonga_get_mac_definition(uint32_t value) case SMU_MAX_LEVELS_MVDD: return SMU72_MAX_LEVELS_MVDD; } - printk("cant't get the mac value %x\n", value); + printk(KERN_WARNING "can't get the mac value %x\n", value); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index 5f9124046b9b..eff9a232e72e 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -140,7 +140,8 @@ static int tonga_start_smu(struct pp_smumgr *smumgr) int result; /* Only start SMC if SMC RAM is not running */ - if (!smu7_is_smc_ram_running(smumgr)) { + if (!(smu7_is_smc_ram_running(smumgr) || + cgs_is_virtualization_enabled(smumgr->device))) { /*Check if SMU is running in protected mode*/ if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)) { diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h index b961a1c6caf3..dbd4fd3a810b 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h @@ -17,7 +17,7 @@ TRACE_EVENT(amd_sched_job, TP_STRUCT__entry( __field(struct amd_sched_entity *, entity) __field(struct amd_sched_job *, sched_job) - __field(struct fence *, fence) + __field(struct dma_fence *, fence) __field(const char *, name) __field(u32, job_count) __field(int, hw_job_count) @@ -42,7 +42,7 @@ TRACE_EVENT(amd_sched_process_job, TP_PROTO(struct amd_sched_fence *fence), TP_ARGS(fence), TP_STRUCT__entry( - __field(struct fence *, fence) + __field(struct dma_fence *, fence) ), TP_fast_assign( diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 910b8d5b21c5..1bf83ed113b3 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -32,10 +32,7 @@ static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity); static void amd_sched_wakeup(struct amd_gpu_scheduler *sched); -static void amd_sched_process_job(struct fence *f, struct fence_cb *cb); - -struct kmem_cache *sched_fence_slab; -atomic_t sched_fence_slab_ref = ATOMIC_INIT(0); +static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb); /* Initialize a given run queue struct */ static void amd_sched_rq_init(struct amd_sched_rq *rq) @@ -141,7 +138,7 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched, return r; atomic_set(&entity->fence_seq, 0); - entity->fence_context = fence_context_alloc(2); + entity->fence_context = dma_fence_context_alloc(2); return 0; } @@ -221,32 +218,32 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, kfifo_free(&entity->job_queue); } -static void amd_sched_entity_wakeup(struct fence *f, struct fence_cb *cb) +static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb) { struct amd_sched_entity *entity = container_of(cb, struct amd_sched_entity, cb); entity->dependency = NULL; - fence_put(f); + dma_fence_put(f); amd_sched_wakeup(entity->sched); } -static void amd_sched_entity_clear_dep(struct fence *f, struct fence_cb *cb) +static void amd_sched_entity_clear_dep(struct dma_fence *f, struct dma_fence_cb *cb) { struct amd_sched_entity *entity = container_of(cb, struct amd_sched_entity, cb); entity->dependency = NULL; - fence_put(f); + dma_fence_put(f); } static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity) { struct amd_gpu_scheduler *sched = entity->sched; - struct fence * fence = entity->dependency; + struct dma_fence * fence = entity->dependency; struct amd_sched_fence *s_fence; if (fence->context == entity->fence_context) { /* We can ignore fences from ourself */ - fence_put(entity->dependency); + dma_fence_put(entity->dependency); return false; } @@ -257,23 +254,23 @@ static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity) * Fence is from the same scheduler, only need to wait for * it to be scheduled */ - fence = fence_get(&s_fence->scheduled); - fence_put(entity->dependency); + fence = dma_fence_get(&s_fence->scheduled); + dma_fence_put(entity->dependency); entity->dependency = fence; - if (!fence_add_callback(fence, &entity->cb, - amd_sched_entity_clear_dep)) + if (!dma_fence_add_callback(fence, &entity->cb, + amd_sched_entity_clear_dep)) return true; /* Ignore it when it is already scheduled */ - fence_put(fence); + dma_fence_put(fence); return false; } - if (!fence_add_callback(entity->dependency, &entity->cb, - amd_sched_entity_wakeup)) + if (!dma_fence_add_callback(entity->dependency, &entity->cb, + amd_sched_entity_wakeup)) return true; - fence_put(entity->dependency); + dma_fence_put(entity->dependency); return false; } @@ -354,7 +351,8 @@ static void amd_sched_job_finish(struct work_struct *work) sched->ops->free_job(s_job); } -static void amd_sched_job_finish_cb(struct fence *f, struct fence_cb *cb) +static void amd_sched_job_finish_cb(struct dma_fence *f, + struct dma_fence_cb *cb) { struct amd_sched_job *job = container_of(cb, struct amd_sched_job, finish_cb); @@ -388,8 +386,8 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched) spin_lock(&sched->job_list_lock); list_for_each_entry_reverse(s_job, &sched->ring_mirror_list, node) { - if (fence_remove_callback(s_job->s_fence->parent, &s_job->s_fence->cb)) { - fence_put(s_job->s_fence->parent); + if (dma_fence_remove_callback(s_job->s_fence->parent, &s_job->s_fence->cb)) { + dma_fence_put(s_job->s_fence->parent); s_job->s_fence->parent = NULL; } } @@ -410,21 +408,21 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { struct amd_sched_fence *s_fence = s_job->s_fence; - struct fence *fence; + struct dma_fence *fence; spin_unlock(&sched->job_list_lock); fence = sched->ops->run_job(s_job); atomic_inc(&sched->hw_rq_count); if (fence) { - s_fence->parent = fence_get(fence); - r = fence_add_callback(fence, &s_fence->cb, - amd_sched_process_job); + s_fence->parent = dma_fence_get(fence); + r = dma_fence_add_callback(fence, &s_fence->cb, + amd_sched_process_job); if (r == -ENOENT) amd_sched_process_job(fence, &s_fence->cb); else if (r) DRM_ERROR("fence add callback failed (%d)\n", r); - fence_put(fence); + dma_fence_put(fence); } else { DRM_ERROR("Failed to run job!\n"); amd_sched_process_job(NULL, &s_fence->cb); @@ -446,8 +444,8 @@ void amd_sched_entity_push_job(struct amd_sched_job *sched_job) struct amd_sched_entity *entity = sched_job->s_entity; trace_amd_sched_job(sched_job); - fence_add_callback(&sched_job->s_fence->finished, &sched_job->finish_cb, - amd_sched_job_finish_cb); + dma_fence_add_callback(&sched_job->s_fence->finished, &sched_job->finish_cb, + amd_sched_job_finish_cb); wait_event(entity->sched->job_scheduled, amd_sched_entity_in(sched_job)); } @@ -511,7 +509,7 @@ amd_sched_select_entity(struct amd_gpu_scheduler *sched) return entity; } -static void amd_sched_process_job(struct fence *f, struct fence_cb *cb) +static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb) { struct amd_sched_fence *s_fence = container_of(cb, struct amd_sched_fence, cb); @@ -521,7 +519,7 @@ static void amd_sched_process_job(struct fence *f, struct fence_cb *cb) amd_sched_fence_finished(s_fence); trace_amd_sched_process_job(s_fence); - fence_put(&s_fence->finished); + dma_fence_put(&s_fence->finished); wake_up_interruptible(&sched->wake_up_worker); } @@ -547,7 +545,7 @@ static int amd_sched_main(void *param) struct amd_sched_entity *entity = NULL; struct amd_sched_fence *s_fence; struct amd_sched_job *sched_job; - struct fence *fence; + struct dma_fence *fence; wait_event_interruptible(sched->wake_up_worker, (!amd_sched_blocked(sched) && @@ -569,15 +567,15 @@ static int amd_sched_main(void *param) fence = sched->ops->run_job(sched_job); amd_sched_fence_scheduled(s_fence); if (fence) { - s_fence->parent = fence_get(fence); - r = fence_add_callback(fence, &s_fence->cb, - amd_sched_process_job); + s_fence->parent = dma_fence_get(fence); + r = dma_fence_add_callback(fence, &s_fence->cb, + amd_sched_process_job); if (r == -ENOENT) amd_sched_process_job(fence, &s_fence->cb); else if (r) DRM_ERROR("fence add callback failed (%d)\n", r); - fence_put(fence); + dma_fence_put(fence); } else { DRM_ERROR("Failed to run job!\n"); amd_sched_process_job(NULL, &s_fence->cb); @@ -618,13 +616,6 @@ int amd_sched_init(struct amd_gpu_scheduler *sched, INIT_LIST_HEAD(&sched->ring_mirror_list); spin_lock_init(&sched->job_list_lock); atomic_set(&sched->hw_rq_count, 0); - if (atomic_inc_return(&sched_fence_slab_ref) == 1) { - sched_fence_slab = kmem_cache_create( - "amd_sched_fence", sizeof(struct amd_sched_fence), 0, - SLAB_HWCACHE_ALIGN, NULL); - if (!sched_fence_slab) - return -ENOMEM; - } /* Each scheduler will run on a seperate kernel thread */ sched->thread = kthread_run(amd_sched_main, sched, sched->name); @@ -645,7 +636,4 @@ void amd_sched_fini(struct amd_gpu_scheduler *sched) { if (sched->thread) kthread_stop(sched->thread); - rcu_barrier(); - if (atomic_dec_and_test(&sched_fence_slab_ref)) - kmem_cache_destroy(sched_fence_slab); } diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 7cbbbfb502ef..d8dc681bcda6 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -25,14 +25,11 @@ #define _GPU_SCHEDULER_H_ #include <linux/kfifo.h> -#include <linux/fence.h> +#include <linux/dma-fence.h> struct amd_gpu_scheduler; struct amd_sched_rq; -extern struct kmem_cache *sched_fence_slab; -extern atomic_t sched_fence_slab_ref; - /** * A scheduler entity is a wrapper around a job queue or a group * of other entities. Entities take turns emitting jobs from their @@ -50,8 +47,8 @@ struct amd_sched_entity { atomic_t fence_seq; uint64_t fence_context; - struct fence *dependency; - struct fence_cb cb; + struct dma_fence *dependency; + struct dma_fence_cb cb; }; /** @@ -66,10 +63,10 @@ struct amd_sched_rq { }; struct amd_sched_fence { - struct fence scheduled; - struct fence finished; - struct fence_cb cb; - struct fence *parent; + struct dma_fence scheduled; + struct dma_fence finished; + struct dma_fence_cb cb; + struct dma_fence *parent; struct amd_gpu_scheduler *sched; spinlock_t lock; void *owner; @@ -79,15 +76,15 @@ struct amd_sched_job { struct amd_gpu_scheduler *sched; struct amd_sched_entity *s_entity; struct amd_sched_fence *s_fence; - struct fence_cb finish_cb; + struct dma_fence_cb finish_cb; struct work_struct finish_work; struct list_head node; struct delayed_work work_tdr; }; -extern const struct fence_ops amd_sched_fence_ops_scheduled; -extern const struct fence_ops amd_sched_fence_ops_finished; -static inline struct amd_sched_fence *to_amd_sched_fence(struct fence *f) +extern const struct dma_fence_ops amd_sched_fence_ops_scheduled; +extern const struct dma_fence_ops amd_sched_fence_ops_finished; +static inline struct amd_sched_fence *to_amd_sched_fence(struct dma_fence *f) { if (f->ops == &amd_sched_fence_ops_scheduled) return container_of(f, struct amd_sched_fence, scheduled); @@ -103,8 +100,8 @@ static inline struct amd_sched_fence *to_amd_sched_fence(struct fence *f) * these functions should be implemented in driver side */ struct amd_sched_backend_ops { - struct fence *(*dependency)(struct amd_sched_job *sched_job); - struct fence *(*run_job)(struct amd_sched_job *sched_job); + struct dma_fence *(*dependency)(struct amd_sched_job *sched_job); + struct dma_fence *(*run_job)(struct amd_sched_job *sched_job); void (*timedout_job)(struct amd_sched_job *sched_job); void (*free_job)(struct amd_sched_job *sched_job); }; @@ -145,6 +142,9 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity); void amd_sched_entity_push_job(struct amd_sched_job *sched_job); +int amd_sched_fence_slab_init(void); +void amd_sched_fence_slab_fini(void); + struct amd_sched_fence *amd_sched_fence_create( struct amd_sched_entity *s_entity, void *owner); void amd_sched_fence_scheduled(struct amd_sched_fence *fence); diff --git a/drivers/gpu/drm/amd/scheduler/sched_fence.c b/drivers/gpu/drm/amd/scheduler/sched_fence.c index 3653b5a40494..33f54d0a5c4f 100644 --- a/drivers/gpu/drm/amd/scheduler/sched_fence.c +++ b/drivers/gpu/drm/amd/scheduler/sched_fence.c @@ -27,6 +27,25 @@ #include <drm/drmP.h> #include "gpu_scheduler.h" +static struct kmem_cache *sched_fence_slab; + +int amd_sched_fence_slab_init(void) +{ + sched_fence_slab = kmem_cache_create( + "amd_sched_fence", sizeof(struct amd_sched_fence), 0, + SLAB_HWCACHE_ALIGN, NULL); + if (!sched_fence_slab) + return -ENOMEM; + + return 0; +} + +void amd_sched_fence_slab_fini(void) +{ + rcu_barrier(); + kmem_cache_destroy(sched_fence_slab); +} + struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *entity, void *owner) { @@ -42,46 +61,50 @@ struct amd_sched_fence *amd_sched_fence_create(struct amd_sched_entity *entity, spin_lock_init(&fence->lock); seq = atomic_inc_return(&entity->fence_seq); - fence_init(&fence->scheduled, &amd_sched_fence_ops_scheduled, - &fence->lock, entity->fence_context, seq); - fence_init(&fence->finished, &amd_sched_fence_ops_finished, - &fence->lock, entity->fence_context + 1, seq); + dma_fence_init(&fence->scheduled, &amd_sched_fence_ops_scheduled, + &fence->lock, entity->fence_context, seq); + dma_fence_init(&fence->finished, &amd_sched_fence_ops_finished, + &fence->lock, entity->fence_context + 1, seq); return fence; } void amd_sched_fence_scheduled(struct amd_sched_fence *fence) { - int ret = fence_signal(&fence->scheduled); + int ret = dma_fence_signal(&fence->scheduled); if (!ret) - FENCE_TRACE(&fence->scheduled, "signaled from irq context\n"); + DMA_FENCE_TRACE(&fence->scheduled, + "signaled from irq context\n"); else - FENCE_TRACE(&fence->scheduled, "was already signaled\n"); + DMA_FENCE_TRACE(&fence->scheduled, + "was already signaled\n"); } void amd_sched_fence_finished(struct amd_sched_fence *fence) { - int ret = fence_signal(&fence->finished); + int ret = dma_fence_signal(&fence->finished); if (!ret) - FENCE_TRACE(&fence->finished, "signaled from irq context\n"); + DMA_FENCE_TRACE(&fence->finished, + "signaled from irq context\n"); else - FENCE_TRACE(&fence->finished, "was already signaled\n"); + DMA_FENCE_TRACE(&fence->finished, + "was already signaled\n"); } -static const char *amd_sched_fence_get_driver_name(struct fence *fence) +static const char *amd_sched_fence_get_driver_name(struct dma_fence *fence) { return "amd_sched"; } -static const char *amd_sched_fence_get_timeline_name(struct fence *f) +static const char *amd_sched_fence_get_timeline_name(struct dma_fence *f) { struct amd_sched_fence *fence = to_amd_sched_fence(f); return (const char *)fence->sched->name; } -static bool amd_sched_fence_enable_signaling(struct fence *f) +static bool amd_sched_fence_enable_signaling(struct dma_fence *f) { return true; } @@ -95,10 +118,10 @@ static bool amd_sched_fence_enable_signaling(struct fence *f) */ static void amd_sched_fence_free(struct rcu_head *rcu) { - struct fence *f = container_of(rcu, struct fence, rcu); + struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); struct amd_sched_fence *fence = to_amd_sched_fence(f); - fence_put(fence->parent); + dma_fence_put(fence->parent); kmem_cache_free(sched_fence_slab, fence); } @@ -110,7 +133,7 @@ static void amd_sched_fence_free(struct rcu_head *rcu) * This function is called when the reference count becomes zero. * It just RCU schedules freeing up the fence. */ -static void amd_sched_fence_release_scheduled(struct fence *f) +static void amd_sched_fence_release_scheduled(struct dma_fence *f) { struct amd_sched_fence *fence = to_amd_sched_fence(f); @@ -124,27 +147,27 @@ static void amd_sched_fence_release_scheduled(struct fence *f) * * Drop the extra reference from the scheduled fence to the base fence. */ -static void amd_sched_fence_release_finished(struct fence *f) +static void amd_sched_fence_release_finished(struct dma_fence *f) { struct amd_sched_fence *fence = to_amd_sched_fence(f); - fence_put(&fence->scheduled); + dma_fence_put(&fence->scheduled); } -const struct fence_ops amd_sched_fence_ops_scheduled = { +const struct dma_fence_ops amd_sched_fence_ops_scheduled = { .get_driver_name = amd_sched_fence_get_driver_name, .get_timeline_name = amd_sched_fence_get_timeline_name, .enable_signaling = amd_sched_fence_enable_signaling, .signaled = NULL, - .wait = fence_default_wait, + .wait = dma_fence_default_wait, .release = amd_sched_fence_release_scheduled, }; -const struct fence_ops amd_sched_fence_ops_finished = { +const struct dma_fence_ops amd_sched_fence_ops_finished = { .get_driver_name = amd_sched_fence_get_driver_name, .get_timeline_name = amd_sched_fence_get_timeline_name, .enable_signaling = amd_sched_fence_enable_signaling, .signaled = NULL, - .wait = fence_default_wait, + .wait = dma_fence_default_wait, .release = amd_sched_fence_release_finished, }; |