diff options
Diffstat (limited to 'drivers/net/phy')
| -rw-r--r-- | drivers/net/phy/Kconfig | 36 | ||||
| -rw-r--r-- | drivers/net/phy/Makefile | 7 | ||||
| -rw-r--r-- | drivers/net/phy/fixed_phy.c | 153 | ||||
| -rw-r--r-- | drivers/net/phy/intel-xway.c | 376 | ||||
| -rw-r--r-- | drivers/net/phy/marvell.c | 346 | ||||
| -rw-r--r-- | drivers/net/phy/mdio-hisi-femac.c | 166 | ||||
| -rw-r--r-- | drivers/net/phy/mdio-mux-bcm-iproc.c | 248 | ||||
| -rw-r--r-- | drivers/net/phy/mdio-mux-gpio.c | 2 | ||||
| -rw-r--r-- | drivers/net/phy/mdio-mux-mmioreg.c | 2 | ||||
| -rw-r--r-- | drivers/net/phy/mdio-mux.c | 26 | ||||
| -rw-r--r-- | drivers/net/phy/mdio-xgene.c | 477 | ||||
| -rw-r--r-- | drivers/net/phy/mdio-xgene.h | 143 | ||||
| -rw-r--r-- | drivers/net/phy/micrel.c | 34 | ||||
| -rw-r--r-- | drivers/net/phy/swphy.c | 179 | ||||
| -rw-r--r-- | drivers/net/phy/swphy.h | 9 |
15 files changed, 2047 insertions, 157 deletions
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 6dad9a9c356c..47a64342cc16 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -12,6 +12,9 @@ menuconfig PHYLIB if PHYLIB +config SWPHY + bool + comment "MII PHY device drivers" config AQUANTIA_PHY @@ -159,6 +162,7 @@ config MICROCHIP_PHY config FIXED_PHY tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" depends on PHYLIB + select SWPHY ---help--- Adds the platform "fixed" MDIO Bus to cover the boards that use PHYs that are not connected to the real MDIO bus. @@ -254,6 +258,17 @@ config MDIO_BUS_MUX_MMIOREG Currently, only 8-bit registers are supported. +config MDIO_BUS_MUX_BCM_IPROC + tristate "Support for iProc based MDIO bus multiplexers" + depends on OF && OF_MDIO && (ARCH_BCM_IPROC || COMPILE_TEST) + select MDIO_BUS_MUX + default ARCH_BCM_IPROC + help + This module provides a driver for MDIO bus multiplexers found in + iProc based Broadcom SoCs. This multiplexer connects one of several + child MDIO bus to a parent bus. Buses could be internal as well as + external and selection logic lies inside the same multiplexer. + config MDIO_BCM_UNIMAC tristate "Broadcom UniMAC MDIO bus controller" depends on HAS_IOMEM @@ -271,6 +286,27 @@ config MDIO_BCM_IPROC This module provides a driver for the MDIO busses found in the Broadcom iProc SoC's. +config INTEL_XWAY_PHY + tristate "Driver for Intel XWAY PHYs" + ---help--- + Supports the Intel XWAY (former Lantiq) 11G and 22E PHYs. + These PHYs are marked as standalone chips under the names + PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel + SoCs xRX200, xRX300, xRX330, xRX350 and xRX550. + +config MDIO_HISI_FEMAC + tristate "Hisilicon FEMAC MDIO bus controller" + depends on HAS_IOMEM && OF_MDIO + help + This module provides a driver for the MDIO busses found in the + Hisilicon SoC that have an Fast Ethernet MAC. + +config MDIO_XGENE + tristate "APM X-Gene SoC MDIO bus controller" + help + This module provides a driver for the MDIO busses found in the + APM X-Gene SoC's. + endif # PHYLIB config MICREL_KS8995MA diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index fcdbb9299fab..534dfa74d5a2 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -1,6 +1,7 @@ # Makefile for Linux PHY drivers -libphy-objs := phy.o phy_device.o mdio_bus.o mdio_device.o +libphy-y := phy.o phy_device.o mdio_bus.o mdio_device.o +libphy-$(CONFIG_SWPHY) += swphy.o obj-$(CONFIG_PHYLIB) += libphy.o obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o @@ -39,8 +40,12 @@ obj-$(CONFIG_AMD_PHY) += amd.o obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o +obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o obj-$(CONFIG_MICROCHIP_PHY) += microchip.o obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o +obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o +obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o +obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o diff --git a/drivers/net/phy/fixed_phy.c b/drivers/net/phy/fixed_phy.c index 9ec7f7353434..c649c101bbab 100644 --- a/drivers/net/phy/fixed_phy.c +++ b/drivers/net/phy/fixed_phy.c @@ -23,9 +23,10 @@ #include <linux/slab.h> #include <linux/of.h> #include <linux/gpio.h> +#include <linux/seqlock.h> #include <linux/idr.h> -#define MII_REGS_NUM 29 +#include "swphy.h" struct fixed_mdio_bus { struct mii_bus *mii_bus; @@ -34,8 +35,8 @@ struct fixed_mdio_bus { struct fixed_phy { int addr; - u16 regs[MII_REGS_NUM]; struct phy_device *phydev; + seqcount_t seqcount; struct fixed_phy_status status; int (*link_update)(struct net_device *, struct fixed_phy_status *); struct list_head node; @@ -47,103 +48,10 @@ static struct fixed_mdio_bus platform_fmb = { .phys = LIST_HEAD_INIT(platform_fmb.phys), }; -static int fixed_phy_update_regs(struct fixed_phy *fp) +static void fixed_phy_update(struct fixed_phy *fp) { - u16 bmsr = BMSR_ANEGCAPABLE; - u16 bmcr = 0; - u16 lpagb = 0; - u16 lpa = 0; - if (gpio_is_valid(fp->link_gpio)) fp->status.link = !!gpio_get_value_cansleep(fp->link_gpio); - - if (fp->status.duplex) { - switch (fp->status.speed) { - case 1000: - bmsr |= BMSR_ESTATEN; - break; - case 100: - bmsr |= BMSR_100FULL; - break; - case 10: - bmsr |= BMSR_10FULL; - break; - default: - break; - } - } else { - switch (fp->status.speed) { - case 1000: - bmsr |= BMSR_ESTATEN; - break; - case 100: - bmsr |= BMSR_100HALF; - break; - case 10: - bmsr |= BMSR_10HALF; - break; - default: - break; - } - } - - if (fp->status.link) { - bmsr |= BMSR_LSTATUS | BMSR_ANEGCOMPLETE; - - if (fp->status.duplex) { - bmcr |= BMCR_FULLDPLX; - - switch (fp->status.speed) { - case 1000: - bmcr |= BMCR_SPEED1000; - lpagb |= LPA_1000FULL; - break; - case 100: - bmcr |= BMCR_SPEED100; - lpa |= LPA_100FULL; - break; - case 10: - lpa |= LPA_10FULL; - break; - default: - pr_warn("fixed phy: unknown speed\n"); - return -EINVAL; - } - } else { - switch (fp->status.speed) { - case 1000: - bmcr |= BMCR_SPEED1000; - lpagb |= LPA_1000HALF; - break; - case 100: - bmcr |= BMCR_SPEED100; - lpa |= LPA_100HALF; - break; - case 10: - lpa |= LPA_10HALF; - break; - default: - pr_warn("fixed phy: unknown speed\n"); - return -EINVAL; - } - } - - if (fp->status.pause) - lpa |= LPA_PAUSE_CAP; - - if (fp->status.asym_pause) - lpa |= LPA_PAUSE_ASYM; - } - - fp->regs[MII_PHYSID1] = 0; - fp->regs[MII_PHYSID2] = 0; - - fp->regs[MII_BMSR] = bmsr; - fp->regs[MII_BMCR] = bmcr; - fp->regs[MII_LPA] = lpa; - fp->regs[MII_STAT1000] = lpagb; - - return 0; } static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) @@ -151,29 +59,23 @@ static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) struct fixed_mdio_bus *fmb = bus->priv; struct fixed_phy *fp; - if (reg_num >= MII_REGS_NUM) - return -1; - - /* We do not support emulating Clause 45 over Clause 22 register reads - * return an error instead of bogus data. - */ - switch (reg_num) { - case MII_MMD_CTRL: - case MII_MMD_DATA: - return -1; - default: - break; - } - list_for_each_entry(fp, &fmb->phys, node) { if (fp->addr == phy_addr) { - /* Issue callback if user registered it. */ - if (fp->link_update) { - fp->link_update(fp->phydev->attached_dev, - &fp->status); - fixed_phy_update_regs(fp); - } - return fp->regs[reg_num]; + struct fixed_phy_status state; + int s; + + do { + s = read_seqcount_begin(&fp->seqcount); + /* Issue callback if user registered it. */ + if (fp->link_update) { + fp->link_update(fp->phydev->attached_dev, + &fp->status); + fixed_phy_update(fp); + } + state = fp->status; + } while (read_seqcount_retry(&fp->seqcount, s)); + + return swphy_read_reg(reg_num, &state); } } @@ -225,6 +127,7 @@ int fixed_phy_update_state(struct phy_device *phydev, list_for_each_entry(fp, &fmb->phys, node) { if (fp->addr == phydev->mdio.addr) { + write_seqcount_begin(&fp->seqcount); #define _UPD(x) if (changed->x) \ fp->status.x = status->x _UPD(link); @@ -233,7 +136,8 @@ int fixed_phy_update_state(struct phy_device *phydev, _UPD(pause); _UPD(asym_pause); #undef _UPD - fixed_phy_update_regs(fp); + fixed_phy_update(fp); + write_seqcount_end(&fp->seqcount); return 0; } } @@ -250,11 +154,15 @@ int fixed_phy_add(unsigned int irq, int phy_addr, struct fixed_mdio_bus *fmb = &platform_fmb; struct fixed_phy *fp; + ret = swphy_validate_state(status); + if (ret < 0) + return ret; + fp = kzalloc(sizeof(*fp), GFP_KERNEL); if (!fp) return -ENOMEM; - memset(fp->regs, 0xFF, sizeof(fp->regs[0]) * MII_REGS_NUM); + seqcount_init(&fp->seqcount); if (irq != PHY_POLL) fmb->mii_bus->irq[phy_addr] = irq; @@ -270,17 +178,12 @@ int fixed_phy_add(unsigned int irq, int phy_addr, goto err_regs; } - ret = fixed_phy_update_regs(fp); - if (ret) - goto err_gpio; + fixed_phy_update(fp); list_add_tail(&fp->node, &fmb->phys); return 0; -err_gpio: - if (gpio_is_valid(fp->link_gpio)) - gpio_free(fp->link_gpio); err_regs: kfree(fp); return ret; diff --git a/drivers/net/phy/intel-xway.c b/drivers/net/phy/intel-xway.c new file mode 100644 index 000000000000..c300ab5587b8 --- /dev/null +++ b/drivers/net/phy/intel-xway.c @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> + * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/mdio.h> +#include <linux/module.h> +#include <linux/phy.h> +#include <linux/of.h> + +#define XWAY_MDIO_IMASK 0x19 /* interrupt mask */ +#define XWAY_MDIO_ISTAT 0x1A /* interrupt status */ + +#define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */ +#define XWAY_MDIO_INIT_MSRE BIT(14) +#define XWAY_MDIO_INIT_NPRX BIT(13) +#define XWAY_MDIO_INIT_NPTX BIT(12) +#define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */ +#define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */ +#define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */ +#define XWAY_MDIO_INIT_MPIPC BIT(4) +#define XWAY_MDIO_INIT_MDIXC BIT(3) +#define XWAY_MDIO_INIT_DXMC BIT(2) /* Duplex mode change */ +#define XWAY_MDIO_INIT_LSPC BIT(1) /* Link speed change */ +#define XWAY_MDIO_INIT_LSTC BIT(0) /* Link state change */ +#define XWAY_MDIO_INIT_MASK (XWAY_MDIO_INIT_LSTC | \ + XWAY_MDIO_INIT_ADSC) + +#define ADVERTISED_MPD BIT(10) /* Multi-port device */ + +/* LED Configuration */ +#define XWAY_MMD_LEDCH 0x01E0 +/* Inverse of SCAN Function */ +#define XWAY_MMD_LEDCH_NACS_NONE 0x0000 +#define XWAY_MMD_LEDCH_NACS_LINK 0x0001 +#define XWAY_MMD_LEDCH_NACS_PDOWN 0x0002 +#define XWAY_MMD_LEDCH_NACS_EEE 0x0003 +#define XWAY_MMD_LEDCH_NACS_ANEG 0x0004 +#define XWAY_MMD_LEDCH_NACS_ABIST 0x0005 +#define XWAY_MMD_LEDCH_NACS_CDIAG 0x0006 +#define XWAY_MMD_LEDCH_NACS_TEST 0x0007 +/* Slow Blink Frequency */ +#define XWAY_MMD_LEDCH_SBF_F02HZ 0x0000 +#define XWAY_MMD_LEDCH_SBF_F04HZ 0x0010 +#define XWAY_MMD_LEDCH_SBF_F08HZ 0x0020 +#define XWAY_MMD_LEDCH_SBF_F16HZ 0x0030 +/* Fast Blink Frequency */ +#define XWAY_MMD_LEDCH_FBF_F02HZ 0x0000 +#define XWAY_MMD_LEDCH_FBF_F04HZ 0x0040 +#define XWAY_MMD_LEDCH_FBF_F08HZ 0x0080 +#define XWAY_MMD_LEDCH_FBF_F16HZ 0x00C0 +/* LED Configuration */ +#define XWAY_MMD_LEDCL 0x01E1 +/* Complex Blinking Configuration */ +#define XWAY_MMD_LEDCH_CBLINK_NONE 0x0000 +#define XWAY_MMD_LEDCH_CBLINK_LINK 0x0001 +#define XWAY_MMD_LEDCH_CBLINK_PDOWN 0x0002 +#define XWAY_MMD_LEDCH_CBLINK_EEE 0x0003 +#define XWAY_MMD_LEDCH_CBLINK_ANEG 0x0004 +#define XWAY_MMD_LEDCH_CBLINK_ABIST 0x0005 +#define XWAY_MMD_LEDCH_CBLINK_CDIAG 0x0006 +#define XWAY_MMD_LEDCH_CBLINK_TEST 0x0007 +/* Complex SCAN Configuration */ +#define XWAY_MMD_LEDCH_SCAN_NONE 0x0000 +#define XWAY_MMD_LEDCH_SCAN_LINK 0x0010 +#define XWAY_MMD_LEDCH_SCAN_PDOWN 0x0020 +#define XWAY_MMD_LEDCH_SCAN_EEE 0x0030 +#define XWAY_MMD_LEDCH_SCAN_ANEG 0x0040 +#define XWAY_MMD_LEDCH_SCAN_ABIST 0x0050 +#define XWAY_MMD_LEDCH_SCAN_CDIAG 0x0060 +#define XWAY_MMD_LEDCH_SCAN_TEST 0x0070 +/* Configuration for LED Pin x */ +#define XWAY_MMD_LED0H 0x01E2 +/* Fast Blinking Configuration */ +#define XWAY_MMD_LEDxH_BLINKF_MASK 0x000F +#define XWAY_MMD_LEDxH_BLINKF_NONE 0x0000 +#define XWAY_MMD_LEDxH_BLINKF_LINK10 0x0001 +#define XWAY_MMD_LEDxH_BLINKF_LINK100 0x0002 +#define XWAY_MMD_LEDxH_BLINKF_LINK10X 0x0003 +#define XWAY_MMD_LEDxH_BLINKF_LINK1000 0x0004 +#define XWAY_MMD_LEDxH_BLINKF_LINK10_0 0x0005 +#define XWAY_MMD_LEDxH_BLINKF_LINK100X 0x0006 +#define XWAY_MMD_LEDxH_BLINKF_LINK10XX 0x0007 +#define XWAY_MMD_LEDxH_BLINKF_PDOWN 0x0008 +#define XWAY_MMD_LEDxH_BLINKF_EEE 0x0009 +#define XWAY_MMD_LEDxH_BLINKF_ANEG 0x000A +#define XWAY_MMD_LEDxH_BLINKF_ABIST 0x000B +#define XWAY_MMD_LEDxH_BLINKF_CDIAG 0x000C +/* Constant On Configuration */ +#define XWAY_MMD_LEDxH_CON_MASK 0x00F0 +#define XWAY_MMD_LEDxH_CON_NONE 0x0000 +#define XWAY_MMD_LEDxH_CON_LINK10 0x0010 +#define XWAY_MMD_LEDxH_CON_LINK100 0x0020 +#define XWAY_MMD_LEDxH_CON_LINK10X 0x0030 +#define XWAY_MMD_LEDxH_CON_LINK1000 0x0040 +#define XWAY_MMD_LEDxH_CON_LINK10_0 0x0050 +#define XWAY_MMD_LEDxH_CON_LINK100X 0x0060 +#define XWAY_MMD_LEDxH_CON_LINK10XX 0x0070 +#define XWAY_MMD_LEDxH_CON_PDOWN 0x0080 +#define XWAY_MMD_LEDxH_CON_EEE 0x0090 +#define XWAY_MMD_LEDxH_CON_ANEG 0x00A0 +#define XWAY_MMD_LEDxH_CON_ABIST 0x00B0 +#define XWAY_MMD_LEDxH_CON_CDIAG 0x00C0 +#define XWAY_MMD_LEDxH_CON_COPPER 0x00D0 +#define XWAY_MMD_LEDxH_CON_FIBER 0x00E0 +/* Configuration for LED Pin x */ +#define XWAY_MMD_LED0L 0x01E3 +/* Pulsing Configuration */ +#define XWAY_MMD_LEDxL_PULSE_MASK 0x000F +#define XWAY_MMD_LEDxL_PULSE_NONE 0x0000 +#define XWAY_MMD_LEDxL_PULSE_TXACT 0x0001 +#define XWAY_MMD_LEDxL_PULSE_RXACT 0x0002 +#define XWAY_MMD_LEDxL_PULSE_COL 0x0004 +/* Slow Blinking Configuration */ +#define XWAY_MMD_LEDxL_BLINKS_MASK 0x00F0 +#define XWAY_MMD_LEDxL_BLINKS_NONE 0x0000 +#define XWAY_MMD_LEDxL_BLINKS_LINK10 0x0010 +#define XWAY_MMD_LEDxL_BLINKS_LINK100 0x0020 +#define XWAY_MMD_LEDxL_BLINKS_LINK10X 0x0030 +#define XWAY_MMD_LEDxL_BLINKS_LINK1000 0x0040 +#define XWAY_MMD_LEDxL_BLINKS_LINK10_0 0x0050 +#define XWAY_MMD_LEDxL_BLINKS_LINK100X 0x0060 +#define XWAY_MMD_LEDxL_BLINKS_LINK10XX 0x0070 +#define XWAY_MMD_LEDxL_BLINKS_PDOWN 0x0080 +#define XWAY_MMD_LEDxL_BLINKS_EEE 0x0090 +#define XWAY_MMD_LEDxL_BLINKS_ANEG 0x00A0 +#define XWAY_MMD_LEDxL_BLINKS_ABIST 0x00B0 +#define XWAY_MMD_LEDxL_BLINKS_CDIAG 0x00C0 +#define XWAY_MMD_LED1H 0x01E4 +#define XWAY_MMD_LED1L 0x01E5 +#define XWAY_MMD_LED2H 0x01E6 +#define XWAY_MMD_LED2L 0x01E7 +#define XWAY_MMD_LED3H 0x01E8 +#define XWAY_MMD_LED3L 0x01E9 + +#define PHY_ID_PHY11G_1_3 0x030260D1 +#define PHY_ID_PHY22F_1_3 0x030260E1 +#define PHY_ID_PHY11G_1_4 0xD565A400 +#define PHY_ID_PHY22F_1_4 0xD565A410 +#define PHY_ID_PHY11G_1_5 0xD565A401 +#define PHY_ID_PHY22F_1_5 0xD565A411 +#define PHY_ID_PHY11G_VR9 0xD565A409 +#define PHY_ID_PHY22F_VR9 0xD565A419 + +static int xway_gphy_config_init(struct phy_device *phydev) +{ + int err; + u32 ledxh; + u32 ledxl; + + /* Mask all interrupts */ + err = phy_write(phydev, XWAY_MDIO_IMASK, 0); + if (err) + return err; + + /* Clear all pending interrupts */ + phy_read(phydev, XWAY_MDIO_ISTAT); + + phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCH, MDIO_MMD_VEND2, + XWAY_MMD_LEDCH_NACS_NONE | + XWAY_MMD_LEDCH_SBF_F02HZ | + XWAY_MMD_LEDCH_FBF_F16HZ); + phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCL, MDIO_MMD_VEND2, + XWAY_MMD_LEDCH_CBLINK_NONE | + XWAY_MMD_LEDCH_SCAN_NONE); + + /** + * In most cases only one LED is connected to this phy, so + * configure them all to constant on and pulse mode. LED3 is + * only available in some packages, leave it in its reset + * configuration. + */ + ledxh = XWAY_MMD_LEDxH_BLINKF_NONE | XWAY_MMD_LEDxH_CON_LINK10XX; + ledxl = XWAY_MMD_LEDxL_PULSE_TXACT | XWAY_MMD_LEDxL_PULSE_RXACT | + XWAY_MMD_LEDxL_BLINKS_NONE; + phy_write_mmd_indirect(phydev, XWAY_MMD_LED0H, MDIO_MMD_VEND2, ledxh); + phy_write_mmd_indirect(phydev, XWAY_MMD_LED0L, MDIO_MMD_VEND2, ledxl); + phy_write_mmd_indirect(phydev, XWAY_MMD_LED1H, MDIO_MMD_VEND2, ledxh); + phy_write_mmd_indirect(phydev, XWAY_MMD_LED1L, MDIO_MMD_VEND2, ledxl); + phy_write_mmd_indirect(phydev, XWAY_MMD_LED2H, MDIO_MMD_VEND2, ledxh); + phy_write_mmd_indirect(phydev, XWAY_MMD_LED2L, MDIO_MMD_VEND2, ledxl); + + return 0; +} + +static int xway_gphy14_config_aneg(struct phy_device *phydev) +{ + int reg, err; + + /* Advertise as multi-port device, see IEEE802.3-2002 40.5.1.1 */ + /* This is a workaround for an errata in rev < 1.5 devices */ + reg = phy_read(phydev, MII_CTRL1000); + reg |= ADVERTISED_MPD; + err = phy_write(phydev, MII_CTRL1000, reg); + if (err) + return err; + + return genphy_config_aneg(phydev); +} + +static int xway_gphy_ack_interrupt(struct phy_device *phydev) +{ + int reg; + + reg = phy_read(phydev, XWAY_MDIO_ISTAT); + return (reg < 0) ? reg : 0; +} + +static int xway_gphy_did_interrupt(struct phy_device *phydev) +{ + int reg; + + reg = phy_read(phydev, XWAY_MDIO_ISTAT); + return reg & XWAY_MDIO_INIT_MASK; +} + +static int xway_gphy_config_intr(struct phy_device *phydev) +{ + u16 mask = 0; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) + mask = XWAY_MDIO_INIT_MASK; + + return phy_write(phydev, XWAY_MDIO_IMASK, mask); +} + +static struct phy_driver xway_gphy[] = { + { + .phy_id = PHY_ID_PHY11G_1_3, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.3", + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause | + SUPPORTED_Asym_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = xway_gphy_config_init, + .config_aneg = xway_gphy14_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = xway_gphy_ack_interrupt, + .did_interrupt = xway_gphy_did_interrupt, + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_PHY22F_1_3, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY22F (PEF 7061) v1.3", + .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | + SUPPORTED_Asym_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = xway_gphy_config_init, + .config_aneg = xway_gphy14_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = xway_gphy_ack_interrupt, + .did_interrupt = xway_gphy_did_interrupt, + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_PHY11G_1_4, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.4", + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause | + SUPPORTED_Asym_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = xway_gphy_config_init, + .config_aneg = xway_gphy14_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = xway_gphy_ack_interrupt, + .did_interrupt = xway_gphy_did_interrupt, + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_PHY22F_1_4, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY22F (PEF 7061) v1.4", + .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | + SUPPORTED_Asym_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = xway_gphy_config_init, + .config_aneg = xway_gphy14_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = xway_gphy_ack_interrupt, + .did_interrupt = xway_gphy_did_interrupt, + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_PHY11G_1_5, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.5 / v1.6", + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause | + SUPPORTED_Asym_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = xway_gphy_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = xway_gphy_ack_interrupt, + .did_interrupt = xway_gphy_did_interrupt, + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_PHY22F_1_5, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY22F (PEF 7061) v1.5 / v1.6", + .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | + SUPPORTED_Asym_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = xway_gphy_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = xway_gphy_ack_interrupt, + .did_interrupt = xway_gphy_did_interrupt, + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_PHY11G_VR9, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY11G (xRX integrated)", + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause | + SUPPORTED_Asym_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = xway_gphy_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = xway_gphy_ack_interrupt, + .did_interrupt = xway_gphy_did_interrupt, + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, { + .phy_id = PHY_ID_PHY22F_VR9, + .phy_id_mask = 0xffffffff, + .name = "Intel XWAY PHY22F (xRX integrated)", + .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | + SUPPORTED_Asym_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = xway_gphy_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = xway_gphy_ack_interrupt, + .did_interrupt = xway_gphy_did_interrupt, + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, + }, +}; +module_phy_driver(xway_gphy); + +static struct mdio_device_id __maybe_unused xway_gphy_tbl[] = { + { PHY_ID_PHY11G_1_3, 0xffffffff }, + { PHY_ID_PHY22F_1_3, 0xffffffff }, + { PHY_ID_PHY11G_1_4, 0xffffffff }, + { PHY_ID_PHY22F_1_4, 0xffffffff }, + { PHY_ID_PHY11G_1_5, 0xffffffff }, + { PHY_ID_PHY22F_1_5, 0xffffffff }, + { PHY_ID_PHY11G_VR9, 0xffffffff }, + { PHY_ID_PHY22F_VR9, 0xffffffff }, + { } +}; +MODULE_DEVICE_TABLE(mdio, xway_gphy_tbl); + +MODULE_DESCRIPTION("Intel XWAY PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index ec2c1eee6405..c2dcf02df202 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -138,6 +138,21 @@ #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */ #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */ +#define LPA_FIBER_1000HALF 0x40 +#define LPA_FIBER_1000FULL 0x20 + +#define LPA_PAUSE_FIBER 0x180 +#define LPA_PAUSE_ASYM_FIBER 0x100 + +#define ADVERTISE_FIBER_1000HALF 0x40 +#define ADVERTISE_FIBER_1000FULL 0x20 + +#define ADVERTISE_PAUSE_FIBER 0x180 +#define ADVERTISE_PAUSE_ASYM_FIBER 0x100 + +#define REGISTER_LINK_STATUS 0x400 +#define NB_FIBER_STATS 1 + MODULE_DESCRIPTION("Marvell PHY driver"); MODULE_AUTHOR("Andy Fleming"); MODULE_LICENSE("GPL"); @@ -150,8 +165,9 @@ struct marvell_hw_stat { }; static struct marvell_hw_stat marvell_hw_stats[] = { - { "phy_receive_errors", 0, 21, 16}, + { "phy_receive_errors_copper", 0, 21, 16}, { "phy_idle_errors", 0, 10, 8 }, + { "phy_receive_errors_fiber", 1, 21, 16}, }; struct marvell_priv { @@ -477,15 +493,122 @@ static int m88e1318_config_aneg(struct phy_device *phydev) return m88e1121_config_aneg(phydev); } +/** + * ethtool_adv_to_fiber_adv_t + * @ethadv: the ethtool advertisement settings + * + * A small helper function that translates ethtool advertisement + * settings to phy autonegotiation advertisements for the + * MII_ADV register for fiber link. + */ +static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv) +{ + u32 result = 0; + + if (ethadv & ADVERTISED_1000baseT_Half) + result |= ADVERTISE_FIBER_1000HALF; + if (ethadv & ADVERTISED_1000baseT_Full) + result |= ADVERTISE_FIBER_1000FULL; + + if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP)) + result |= LPA_PAUSE_ASYM_FIBER; + else if (ethadv & ADVERTISE_PAUSE_CAP) + result |= (ADVERTISE_PAUSE_FIBER + & (~ADVERTISE_PAUSE_ASYM_FIBER)); + + return result; +} + +/** + * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR + * @phydev: target phy_device struct + * + * Description: If auto-negotiation is enabled, we configure the + * advertising, and then restart auto-negotiation. If it is not + * enabled, then we write the BMCR. Adapted for fiber link in + * some Marvell's devices. + */ +static int marvell_config_aneg_fiber(struct phy_device *phydev) +{ + int changed = 0; + int err; + int adv, oldadv; + u32 advertise; + + if (phydev->autoneg != AUTONEG_ENABLE) + return genphy_setup_forced(phydev); + + /* Only allow advertising what this PHY supports */ + phydev->advertising &= phydev->supported; + advertise = phydev->advertising; + + /* Setup fiber advertisement */ + adv = phy_read(phydev, MII_ADVERTISE); + if (adv < 0) + return adv; + + oldadv = adv; + adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL + | LPA_PAUSE_FIBER); + adv |= ethtool_adv_to_fiber_adv_t(advertise); + + if (adv != oldadv) { + err = phy_write(phydev, MII_ADVERTISE, adv); + if (err < 0) + return err; + + changed = 1; + } + + if (changed == 0) { + /* Advertisement hasn't changed, but maybe aneg was never on to + * begin with? Or maybe phy was isolated? + */ + int ctl = phy_read(phydev, MII_BMCR); + + if (ctl < 0) + return ctl; + + if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) + changed = 1; /* do restart aneg */ + } + + /* Only restart aneg if we are advertising something different + * than we were before. + */ + if (changed > 0) + changed = genphy_restart_aneg(phydev); + + return changed; +} + static int m88e1510_config_aneg(struct phy_device *phydev) { int err; + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + if (err < 0) + goto error; + + /* Configure the copper link first */ err = m88e1318_config_aneg(phydev); if (err < 0) - return err; + goto error; - return 0; + /* Then the fiber link */ + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER); + if (err < 0) + goto error; + + err = marvell_config_aneg_fiber(phydev); + if (err < 0) + goto error; + + return phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + +error: + phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + return err; } static int marvell_config_init(struct phy_device *phydev) @@ -890,26 +1013,79 @@ static int m88e1145_config_init(struct phy_device *phydev) return 0; } -/* marvell_read_status +/** + * fiber_lpa_to_ethtool_lpa_t + * @lpa: value of the MII_LPA register for fiber link + * + * A small helper function that translates MII_LPA + * bits to ethtool LP advertisement settings. + */ +static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa) +{ + u32 result = 0; + + if (lpa & LPA_FIBER_1000HALF) + result |= ADVERTISED_1000baseT_Half; + if (lpa & LPA_FIBER_1000FULL) + result |= ADVERTISED_1000baseT_Full; + + return result; +} + +/** + * marvell_update_link - update link status in real time in @phydev + * @phydev: target phy_device struct + * + * Description: Update the value in phydev->link to reflect the + * current link value. + */ +static int marvell_update_link(struct phy_device *phydev, int fiber) +{ + int status; + + /* Use the generic register for copper link, or specific + * register for fiber case */ + if (fiber) { + status = phy_read(phydev, MII_M1011_PHY_STATUS); + if (status < 0) + return status; + + if ((status & REGISTER_LINK_STATUS) == 0) + phydev->link = 0; + else + phydev->link = 1; + } else { + return genphy_update_link(phydev); + } + + return 0; +} + +/* marvell_read_status_page * - * Generic status code does not detect Fiber correctly! * Description: * Check the link, then figure out the current state * by comparing what we advertise with what the link partner * advertises. Start by checking the gigabit possibilities, * then move on to 10/100. */ -static int marvell_read_status(struct phy_device *phydev) +static int marvell_read_status_page(struct phy_device *phydev, int page) { int adv; int err; int lpa; int lpagb; int status = 0; + int fiber; - /* Update the link, but return if there + /* Detect and update the link, but return if there * was an error */ - err = genphy_update_link(phydev); + if (page == MII_M1111_FIBER) + fiber = 1; + else + fiber = 0; + + err = marvell_update_link(phydev, fiber); if (err) return err; @@ -930,9 +1106,6 @@ static int marvell_read_status(struct phy_device *phydev) if (adv < 0) return adv; - phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) | - mii_lpa_to_ethtool_lpa_t(lpa); - lpa &= adv; if (status & MII_M1011_PHY_STATUS_FULLDUPLEX) @@ -957,9 +1130,30 @@ static int marvell_read_status(struct phy_device *phydev) break; } - if (phydev->duplex == DUPLEX_FULL) { - phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; - phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; + if (!fiber) { + phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) | + mii_lpa_to_ethtool_lpa_t(lpa); + + if (phydev->duplex == DUPLEX_FULL) { + phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; + phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; + } + } else { + /* The fiber link is only 1000M capable */ + phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa); + + if (phydev->duplex == DUPLEX_FULL) { + if (!(lpa & LPA_PAUSE_FIBER)) { + phydev->pause = 0; + phydev->asym_pause = 0; + } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) { + phydev->pause = 1; + phydev->asym_pause = 1; + } else { + phydev->pause = 1; + phydev->asym_pause = 0; + } + } } } else { int bmcr = phy_read(phydev, MII_BMCR); @@ -986,6 +1180,119 @@ static int marvell_read_status(struct phy_device *phydev) return 0; } +/* marvell_read_status + * + * Some Marvell's phys have two modes: fiber and copper. + * Both need status checked. + * Description: + * First, check the fiber link and status. + * If the fiber link is down, check the copper link and status which + * will be the default value if both link are down. + */ +static int marvell_read_status(struct phy_device *phydev) +{ + int err; + + /* Check the fiber mode first */ + if (phydev->supported & SUPPORTED_FIBRE) { + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER); + if (err < 0) + goto error; + + err = marvell_read_status_page(phydev, MII_M1111_FIBER); + if (err < 0) + goto error; + + /* If the fiber link is up, it is the selected and used link. + * In this case, we need to stay in the fiber page. + * Please to be careful about that, avoid to restore Copper page + * in other functions which could break the behaviour + * for some fiber phy like 88E1512. + * */ + if (phydev->link) + return 0; + + /* If fiber link is down, check and save copper mode state */ + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + if (err < 0) + goto error; + } + + return marvell_read_status_page(phydev, MII_M1111_COPPER); + +error: + phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + return err; +} + +/* marvell_suspend + * + * Some Marvell's phys have two modes: fiber and copper. + * Both need to be suspended + */ +static int marvell_suspend(struct phy_device *phydev) +{ + int err; + + /* Suspend the fiber mode first */ + if (!(phydev->supported & SUPPORTED_FIBRE)) { + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER); + if (err < 0) + goto error; + + /* With the page set, use the generic suspend */ + err = genphy_suspend(phydev); + if (err < 0) + goto error; + + /* Then, the copper link */ + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + if (err < 0) + goto error; + } + + /* With the page set, use the generic suspend */ + return genphy_suspend(phydev); + +error: + phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + return err; +} + +/* marvell_resume + * + * Some Marvell's phys have two modes: fiber and copper. + * Both need to be resumed + */ +static int marvell_resume(struct phy_device *phydev) +{ + int err; + + /* Resume the fiber mode first */ + if (!(phydev->supported & SUPPORTED_FIBRE)) { + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER); + if (err < 0) + goto error; + + /* With the page set, use the generic resume */ + err = genphy_resume(phydev); + if (err < 0) + goto error; + + /* Then, the copper link */ + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + if (err < 0) + goto error; + } + + /* With the page set, use the generic resume */ + return genphy_resume(phydev); + +error: + phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); + return err; +} + static int marvell_aneg_done(struct phy_device *phydev) { int retval = phy_read(phydev, MII_M1011_PHY_STATUS); @@ -1107,7 +1414,10 @@ static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *w static int marvell_get_sset_count(struct phy_device *phydev) { - return ARRAY_SIZE(marvell_hw_stats); + if (phydev->supported & SUPPORTED_FIBRE) + return ARRAY_SIZE(marvell_hw_stats); + else + return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS; } static void marvell_get_strings(struct phy_device *phydev, u8 *data) @@ -1361,7 +1671,7 @@ static struct phy_driver marvell_drivers[] = { .phy_id = MARVELL_PHY_ID_88E1510, .phy_id_mask = MARVELL_PHY_ID_MASK, .name = "Marvell 88E1510", - .features = PHY_GBIT_FEATURES, + .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE, .flags = PHY_HAS_INTERRUPT, .probe = marvell_probe, .config_init = &m88e1510_config_init, @@ -1370,8 +1680,8 @@ static struct phy_driver marvell_drivers[] = { .ack_interrupt = &marvell_ack_interrupt, .config_intr = &marvell_config_intr, .did_interrupt = &m88e1121_did_interrupt, - .resume = &genphy_resume, - .suspend = &genphy_suspend, + .resume = &marvell_resume, + .suspend = &marvell_suspend, .get_sset_count = marvell_get_sset_count, .get_strings = marvell_get_strings, .get_stats = marvell_get_stats, diff --git a/drivers/net/phy/mdio-hisi-femac.c b/drivers/net/phy/mdio-hisi-femac.c new file mode 100644 index 000000000000..b03fedd6c1d8 --- /dev/null +++ b/drivers/net/phy/mdio-hisi-femac.c @@ -0,0 +1,166 @@ +/* + * Hisilicon Fast Ethernet MDIO Bus Driver + * + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/clk.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_mdio.h> +#include <linux/platform_device.h> + +#define MDIO_RWCTRL 0x00 +#define MDIO_RO_DATA 0x04 +#define MDIO_WRITE BIT(13) +#define MDIO_RW_FINISH BIT(15) +#define BIT_PHY_ADDR_OFFSET 8 +#define BIT_WR_DATA_OFFSET 16 + +struct hisi_femac_mdio_data { + struct clk *clk; + void __iomem *membase; +}; + +static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data) +{ + u32 val; + + return readl_poll_timeout(data->membase + MDIO_RWCTRL, + val, val & MDIO_RW_FINISH, 20, 10000); +} + +static int hisi_femac_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + struct hisi_femac_mdio_data *data = bus->priv; + int ret; + + ret = hisi_femac_mdio_wait_ready(data); + if (ret) + return ret; + + writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum, + data->membase + MDIO_RWCTRL); + + ret = hisi_femac_mdio_wait_ready(data); + if (ret) + return ret; + + return readl(data->membase + MDIO_RO_DATA) & 0xFFFF; +} + +static int hisi_femac_mdio_write(struct mii_bus *bus, int mii_id, int regnum, + u16 value) +{ + struct hisi_femac_mdio_data *data = bus->priv; + int ret; + + ret = hisi_femac_mdio_wait_ready(data); + if (ret) + return ret; + + writel(MDIO_WRITE | (value << BIT_WR_DATA_OFFSET) | + (mii_id << BIT_PHY_ADDR_OFFSET) | regnum, + data->membase + MDIO_RWCTRL); + + return hisi_femac_mdio_wait_ready(data); +} + +static int hisi_femac_mdio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct mii_bus *bus; + struct hisi_femac_mdio_data *data; + struct resource *res; + int ret; + + bus = mdiobus_alloc_size(sizeof(*data)); + if (!bus) + return -ENOMEM; + + bus->name = "hisi_femac_mii_bus"; + bus->read = &hisi_femac_mdio_read; + bus->write = &hisi_femac_mdio_write; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name); + bus->parent = &pdev->dev; + + data = bus->priv; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->membase)) { + ret = PTR_ERR(data->membase); + goto err_out_free_mdiobus; + } + + data->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(data->clk)) { + ret = PTR_ERR(data->clk); + goto err_out_free_mdiobus; + } + + ret = clk_prepare_enable(data->clk); + if (ret) + goto err_out_free_mdiobus; + + ret = of_mdiobus_register(bus, np); + if (ret) + goto err_out_disable_clk; + + platform_set_drvdata(pdev, bus); + + return 0; + +err_out_disable_clk: + clk_disable_unprepare(data->clk); +err_out_free_mdiobus: + mdiobus_free(bus); + return ret; +} + +static int hisi_femac_mdio_remove(struct platform_device *pdev) +{ + struct mii_bus *bus = platform_get_drvdata(pdev); + struct hisi_femac_mdio_data *data = bus->priv; + + mdiobus_unregister(bus); + clk_disable_unprepare(data->clk); + mdiobus_free(bus); + + return 0; +} + +static const struct of_device_id hisi_femac_mdio_dt_ids[] = { + { .compatible = "hisilicon,hisi-femac-mdio" }, + { } +}; +MODULE_DEVICE_TABLE(of, hisi_femac_mdio_dt_ids); + +static struct platform_driver hisi_femac_mdio_driver = { + .probe = hisi_femac_mdio_probe, + .remove = hisi_femac_mdio_remove, + .driver = { + .name = "hisi-femac-mdio", + .of_match_table = hisi_femac_mdio_dt_ids, + }, +}; + +module_platform_driver(hisi_femac_mdio_driver); + +MODULE_DESCRIPTION("Hisilicon Fast Ethernet MAC MDIO interface driver"); +MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/phy/mdio-mux-bcm-iproc.c b/drivers/net/phy/mdio-mux-bcm-iproc.c new file mode 100644 index 000000000000..0a0412524cec --- /dev/null +++ b/drivers/net/phy/mdio-mux-bcm-iproc.c @@ -0,0 +1,248 @@ +/* + * Copyright 2016 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation (the "GPL"). + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License version 2 (GPLv2) for more details. + * + * You should have received a copy of the GNU General Public License + * version 2 (GPLv2) along with this source code. + */ + +#include <linux/platform_device.h> +#include <linux/device.h> +#include <linux/of_mdio.h> +#include <linux/module.h> +#include <linux/phy.h> +#include <linux/mdio-mux.h> +#include <linux/delay.h> + +#define MDIO_PARAM_OFFSET 0x00 +#define MDIO_PARAM_MIIM_CYCLE 29 +#define MDIO_PARAM_INTERNAL_SEL 25 +#define MDIO_PARAM_BUS_ID 22 +#define MDIO_PARAM_C45_SEL 21 +#define MDIO_PARAM_PHY_ID 16 +#define MDIO_PARAM_PHY_DATA 0 + +#define MDIO_READ_OFFSET 0x04 +#define MDIO_READ_DATA_MASK 0xffff +#define MDIO_ADDR_OFFSET 0x08 + +#define MDIO_CTRL_OFFSET 0x0C +#define MDIO_CTRL_WRITE_OP 0x1 +#define MDIO_CTRL_READ_OP 0x2 + +#define MDIO_STAT_OFFSET 0x10 +#define MDIO_STAT_DONE 1 + +#define BUS_MAX_ADDR 32 +#define EXT_BUS_START_ADDR 16 + +struct iproc_mdiomux_desc { + void *mux_handle; + void __iomem *base; + struct device *dev; + struct mii_bus *mii_bus; +}; + +static int iproc_mdio_wait_for_idle(void __iomem *base, bool result) +{ + unsigned int timeout = 1000; /* loop for 1s */ + u32 val; + + do { + val = readl(base + MDIO_STAT_OFFSET); + if ((val & MDIO_STAT_DONE) == result) + return 0; + + usleep_range(1000, 2000); + } while (timeout--); + + return -ETIMEDOUT; +} + +/* start_miim_ops- Program and start MDIO transaction over mdio bus. + * @base: Base address + * @phyid: phyid of the selected bus. + * @reg: register offset to be read/written. + * @val :0 if read op else value to be written in @reg; + * @op: Operation that need to be carried out. + * MDIO_CTRL_READ_OP: Read transaction. + * MDIO_CTRL_WRITE_OP: Write transaction. + * + * Return value: Successful Read operation returns read reg values and write + * operation returns 0. Failure operation returns negative error code. + */ +static int start_miim_ops(void __iomem *base, + u16 phyid, u32 reg, u16 val, u32 op) +{ + u32 param; + int ret; + + writel(0, base + MDIO_CTRL_OFFSET); + ret = iproc_mdio_wait_for_idle(base, 0); + if (ret) + goto err; + + param = readl(base + MDIO_PARAM_OFFSET); + param |= phyid << MDIO_PARAM_PHY_ID; + param |= val << MDIO_PARAM_PHY_DATA; + if (reg & MII_ADDR_C45) + param |= BIT(MDIO_PARAM_C45_SEL); + + writel(param, base + MDIO_PARAM_OFFSET); + + writel(reg, base + MDIO_ADDR_OFFSET); + + writel(op, base + MDIO_CTRL_OFFSET); + + ret = iproc_mdio_wait_for_idle(base, 1); + if (ret) + goto err; + + if (op == MDIO_CTRL_READ_OP) + ret = readl(base + MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK; +err: + return ret; +} + +static int iproc_mdiomux_read(struct mii_bus *bus, int phyid, int reg) +{ + struct iproc_mdiomux_desc *md = bus->priv; + int ret; + + ret = start_miim_ops(md->base, phyid, reg, 0, MDIO_CTRL_READ_OP); + if (ret < 0) + dev_err(&bus->dev, "mdiomux read operation failed!!!"); + + return ret; +} + +static int iproc_mdiomux_write(struct mii_bus *bus, + int phyid, int reg, u16 val) +{ + struct iproc_mdiomux_desc *md = bus->priv; + int ret; + + /* Write val at reg offset */ + ret = start_miim_ops(md->base, phyid, reg, val, MDIO_CTRL_WRITE_OP); + if (ret < 0) + dev_err(&bus->dev, "mdiomux write operation failed!!!"); + + return ret; +} + +static int mdio_mux_iproc_switch_fn(int current_child, int desired_child, + void *data) +{ + struct iproc_mdiomux_desc *md = data; + u32 param, bus_id; + bool bus_dir; + + /* select bus and its properties */ + bus_dir = (desired_child < EXT_BUS_START_ADDR); + bus_id = bus_dir ? desired_child : (desired_child - EXT_BUS_START_ADDR); + + param = (bus_dir ? 1 : 0) << MDIO_PARAM_INTERNAL_SEL; + param |= (bus_id << MDIO_PARAM_BUS_ID); + + writel(param, md->base + MDIO_PARAM_OFFSET); + return 0; +} + +static int mdio_mux_iproc_probe(struct platform_device *pdev) +{ + struct iproc_mdiomux_desc *md; + struct mii_bus *bus; + struct resource *res; + int rc; + + md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL); + if (!md) + return -ENOMEM; + md->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + md->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(md->base)) { + dev_err(&pdev->dev, "failed to ioremap register\n"); + return PTR_ERR(md->base); + } + + md->mii_bus = mdiobus_alloc(); + if (!md->mii_bus) { + dev_err(&pdev->dev, "mdiomux bus alloc failed\n"); + return -ENOMEM; + } + + bus = md->mii_bus; + bus->priv = md; + bus->name = "iProc MDIO mux bus"; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id); + bus->parent = &pdev->dev; + bus->read = iproc_mdiomux_read; + bus->write = iproc_mdiomux_write; + + bus->phy_mask = ~0; + bus->dev.of_node = pdev->dev.of_node; + rc = mdiobus_register(bus); + if (rc) { + dev_err(&pdev->dev, "mdiomux registration failed\n"); + goto out; + } + + platform_set_drvdata(pdev, md); + + rc = mdio_mux_init(md->dev, mdio_mux_iproc_switch_fn, + &md->mux_handle, md, md->mii_bus); + if (rc) { + dev_info(md->dev, "mdiomux initialization failed\n"); + goto out; + } + + dev_info(md->dev, "iProc mdiomux registered\n"); + return 0; +out: + mdiobus_free(bus); + return rc; +} + +static int mdio_mux_iproc_remove(struct platform_device *pdev) +{ + struct iproc_mdiomux_desc *md = dev_get_platdata(&pdev->dev); + + mdio_mux_uninit(md->mux_handle); + mdiobus_unregister(md->mii_bus); + mdiobus_free(md->mii_bus); + + return 0; +} + +static const struct of_device_id mdio_mux_iproc_match[] = { + { + .compatible = "brcm,mdio-mux-iproc", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mdio_mux_iproc_match); + +static struct platform_driver mdiomux_iproc_driver = { + .driver = { + .name = "mdio-mux-iproc", + .of_match_table = mdio_mux_iproc_match, + }, + .probe = mdio_mux_iproc_probe, + .remove = mdio_mux_iproc_remove, +}; + +module_platform_driver(mdiomux_iproc_driver); + +MODULE_DESCRIPTION("iProc MDIO Mux Bus Driver"); +MODULE_AUTHOR("Pramod Kumar <pramod.kumar@broadcom.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/phy/mdio-mux-gpio.c b/drivers/net/phy/mdio-mux-gpio.c index 7ddb1ab70891..919949960a10 100644 --- a/drivers/net/phy/mdio-mux-gpio.c +++ b/drivers/net/phy/mdio-mux-gpio.c @@ -55,7 +55,7 @@ static int mdio_mux_gpio_probe(struct platform_device *pdev) return PTR_ERR(s->gpios); r = mdio_mux_init(&pdev->dev, - mdio_mux_gpio_switch_fn, &s->mux_handle, s); + mdio_mux_gpio_switch_fn, &s->mux_handle, s, NULL); if (r != 0) { gpiod_put_array(s->gpios); diff --git a/drivers/net/phy/mdio-mux-mmioreg.c b/drivers/net/phy/mdio-mux-mmioreg.c index 7fde454fbc4f..d0bed52c8d16 100644 --- a/drivers/net/phy/mdio-mux-mmioreg.c +++ b/drivers/net/phy/mdio-mux-mmioreg.c @@ -126,7 +126,7 @@ static int mdio_mux_mmioreg_probe(struct platform_device *pdev) } ret = mdio_mux_init(&pdev->dev, mdio_mux_mmioreg_switch_fn, - &s->mux_handle, s); + &s->mux_handle, s, NULL); if (ret) { dev_err(&pdev->dev, "failed to register mdio-mux bus %s\n", np->full_name); diff --git a/drivers/net/phy/mdio-mux.c b/drivers/net/phy/mdio-mux.c index 5c81d6faf304..963838d4fac1 100644 --- a/drivers/net/phy/mdio-mux.c +++ b/drivers/net/phy/mdio-mux.c @@ -89,7 +89,8 @@ static int parent_count; int mdio_mux_init(struct device *dev, int (*switch_fn)(int cur, int desired, void *data), void **mux_handle, - void *data) + void *data, + struct mii_bus *mux_bus) { struct device_node *parent_bus_node; struct device_node *child_bus_node; @@ -101,10 +102,22 @@ int mdio_mux_init(struct device *dev, if (!dev->of_node) return -ENODEV; - parent_bus_node = of_parse_phandle(dev->of_node, "mdio-parent-bus", 0); + if (!mux_bus) { + parent_bus_node = of_parse_phandle(dev->of_node, + "mdio-parent-bus", 0); - if (!parent_bus_node) - return -ENODEV; + if (!parent_bus_node) + return -ENODEV; + + parent_bus = of_mdio_find_bus(parent_bus_node); + if (!parent_bus) { + ret_val = -EPROBE_DEFER; + goto err_parent_bus; + } + } else { + parent_bus_node = NULL; + parent_bus = mux_bus; + } pb = devm_kzalloc(dev, sizeof(*pb), GFP_KERNEL); if (pb == NULL) { @@ -112,11 +125,6 @@ int mdio_mux_init(struct device *dev, goto err_parent_bus; } - parent_bus = of_mdio_find_bus(parent_bus_node); - if (parent_bus == NULL) { - ret_val = -EPROBE_DEFER; - goto err_parent_bus; - } pb->switch_data = data; pb->switch_fn = switch_fn; diff --git a/drivers/net/phy/mdio-xgene.c b/drivers/net/phy/mdio-xgene.c new file mode 100644 index 000000000000..d94a978024d9 --- /dev/null +++ b/drivers/net/phy/mdio-xgene.c @@ -0,0 +1,477 @@ +/* Applied Micro X-Gene SoC MDIO Driver + * + * Copyright (c) 2016, Applied Micro Circuits Corporation + * Author: Iyappan Subramanian <isubramanian@apm.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/acpi.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/efi.h> +#include <linux/if_vlan.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/of_net.h> +#include <linux/of_mdio.h> +#include <linux/prefetch.h> +#include <linux/phy.h> +#include <net/ip.h> +#include "mdio-xgene.h" + +static bool xgene_mdio_status; + +static u32 xgene_enet_rd_mac(void __iomem *base_addr, u32 rd_addr) +{ + void __iomem *addr, *rd, *cmd, *cmd_done; + u32 done, rd_data = BUSY_MASK; + u8 wait = 10; + + addr = base_addr + MAC_ADDR_REG_OFFSET; + rd = base_addr + MAC_READ_REG_OFFSET; + cmd = base_addr + MAC_COMMAND_REG_OFFSET; + cmd_done = base_addr + MAC_COMMAND_DONE_REG_OFFSET; + + iowrite32(rd_addr, addr); + iowrite32(XGENE_ENET_RD_CMD, cmd); + + while (wait--) { + done = ioread32(cmd_done); + if (done) + break; + udelay(1); + } + + if (!done) + return rd_data; + + rd_data = ioread32(rd); + iowrite32(0, cmd); + + return rd_data; +} + +static void xgene_enet_wr_mac(void __iomem *base_addr, u32 wr_addr, u32 wr_data) +{ + void __iomem *addr, *wr, *cmd, *cmd_done; + u8 wait = 10; + u32 done; + + addr = base_addr + MAC_ADDR_REG_OFFSET; + wr = base_addr + MAC_WRITE_REG_OFFSET; + cmd = base_addr + MAC_COMMAND_REG_OFFSET; + cmd_done = base_addr + MAC_COMMAND_DONE_REG_OFFSET; + + iowrite32(wr_addr, addr); + iowrite32(wr_data, wr); + iowrite32(XGENE_ENET_WR_CMD, cmd); + + while (wait--) { + done = ioread32(cmd_done); + if (done) + break; + udelay(1); + } + + if (!done) + pr_err("MCX mac write failed, addr: 0x%04x\n", wr_addr); + + iowrite32(0, cmd); +} + +int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg) +{ + void __iomem *addr = (void __iomem *)bus->priv; + u32 data, done; + u8 wait = 10; + + data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); + xgene_enet_wr_mac(addr, MII_MGMT_ADDRESS_ADDR, data); + xgene_enet_wr_mac(addr, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); + do { + usleep_range(5, 10); + done = xgene_enet_rd_mac(addr, MII_MGMT_INDICATORS_ADDR); + } while ((done & BUSY_MASK) && wait--); + + if (done & BUSY_MASK) { + dev_err(&bus->dev, "MII_MGMT read failed\n"); + return -EBUSY; + } + + data = xgene_enet_rd_mac(addr, MII_MGMT_STATUS_ADDR); + xgene_enet_wr_mac(addr, MII_MGMT_COMMAND_ADDR, 0); + + return data; +} +EXPORT_SYMBOL(xgene_mdio_rgmii_read); + +int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data) +{ + void __iomem *addr = (void __iomem *)bus->priv; + u32 val, done; + u8 wait = 10; + + val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); + xgene_enet_wr_mac(addr, MII_MGMT_ADDRESS_ADDR, val); + + xgene_enet_wr_mac(addr, MII_MGMT_CONTROL_ADDR, data); + do { + usleep_range(5, 10); + done = xgene_enet_rd_mac(addr, MII_MGMT_INDICATORS_ADDR); + } while ((done & BUSY_MASK) && wait--); + + if (done & BUSY_MASK) { + dev_err(&bus->dev, "MII_MGMT write failed\n"); + return -EBUSY; + } + + return 0; +} +EXPORT_SYMBOL(xgene_mdio_rgmii_write); + +static u32 xgene_menet_rd_diag_csr(struct xgene_mdio_pdata *pdata, u32 offset) +{ + return ioread32(pdata->diag_csr_addr + offset); +} + +static void xgene_menet_wr_diag_csr(struct xgene_mdio_pdata *pdata, + u32 offset, u32 val) +{ + iowrite32(val, pdata->diag_csr_addr + offset); +} + +static int xgene_enet_ecc_init(struct xgene_mdio_pdata *pdata) +{ + u32 data; + u8 wait = 10; + + xgene_menet_wr_diag_csr(pdata, MENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0); + do { + usleep_range(100, 110); + data = xgene_menet_rd_diag_csr(pdata, MENET_BLOCK_MEM_RDY_ADDR); + } while ((data != 0xffffffff) && wait--); + + if (data != 0xffffffff) { + dev_err(pdata->dev, "Failed to release memory from shutdown\n"); + return -ENODEV; + } + + return 0; +} + +static void xgene_gmac_reset(struct xgene_mdio_pdata *pdata) +{ + xgene_enet_wr_mac(pdata->mac_csr_addr, MAC_CONFIG_1_ADDR, SOFT_RESET); + xgene_enet_wr_mac(pdata->mac_csr_addr, MAC_CONFIG_1_ADDR, 0); +} + +static int xgene_mdio_reset(struct xgene_mdio_pdata *pdata) +{ + int ret; + + if (pdata->dev->of_node) { + clk_prepare_enable(pdata->clk); + udelay(5); + clk_disable_unprepare(pdata->clk); + udelay(5); + clk_prepare_enable(pdata->clk); + udelay(5); + } else { +#ifdef CONFIG_ACPI + acpi_evaluate_object(ACPI_HANDLE(pdata->dev), + "_RST", NULL, NULL); +#endif + } + + ret = xgene_enet_ecc_init(pdata); + if (ret) + return ret; + xgene_gmac_reset(pdata); + + return 0; +} + +static void xgene_enet_rd_mdio_csr(void __iomem *base_addr, + u32 offset, u32 *val) +{ + void __iomem *addr = base_addr + offset; + + *val = ioread32(addr); +} + +static void xgene_enet_wr_mdio_csr(void __iomem *base_addr, + u32 offset, u32 val) +{ + void __iomem *addr = base_addr + offset; + + iowrite32(val, addr); +} + +static int xgene_xfi_mdio_write(struct mii_bus *bus, int phy_id, + int reg, u16 data) +{ + void __iomem *addr = (void __iomem *)bus->priv; + int timeout = 100; + u32 status, val; + + val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg) | + SET_VAL(HSTMIIMWRDAT, data); + xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, data); + + val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_WRITE); + xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val); + + do { + usleep_range(5, 10); + xgene_enet_rd_mdio_csr(addr, MIIM_INDICATOR_ADDR, &status); + } while ((status & BUSY_MASK) && timeout--); + + xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, 0); + + return 0; +} + +static int xgene_xfi_mdio_read(struct mii_bus *bus, int phy_id, int reg) +{ + void __iomem *addr = (void __iomem *)bus->priv; + u32 data, status, val; + int timeout = 100; + + val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg); + xgene_enet_wr_mdio_csr(addr, MIIM_FIELD_ADDR, val); + + val = HSTLDCMD | SET_VAL(HSTMIIMCMD, MIIM_CMD_LEGACY_READ); + xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, val); + + do { + usleep_range(5, 10); + xgene_enet_rd_mdio_csr(addr, MIIM_INDICATOR_ADDR, &status); + } while ((status & BUSY_MASK) && timeout--); + + if (status & BUSY_MASK) { + pr_err("XGENET_MII_MGMT write failed\n"); + return -EBUSY; + } + + xgene_enet_rd_mdio_csr(addr, MIIMRD_FIELD_ADDR, &data); + xgene_enet_wr_mdio_csr(addr, MIIM_COMMAND_ADDR, 0); + + return data; +} + +struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr) +{ + struct phy_device *phy_dev; + + phy_dev = get_phy_device(bus, phy_addr, false); + if (!phy_dev || IS_ERR(phy_dev)) + return NULL; + + if (phy_device_register(phy_dev)) + phy_device_free(phy_dev); + + return phy_dev; +} +EXPORT_SYMBOL(xgene_enet_phy_register); + +#ifdef CONFIG_ACPI +static acpi_status acpi_register_phy(acpi_handle handle, u32 lvl, + void *context, void **ret) +{ + struct mii_bus *mdio = context; + struct acpi_device *adev; + struct phy_device *phy_dev; + const union acpi_object *obj; + u32 phy_addr; + + if (acpi_bus_get_device(handle, &adev)) + return AE_OK; + + if (acpi_dev_get_property(adev, "phy-channel", ACPI_TYPE_INTEGER, &obj)) + return AE_OK; + phy_addr = obj->integer.value; + + phy_dev = xgene_enet_phy_register(mdio, phy_addr); + adev->driver_data = phy_dev; + + return AE_OK; +} +#endif + +static int xgene_mdio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mii_bus *mdio_bus; + const struct of_device_id *of_id; + struct resource *res; + struct xgene_mdio_pdata *pdata; + void __iomem *csr_base; + int mdio_id = 0, ret = 0; + + of_id = of_match_device(xgene_mdio_of_match, &pdev->dev); + if (of_id) { + mdio_id = (enum xgene_mdio_id)of_id->data; + } else { +#ifdef CONFIG_ACPI + const struct acpi_device_id *acpi_id; + + acpi_id = acpi_match_device(xgene_mdio_acpi_match, &pdev->dev); + if (acpi_id) + mdio_id = (enum xgene_mdio_id)acpi_id->driver_data; +#endif + } + + if (!mdio_id) + return -ENODEV; + + pdata = devm_kzalloc(dev, sizeof(struct xgene_mdio_pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + pdata->mdio_id = mdio_id; + pdata->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + csr_base = devm_ioremap_resource(dev, res); + if (IS_ERR(csr_base)) { + dev_err(dev, "Unable to retrieve mac CSR region\n"); + return PTR_ERR(csr_base); + } + pdata->mac_csr_addr = csr_base; + pdata->mdio_csr_addr = csr_base + BLOCK_XG_MDIO_CSR_OFFSET; + pdata->diag_csr_addr = csr_base + BLOCK_DIAG_CSR_OFFSET; + + if (dev->of_node) { + pdata->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pdata->clk)) { + dev_err(dev, "Unable to retrieve clk\n"); + return PTR_ERR(pdata->clk); + } + } + + ret = xgene_mdio_reset(pdata); + if (ret) + return ret; + + mdio_bus = mdiobus_alloc(); + if (!mdio_bus) + return -ENOMEM; + + mdio_bus->name = "APM X-Gene MDIO bus"; + + if (mdio_id == XGENE_MDIO_RGMII) { + mdio_bus->read = xgene_mdio_rgmii_read; + mdio_bus->write = xgene_mdio_rgmii_write; + mdio_bus->priv = (void __force *)pdata->mac_csr_addr; + snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s", + "xgene-mii-rgmii"); + } else { + mdio_bus->read = xgene_xfi_mdio_read; + mdio_bus->write = xgene_xfi_mdio_write; + mdio_bus->priv = (void __force *)pdata->mdio_csr_addr; + snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s", + "xgene-mii-xfi"); + } + + mdio_bus->parent = dev; + platform_set_drvdata(pdev, pdata); + + if (dev->of_node) { + ret = of_mdiobus_register(mdio_bus, dev->of_node); + } else { +#ifdef CONFIG_ACPI + /* Mask out all PHYs from auto probing. */ + mdio_bus->phy_mask = ~0; + ret = mdiobus_register(mdio_bus); + if (ret) + goto out; + + acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_HANDLE(dev), 1, + acpi_register_phy, NULL, mdio_bus, NULL); +#endif + } + + if (ret) + goto out; + + pdata->mdio_bus = mdio_bus; + xgene_mdio_status = true; + + return 0; + +out: + mdiobus_free(mdio_bus); + + return ret; +} + +static int xgene_mdio_remove(struct platform_device *pdev) +{ + struct xgene_mdio_pdata *pdata = platform_get_drvdata(pdev); + struct mii_bus *mdio_bus = pdata->mdio_bus; + struct device *dev = &pdev->dev; + + mdiobus_unregister(mdio_bus); + mdiobus_free(mdio_bus); + + if (dev->of_node) { + if (IS_ERR(pdata->clk)) + clk_disable_unprepare(pdata->clk); + } + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id xgene_mdio_of_match[] = { + { + .compatible = "apm,xgene-mdio-rgmii", + .data = (void *)XGENE_MDIO_RGMII + }, + { + .compatible = "apm,xgene-mdio-xfi", + .data = (void *)XGENE_MDIO_XFI + }, + {}, +}; + +MODULE_DEVICE_TABLE(of, xgene_mdio_of_match); +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id xgene_mdio_acpi_match[] = { + { "APMC0D65", XGENE_MDIO_RGMII }, + { "APMC0D66", XGENE_MDIO_XFI }, + { } +}; + +MODULE_DEVICE_TABLE(acpi, xgene_mdio_acpi_match); +#endif + +static struct platform_driver xgene_mdio_driver = { + .driver = { + .name = "xgene-mdio", + .of_match_table = of_match_ptr(xgene_mdio_of_match), + .acpi_match_table = ACPI_PTR(xgene_mdio_acpi_match), + }, + .probe = xgene_mdio_probe, + .remove = xgene_mdio_remove, +}; + +module_platform_driver(xgene_mdio_driver); + +MODULE_DESCRIPTION("APM X-Gene SoC MDIO driver"); +MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/phy/mdio-xgene.h b/drivers/net/phy/mdio-xgene.h new file mode 100644 index 000000000000..354241b53c1d --- /dev/null +++ b/drivers/net/phy/mdio-xgene.h @@ -0,0 +1,143 @@ +/* Applied Micro X-Gene SoC MDIO Driver + * + * Copyright (c) 2016, Applied Micro Circuits Corporation + * Author: Iyappan Subramanian <isubramanian@apm.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __MDIO_XGENE_H__ +#define __MDIO_XGENE_H__ + +#define BLOCK_XG_MDIO_CSR_OFFSET 0x5000 +#define BLOCK_DIAG_CSR_OFFSET 0xd000 +#define XGENET_CONFIG_REG_ADDR 0x20 + +#define MAC_ADDR_REG_OFFSET 0x00 +#define MAC_COMMAND_REG_OFFSET 0x04 +#define MAC_WRITE_REG_OFFSET 0x08 +#define MAC_READ_REG_OFFSET 0x0c +#define MAC_COMMAND_DONE_REG_OFFSET 0x10 + +#define CLKEN_OFFSET 0x08 +#define SRST_OFFSET 0x00 + +#define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 +#define MENET_BLOCK_MEM_RDY_ADDR 0x74 + +#define MAC_CONFIG_1_ADDR 0x00 +#define MII_MGMT_COMMAND_ADDR 0x24 +#define MII_MGMT_ADDRESS_ADDR 0x28 +#define MII_MGMT_CONTROL_ADDR 0x2c +#define MII_MGMT_STATUS_ADDR 0x30 +#define MII_MGMT_INDICATORS_ADDR 0x34 +#define SOFT_RESET BIT(31) + +#define MII_MGMT_CONFIG_ADDR 0x20 +#define MII_MGMT_COMMAND_ADDR 0x24 +#define MII_MGMT_ADDRESS_ADDR 0x28 +#define MII_MGMT_CONTROL_ADDR 0x2c +#define MII_MGMT_STATUS_ADDR 0x30 +#define MII_MGMT_INDICATORS_ADDR 0x34 + +#define MIIM_COMMAND_ADDR 0x20 +#define MIIM_FIELD_ADDR 0x24 +#define MIIM_CONFIGURATION_ADDR 0x28 +#define MIIM_LINKFAILVECTOR_ADDR 0x2c +#define MIIM_INDICATOR_ADDR 0x30 +#define MIIMRD_FIELD_ADDR 0x34 + +#define MDIO_CSR_OFFSET 0x5000 + +#define REG_ADDR_POS 0 +#define REG_ADDR_LEN 5 +#define PHY_ADDR_POS 8 +#define PHY_ADDR_LEN 5 + +#define HSTMIIMWRDAT_POS 0 +#define HSTMIIMWRDAT_LEN 16 +#define HSTPHYADX_POS 23 +#define HSTPHYADX_LEN 5 +#define HSTREGADX_POS 18 +#define HSTREGADX_LEN 5 +#define HSTLDCMD BIT(3) +#define HSTMIIMCMD_POS 0 +#define HSTMIIMCMD_LEN 3 + +#define BUSY_MASK BIT(0) +#define READ_CYCLE_MASK BIT(0) + +enum xgene_enet_cmd { + XGENE_ENET_WR_CMD = BIT(31), + XGENE_ENET_RD_CMD = BIT(30) +}; + +enum { + MIIM_CMD_IDLE, + MIIM_CMD_LEGACY_WRITE, + MIIM_CMD_LEGACY_READ, +}; + +enum xgene_mdio_id { + XGENE_MDIO_RGMII = 1, + XGENE_MDIO_XFI +}; + +struct xgene_mdio_pdata { + struct clk *clk; + struct device *dev; + void __iomem *mac_csr_addr; + void __iomem *diag_csr_addr; + void __iomem *mdio_csr_addr; + struct mii_bus *mdio_bus; + int mdio_id; +}; + +/* Set the specified value into a bit-field defined by its starting position + * and length within a single u64. + */ +static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val) +{ + return (val & ((1ULL << len) - 1)) << pos; +} + +#define SET_VAL(field, val) \ + xgene_enet_set_field_value(field ## _POS, field ## _LEN, val) + +#define SET_BIT(field) \ + xgene_enet_set_field_value(field ## _POS, 1, 1) + +/* Get the value from a bit-field defined by its starting position + * and length within the specified u64. + */ +static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src) +{ + return (src >> pos) & ((1ULL << len) - 1); +} + +#define GET_VAL(field, src) \ + xgene_enet_get_field_value(field ## _POS, field ## _LEN, src) + +#define GET_BIT(field, src) \ + xgene_enet_get_field_value(field ## _POS, 1, src) + +static const struct of_device_id xgene_mdio_of_match[]; +#ifdef CONFIG_ACPI +static const struct acpi_device_id xgene_mdio_acpi_match[]; +#endif +int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg); +int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data); +struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr); + +#endif /* __MDIO_XGENE_H__ */ diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5a8fefc25157..059f13b60fe0 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -311,6 +311,36 @@ static int kszphy_config_init(struct phy_device *phydev) return 0; } +static int ksz8041_config_init(struct phy_device *phydev) +{ + struct device_node *of_node = phydev->mdio.dev.of_node; + + /* Limit supported and advertised modes in fiber mode */ + if (of_property_read_bool(of_node, "micrel,fiber-mode")) { + phydev->dev_flags |= MICREL_PHY_FXEN; + phydev->supported &= SUPPORTED_FIBRE | + SUPPORTED_100baseT_Full | + SUPPORTED_100baseT_Half; + phydev->advertising &= ADVERTISED_FIBRE | + ADVERTISED_100baseT_Full | + ADVERTISED_100baseT_Half; + phydev->autoneg = AUTONEG_DISABLE; + } + + return kszphy_config_init(phydev); +} + +static int ksz8041_config_aneg(struct phy_device *phydev) +{ + /* Skip auto-negotiation in fiber mode */ + if (phydev->dev_flags & MICREL_PHY_FXEN) { + phydev->speed = SPEED_100; + return 0; + } + + return genphy_config_aneg(phydev); +} + static int ksz9021_load_values_from_of(struct phy_device *phydev, const struct device_node *of_node, u16 reg, @@ -788,8 +818,8 @@ static struct phy_driver ksphy_driver[] = { .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, .driver_data = &ksz8041_type, .probe = kszphy_probe, - .config_init = kszphy_config_init, - .config_aneg = genphy_config_aneg, + .config_init = ksz8041_config_init, + .config_aneg = ksz8041_config_aneg, .read_status = genphy_read_status, .ack_interrupt = kszphy_ack_interrupt, .config_intr = kszphy_config_intr, diff --git a/drivers/net/phy/swphy.c b/drivers/net/phy/swphy.c new file mode 100644 index 000000000000..34f58f2349e9 --- /dev/null +++ b/drivers/net/phy/swphy.c @@ -0,0 +1,179 @@ +/* + * Software PHY emulation + * + * Code taken from fixed_phy.c by Russell King <rmk+kernel@arm.linux.org.uk> + * + * Author: Vitaly Bordug <vbordug@ru.mvista.com> + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * Copyright (c) 2006-2007 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/export.h> +#include <linux/mii.h> +#include <linux/phy.h> +#include <linux/phy_fixed.h> + +#include "swphy.h" + +#define MII_REGS_NUM 29 + +struct swmii_regs { + u16 bmcr; + u16 bmsr; + u16 lpa; + u16 lpagb; +}; + +enum { + SWMII_SPEED_10 = 0, + SWMII_SPEED_100, + SWMII_SPEED_1000, + SWMII_DUPLEX_HALF = 0, + SWMII_DUPLEX_FULL, +}; + +/* + * These two tables get bitwise-anded together to produce the final result. + * This means the speed table must contain both duplex settings, and the + * duplex table must contain all speed settings. + */ +static const struct swmii_regs speed[] = { + [SWMII_SPEED_10] = { + .bmcr = BMCR_FULLDPLX, + .lpa = LPA_10FULL | LPA_10HALF, + }, + [SWMII_SPEED_100] = { + .bmcr = BMCR_FULLDPLX | BMCR_SPEED100, + .bmsr = BMSR_100FULL | BMSR_100HALF, + .lpa = LPA_100FULL | LPA_100HALF, + }, + [SWMII_SPEED_1000] = { + .bmcr = BMCR_FULLDPLX | BMCR_SPEED1000, + .bmsr = BMSR_ESTATEN, + .lpagb = LPA_1000FULL | LPA_1000HALF, + }, +}; + +static const struct swmii_regs duplex[] = { + [SWMII_DUPLEX_HALF] = { + .bmcr = ~BMCR_FULLDPLX, + .bmsr = BMSR_ESTATEN | BMSR_100HALF, + .lpa = LPA_10HALF | LPA_100HALF, + .lpagb = LPA_1000HALF, + }, + [SWMII_DUPLEX_FULL] = { + .bmcr = ~0, + .bmsr = BMSR_ESTATEN | BMSR_100FULL, + .lpa = LPA_10FULL | LPA_100FULL, + .lpagb = LPA_1000FULL, + }, +}; + +static int swphy_decode_speed(int speed) +{ + switch (speed) { + case 1000: + return SWMII_SPEED_1000; + case 100: + return SWMII_SPEED_100; + case 10: + return SWMII_SPEED_10; + default: + return -EINVAL; + } +} + +/** + * swphy_validate_state - validate the software phy status + * @state: software phy status + * + * This checks that we can represent the state stored in @state can be + * represented in the emulated MII registers. Returns 0 if it can, + * otherwise returns -EINVAL. + */ +int swphy_validate_state(const struct fixed_phy_status *state) +{ + int err; + + if (state->link) { + err = swphy_decode_speed(state->speed); + if (err < 0) { + pr_warn("swphy: unknown speed\n"); + return -EINVAL; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(swphy_validate_state); + +/** + * swphy_read_reg - return a MII register from the fixed phy state + * @reg: MII register + * @state: fixed phy status + * + * Return the MII @reg register generated from the fixed phy state @state. + */ +int swphy_read_reg(int reg, const struct fixed_phy_status *state) +{ + int speed_index, duplex_index; + u16 bmsr = BMSR_ANEGCAPABLE; + u16 bmcr = 0; + u16 lpagb = 0; + u16 lpa = 0; + + if (reg > MII_REGS_NUM) + return -1; + + speed_index = swphy_decode_speed(state->speed); + if (WARN_ON(speed_index < 0)) + return 0; + + duplex_index = state->duplex ? SWMII_DUPLEX_FULL : SWMII_DUPLEX_HALF; + + bmsr |= speed[speed_index].bmsr & duplex[duplex_index].bmsr; + + if (state->link) { + bmsr |= BMSR_LSTATUS | BMSR_ANEGCOMPLETE; + + bmcr |= speed[speed_index].bmcr & duplex[duplex_index].bmcr; + lpa |= speed[speed_index].lpa & duplex[duplex_index].lpa; + lpagb |= speed[speed_index].lpagb & duplex[duplex_index].lpagb; + + if (state->pause) + lpa |= LPA_PAUSE_CAP; + + if (state->asym_pause) + lpa |= LPA_PAUSE_ASYM; + } + + switch (reg) { + case MII_BMCR: + return bmcr; + case MII_BMSR: + return bmsr; + case MII_PHYSID1: + case MII_PHYSID2: + return 0; + case MII_LPA: + return lpa; + case MII_STAT1000: + return lpagb; + + /* + * We do not support emulating Clause 45 over Clause 22 register + * reads. Return an error instead of bogus data. + */ + case MII_MMD_CTRL: + case MII_MMD_DATA: + return -1; + + default: + return 0xffff; + } +} +EXPORT_SYMBOL_GPL(swphy_read_reg); diff --git a/drivers/net/phy/swphy.h b/drivers/net/phy/swphy.h new file mode 100644 index 000000000000..2f09ac324e18 --- /dev/null +++ b/drivers/net/phy/swphy.h @@ -0,0 +1,9 @@ +#ifndef SWPHY_H +#define SWPHY_H + +struct fixed_phy_status; + +int swphy_validate_state(const struct fixed_phy_status *state); +int swphy_read_reg(int reg, const struct fixed_phy_status *state); + +#endif |