diff options
Diffstat (limited to 'drivers/pinctrl')
28 files changed, 5090 insertions, 91 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 99a4c10ed43f..a4c07394e313 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -168,37 +168,6 @@ config PINCTRL_ST select PINCONF select GPIOLIB_IRQCHIP -config PINCTRL_TEGRA - bool - select PINMUX - select PINCONF - -config PINCTRL_TEGRA20 - bool - select PINCTRL_TEGRA - -config PINCTRL_TEGRA30 - bool - select PINCTRL_TEGRA - -config PINCTRL_TEGRA114 - bool - select PINCTRL_TEGRA - -config PINCTRL_TEGRA124 - bool - select PINCTRL_TEGRA - -config PINCTRL_TEGRA210 - bool - select PINCTRL_TEGRA - -config PINCTRL_TEGRA_XUSB - def_bool y if ARCH_TEGRA - select GENERIC_PHY - select PINCONF - select PINMUX - config PINCTRL_TZ1090 bool "Toumaz Xenif TZ1090 pin control driver" depends on SOC_TZ1090 @@ -238,6 +207,23 @@ config PINCTRL_PALMAS open drain configuration for the Palmas series devices like TPS65913, TPS80036 etc. +config PINCTRL_PIC32 + bool "Microchip PIC32 pin controller driver" + depends on OF + depends on MACH_PIC32 + select PINMUX + select GENERIC_PINCONF + select GPIOLIB_IRQCHIP + select OF_GPIO + help + This is the pin controller and gpio driver for Microchip PIC32 + microcontrollers. This option is selected automatically when specific + machine and arch are selected to build. + +config PINCTRL_PIC32MZDA + def_bool y if PIC32MZDA + select PINCTRL_PIC32 + config PINCTRL_ZYNQ bool "Pinctrl driver for Xilinx Zynq" depends on ARCH_ZYNQ @@ -257,7 +243,9 @@ source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" +source "drivers/pinctrl/stm32/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" +source "drivers/pinctrl/tegra/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index bf1b5ca5180b..7ea62ef0c4e5 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -18,17 +18,12 @@ obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o +obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ -obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o -obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o -obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o -obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o -obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o -obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o -obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o +obj-$(CONFIG_PINCTRL_TEGRA) += tegra/ obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o @@ -46,12 +41,13 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/ obj-y += nomadik/ -obj-$(CONFIG_ARCH_PXA) += pxa/ +obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ -obj-$(CONFIG_ARCH_SUNXI) += sunxi/ +obj-$(CONFIG_PINCTRL_STM32) += stm32/ +obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index a5bb93987378..4c435cfa5d6e 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -341,6 +341,31 @@ mux_pin: return 0; } +static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned offset) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg; + u32 reg; + + /* + * Only Vybrid has the input/output buffer enable flags (IBE/OBE) + * They are part of the shared mux/conf register. + */ + if (!(info->flags & SHARE_MUX_CONF_REG)) + return; + + pin_reg = &info->pin_regs[offset]; + if (pin_reg->mux_reg == -1) + return; + + /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */ + reg = readl(ipctl->base + pin_reg->mux_reg); + reg &= ~0x7; + writel(reg, ipctl->base + pin_reg->mux_reg); +} + static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, bool input) { @@ -377,6 +402,7 @@ static const struct pinmux_ops imx_pmx_ops = { .get_function_groups = imx_pmx_get_groups, .set_mux = imx_pmx_set, .gpio_request_enable = imx_pmx_gpio_request_enable, + .gpio_disable_free = imx_pmx_gpio_disable_free, .gpio_set_direction = imx_pmx_gpio_set_direction, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index 98e0bebfdf92..d76491574841 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/of_device.h> @@ -336,7 +336,6 @@ static const struct of_device_id mt8127_pctrl_match[] = { { .compatible = "mediatek,mt8127-pinctrl", }, { } }; -MODULE_DEVICE_TABLE(of, mt8127_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt8127_pinctrl_probe, @@ -350,9 +349,4 @@ static int __init mtk_pinctrl_init(void) { return platform_driver_register(&mtk_pinctrl_driver); } - arch_initcall(mtk_pinctrl_init); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver"); -MODULE_AUTHOR("Yingjoe Chen <yingjoe.chen@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 1c153b860f36..d8c645f16f21 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -12,7 +12,7 @@ * GNU General Public License for more details. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/of_device.h> @@ -351,7 +351,6 @@ static const struct of_device_id mt8135_pctrl_match[] = { }, { } }; -MODULE_DEVICE_TABLE(of, mt8135_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt8135_pinctrl_probe, @@ -365,9 +364,4 @@ static int __init mtk_pinctrl_init(void) { return platform_driver_register(&mtk_pinctrl_driver); } - arch_initcall(mtk_pinctrl_init); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); -MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index a62514eb2129..8bfd427b9135 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -12,7 +12,7 @@ * GNU General Public License for more details. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/of_device.h> @@ -378,7 +378,6 @@ static const struct of_device_id mt8173_pctrl_match[] = { }, { } }; -MODULE_DEVICE_TABLE(of, mt8173_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt8173_pinctrl_probe, @@ -393,9 +392,4 @@ static int __init mtk_pinctrl_init(void) { return platform_driver_register(&mtk_pinctrl_driver); } - arch_initcall(mtk_pinctrl_init); - -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); -MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c index 587b222f12f3..e852048c4c04 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c @@ -287,6 +287,10 @@ static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 }; /* Altfunction B */ static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 }; static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 }; +static const unsigned clcd_16_23_b_1_pins[] = { STN8815_PIN_AB6, + STN8815_PIN_AA6, STN8815_PIN_Y6, STN8815_PIN_Y5, STN8815_PIN_AA5, + STN8815_PIN_AB5, STN8815_PIN_AB4, STN8815_PIN_Y4 }; + #define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ .npins = ARRAY_SIZE(a##_pins), .altsetting = b } @@ -302,6 +306,7 @@ static const struct nmk_pingroup nmk_stn8815_groups[] = { STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B), STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B), + STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B), }; /* We use this macro to define the groups applicable to a function */ @@ -314,6 +319,7 @@ STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1"); STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1"); STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1"); STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1"); +STN8815_FUNC_GROUPS(clcd, "clcd_16_23_b_1"); #define FUNCTION(fname) \ { \ @@ -329,6 +335,7 @@ static const struct nmk_function nmk_stn8815_functions[] = { FUNCTION(i2c1), FUNCTION(i2c0), FUNCTION(i2cusb), + FUNCTION(clcd), }; static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = { diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c new file mode 100644 index 000000000000..0b07d4bdab95 --- /dev/null +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -0,0 +1,2312 @@ +/* + * PIC32 pinctrl driver + * + * Joshua Henderson, <joshua.henderson@microchip.com> + * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#include <linux/clk.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +#include <asm/mach-pic32/pic32.h> + +#include "pinctrl-utils.h" +#include "pinctrl-pic32.h" + +#define PINS_PER_BANK 16 + +#define PIC32_CNCON_EDGE 11 +#define PIC32_CNCON_ON 15 + +#define PIN_CONFIG_MICROCHIP_DIGITAL (PIN_CONFIG_END + 1) +#define PIN_CONFIG_MICROCHIP_ANALOG (PIN_CONFIG_END + 2) + +static const struct pinconf_generic_params pic32_mpp_bindings[] = { + {"microchip,digital", PIN_CONFIG_MICROCHIP_DIGITAL, 0}, + {"microchip,analog", PIN_CONFIG_MICROCHIP_ANALOG, 0}, +}; + +#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) + +struct pic32_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +struct pic32_pin_group { + const char *name; + unsigned int pin; + struct pic32_desc_function *functions; +}; + +struct pic32_desc_function { + const char *name; + u32 muxreg; + u32 muxval; +}; + +struct pic32_gpio_bank { + void __iomem *reg_base; + struct gpio_chip gpio_chip; + struct irq_chip irq_chip; + struct clk *clk; +}; + +struct pic32_pinctrl { + void __iomem *reg_base; + struct device *dev; + struct pinctrl_dev *pctldev; + const struct pinctrl_pin_desc *pins; + unsigned int npins; + const struct pic32_function *functions; + unsigned int nfunctions; + const struct pic32_pin_group *groups; + unsigned int ngroups; + struct pic32_gpio_bank *gpio_banks; + unsigned int nbanks; + struct clk *clk; +}; + +static const struct pinctrl_pin_desc pic32_pins[] = { + PINCTRL_PIN(0, "A0"), + PINCTRL_PIN(1, "A1"), + PINCTRL_PIN(2, "A2"), + PINCTRL_PIN(3, "A3"), + PINCTRL_PIN(4, "A4"), + PINCTRL_PIN(5, "A5"), + PINCTRL_PIN(6, "A6"), + PINCTRL_PIN(7, "A7"), + PINCTRL_PIN(8, "A8"), + PINCTRL_PIN(9, "A9"), + PINCTRL_PIN(10, "A10"), + PINCTRL_PIN(11, "A11"), + PINCTRL_PIN(12, "A12"), + PINCTRL_PIN(13, "A13"), + PINCTRL_PIN(14, "A14"), + PINCTRL_PIN(15, "A15"), + PINCTRL_PIN(16, "B0"), + PINCTRL_PIN(17, "B1"), + PINCTRL_PIN(18, "B2"), + PINCTRL_PIN(19, "B3"), + PINCTRL_PIN(20, "B4"), + PINCTRL_PIN(21, "B5"), + PINCTRL_PIN(22, "B6"), + PINCTRL_PIN(23, "B7"), + PINCTRL_PIN(24, "B8"), + PINCTRL_PIN(25, "B9"), + PINCTRL_PIN(26, "B10"), + PINCTRL_PIN(27, "B11"), + PINCTRL_PIN(28, "B12"), + PINCTRL_PIN(29, "B13"), + PINCTRL_PIN(30, "B14"), + PINCTRL_PIN(31, "B15"), + PINCTRL_PIN(33, "C1"), + PINCTRL_PIN(34, "C2"), + PINCTRL_PIN(35, "C3"), + PINCTRL_PIN(36, "C4"), + PINCTRL_PIN(44, "C12"), + PINCTRL_PIN(45, "C13"), + PINCTRL_PIN(46, "C14"), + PINCTRL_PIN(47, "C15"), + PINCTRL_PIN(48, "D0"), + PINCTRL_PIN(49, "D1"), + PINCTRL_PIN(50, "D2"), + PINCTRL_PIN(51, "D3"), + PINCTRL_PIN(52, "D4"), + PINCTRL_PIN(53, "D5"), + PINCTRL_PIN(54, "D6"), + PINCTRL_PIN(55, "D7"), + PINCTRL_PIN(57, "D9"), + PINCTRL_PIN(58, "D10"), + PINCTRL_PIN(59, "D11"), + PINCTRL_PIN(60, "D12"), + PINCTRL_PIN(61, "D13"), + PINCTRL_PIN(62, "D14"), + PINCTRL_PIN(63, "D15"), + PINCTRL_PIN(64, "E0"), + PINCTRL_PIN(65, "E1"), + PINCTRL_PIN(66, "E2"), + PINCTRL_PIN(67, "E3"), + PINCTRL_PIN(68, "E4"), + PINCTRL_PIN(69, "E5"), + PINCTRL_PIN(70, "E6"), + PINCTRL_PIN(71, "E7"), + PINCTRL_PIN(72, "E8"), + PINCTRL_PIN(73, "E9"), + PINCTRL_PIN(80, "F0"), + PINCTRL_PIN(81, "F1"), + PINCTRL_PIN(82, "F2"), + PINCTRL_PIN(83, "F3"), + PINCTRL_PIN(84, "F4"), + PINCTRL_PIN(85, "F5"), + PINCTRL_PIN(88, "F8"), + PINCTRL_PIN(92, "F12"), + PINCTRL_PIN(93, "F13"), + PINCTRL_PIN(96, "G0"), + PINCTRL_PIN(97, "G1"), + PINCTRL_PIN(102, "G6"), + PINCTRL_PIN(103, "G7"), + PINCTRL_PIN(104, "G8"), + PINCTRL_PIN(105, "G9"), + PINCTRL_PIN(108, "G12"), + PINCTRL_PIN(109, "G13"), + PINCTRL_PIN(110, "G14"), + PINCTRL_PIN(111, "G15"), + PINCTRL_PIN(112, "H0"), + PINCTRL_PIN(113, "H1"), + PINCTRL_PIN(114, "H2"), + PINCTRL_PIN(115, "H3"), + PINCTRL_PIN(116, "H4"), + PINCTRL_PIN(117, "H5"), + PINCTRL_PIN(118, "H6"), + PINCTRL_PIN(119, "H7"), + PINCTRL_PIN(120, "H8"), + PINCTRL_PIN(121, "H9"), + PINCTRL_PIN(122, "H10"), + PINCTRL_PIN(123, "H11"), + PINCTRL_PIN(124, "H12"), + PINCTRL_PIN(125, "H13"), + PINCTRL_PIN(126, "H14"), + PINCTRL_PIN(127, "H15"), + PINCTRL_PIN(128, "J0"), + PINCTRL_PIN(129, "J1"), + PINCTRL_PIN(130, "J2"), + PINCTRL_PIN(131, "J3"), + PINCTRL_PIN(132, "J4"), + PINCTRL_PIN(133, "J5"), + PINCTRL_PIN(134, "J6"), + PINCTRL_PIN(135, "J7"), + PINCTRL_PIN(136, "J8"), + PINCTRL_PIN(137, "J9"), + PINCTRL_PIN(138, "J10"), + PINCTRL_PIN(139, "J11"), + PINCTRL_PIN(140, "J12"), + PINCTRL_PIN(141, "J13"), + PINCTRL_PIN(142, "J14"), + PINCTRL_PIN(143, "J15"), + PINCTRL_PIN(144, "K0"), + PINCTRL_PIN(145, "K1"), + PINCTRL_PIN(146, "K2"), + PINCTRL_PIN(147, "K3"), + PINCTRL_PIN(148, "K4"), + PINCTRL_PIN(149, "K5"), + PINCTRL_PIN(150, "K6"), + PINCTRL_PIN(151, "K7"), +}; + +static const char * const pic32_input0_group[] = { + "D2", "G8", "F4", "F1", "B9", "B10", "C14", "B5", + "C1", "D14", "G1", "A14", "D6", +}; + +static const char * const pic32_input1_group[] = { + "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13", + "B3", "C4", "G0", "A15", "D7", +}; + +static const char * const pic32_input2_group[] = { + "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7", + "F12", "D12", "F8", "C3", "E9", +}; + +static const char * const pic32_input3_group[] = { + "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13", + "F2", "C2", "E8", +}; + +static const char * const pic32_output0_group[] = { + "D2", "G8", "F4", "D10", "F1", "B9", "B10", "C14", + "B5", "C1", "D14", "G1", "A14", "D6", +}; + +static const char * const pic32_output0_1_group[] = { + "D2", "G8", "F4", "D10", "F1", "B9", "B10", "C14", + "B5", "C1", "D14", "G1", "A14", "D6", + "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13", + "B3", "C4", "D15", "G0", "A15", "D7", +}; + +static const char *const pic32_output1_group[] = { + "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13", + "B3", "C4", "D15", "G0", "A15", "D7", +}; + +static const char *const pic32_output1_3_group[] = { + "D3", "G7", "F5", "D11", "F0", "B1", "E5", "C13", + "B3", "C4", "D15", "G0", "A15", "D7", + "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13", + "C2", "E8", "F2", +}; + +static const char * const pic32_output2_group[] = { + "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7", + "F12", "D12", "F8", "C3", "E9", +}; + +static const char * const pic32_output2_3_group[] = { + "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7", + "F12", "D12", "F8", "C3", "E9", + "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13", + "C2", "E8", "F2", +}; + +static const char * const pic32_output3_group[] = { + "G9", "B14", "D0", "B6", "D5", "B2", "F3", "F13", + "C2", "E8", "F2", +}; + +#define FUNCTION(_name, _gr) \ + { \ + .name = #_name, \ + .groups = pic32_##_gr##_group, \ + .ngroups = ARRAY_SIZE(pic32_##_gr##_group), \ + } + +static const struct pic32_function pic32_functions[] = { + FUNCTION(INT3, input0), + FUNCTION(T2CK, input0), + FUNCTION(T6CK, input0), + FUNCTION(IC3, input0), + FUNCTION(IC7, input0), + FUNCTION(U1RX, input0), + FUNCTION(U2CTS, input0), + FUNCTION(U5RX, input0), + FUNCTION(U6CTS, input0), + FUNCTION(SDI1, input0), + FUNCTION(SDI3, input0), + FUNCTION(SDI5, input0), + FUNCTION(SS6IN, input0), + FUNCTION(REFCLKI1, input0), + FUNCTION(INT4, input1), + FUNCTION(T5CK, input1), + FUNCTION(T7CK, input1), + FUNCTION(IC4, input1), + FUNCTION(IC8, input1), + FUNCTION(U3RX, input1), + FUNCTION(U4CTS, input1), + FUNCTION(SDI2, input1), + FUNCTION(SDI4, input1), + FUNCTION(C1RX, input1), + FUNCTION(REFCLKI4, input1), + FUNCTION(INT2, input2), + FUNCTION(T3CK, input2), + FUNCTION(T8CK, input2), + FUNCTION(IC2, input2), + FUNCTION(IC5, input2), + FUNCTION(IC9, input2), + FUNCTION(U1CTS, input2), + FUNCTION(U2RX, input2), + FUNCTION(U5CTS, input2), + FUNCTION(SS1IN, input2), + FUNCTION(SS3IN, input2), + FUNCTION(SS4IN, input2), + FUNCTION(SS5IN, input2), + FUNCTION(C2RX, input2), + FUNCTION(INT1, input3), + FUNCTION(T4CK, input3), + FUNCTION(T9CK, input3), + FUNCTION(IC1, input3), + FUNCTION(IC6, input3), + FUNCTION(U3CTS, input3), + FUNCTION(U4RX, input3), + FUNCTION(U6RX, input3), + FUNCTION(SS2IN, input3), + FUNCTION(SDI6, input3), + FUNCTION(OCFA, input3), + FUNCTION(REFCLKI3, input3), + FUNCTION(U3TX, output0), + FUNCTION(U4RTS, output0), + FUNCTION(SDO1, output0_1), + FUNCTION(SDO2, output0_1), + FUNCTION(SDO3, output0_1), + FUNCTION(SDO5, output0_1), + FUNCTION(SS6OUT, output0), + FUNCTION(OC3, output0), + FUNCTION(OC6, output0), + FUNCTION(REFCLKO4, output0), + FUNCTION(C2OUT, output0), + FUNCTION(C1TX, output0), + FUNCTION(U1TX, output1), + FUNCTION(U2RTS, output1), + FUNCTION(U5TX, output1), + FUNCTION(U6RTS, output1), + FUNCTION(SDO4, output1_3), + FUNCTION(OC4, output1), + FUNCTION(OC7, output1), + FUNCTION(REFCLKO1, output1), + FUNCTION(U3RTS, output2), + FUNCTION(U4TX, output2), + FUNCTION(U6TX, output2_3), + FUNCTION(SS1OUT, output2), + FUNCTION(SS3OUT, output2), + FUNCTION(SS4OUT, output2), + FUNCTION(SS5OUT, output2), + FUNCTION(SDO6, output2_3), + FUNCTION(OC5, output2), + FUNCTION(OC8, output2), + FUNCTION(C1OUT, output2), + FUNCTION(REFCLKO3, output2), + FUNCTION(U1RTS, output3), + FUNCTION(U2TX, output3), + FUNCTION(U5RTS, output3), + FUNCTION(SS2OUT, output3), + FUNCTION(OC2, output3), + FUNCTION(OC1, output3), + FUNCTION(OC9, output3), + FUNCTION(C2TX, output3), +}; + +#define PIC32_PINCTRL_GROUP(_pin, _name, ...) \ + { \ + .name = #_name, \ + .pin = _pin, \ + .functions = (struct pic32_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define PIC32_PINCTRL_FUNCTION(_name, _muxreg, _muxval) \ + { \ + .name = #_name, \ + .muxreg = _muxreg, \ + .muxval = _muxval, \ + } + +static const struct pic32_pin_group pic32_groups[] = { + PIC32_PINCTRL_GROUP(14, A14, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 13), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 13), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 13), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 13), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 13), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 13), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 13), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 13), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 13), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 13), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 13), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 13), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 13), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 13), + PIC32_PINCTRL_FUNCTION(U3TX, RPA14R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPA14R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPA14R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPA14R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPA14R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPA14R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPA14R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPA14R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPA14R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPA14R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPA14R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPA14R, 15)), + PIC32_PINCTRL_GROUP(15, A15, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 13), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 13), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 13), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 13), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 13), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 13), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 13), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 13), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 13), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 13), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 13), + PIC32_PINCTRL_FUNCTION(U1TX, RPA15R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPA15R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPA15R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPA15R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPA15R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPA15R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPA15R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPA15R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPA15R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPA15R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPA15R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPA15R, 15)), + PIC32_PINCTRL_GROUP(16, B0, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 5), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 5), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 5), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 5), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 5), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 5), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 5), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 5), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 5), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 5), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 5), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 5), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 5), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 5), + PIC32_PINCTRL_FUNCTION(U3RTS, RPB0R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPB0R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPB0R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPB0R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPB0R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPB0R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPB0R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPB0R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPB0R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPB0R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPB0R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB0R, 15)), + PIC32_PINCTRL_GROUP(17, B1, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 5), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 5), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 5), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 5), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 5), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 5), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 5), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 5), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 5), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 5), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 5), + PIC32_PINCTRL_FUNCTION(U1TX, RPB1R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPB1R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPB1R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPB1R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPB1R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPB1R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPB1R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPB1R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPB1R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPB1R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPB1R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPB1R, 15)), + PIC32_PINCTRL_GROUP(18, B2, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 7), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 7), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 7), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 7), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 7), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 7), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 7), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 7), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 7), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 7), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 7), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 7), + PIC32_PINCTRL_FUNCTION(U1RTS, RPB2R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPB2R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPB2R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPB2R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPB2R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPB2R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPB2R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPB2R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPB2R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPB2R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPB2R, 15)), + PIC32_PINCTRL_GROUP(19, B3, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 8), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 8), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 8), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 8), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 8), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 8), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 8), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 8), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 8), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 8), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 8), + PIC32_PINCTRL_FUNCTION(U1TX, RPB3R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPB3R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPB3R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPB3R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPB3R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPB3R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPB3R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPB3R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPB3R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPB3R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPB3R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPB3R, 15)), + PIC32_PINCTRL_GROUP(21, B5, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 8), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 8), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 8), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 8), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 8), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 8), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 8), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 8), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 8), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 8), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 8), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 8), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 8), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 8), + PIC32_PINCTRL_FUNCTION(U3TX, RPB5R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPB5R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPB5R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPB5R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPB5R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPB5R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPB5R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPB5R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPB5R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB5R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPB5R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPB5R, 15)), + PIC32_PINCTRL_GROUP(22, B6, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 4), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 4), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 4), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 4), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 4), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 4), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 4), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 4), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 4), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 4), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 4), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 4), + PIC32_PINCTRL_FUNCTION(U1RTS, RPB6R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPB6R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPB6R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPB6R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPB6R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPB6R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPB6R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPB6R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPB6R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPB6R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPB6R, 15)), + PIC32_PINCTRL_GROUP(23, B7, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 7), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 7), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 7), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 7), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 7), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 7), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 7), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 7), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 7), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 7), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 7), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 7), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 7), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 7), + PIC32_PINCTRL_FUNCTION(U3RTS, RPB7R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPB7R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPB7R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPB7R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPB7R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPB7R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPB7R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPB7R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPB7R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPB7R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPB7R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB7R, 15)), + PIC32_PINCTRL_GROUP(24, B8, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 2), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 2), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 2), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 2), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 2), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 2), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 2), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 2), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 2), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 2), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 2), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 2), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 2), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 2), + PIC32_PINCTRL_FUNCTION(U3RTS, RPB8R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPB8R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPB8R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPB8R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPB8R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPB8R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPB8R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPB8R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPB8R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPB8R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPB8R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB8R, 15)), + PIC32_PINCTRL_GROUP(25, B9, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 5), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 5), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 5), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 5), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 5), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 5), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 5), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 5), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 5), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 5), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 5), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 5), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 5), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 5), + PIC32_PINCTRL_FUNCTION(U3TX, RPB9R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPB9R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPB9R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPB9R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPB9R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPB9R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPB9R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPB9R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPB9R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB9R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPB9R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPB9R, 15)), + PIC32_PINCTRL_GROUP(26, B10, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 6), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 6), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 6), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 6), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 6), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 6), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 6), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 6), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 6), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 6), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 6), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 6), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 6), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 6), + PIC32_PINCTRL_FUNCTION(U3TX, RPB10R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPB10R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPB10R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPB10R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPB10R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPB10R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPB10R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPB10R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPB10R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPB10R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPB10R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPB10R, 15)), + PIC32_PINCTRL_GROUP(30, B14, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 2), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 2), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 2), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 2), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 2), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 2), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 2), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 2), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 2), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 2), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 2), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 2), + PIC32_PINCTRL_FUNCTION(U1RTS, RPB14R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPB14R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPB14R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPB14R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPB14R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPB14R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPB14R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPB14R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPB14R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPB14R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPB14R, 15)), + PIC32_PINCTRL_GROUP(31, B15, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 3), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 3), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 3), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 3), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 3), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 3), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 3), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 3), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 3), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 3), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 3), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 3), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 3), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 3), + PIC32_PINCTRL_FUNCTION(U3RTS, RPB15R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPB15R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPB15R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPB15R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPB15R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPB15R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPB15R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPB15R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPB15R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPB15R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPB15R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPB15R, 15)), + PIC32_PINCTRL_GROUP(33, C1, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 10), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 10), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 10), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 10), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 10), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 10), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 10), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 10), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 10), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 10), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 10), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 10), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 10), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 10), + PIC32_PINCTRL_FUNCTION(U3TX, RPC1R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPC1R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPC1R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPC1R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPC1R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPC1R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPC1R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPC1R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPC1R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPC1R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPC1R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPC1R, 15)), + PIC32_PINCTRL_GROUP(34, C2, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 12), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 12), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 12), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 12), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 12), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 12), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 12), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 12), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 12), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 12), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 12), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 12), + PIC32_PINCTRL_FUNCTION(U1RTS, RPC2R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPC2R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPC2R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPC2R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPC2R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPC2R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPC2R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPC2R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPC2R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPC2R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPC2R, 15)), + PIC32_PINCTRL_GROUP(35, C3, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 12), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 12), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 12), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 12), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 12), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 12), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 12), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 12), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 12), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 12), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 12), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 12), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 12), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 12), + PIC32_PINCTRL_FUNCTION(U3RTS, RPC3R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPC3R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPC3R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPC3R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPC3R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPC3R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPC3R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPC3R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPC3R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPC3R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPC3R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPC3R, 15)), + PIC32_PINCTRL_GROUP(36, C4, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 10), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 10), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 10), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 10), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 10), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 10), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 10), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 10), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 10), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 10), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 10), + PIC32_PINCTRL_FUNCTION(U1TX, RPC4R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPC4R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPC4R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPC4R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPC4R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPC4R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPC4R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPC4R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPC4R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPC4R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPC4R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPC4R, 15)), + PIC32_PINCTRL_GROUP(45, C13, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 7), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 7), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 7), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 7), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 7), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 7), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 7), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 7), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 7), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 7), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 7), + PIC32_PINCTRL_FUNCTION(U1TX, RPC13R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPC13R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPC13R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPC13R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPC13R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPC13R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPC13R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPC13R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPC13R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPC13R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPC13R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPC13R, 15)), + PIC32_PINCTRL_GROUP(46, C14, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 7), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 7), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 7), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 7), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 7), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 7), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 7), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 7), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 7), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 7), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 7), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 7), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 7), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 7), + PIC32_PINCTRL_FUNCTION(U3TX, RPC14R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPC14R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPC14R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPC14R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPC14R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPC14R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPC14R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPC14R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPC14R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPC14R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPC14R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPC14R, 15)), + PIC32_PINCTRL_GROUP(48, D0, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 3), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 3), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 3), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 3), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 3), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 3), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 3), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 3), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 3), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 3), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 3), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 3), + PIC32_PINCTRL_FUNCTION(U1RTS, RPD0R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPD0R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPD0R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPD0R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPD0R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPD0R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPD0R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPD0R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPD0R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPD0R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPD0R, 15)), + PIC32_PINCTRL_GROUP(50, D2, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 0), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 0), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 0), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 0), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 0), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 0), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 0), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 0), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 0), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 0), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 0), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 0), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 0), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 0), + PIC32_PINCTRL_FUNCTION(U3TX, RPD2R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPD2R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPD2R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPD2R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPD2R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPD2R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPD2R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPD2R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPD2R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD2R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPD2R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPD2R, 15)), + PIC32_PINCTRL_GROUP(51, D3, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 0), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 0), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 0), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 0), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 0), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 0), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 0), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 0), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 0), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 0), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 0), + PIC32_PINCTRL_FUNCTION(U1TX, RPD3R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPD3R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPD3R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPD3R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPD3R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPD3R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPD3R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPD3R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPD3R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPD3R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPD3R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD3R, 15)), + PIC32_PINCTRL_GROUP(52, D4, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 4), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 4), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 4), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 4), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 4), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 4), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 4), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 4), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 4), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 4), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 4), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 4), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 4), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 4), + PIC32_PINCTRL_FUNCTION(U3RTS, RPD4R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPD4R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPD4R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPD4R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPD4R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPD4R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPD4R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPD4R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPD4R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPD4R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPD4R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD4R, 15)), + PIC32_PINCTRL_GROUP(53, D5, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 6), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 6), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 6), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 6), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 6), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 6), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 6), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 6), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 6), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 6), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 6), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 6), + PIC32_PINCTRL_FUNCTION(U1RTS, RPD5R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPD5R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPD5R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPD5R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPD5R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPD5R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPD5R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPD5R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPD5R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPD5R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPD5R, 15)), + PIC32_PINCTRL_GROUP(54, D6, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 14), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 14), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 14), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 14), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 14), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 14), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 14), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 14), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 14), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 14), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 14), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 14), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 14), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 14), + PIC32_PINCTRL_FUNCTION(U3TX, RPD6R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPD6R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPD6R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPD6R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPD6R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPD6R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPD6R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPD6R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPD6R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD6R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPD6R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPD6R, 15)), + PIC32_PINCTRL_GROUP(55, D7, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 14), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 14), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 14), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 14), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 14), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 14), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 14), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 14), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 14), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 14), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 14), + PIC32_PINCTRL_FUNCTION(U1TX, RPD7R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPD7R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPD7R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPD7R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPD7R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPD7R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPD7R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPD7R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPD7R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPD7R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPD7R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD7R, 15)), + PIC32_PINCTRL_GROUP(57, D9, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 0), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 0), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 0), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 0), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 0), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 0), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 0), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 0), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 0), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 0), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 0), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 0), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 0), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 0), + PIC32_PINCTRL_FUNCTION(U3RTS, RPD9R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPD9R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPD9R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPD9R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPD9R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPD9R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPD9R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPD9R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPD9R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPD9R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPD9R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD9R, 15)), + PIC32_PINCTRL_GROUP(58, D10, + PIC32_PINCTRL_FUNCTION(U3TX, RPD10R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPD10R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPD10R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPD10R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPD10R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPD10R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPD10R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPD10R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPD10R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD10R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPD10R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPD10R, 15)), + PIC32_PINCTRL_GROUP(59, D11, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 3), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 3), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 3), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 3), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 3), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 3), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 3), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 3), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 3), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 3), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 3), + PIC32_PINCTRL_FUNCTION(U1TX, RPD11R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPD11R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPD11R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPD11R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPD11R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPD11R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPD11R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPD11R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPD11R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPD11R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPD11R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD11R, 15)), + PIC32_PINCTRL_GROUP(60, D12, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 10), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 10), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 10), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 10), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 10), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 10), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 10), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 10), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 10), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 10), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 10), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 10), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 10), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 10), + PIC32_PINCTRL_FUNCTION(U3RTS, RPD12R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPD12R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPD12R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPD12R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPD12R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPD12R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPD12R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPD12R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPD12R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPD12R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPD12R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPD12R, 15)), + PIC32_PINCTRL_GROUP(62, D14, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 11), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 11), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 11), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 11), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 11), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 11), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 11), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 11), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 11), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 11), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 11), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 11), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 11), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 11), + PIC32_PINCTRL_FUNCTION(U3TX, RPD14R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPD14R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPD14R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPD14R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPD14R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPD14R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPD14R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPD14R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPD14R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPD14R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPD14R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPD14R, 15)), + PIC32_PINCTRL_GROUP(63, D15, + PIC32_PINCTRL_FUNCTION(U1TX, RPD15R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPD15R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPD15R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPD15R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPD15R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPD15R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPD15R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPD15R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPD15R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPD15R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPD15R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPD15R, 15)), + PIC32_PINCTRL_GROUP(67, E3, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 6), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 6), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 6), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 6), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 6), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 6), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 6), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 6), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 6), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 6), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 6), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 6), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 6), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 6), + PIC32_PINCTRL_FUNCTION(U3RTS, RPE3R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPE3R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPE3R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPE3R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPE3R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPE3R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPE3R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPE3R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPE3R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPE3R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPE3R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPE3R, 15)), + PIC32_PINCTRL_GROUP(69, E5, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 6), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 6), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 6), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 6), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 6), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 6), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 6), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 6), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 6), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 6), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 6), + PIC32_PINCTRL_FUNCTION(U1TX, RPE5R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPE5R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPE5R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPE5R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPE5R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPE5R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPE5R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPE5R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPE5R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPE5R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPE5R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPE5R, 15)), + PIC32_PINCTRL_GROUP(72, E8, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 13), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 13), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 13), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 13), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 13), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 13), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 13), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 13), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 13), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 13), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 13), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 13), + PIC32_PINCTRL_FUNCTION(U1RTS, RPE8R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPE8R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPE8R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPE8R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPE8R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPE8R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPE8R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPE8R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPE8R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPE8R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPE8R, 15)), + PIC32_PINCTRL_GROUP(73, E9, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 13), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 13), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 13), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 13), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 13), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 13), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 13), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 13), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 13), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 13), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 13), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 13), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 13), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 13), + PIC32_PINCTRL_FUNCTION(U3RTS, RPE9R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPE9R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPE9R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPE9R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPE9R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPE9R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPE9R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPE9R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPE9R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPE9R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPE9R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPE9R, 15)), + PIC32_PINCTRL_GROUP(80, F0, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 4), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 4), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 4), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 4), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 4), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 4), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 4), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 4), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 4), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 4), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 4), + PIC32_PINCTRL_FUNCTION(U1TX, RPF0R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPF0R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPF0R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPF0R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPF0R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPF0R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPF0R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPF0R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPF0R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPF0R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPF0R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPF0R, 15)), + PIC32_PINCTRL_GROUP(81, F1, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 4), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 4), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 4), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 4), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 4), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 4), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 4), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 4), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 4), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 4), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 4), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 4), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 4), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 4), + PIC32_PINCTRL_FUNCTION(U3TX, RPF1R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPF1R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPF1R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPF1R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPF1R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPF1R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPF1R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPF1R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPF1R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPF1R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPF1R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPF1R, 15)), + PIC32_PINCTRL_GROUP(82, F2, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 11), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 11), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 11), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 11), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 11), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 11), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 11), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 11), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 11), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 11), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 11), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 11), + PIC32_PINCTRL_FUNCTION(U1RTS, RPF2R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPF2R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPF2R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPF2R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPF2R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPF2R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPF2R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPF2R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPF2R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPF2R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPF2R, 15)), + PIC32_PINCTRL_GROUP(83, F3, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 8), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 8), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 8), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 8), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 8), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 8), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 8), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 8), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 8), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 8), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 8), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 8), + PIC32_PINCTRL_FUNCTION(U1RTS, RPF3R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPF3R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPF3R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPF3R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPF3R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPF3R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPF3R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPF3R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPF3R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPF3R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPF3R, 15)), + PIC32_PINCTRL_GROUP(84, F4, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 2), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 2), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 2), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 2), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 2), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 2), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 2), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 2), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 2), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 2), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 2), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 2), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 2), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 2), + PIC32_PINCTRL_FUNCTION(U3TX, RPF4R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPF4R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPF4R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPF4R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPF4R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPF4R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPF4R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPF4R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPF4R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPF4R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPF4R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPF4R, 15)), + PIC32_PINCTRL_GROUP(85, F5, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 2), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 2), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 2), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 2), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 2), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 2), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 2), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 2), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 2), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 2), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 2), + PIC32_PINCTRL_FUNCTION(U1TX, RPF5R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPF5R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPF5R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPF5R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPF5R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPF5R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPF5R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPF5R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPF5R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPF5R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPF5R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPF5R, 15)), + PIC32_PINCTRL_GROUP(88, F8, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 11), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 11), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 11), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 11), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 11), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 11), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 11), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 11), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 11), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 11), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 11), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 11), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 11), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 11), + PIC32_PINCTRL_FUNCTION(U3RTS, RPF8R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPF8R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPF8R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPF8R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPF8R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPF8R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPF8R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPF8R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPF8R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPF8R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPF8R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPF8R, 15)), + PIC32_PINCTRL_GROUP(92, F12, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 9), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 9), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 9), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 9), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 9), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 9), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 9), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 9), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 9), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 9), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 9), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 9), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 9), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 9), + PIC32_PINCTRL_FUNCTION(U3RTS, RPF12R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPF12R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPF12R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPF12R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPF12R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPF12R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPF12R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPF12R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPF12R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPF12R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPF12R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPF12R, 15)), + PIC32_PINCTRL_GROUP(93, F13, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 9), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 9), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 9), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 9), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 9), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 9), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 9), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 9), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 9), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 9), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 9), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 9), + PIC32_PINCTRL_FUNCTION(U1RTS, RPF13R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPF13R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPF13R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPF13R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPF13R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPF13R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPF13R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPF13R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPF13R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPF13R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPF13R, 15)), + PIC32_PINCTRL_GROUP(96, G0, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 12), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 12), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 12), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 12), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 12), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 12), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 12), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 12), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 12), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 12), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 12), + PIC32_PINCTRL_FUNCTION(U1TX, RPG0R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPG0R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPG0R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPG0R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPG0R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPG0R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPG0R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPG0R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPG0R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPG0R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPG0R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPG0R, 15)), + PIC32_PINCTRL_GROUP(97, G1, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 12), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 12), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 12), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 12), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 12), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 12), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 12), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 12), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 12), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 12), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 12), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 12), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 12), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 12), + PIC32_PINCTRL_FUNCTION(U3TX, RPG1R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPG1R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPG1R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPG1R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPG1R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPG1R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPG1R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPG1R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPG1R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPG1R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPG1R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPG1R, 15)), + PIC32_PINCTRL_GROUP(102, G6, + PIC32_PINCTRL_FUNCTION(INT2, INT2R, 1), + PIC32_PINCTRL_FUNCTION(T3CK, T3CKR, 1), + PIC32_PINCTRL_FUNCTION(T8CK, T8CKR, 1), + PIC32_PINCTRL_FUNCTION(IC2, IC2R, 1), + PIC32_PINCTRL_FUNCTION(IC5, IC5R, 1), + PIC32_PINCTRL_FUNCTION(IC9, IC9R, 1), + PIC32_PINCTRL_FUNCTION(U1CTS, U1CTSR, 1), + PIC32_PINCTRL_FUNCTION(U2RX, U2RXR, 1), + PIC32_PINCTRL_FUNCTION(U5CTS, U5CTSR, 1), + PIC32_PINCTRL_FUNCTION(SS1IN, SS1INR, 1), + PIC32_PINCTRL_FUNCTION(SS3IN, SS3INR, 1), + PIC32_PINCTRL_FUNCTION(SS4IN, SS4INR, 1), + PIC32_PINCTRL_FUNCTION(SS5IN, SS5INR, 1), + PIC32_PINCTRL_FUNCTION(C2RX, C2RXR, 1), + PIC32_PINCTRL_FUNCTION(U3RTS, RPG6R, 1), + PIC32_PINCTRL_FUNCTION(U4TX, RPG6R, 2), + PIC32_PINCTRL_FUNCTION(U6TX, RPG6R, 4), + PIC32_PINCTRL_FUNCTION(SS1OUT, RPG6R, 5), + PIC32_PINCTRL_FUNCTION(SS3OUT, RPG6R, 7), + PIC32_PINCTRL_FUNCTION(SS4OUT, RPG6R, 8), + PIC32_PINCTRL_FUNCTION(SS5OUT, RPG6R, 9), + PIC32_PINCTRL_FUNCTION(SDO6, RPG6R, 10), + PIC32_PINCTRL_FUNCTION(OC5, RPG6R, 11), + PIC32_PINCTRL_FUNCTION(OC8, RPG6R, 12), + PIC32_PINCTRL_FUNCTION(C1OUT, RPG6R, 14), + PIC32_PINCTRL_FUNCTION(REFCLKO3, RPG6R, 15)), + PIC32_PINCTRL_GROUP(103, G7, + PIC32_PINCTRL_FUNCTION(INT4, INT4R, 1), + PIC32_PINCTRL_FUNCTION(T5CK, T5CKR, 1), + PIC32_PINCTRL_FUNCTION(T7CK, T7CKR, 1), + PIC32_PINCTRL_FUNCTION(IC4, IC4R, 1), + PIC32_PINCTRL_FUNCTION(IC8, IC8R, 1), + PIC32_PINCTRL_FUNCTION(U3RX, U3RXR, 1), + PIC32_PINCTRL_FUNCTION(U4CTS, U4CTSR, 1), + PIC32_PINCTRL_FUNCTION(SDI2, SDI2R, 1), + PIC32_PINCTRL_FUNCTION(SDI4, SDI4R, 1), + PIC32_PINCTRL_FUNCTION(C1RX, C1RXR, 1), + PIC32_PINCTRL_FUNCTION(REFCLKI4, REFCLKI4R, 1), + PIC32_PINCTRL_FUNCTION(U1TX, RPG7R, 1), + PIC32_PINCTRL_FUNCTION(U2RTS, RPG7R, 2), + PIC32_PINCTRL_FUNCTION(U5TX, RPG7R, 3), + PIC32_PINCTRL_FUNCTION(U6RTS, RPG7R, 4), + PIC32_PINCTRL_FUNCTION(SDO1, RPG7R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPG7R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPG7R, 7), + PIC32_PINCTRL_FUNCTION(SDO4, RPG7R, 8), + PIC32_PINCTRL_FUNCTION(SDO5, RPG7R, 9), + PIC32_PINCTRL_FUNCTION(OC4, RPG7R, 11), + PIC32_PINCTRL_FUNCTION(OC7, RPG7R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO1, RPG7R, 15)), + PIC32_PINCTRL_GROUP(104, G8, + PIC32_PINCTRL_FUNCTION(INT3, INT3R, 1), + PIC32_PINCTRL_FUNCTION(T2CK, T2CKR, 1), + PIC32_PINCTRL_FUNCTION(T6CK, T6CKR, 1), + PIC32_PINCTRL_FUNCTION(IC3, IC3R, 1), + PIC32_PINCTRL_FUNCTION(IC7, IC7R, 1), + PIC32_PINCTRL_FUNCTION(U1RX, U1RXR, 1), + PIC32_PINCTRL_FUNCTION(U2CTS, U2CTSR, 1), + PIC32_PINCTRL_FUNCTION(U5RX, U5RXR, 1), + PIC32_PINCTRL_FUNCTION(U6CTS, U6CTSR, 1), + PIC32_PINCTRL_FUNCTION(SDI1, SDI1R, 1), + PIC32_PINCTRL_FUNCTION(SDI3, SDI3R, 1), + PIC32_PINCTRL_FUNCTION(SDI5, SDI5R, 1), + PIC32_PINCTRL_FUNCTION(SS6IN, SS6INR, 1), + PIC32_PINCTRL_FUNCTION(REFCLKI1, REFCLKI1R, 1), + PIC32_PINCTRL_FUNCTION(U3TX, RPG8R, 1), + PIC32_PINCTRL_FUNCTION(U4RTS, RPG8R, 2), + PIC32_PINCTRL_FUNCTION(SDO1, RPG8R, 5), + PIC32_PINCTRL_FUNCTION(SDO2, RPG8R, 6), + PIC32_PINCTRL_FUNCTION(SDO3, RPG8R, 7), + PIC32_PINCTRL_FUNCTION(SDO5, RPG8R, 9), + PIC32_PINCTRL_FUNCTION(SS6OUT, RPG8R, 10), + PIC32_PINCTRL_FUNCTION(OC3, RPG8R, 11), + PIC32_PINCTRL_FUNCTION(OC6, RPG8R, 12), + PIC32_PINCTRL_FUNCTION(REFCLKO4, RPG8R, 13), + PIC32_PINCTRL_FUNCTION(C2OUT, RPG8R, 14), + PIC32_PINCTRL_FUNCTION(C1TX, RPG8R, 15)), + PIC32_PINCTRL_GROUP(105, G9, + PIC32_PINCTRL_FUNCTION(INT1, INT1R, 1), + PIC32_PINCTRL_FUNCTION(T4CK, T4CKR, 1), + PIC32_PINCTRL_FUNCTION(T9CK, T9CKR, 1), + PIC32_PINCTRL_FUNCTION(IC1, IC1R, 1), + PIC32_PINCTRL_FUNCTION(IC6, IC6R, 1), + PIC32_PINCTRL_FUNCTION(U3CTS, U3CTSR, 1), + PIC32_PINCTRL_FUNCTION(U4RX, U4RXR, 1), + PIC32_PINCTRL_FUNCTION(U6RX, U6RXR, 1), + PIC32_PINCTRL_FUNCTION(SS2IN, SS2INR, 1), + PIC32_PINCTRL_FUNCTION(SDI6, SDI6R, 1), + PIC32_PINCTRL_FUNCTION(OCFA, OCFAR, 1), + PIC32_PINCTRL_FUNCTION(REFCLKI3, REFCLKI3R, 1), + PIC32_PINCTRL_FUNCTION(U1RTS, RPG9R, 1), + PIC32_PINCTRL_FUNCTION(U2TX, RPG9R, 2), + PIC32_PINCTRL_FUNCTION(U5RTS, RPG9R, 3), + PIC32_PINCTRL_FUNCTION(U6TX, RPG9R, 4), + PIC32_PINCTRL_FUNCTION(SS2OUT, RPG9R, 6), + PIC32_PINCTRL_FUNCTION(SDO4, RPG9R, 8), + PIC32_PINCTRL_FUNCTION(SDO6, RPG9R, 10), + PIC32_PINCTRL_FUNCTION(OC2, RPG9R, 11), + PIC32_PINCTRL_FUNCTION(OC1, RPG9R, 12), + PIC32_PINCTRL_FUNCTION(OC9, RPG9R, 13), + PIC32_PINCTRL_FUNCTION(C2TX, RPG9R, 15)), +}; + +static inline struct pic32_gpio_bank *irqd_to_bank(struct irq_data *d) +{ + return gpiochip_get_data(irq_data_get_irq_chip_data(d)); +} + +static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl, + unsigned pin) +{ + return &pctl->gpio_banks[pin / PINS_PER_BANK]; +} + +static int pic32_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->groups[group].name; +} + +static int pic32_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops pic32_pinctrl_ops = { + .get_groups_count = pic32_pinctrl_get_groups_count, + .get_group_name = pic32_pinctrl_get_group_name, + .get_group_pins = pic32_pinctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int pic32_pinmux_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->nfunctions; +} + +static const char * +pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->functions[func].name; +} + +static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned func, + const char * const **groups, + unsigned * const num_groups) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->functions[func].groups; + *num_groups = pctl->functions[func].ngroups; + + return 0; +} + +static int pic32_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned func, unsigned group) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct pic32_pin_group *pg = &pctl->groups[group]; + const struct pic32_function *pf = &pctl->functions[func]; + const char *fname = pf->name; + struct pic32_desc_function *functions = pg->functions; + + while (functions->name) { + if (!strcmp(functions->name, fname)) { + dev_dbg(pctl->dev, + "setting function %s reg 0x%x = %d\n", + fname, functions->muxreg, functions->muxval); + + writel(functions->muxval, pctl->reg_base + functions->muxreg); + + return 0; + } + + functions++; + } + + dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); + + return -EINVAL; +} + +static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc); + u32 mask = BIT(offset - bank->gpio_chip.base); + + dev_dbg(pctl->dev, "requesting gpio %d in bank %d with mask 0x%x\n", + offset, bank->gpio_chip.base, mask); + + writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); + + return 0; +} + +static int pic32_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct pic32_gpio_bank *bank = gpiochip_get_data(chip); + u32 mask = BIT(offset); + + writel(mask, bank->reg_base + PIC32_SET(TRIS_REG)); + + return 0; +} + +static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct pic32_gpio_bank *bank = gpiochip_get_data(chip); + + return !!(readl(bank->reg_base + PORT_REG) & BIT(offset)); +} + +static void pic32_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct pic32_gpio_bank *bank = gpiochip_get_data(chip); + u32 mask = BIT(offset); + + if (value) + writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); + else + writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); +} + +static int pic32_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct pic32_gpio_bank *bank = gpiochip_get_data(chip); + u32 mask = BIT(offset); + + pic32_gpio_set(chip, offset, value); + writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG)); + + return 0; +} + +static int pic32_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, bool input) +{ + struct gpio_chip *chip = range->gc; + + if (input) + pic32_gpio_direction_input(chip, offset); + else + pic32_gpio_direction_output(chip, offset, 0); + + return 0; +} + +static const struct pinmux_ops pic32_pinmux_ops = { + .get_functions_count = pic32_pinmux_get_functions_count, + .get_function_name = pic32_pinmux_get_function_name, + .get_function_groups = pic32_pinmux_get_function_groups, + .set_mux = pic32_pinmux_enable, + .gpio_request_enable = pic32_gpio_request_enable, + .gpio_set_direction = pic32_gpio_set_direction, +}; + +static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin); + unsigned param = pinconf_to_config_param(*config); + u32 mask = BIT(pin - bank->gpio_chip.base); + u32 arg; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + arg = !!(readl(bank->reg_base + CNPU_REG) & mask); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = !!(readl(bank->reg_base + CNPD_REG) & mask); + break; + case PIN_CONFIG_MICROCHIP_DIGITAL: + arg = !(readl(bank->reg_base + ANSEL_REG) & mask); + break; + case PIN_CONFIG_MICROCHIP_ANALOG: + arg = !!(readl(bank->reg_base + ANSEL_REG) & mask); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + arg = !!(readl(bank->reg_base + ODCU_REG) & mask); + break; + case PIN_CONFIG_INPUT_ENABLE: + arg = !!(readl(bank->reg_base + TRIS_REG) & mask); + break; + case PIN_CONFIG_OUTPUT: + arg = !(readl(bank->reg_base + TRIS_REG) & mask); + break; + default: + dev_err(pctl->dev, "Property %u not supported\n", param); + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) +{ + struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin); + unsigned param; + u32 arg; + unsigned int i; + u32 offset = pin - bank->gpio_chip.base; + u32 mask = BIT(offset); + + dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n", + pin, bank->gpio_chip.base, mask); + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + dev_dbg(pctl->dev, " pullup\n"); + writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + dev_dbg(pctl->dev, " pulldown\n"); + writel(mask, bank->reg_base + PIC32_SET(CNPD_REG)); + break; + case PIN_CONFIG_MICROCHIP_DIGITAL: + dev_dbg(pctl->dev, " digital\n"); + writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); + break; + case PIN_CONFIG_MICROCHIP_ANALOG: + dev_dbg(pctl->dev, " analog\n"); + writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG)); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + dev_dbg(pctl->dev, " opendrain\n"); + writel(mask, bank->reg_base + PIC32_SET(ODCU_REG)); + break; + case PIN_CONFIG_INPUT_ENABLE: + pic32_gpio_direction_input(&bank->gpio_chip, offset); + break; + case PIN_CONFIG_OUTPUT: + pic32_gpio_direction_output(&bank->gpio_chip, + offset, arg); + break; + default: + dev_err(pctl->dev, "Property %u not supported\n", + param); + return -ENOTSUPP; + } + } + + return 0; +} + +static const struct pinconf_ops pic32_pinconf_ops = { + .pin_config_get = pic32_pinconf_get, + .pin_config_set = pic32_pinconf_set, + .is_generic = true, +}; + +static struct pinctrl_desc pic32_pinctrl_desc = { + .name = "pic32-pinctrl", + .pctlops = &pic32_pinctrl_ops, + .pmxops = &pic32_pinmux_ops, + .confops = &pic32_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + struct pic32_gpio_bank *bank = gpiochip_get_data(chip); + + return !!(readl(bank->reg_base + TRIS_REG) & BIT(offset)); +} + +static void pic32_gpio_irq_ack(struct irq_data *data) +{ + struct pic32_gpio_bank *bank = irqd_to_bank(data); + + writel(0, bank->reg_base + CNF_REG); +} + +static void pic32_gpio_irq_mask(struct irq_data *data) +{ + struct pic32_gpio_bank *bank = irqd_to_bank(data); + + writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); +} + +static void pic32_gpio_irq_unmask(struct irq_data *data) +{ + struct pic32_gpio_bank *bank = irqd_to_bank(data); + + writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); +} + +static unsigned int pic32_gpio_irq_startup(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + + pic32_gpio_direction_input(chip, data->hwirq); + pic32_gpio_irq_unmask(data); + + return 0; +} + +static int pic32_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct pic32_gpio_bank *bank = irqd_to_bank(data); + u32 mask = BIT(data->hwirq); + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + /* enable RISE */ + writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); + /* disable FALL */ + writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG)); + /* enable EDGE */ + writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); + break; + case IRQ_TYPE_EDGE_FALLING: + /* disable RISE */ + writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG)); + /* enable FALL */ + writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); + /* enable EDGE */ + writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); + break; + case IRQ_TYPE_EDGE_BOTH: + /* enable RISE */ + writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); + /* enable FALL */ + writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); + /* enable EDGE */ + writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); + break; + default: + return -EINVAL; + } + + irq_set_handler_locked(data, handle_edge_irq); + + return 0; +} + +static u32 pic32_gpio_get_pending(struct gpio_chip *gc, unsigned long status) +{ + struct pic32_gpio_bank *bank = gpiochip_get_data(gc); + u32 pending = 0; + u32 cnen_rise, cnne_fall; + u32 pin; + + cnen_rise = readl(bank->reg_base + CNEN_REG); + cnne_fall = readl(bank->reg_base + CNNE_REG); + + for_each_set_bit(pin, &status, BITS_PER_LONG) { + u32 mask = BIT(pin); + + if ((mask & cnen_rise) || (mask && cnne_fall)) + pending |= mask; + } + + return pending; +} + +static void pic32_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct pic32_gpio_bank *bank = gpiochip_get_data(gc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long pending; + unsigned int pin; + u32 stat; + + chained_irq_enter(chip, desc); + + stat = readl(bank->reg_base + CNF_REG); + pending = pic32_gpio_get_pending(gc, stat); + + for_each_set_bit(pin, &pending, BITS_PER_LONG) + generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin)); + + chained_irq_exit(chip, desc); +} + +#define GPIO_BANK(_bank, _npins) \ + { \ + .gpio_chip = { \ + .label = "GPIO" #_bank, \ + .request = gpiochip_generic_request, \ + .free = gpiochip_generic_free, \ + .get_direction = pic32_gpio_get_direction, \ + .direction_input = pic32_gpio_direction_input, \ + .direction_output = pic32_gpio_direction_output, \ + .get = pic32_gpio_get, \ + .set = pic32_gpio_set, \ + .ngpio = _npins, \ + .base = GPIO_BANK_START(_bank), \ + .owner = THIS_MODULE, \ + .can_sleep = 0, \ + }, \ + .irq_chip = { \ + .name = "GPIO" #_bank, \ + .irq_startup = pic32_gpio_irq_startup, \ + .irq_ack = pic32_gpio_irq_ack, \ + .irq_mask = pic32_gpio_irq_mask, \ + .irq_unmask = pic32_gpio_irq_unmask, \ + .irq_set_type = pic32_gpio_irq_set_type, \ + }, \ + } + +static struct pic32_gpio_bank pic32_gpio_banks[] = { + GPIO_BANK(0, PINS_PER_BANK), + GPIO_BANK(1, PINS_PER_BANK), + GPIO_BANK(2, PINS_PER_BANK), + GPIO_BANK(3, PINS_PER_BANK), + GPIO_BANK(4, PINS_PER_BANK), + GPIO_BANK(5, PINS_PER_BANK), + GPIO_BANK(6, PINS_PER_BANK), + GPIO_BANK(7, PINS_PER_BANK), + GPIO_BANK(8, PINS_PER_BANK), + GPIO_BANK(9, PINS_PER_BANK), +}; + +static int pic32_pinctrl_probe(struct platform_device *pdev) +{ + struct pic32_pinctrl *pctl; + struct resource *res; + int ret; + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + pctl->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, pctl); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctl->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctl->reg_base)) + return PTR_ERR(pctl->reg_base); + + pctl->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pctl->clk)) { + ret = PTR_ERR(pctl->clk); + dev_err(&pdev->dev, "clk get failed\n"); + return ret; + } + + ret = clk_prepare_enable(pctl->clk); + if (ret) { + dev_err(&pdev->dev, "clk enable failed\n"); + return ret; + } + + pctl->pins = pic32_pins; + pctl->npins = ARRAY_SIZE(pic32_pins); + pctl->functions = pic32_functions; + pctl->nfunctions = ARRAY_SIZE(pic32_functions); + pctl->groups = pic32_groups; + pctl->ngroups = ARRAY_SIZE(pic32_groups); + pctl->gpio_banks = pic32_gpio_banks; + pctl->nbanks = ARRAY_SIZE(pic32_gpio_banks); + + pic32_pinctrl_desc.pins = pctl->pins; + pic32_pinctrl_desc.npins = pctl->npins; + pic32_pinctrl_desc.custom_params = pic32_mpp_bindings; + pic32_pinctrl_desc.num_custom_params = ARRAY_SIZE(pic32_mpp_bindings); + + pctl->pctldev = pinctrl_register(&pic32_pinctrl_desc, &pdev->dev, pctl); + if (IS_ERR(pctl->pctldev)) { + dev_err(&pdev->dev, "Failed to register pinctrl device\n"); + return PTR_ERR(pctl->pctldev); + } + + return 0; +} + +static int pic32_gpio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct pic32_gpio_bank *bank; + u32 id; + int irq, ret; + struct resource *res; + + if (of_property_read_u32(np, "microchip,gpio-bank", &id)) { + dev_err(&pdev->dev, "microchip,gpio-bank property not found\n"); + return -EINVAL; + } + + if (id >= ARRAY_SIZE(pic32_gpio_banks)) { + dev_err(&pdev->dev, "invalid microchip,gpio-bank property\n"); + return -EINVAL; + } + + bank = &pic32_gpio_banks[id]; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + bank->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(bank->reg_base)) + return PTR_ERR(bank->reg_base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "irq get failed\n"); + return irq; + } + + bank->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(bank->clk)) { + ret = PTR_ERR(bank->clk); + dev_err(&pdev->dev, "clk get failed\n"); + return ret; + } + + ret = clk_prepare_enable(bank->clk); + if (ret) { + dev_err(&pdev->dev, "clk enable failed\n"); + return ret; + } + + bank->gpio_chip.parent = &pdev->dev; + bank->gpio_chip.of_node = np; + ret = gpiochip_add_data(&bank->gpio_chip, bank); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", + id, ret); + return ret; + } + + ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, + 0, handle_level_irq, IRQ_TYPE_NONE); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n", + id, ret); + gpiochip_remove(&bank->gpio_chip); + return ret; + } + + gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, + irq, pic32_gpio_irq_handler); + + return 0; +} + +static const struct of_device_id pic32_pinctrl_of_match[] = { + { .compatible = "microchip,pic32mzda-pinctrl", }, + { }, +}; + +static struct platform_driver pic32_pinctrl_driver = { + .driver = { + .name = "pic32-pinctrl", + .of_match_table = pic32_pinctrl_of_match, + .suppress_bind_attrs = true, + }, + .probe = pic32_pinctrl_probe, +}; + +static const struct of_device_id pic32_gpio_of_match[] = { + { .compatible = "microchip,pic32mzda-gpio", }, + { }, +}; + +static struct platform_driver pic32_gpio_driver = { + .driver = { + .name = "pic32-gpio", + .of_match_table = pic32_gpio_of_match, + .suppress_bind_attrs = true, + }, + .probe = pic32_gpio_probe, +}; + +static int __init pic32_gpio_register(void) +{ + return platform_driver_register(&pic32_gpio_driver); +} +arch_initcall(pic32_gpio_register); + +static int __init pic32_pinctrl_register(void) +{ + return platform_driver_register(&pic32_pinctrl_driver); +} +arch_initcall(pic32_pinctrl_register); diff --git a/drivers/pinctrl/pinctrl-pic32.h b/drivers/pinctrl/pinctrl-pic32.h new file mode 100644 index 000000000000..12826267dc96 --- /dev/null +++ b/drivers/pinctrl/pinctrl-pic32.h @@ -0,0 +1,141 @@ +/* + * PIC32 pinctrl driver + * + * Joshua Henderson, <joshua.henderson@microchip.com> + * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef PINCTRL_PINCTRL_PIC32_H +#define PINCTRL_PINCTRL_PIC32_H + +/* PORT Registers */ +#define ANSEL_REG 0x00 +#define TRIS_REG 0x10 +#define PORT_REG 0x20 +#define LAT_REG 0x30 +#define ODCU_REG 0x40 +#define CNPU_REG 0x50 +#define CNPD_REG 0x60 +#define CNCON_REG 0x70 +#define CNEN_REG 0x80 +#define CNSTAT_REG 0x90 +#define CNNE_REG 0xA0 +#define CNF_REG 0xB0 + +/* Input PPS Registers */ +#define INT1R 0x04 +#define INT2R 0x08 +#define INT3R 0x0C +#define INT4R 0x10 +#define T2CKR 0x18 +#define T3CKR 0x1C +#define T4CKR 0x20 +#define T5CKR 0x24 +#define T6CKR 0x28 +#define T7CKR 0x2C +#define T8CKR 0x30 +#define T9CKR 0x34 +#define IC1R 0x38 +#define IC2R 0x3C +#define IC3R 0x40 +#define IC4R 0x44 +#define IC5R 0x48 +#define IC6R 0x4C +#define IC7R 0x50 +#define IC8R 0x54 +#define IC9R 0x58 +#define OCFAR 0x60 +#define U1RXR 0x68 +#define U1CTSR 0x6C +#define U2RXR 0x70 +#define U2CTSR 0x74 +#define U3RXR 0x78 +#define U3CTSR 0x7C +#define U4RXR 0x80 +#define U4CTSR 0x84 +#define U5RXR 0x88 +#define U5CTSR 0x8C +#define U6RXR 0x90 +#define U6CTSR 0x94 +#define SDI1R 0x9C +#define SS1INR 0xA0 +#define SDI2R 0xA8 +#define SS2INR 0xAC +#define SDI3R 0xB4 +#define SS3INR 0xB8 +#define SDI4R 0xC0 +#define SS4INR 0xC4 +#define SDI5R 0xCC +#define SS5INR 0xD0 +#define SDI6R 0xD8 +#define SS6INR 0xDC +#define C1RXR 0xE0 +#define C2RXR 0xE4 +#define REFCLKI1R 0xE8 +#define REFCLKI3R 0xF0 +#define REFCLKI4R 0xF4 + +/* Output PPS Registers */ +#define RPA14R 0x138 +#define RPA15R 0x13C +#define RPB0R 0x140 +#define RPB1R 0x144 +#define RPB2R 0x148 +#define RPB3R 0x14C +#define RPB5R 0x154 +#define RPB6R 0x158 +#define RPB7R 0x15C +#define RPB8R 0x160 +#define RPB9R 0x164 +#define RPB10R 0x168 +#define RPB14R 0x178 +#define RPB15R 0x17C +#define RPC1R 0x184 +#define RPC2R 0x188 +#define RPC3R 0x18C +#define RPC4R 0x190 +#define RPC13R 0x1B4 +#define RPC14R 0x1B8 +#define RPD0R 0x1C0 +#define RPD1R 0x1C4 +#define RPD2R 0x1C8 +#define RPD3R 0x1CC +#define RPD4R 0x1D0 +#define RPD5R 0x1D4 +#define RPD6R 0x1D8 +#define RPD7R 0x1DC +#define RPD9R 0x1E4 +#define RPD10R 0x1E8 +#define RPD11R 0x1EC +#define RPD12R 0x1F0 +#define RPD14R 0x1F8 +#define RPD15R 0x1FC +#define RPE3R 0x20C +#define RPE5R 0x214 +#define RPE8R 0x220 +#define RPE9R 0x224 +#define RPF0R 0x240 +#define RPF1R 0x244 +#define RPF2R 0x248 +#define RPF3R 0x24C +#define RPF4R 0x250 +#define RPF5R 0x254 +#define RPF8R 0x260 +#define RPF12R 0x270 +#define RPF13R 0x274 +#define RPG0R 0x280 +#define RPG1R 0x284 +#define RPG6R 0x298 +#define RPG7R 0x29C +#define RPG8R 0x2A0 +#define RPG9R 0x2A4 + +#endif /* PINCTRL_PINCTRL_PIC32_H */ diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index fac844a85cb4..cab66c64149f 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -985,6 +985,7 @@ static struct pinmux_ops st_pmxops = { .get_function_groups = st_pmx_get_groups, .set_mux = st_pmx_set_mux, .gpio_set_direction = st_pmx_set_gpio_direction, + .strict = true, }; /* Pinconf */ diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 2f18323571a6..2a3e5490a483 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -117,6 +117,7 @@ * @output_enabled: Set to true if MPP output logic is enabled. * @input_enabled: Set to true if MPP input buffer logic is enabled. * @paired: Pin operates in paired mode + * @has_pullup: Pin has support to configure pullup * @num_sources: Number of power-sources supported by this MPP. * @power_source: Current power-source used. * @amux_input: Set the source for analog input. @@ -134,6 +135,7 @@ struct pmic_mpp_pad { bool output_enabled; bool input_enabled; bool paired; + bool has_pullup; unsigned int num_sources; unsigned int power_source; unsigned int amux_input; @@ -477,11 +479,14 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, if (ret < 0) return ret; - val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; + if (pad->has_pullup) { + val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; - ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val); - if (ret < 0) - return ret; + ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, + val); + if (ret < 0) + return ret; + } val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; @@ -534,7 +539,8 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); seq_printf(s, " vin-%d", pad->power_source); seq_printf(s, " %d", pad->aout_level); - seq_printf(s, " %-8s", biases[pad->pullup]); + if (pad->has_pullup) + seq_printf(s, " %-8s", biases[pad->pullup]); seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); if (pad->dtest) seq_printf(s, " dtest%d", pad->dtest); @@ -748,12 +754,16 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; pad->power_source &= PMIC_MPP_REG_VIN_MASK; - val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); - if (val < 0) - return val; + if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT && + subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) { + val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); + if (val < 0) + return val; - pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; - pad->pullup &= PMIC_MPP_REG_PULL_MASK; + pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; + pad->pullup &= PMIC_MPP_REG_PULL_MASK; + pad->has_pullup = true; + } val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); if (val < 0) diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig new file mode 100644 index 000000000000..0f28841b2332 --- /dev/null +++ b/drivers/pinctrl/stm32/Kconfig @@ -0,0 +1,16 @@ +if ARCH_STM32 || COMPILE_TEST + +config PINCTRL_STM32 + bool + depends on OF + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + +config PINCTRL_STM32F429 + bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429 + depends on OF + default MACH_STM32F429 + select PINCTRL_STM32 + +endif diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile new file mode 100644 index 000000000000..fc17d4238845 --- /dev/null +++ b/drivers/pinctrl/stm32/Makefile @@ -0,0 +1,5 @@ +# Core +obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o + +# SoC Drivers +obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c new file mode 100644 index 000000000000..8deb566ed4cd --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -0,0 +1,829 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + * + * Heavily based on Mediatek's pinctrl driver + */ +#include <linux/clk.h> +#include <linux/gpio/driver.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/reset.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "pinctrl-stm32.h" + +#define STM32_GPIO_MODER 0x00 +#define STM32_GPIO_TYPER 0x04 +#define STM32_GPIO_SPEEDR 0x08 +#define STM32_GPIO_PUPDR 0x0c +#define STM32_GPIO_IDR 0x10 +#define STM32_GPIO_ODR 0x14 +#define STM32_GPIO_BSRR 0x18 +#define STM32_GPIO_LCKR 0x1c +#define STM32_GPIO_AFRL 0x20 +#define STM32_GPIO_AFRH 0x24 + +#define STM32_GPIO_PINS_PER_BANK 16 + +#define gpio_range_to_bank(chip) \ + container_of(chip, struct stm32_gpio_bank, range) + +static const char * const stm32_gpio_functions[] = { + "gpio", "af0", "af1", + "af2", "af3", "af4", + "af5", "af6", "af7", + "af8", "af9", "af10", + "af11", "af12", "af13", + "af14", "af15", "analog", +}; + +struct stm32_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +struct stm32_gpio_bank { + void __iomem *base; + struct clk *clk; + spinlock_t lock; + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range range; +}; + +struct stm32_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl_dev; + struct pinctrl_desc pctl_desc; + struct stm32_pinctrl_group *groups; + unsigned ngroups; + const char **grp_names; + struct stm32_gpio_bank *banks; + unsigned nbanks; + const struct stm32_pinctrl_match_data *match_data; +}; + +static inline int stm32_gpio_pin(int gpio) +{ + return gpio % STM32_GPIO_PINS_PER_BANK; +} + +static inline u32 stm32_gpio_get_mode(u32 function) +{ + switch (function) { + case STM32_PIN_GPIO: + return 0; + case STM32_PIN_AF(0) ... STM32_PIN_AF(15): + return 2; + case STM32_PIN_ANALOG: + return 3; + } + + return 0; +} + +static inline u32 stm32_gpio_get_alt(u32 function) +{ + switch (function) { + case STM32_PIN_GPIO: + return 0; + case STM32_PIN_AF(0) ... STM32_PIN_AF(15): + return function - 1; + case STM32_PIN_ANALOG: + return 0; + } + + return 0; +} + +/* GPIO functions */ + +static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, + unsigned offset, int value) +{ + if (!value) + offset += STM32_GPIO_PINS_PER_BANK; + + clk_enable(bank->clk); + + writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); + + clk_disable(bank->clk); +} + +static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct stm32_gpio_bank *bank = gpiochip_get_data(chip); + int ret; + + clk_enable(bank->clk); + + ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); + + clk_disable(bank->clk); + + return ret; +} + +static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct stm32_gpio_bank *bank = gpiochip_get_data(chip); + + __stm32_gpio_set(bank, offset, value); +} + +static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int stm32_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct stm32_gpio_bank *bank = gpiochip_get_data(chip); + + __stm32_gpio_set(bank, offset, value); + pinctrl_gpio_direction_output(chip->base + offset); + + return 0; +} + +static struct gpio_chip stm32_gpio_template = { + .request = stm32_gpio_request, + .free = stm32_gpio_free, + .get = stm32_gpio_get, + .set = stm32_gpio_set, + .direction_input = stm32_gpio_direction_input, + .direction_output = stm32_gpio_direction_output, +}; + +/* Pinctrl functions */ + +static struct stm32_pinctrl_group * +stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) +{ + int i; + + for (i = 0; i < pctl->ngroups; i++) { + struct stm32_pinctrl_group *grp = pctl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, + u32 pin_num, u32 fnum) +{ + int i; + + for (i = 0; i < pctl->match_data->npins; i++) { + const struct stm32_desc_pin *pin = pctl->match_data->pins + i; + const struct stm32_desc_function *func = pin->functions; + + if (pin->pin.number != pin_num) + continue; + + while (func && func->name) { + if (func->num == fnum) + return true; + func++; + } + + break; + } + + return false; +} + +static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, + u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, + struct pinctrl_map **map, unsigned *reserved_maps, + unsigned *num_maps) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = grp->name; + + if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { + dev_err(pctl->dev, "invalid function %d on pin %d .\n", + fnum, pin); + return -EINVAL; + } + + (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; + (*num_maps)++; + + return 0; +} + +static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + struct stm32_pinctrl *pctl; + struct stm32_pinctrl_group *grp; + struct property *pins; + u32 pinfunc, pin, func; + unsigned long *configs; + unsigned int num_configs; + bool has_config = 0; + unsigned reserve = 0; + int num_pins, num_funcs, maps_per_pin, i, err; + + pctl = pinctrl_dev_get_drvdata(pctldev); + + pins = of_find_property(node, "pinmux", NULL); + if (!pins) { + dev_err(pctl->dev, "missing pins property in node %s .\n", + node->name); + return -EINVAL; + } + + err = pinconf_generic_parse_dt_config(node, pctldev, &configs, + &num_configs); + if (err) + return err; + + if (num_configs) + has_config = 1; + + num_pins = pins->length / sizeof(u32); + num_funcs = num_pins; + maps_per_pin = 0; + if (num_funcs) + maps_per_pin++; + if (has_config && num_pins >= 1) + maps_per_pin++; + + if (!num_pins || !maps_per_pin) + return -EINVAL; + + reserve = num_pins * maps_per_pin; + + err = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, num_maps, reserve); + if (err) + return err; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(node, "pinmux", + i, &pinfunc); + if (err) + return err; + + pin = STM32_GET_PIN_NO(pinfunc); + func = STM32_GET_PIN_FUNC(pinfunc); + + if (pin >= pctl->match_data->npins) { + dev_err(pctl->dev, "invalid pin number.\n"); + return -EINVAL; + } + + if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { + dev_err(pctl->dev, "invalid function.\n"); + return -EINVAL; + } + + grp = stm32_pctrl_find_group_by_pin(pctl, pin); + if (!grp) { + dev_err(pctl->dev, "unable to match pin %d to group\n", + pin); + return -EINVAL; + } + + err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, + reserved_maps, num_maps); + if (err) + return err; + + if (has_config) { + err = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, grp->name, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (err) + return err; + } + } + + return 0; +} + +static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct device_node *np; + unsigned reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->ngroups; +} + +static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->groups[group].name; +} + +static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned *)&pctl->groups[group].pin; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops stm32_pctrl_ops = { + .dt_node_to_map = stm32_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, + .get_groups_count = stm32_pctrl_get_groups_count, + .get_group_name = stm32_pctrl_get_group_name, + .get_group_pins = stm32_pctrl_get_group_pins, +}; + + +/* Pinmux functions */ + +static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(stm32_gpio_functions); +} + +static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return stm32_gpio_functions[selector]; +} + +static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->grp_names; + *num_groups = pctl->ngroups; + + return 0; +} + +static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, + int pin, u32 mode, u32 alt) +{ + u32 val; + int alt_shift = (pin % 8) * 4; + int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; + unsigned long flags; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + alt_offset); + val &= ~GENMASK(alt_shift + 3, alt_shift); + val |= (alt << alt_shift); + writel_relaxed(val, bank->base + alt_offset); + + val = readl_relaxed(bank->base + STM32_GPIO_MODER); + val &= ~GENMASK(pin * 2 + 1, pin * 2); + val |= mode << (pin * 2); + writel_relaxed(val, bank->base + STM32_GPIO_MODER); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + bool ret; + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct stm32_pinctrl_group *g = pctl->groups + group; + struct pinctrl_gpio_range *range; + struct stm32_gpio_bank *bank; + u32 mode, alt; + int pin; + + ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); + if (!ret) { + dev_err(pctl->dev, "invalid function %d on group %d .\n", + function, group); + return -EINVAL; + } + + range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); + bank = gpio_range_to_bank(range); + pin = stm32_gpio_pin(g->pin); + + mode = stm32_gpio_get_mode(function); + alt = stm32_gpio_get_alt(function); + + stm32_pmx_set_mode(bank, pin, mode, alt); + + return 0; +} + +static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned gpio, + bool input) +{ + struct stm32_gpio_bank *bank = gpio_range_to_bank(range); + int pin = stm32_gpio_pin(gpio); + + stm32_pmx_set_mode(bank, pin, !input, 0); + + return 0; +} + +static const struct pinmux_ops stm32_pmx_ops = { + .get_functions_count = stm32_pmx_get_funcs_cnt, + .get_function_name = stm32_pmx_get_func_name, + .get_function_groups = stm32_pmx_get_func_groups, + .set_mux = stm32_pmx_set_mux, + .gpio_set_direction = stm32_pmx_gpio_set_direction, +}; + +/* Pinconf functions */ + +static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, + unsigned offset, u32 drive) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_TYPER); + val &= ~BIT(offset); + val |= drive << offset; + writel_relaxed(val, bank->base + STM32_GPIO_TYPER); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, + unsigned offset, u32 speed) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); + val &= ~GENMASK(offset * 2 + 1, offset * 2); + val |= speed << (offset * 2); + writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, + unsigned offset, u32 bias) +{ + unsigned long flags; + u32 val; + + clk_enable(bank->clk); + spin_lock_irqsave(&bank->lock, flags); + + val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); + val &= ~GENMASK(offset * 2 + 1, offset * 2); + val |= bias << (offset * 2); + writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); + + spin_unlock_irqrestore(&bank->lock, flags); + clk_disable(bank->clk); +} + +static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, + unsigned int pin, enum pin_config_param param, + enum pin_config_param arg) +{ + struct pinctrl_gpio_range *range; + struct stm32_gpio_bank *bank; + int offset, ret = 0; + + range = pinctrl_find_gpio_range_from_pin(pctldev, pin); + bank = gpio_range_to_bank(range); + offset = stm32_gpio_pin(pin); + + switch (param) { + case PIN_CONFIG_DRIVE_PUSH_PULL: + stm32_pconf_set_driving(bank, offset, 0); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + stm32_pconf_set_driving(bank, offset, 1); + break; + case PIN_CONFIG_SLEW_RATE: + stm32_pconf_set_speed(bank, offset, arg); + break; + case PIN_CONFIG_BIAS_DISABLE: + stm32_pconf_set_bias(bank, offset, 0); + break; + case PIN_CONFIG_BIAS_PULL_UP: + stm32_pconf_set_bias(bank, offset, 1); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + stm32_pconf_set_bias(bank, offset, 2); + break; + case PIN_CONFIG_OUTPUT: + __stm32_gpio_set(bank, offset, arg); + ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *config = pctl->groups[group].config; + + return 0; +} + +static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + unsigned long *configs, unsigned num_configs) +{ + struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct stm32_pinctrl_group *g = &pctl->groups[group]; + int i, ret; + + for (i = 0; i < num_configs; i++) { + ret = stm32_pconf_parse_conf(pctldev, g->pin, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + if (ret < 0) + return ret; + + g->config = configs[i]; + } + + return 0; +} + +static const struct pinconf_ops stm32_pconf_ops = { + .pin_config_group_get = stm32_pconf_group_get, + .pin_config_group_set = stm32_pconf_group_set, +}; + +static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, + struct device_node *np) +{ + int bank_nr = pctl->nbanks; + struct stm32_gpio_bank *bank = &pctl->banks[bank_nr]; + struct pinctrl_gpio_range *range = &bank->range; + struct device *dev = pctl->dev; + struct resource res; + struct reset_control *rstc; + int err, npins; + + rstc = of_reset_control_get(np, NULL); + if (!IS_ERR(rstc)) + reset_control_deassert(rstc); + + if (of_address_to_resource(np, 0, &res)) + return -ENODEV; + + bank->base = devm_ioremap_resource(dev, &res); + if (IS_ERR(bank->base)) + return PTR_ERR(bank->base); + + bank->clk = of_clk_get_by_name(np, NULL); + if (IS_ERR(bank->clk)) { + dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); + return PTR_ERR(bank->clk); + } + + err = clk_prepare(bank->clk); + if (err) { + dev_err(dev, "failed to prepare clk (%d)\n", err); + return err; + } + + npins = pctl->match_data->npins; + npins -= bank_nr * STM32_GPIO_PINS_PER_BANK; + if (npins < 0) + return -EINVAL; + else if (npins > STM32_GPIO_PINS_PER_BANK) + npins = STM32_GPIO_PINS_PER_BANK; + + bank->gpio_chip = stm32_gpio_template; + bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; + bank->gpio_chip.ngpio = npins; + bank->gpio_chip.of_node = np; + bank->gpio_chip.parent = dev; + spin_lock_init(&bank->lock); + + of_property_read_string(np, "st,bank-name", &range->name); + bank->gpio_chip.label = range->name; + + range->id = bank_nr; + range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; + range->npins = bank->gpio_chip.ngpio; + range->gc = &bank->gpio_chip; + err = gpiochip_add_data(&bank->gpio_chip, bank); + if (err) { + dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); + return err; + } + + dev_info(dev, "%s bank added\n", range->name); + return 0; +} + +static int stm32_pctrl_build_state(struct platform_device *pdev) +{ + struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); + int i; + + pctl->ngroups = pctl->match_data->npins; + + /* Allocate groups */ + pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->groups), GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + /* We assume that one pin is one group, use pin name as group name. */ + pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->grp_names), GFP_KERNEL); + if (!pctl->grp_names) + return -ENOMEM; + + for (i = 0; i < pctl->match_data->npins; i++) { + const struct stm32_desc_pin *pin = pctl->match_data->pins + i; + struct stm32_pinctrl_group *group = pctl->groups + i; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + + pctl->grp_names[i] = pin->pin.name; + } + + return 0; +} + +int stm32_pctl_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct stm32_pinctrl *pctl; + struct pinctrl_pin_desc *pins; + int i, ret, banks = 0; + + if (!np) + return -EINVAL; + + match = of_match_device(dev->driver->of_match_table, dev); + if (!match || !match->data) + return -EINVAL; + + if (!of_find_property(np, "pins-are-numbered", NULL)) { + dev_err(dev, "only support pins-are-numbered format\n"); + return -EINVAL; + } + + pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctl); + + pctl->dev = dev; + pctl->match_data = match->data; + ret = stm32_pctrl_build_state(pdev); + if (ret) { + dev_err(dev, "build state failed: %d\n", ret); + return -EINVAL; + } + + for_each_child_of_node(np, child) + if (of_property_read_bool(child, "gpio-controller")) + banks++; + + if (!banks) { + dev_err(dev, "at least one GPIO bank is required\n"); + return -EINVAL; + } + + pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), + GFP_KERNEL); + if (!pctl->banks) + return -ENOMEM; + + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + ret = stm32_gpiolib_register_bank(pctl, child); + if (ret) + return ret; + + pctl->nbanks++; + } + } + + pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctl->match_data->npins; i++) + pins[i] = pctl->match_data->pins[i].pin; + + pctl->pctl_desc.name = dev_name(&pdev->dev); + pctl->pctl_desc.owner = THIS_MODULE; + pctl->pctl_desc.pins = pins; + pctl->pctl_desc.npins = pctl->match_data->npins; + pctl->pctl_desc.confops = &stm32_pconf_ops; + pctl->pctl_desc.pctlops = &stm32_pctrl_ops; + pctl->pctl_desc.pmxops = &stm32_pmx_ops; + pctl->dev = &pdev->dev; + + pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl); + if (!pctl->pctl_dev) { + dev_err(&pdev->dev, "Failed pinctrl registration\n"); + return -EINVAL; + } + + for (i = 0; i < pctl->nbanks; i++) + pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range); + + dev_info(dev, "Pinctrl STM32 initialized\n"); + + return 0; +} + diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h new file mode 100644 index 000000000000..35ebc94c01e4 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + */ +#ifndef __PINCTRL_STM32_H +#define __PINCTRL_STM32_H + +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> + +#define STM32_PIN_NO(x) ((x) << 8) +#define STM32_GET_PIN_NO(x) ((x) >> 8) +#define STM32_GET_PIN_FUNC(x) ((x) & 0xff) + +#define STM32_PIN_GPIO 0 +#define STM32_PIN_AF(x) ((x) + 1) +#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1) + +struct stm32_desc_function { + const char *name; + const unsigned char num; +}; + +struct stm32_desc_pin { + struct pinctrl_pin_desc pin; + const struct stm32_desc_function *functions; +}; + +#define STM32_PIN(_pin, ...) \ + { \ + .pin = _pin, \ + .functions = (struct stm32_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define STM32_FUNCTION(_num, _name) \ + { \ + .num = _num, \ + .name = _name, \ + } + +struct stm32_pinctrl_match_data { + const struct stm32_desc_pin *pins; + const unsigned int npins; +}; + +int stm32_pctl_probe(struct platform_device *pdev); + +#endif /* __PINCTRL_STM32_H */ + diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f429.c b/drivers/pinctrl/stm32/pinctrl-stm32f429.c new file mode 100644 index 000000000000..f34016b51375 --- /dev/null +++ b/drivers/pinctrl/stm32/pinctrl-stm32f429.c @@ -0,0 +1,1598 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-stm32.h" + +static const struct stm32_desc_pin stm32f429_pins[] = { + STM32_PIN( + PINCTRL_PIN(0, "PA0"), + STM32_FUNCTION(0, "GPIOA0"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(1, "PA1"), + STM32_FUNCTION(0, "GPIOA1"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(8, "USART2_RTS"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(2, "PA2"), + STM32_FUNCTION(0, "GPIOA2"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(12, "ETH_MDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(3, "PA3"), + STM32_FUNCTION(0, "GPIOA3"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D0"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(4, "PA4"), + STM32_FUNCTION(0, "GPIOA4"), + STM32_FUNCTION(6, "SPI1_NSS"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(8, "USART2_CK"), + STM32_FUNCTION(13, "OTG_HS_SOF"), + STM32_FUNCTION(14, "DCMI_HSYNC"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(5, "PA5"), + STM32_FUNCTION(0, "GPIOA5"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(6, "SPI1_SCK"), + STM32_FUNCTION(11, "OTG_HS_ULPI_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(6, "PA6"), + STM32_FUNCTION(0, "GPIOA6"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(14, "DCMI_PIXCLK"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(7, "PA7"), + STM32_FUNCTION(0, "GPIOA7"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(8, "PA8"), + STM32_FUNCTION(0, "GPIOA8"), + STM32_FUNCTION(1, "MCO1"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(8, "USART1_CK"), + STM32_FUNCTION(11, "OTG_FS_SOF"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(9, "PA9"), + STM32_FUNCTION(0, "GPIOA9"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(10, "PA10"), + STM32_FUNCTION(0, "GPIOA10"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(11, "OTG_FS_ID"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(11, "PA11"), + STM32_FUNCTION(0, "GPIOA11"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(8, "USART1_CTS"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(11, "OTG_FS_DM"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(12, "PA12"), + STM32_FUNCTION(0, "GPIOA12"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(8, "USART1_RTS"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(11, "OTG_FS_DP"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(13, "PA13"), + STM32_FUNCTION(0, "GPIOA13"), + STM32_FUNCTION(1, "JTMS SWDIO"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(14, "PA14"), + STM32_FUNCTION(0, "GPIOA14"), + STM32_FUNCTION(1, "JTCK SWCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(15, "PA15"), + STM32_FUNCTION(0, "GPIOA15"), + STM32_FUNCTION(1, "JTDI"), + STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), + STM32_FUNCTION(6, "SPI1_NSS"), + STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(16, "PB0"), + STM32_FUNCTION(0, "GPIOB0"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(10, "LCD_R3"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D1"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(17, "PB1"), + STM32_FUNCTION(0, "GPIOB1"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(10, "LCD_R6"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D2"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(18, "PB2"), + STM32_FUNCTION(0, "GPIOB2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(19, "PB3"), + STM32_FUNCTION(0, "GPIOB3"), + STM32_FUNCTION(1, "JTDO TRACESWO"), + STM32_FUNCTION(2, "TIM2_CH2"), + STM32_FUNCTION(6, "SPI1_SCK"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(20, "PB4"), + STM32_FUNCTION(0, "GPIOB4"), + STM32_FUNCTION(1, "NJTRST"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(6, "SPI1_MISO"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "I2S3EXT_SD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(21, "PB5"), + STM32_FUNCTION(0, "GPIOB5"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(5, "I2C1_SMBA"), + STM32_FUNCTION(6, "SPI1_MOSI"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(10, "CAN2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D7"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(22, "PB6"), + STM32_FUNCTION(0, "GPIOB6"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(8, "USART1_TX"), + STM32_FUNCTION(10, "CAN2_TX"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(23, "PB7"), + STM32_FUNCTION(0, "GPIOB7"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(8, "USART1_RX"), + STM32_FUNCTION(13, "FMC_NL"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(24, "PB8"), + STM32_FUNCTION(0, "GPIOB8"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(4, "TIM10_CH1"), + STM32_FUNCTION(5, "I2C1_SCL"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "SDIO_D4"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(25, "PB9"), + STM32_FUNCTION(0, "GPIOB9"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(4, "TIM11_CH1"), + STM32_FUNCTION(5, "I2C1_SDA"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "SDIO_D5"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(26, "PB10"), + STM32_FUNCTION(0, "GPIOB10"), + STM32_FUNCTION(2, "TIM2_CH3"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D3"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(27, "PB11"), + STM32_FUNCTION(0, "GPIOB11"), + STM32_FUNCTION(2, "TIM2_CH4"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D4"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(28, "PB12"), + STM32_FUNCTION(0, "GPIOB12"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(10, "CAN2_RX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D5"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "OTG_HS_ID"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(29, "PB13"), + STM32_FUNCTION(0, "GPIOB13"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(10, "CAN2_TX"), + STM32_FUNCTION(11, "OTG_HS_ULPI_D6"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(30, "PB14"), + STM32_FUNCTION(0, "GPIOB14"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(13, "OTG_HS_DM"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(31, "PB15"), + STM32_FUNCTION(0, "GPIOB15"), + STM32_FUNCTION(1, "RTC_REFIN"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(13, "OTG_HS_DP"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(32, "PC0"), + STM32_FUNCTION(0, "GPIOC0"), + STM32_FUNCTION(11, "OTG_HS_ULPI_STP"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(33, "PC1"), + STM32_FUNCTION(0, "GPIOC1"), + STM32_FUNCTION(12, "ETH_MDC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(34, "PC2"), + STM32_FUNCTION(0, "GPIOC2"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"), + STM32_FUNCTION(12, "ETH_MII_TXD2"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(35, "PC3"), + STM32_FUNCTION(0, "GPIOC3"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"), + STM32_FUNCTION(12, "ETH_MII_TX_CLK"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(36, "PC4"), + STM32_FUNCTION(0, "GPIOC4"), + STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(37, "PC5"), + STM32_FUNCTION(0, "GPIOC5"), + STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(38, "PC6"), + STM32_FUNCTION(0, "GPIOC6"), + STM32_FUNCTION(3, "TIM3_CH1"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(6, "I2S2_MCK"), + STM32_FUNCTION(9, "USART6_TX"), + STM32_FUNCTION(13, "SDIO_D6"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(39, "PC7"), + STM32_FUNCTION(0, "GPIOC7"), + STM32_FUNCTION(3, "TIM3_CH2"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(7, "I2S3_MCK"), + STM32_FUNCTION(9, "USART6_RX"), + STM32_FUNCTION(13, "SDIO_D7"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(40, "PC8"), + STM32_FUNCTION(0, "GPIOC8"), + STM32_FUNCTION(3, "TIM3_CH3"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(9, "USART6_CK"), + STM32_FUNCTION(13, "SDIO_D0"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(41, "PC9"), + STM32_FUNCTION(0, "GPIOC9"), + STM32_FUNCTION(1, "MCO2"), + STM32_FUNCTION(3, "TIM3_CH4"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(6, "I2S_CKIN"), + STM32_FUNCTION(13, "SDIO_D1"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(42, "PC10"), + STM32_FUNCTION(0, "GPIOC10"), + STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(9, "UART4_TX"), + STM32_FUNCTION(13, "SDIO_D2"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(43, "PC11"), + STM32_FUNCTION(0, "GPIOC11"), + STM32_FUNCTION(6, "I2S3EXT_SD"), + STM32_FUNCTION(7, "SPI3_MISO"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(9, "UART4_RX"), + STM32_FUNCTION(13, "SDIO_D3"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(44, "PC12"), + STM32_FUNCTION(0, "GPIOC12"), + STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(9, "UART5_TX"), + STM32_FUNCTION(13, "SDIO_CK"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(45, "PC13"), + STM32_FUNCTION(0, "GPIOC13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(46, "PC14"), + STM32_FUNCTION(0, "GPIOC14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(47, "PC15"), + STM32_FUNCTION(0, "GPIOC15"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(48, "PD0"), + STM32_FUNCTION(0, "GPIOD0"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(13, "FMC_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(49, "PD1"), + STM32_FUNCTION(0, "GPIOD1"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "FMC_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(50, "PD2"), + STM32_FUNCTION(0, "GPIOD2"), + STM32_FUNCTION(3, "TIM3_ETR"), + STM32_FUNCTION(9, "UART5_RX"), + STM32_FUNCTION(13, "SDIO_CMD"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(51, "PD3"), + STM32_FUNCTION(0, "GPIOD3"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(8, "USART2_CTS"), + STM32_FUNCTION(13, "FMC_CLK"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(52, "PD4"), + STM32_FUNCTION(0, "GPIOD4"), + STM32_FUNCTION(8, "USART2_RTS"), + STM32_FUNCTION(13, "FMC_NOE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(53, "PD5"), + STM32_FUNCTION(0, "GPIOD5"), + STM32_FUNCTION(8, "USART2_TX"), + STM32_FUNCTION(13, "FMC_NWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(54, "PD6"), + STM32_FUNCTION(0, "GPIOD6"), + STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(8, "USART2_RX"), + STM32_FUNCTION(13, "FMC_NWAIT"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(55, "PD7"), + STM32_FUNCTION(0, "GPIOD7"), + STM32_FUNCTION(8, "USART2_CK"), + STM32_FUNCTION(13, "FMC_NE1 FMC_NCE2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(56, "PD8"), + STM32_FUNCTION(0, "GPIOD8"), + STM32_FUNCTION(8, "USART3_TX"), + STM32_FUNCTION(13, "FMC_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(57, "PD9"), + STM32_FUNCTION(0, "GPIOD9"), + STM32_FUNCTION(8, "USART3_RX"), + STM32_FUNCTION(13, "FMC_D14"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(58, "PD10"), + STM32_FUNCTION(0, "GPIOD10"), + STM32_FUNCTION(8, "USART3_CK"), + STM32_FUNCTION(13, "FMC_D15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(59, "PD11"), + STM32_FUNCTION(0, "GPIOD11"), + STM32_FUNCTION(8, "USART3_CTS"), + STM32_FUNCTION(13, "FMC_A16"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(60, "PD12"), + STM32_FUNCTION(0, "GPIOD12"), + STM32_FUNCTION(3, "TIM4_CH1"), + STM32_FUNCTION(8, "USART3_RTS"), + STM32_FUNCTION(13, "FMC_A17"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(61, "PD13"), + STM32_FUNCTION(0, "GPIOD13"), + STM32_FUNCTION(3, "TIM4_CH2"), + STM32_FUNCTION(13, "FMC_A18"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(62, "PD14"), + STM32_FUNCTION(0, "GPIOD14"), + STM32_FUNCTION(3, "TIM4_CH3"), + STM32_FUNCTION(13, "FMC_D0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(63, "PD15"), + STM32_FUNCTION(0, "GPIOD15"), + STM32_FUNCTION(3, "TIM4_CH4"), + STM32_FUNCTION(13, "FMC_D1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(64, "PE0"), + STM32_FUNCTION(0, "GPIOE0"), + STM32_FUNCTION(3, "TIM4_ETR"), + STM32_FUNCTION(9, "UART8_RX"), + STM32_FUNCTION(13, "FMC_NBL0"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(65, "PE1"), + STM32_FUNCTION(0, "GPIOE1"), + STM32_FUNCTION(9, "UART8_TX"), + STM32_FUNCTION(13, "FMC_NBL1"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(66, "PE2"), + STM32_FUNCTION(0, "GPIOE2"), + STM32_FUNCTION(1, "TRACECLK"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_A"), + STM32_FUNCTION(12, "ETH_MII_TXD3"), + STM32_FUNCTION(13, "FMC_A23"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(67, "PE3"), + STM32_FUNCTION(0, "GPIOE3"), + STM32_FUNCTION(1, "TRACED0"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(13, "FMC_A19"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(68, "PE4"), + STM32_FUNCTION(0, "GPIOE4"), + STM32_FUNCTION(1, "TRACED1"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(7, "SAI1_FS_A"), + STM32_FUNCTION(13, "FMC_A20"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(69, "PE5"), + STM32_FUNCTION(0, "GPIOE5"), + STM32_FUNCTION(1, "TRACED2"), + STM32_FUNCTION(4, "TIM9_CH1"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_A"), + STM32_FUNCTION(13, "FMC_A21"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(70, "PE6"), + STM32_FUNCTION(0, "GPIOE6"), + STM32_FUNCTION(1, "TRACED3"), + STM32_FUNCTION(4, "TIM9_CH2"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(7, "SAI1_SD_A"), + STM32_FUNCTION(13, "FMC_A22"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(71, "PE7"), + STM32_FUNCTION(0, "GPIOE7"), + STM32_FUNCTION(2, "TIM1_ETR"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(13, "FMC_D4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(72, "PE8"), + STM32_FUNCTION(0, "GPIOE8"), + STM32_FUNCTION(2, "TIM1_CH1N"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(13, "FMC_D5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(73, "PE9"), + STM32_FUNCTION(0, "GPIOE9"), + STM32_FUNCTION(2, "TIM1_CH1"), + STM32_FUNCTION(13, "FMC_D6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(74, "PE10"), + STM32_FUNCTION(0, "GPIOE10"), + STM32_FUNCTION(2, "TIM1_CH2N"), + STM32_FUNCTION(13, "FMC_D7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(75, "PE11"), + STM32_FUNCTION(0, "GPIOE11"), + STM32_FUNCTION(2, "TIM1_CH2"), + STM32_FUNCTION(6, "SPI4_NSS"), + STM32_FUNCTION(13, "FMC_D8"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(76, "PE12"), + STM32_FUNCTION(0, "GPIOE12"), + STM32_FUNCTION(2, "TIM1_CH3N"), + STM32_FUNCTION(6, "SPI4_SCK"), + STM32_FUNCTION(13, "FMC_D9"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(77, "PE13"), + STM32_FUNCTION(0, "GPIOE13"), + STM32_FUNCTION(2, "TIM1_CH3"), + STM32_FUNCTION(6, "SPI4_MISO"), + STM32_FUNCTION(13, "FMC_D10"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(78, "PE14"), + STM32_FUNCTION(0, "GPIOE14"), + STM32_FUNCTION(2, "TIM1_CH4"), + STM32_FUNCTION(6, "SPI4_MOSI"), + STM32_FUNCTION(13, "FMC_D11"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(79, "PE15"), + STM32_FUNCTION(0, "GPIOE15"), + STM32_FUNCTION(2, "TIM1_BKIN"), + STM32_FUNCTION(13, "FMC_D12"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(80, "PF0"), + STM32_FUNCTION(0, "GPIOF0"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(13, "FMC_A0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(81, "PF1"), + STM32_FUNCTION(0, "GPIOF1"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(13, "FMC_A1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(82, "PF2"), + STM32_FUNCTION(0, "GPIOF2"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(13, "FMC_A2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(83, "PF3"), + STM32_FUNCTION(0, "GPIOF3"), + STM32_FUNCTION(13, "FMC_A3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(84, "PF4"), + STM32_FUNCTION(0, "GPIOF4"), + STM32_FUNCTION(13, "FMC_A4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(85, "PF5"), + STM32_FUNCTION(0, "GPIOF5"), + STM32_FUNCTION(13, "FMC_A5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(86, "PF6"), + STM32_FUNCTION(0, "GPIOF6"), + STM32_FUNCTION(4, "TIM10_CH1"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(7, "SAI1_SD_B"), + STM32_FUNCTION(9, "UART7_RX"), + STM32_FUNCTION(13, "FMC_NIORD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(87, "PF7"), + STM32_FUNCTION(0, "GPIOF7"), + STM32_FUNCTION(4, "TIM11_CH1"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(7, "SAI1_MCLK_B"), + STM32_FUNCTION(9, "UART7_TX"), + STM32_FUNCTION(13, "FMC_NREG"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(88, "PF8"), + STM32_FUNCTION(0, "GPIOF8"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(7, "SAI1_SCK_B"), + STM32_FUNCTION(10, "TIM13_CH1"), + STM32_FUNCTION(13, "FMC_NIOWR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(89, "PF9"), + STM32_FUNCTION(0, "GPIOF9"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(7, "SAI1_FS_B"), + STM32_FUNCTION(10, "TIM14_CH1"), + STM32_FUNCTION(13, "FMC_CD"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(90, "PF10"), + STM32_FUNCTION(0, "GPIOF10"), + STM32_FUNCTION(13, "FMC_INTR"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(91, "PF11"), + STM32_FUNCTION(0, "GPIOF11"), + STM32_FUNCTION(6, "SPI5_MOSI"), + STM32_FUNCTION(13, "FMC_SDNRAS"), + STM32_FUNCTION(14, "DCMI_D12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(92, "PF12"), + STM32_FUNCTION(0, "GPIOF12"), + STM32_FUNCTION(13, "FMC_A6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(93, "PF13"), + STM32_FUNCTION(0, "GPIOF13"), + STM32_FUNCTION(13, "FMC_A7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(94, "PF14"), + STM32_FUNCTION(0, "GPIOF14"), + STM32_FUNCTION(13, "FMC_A8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(95, "PF15"), + STM32_FUNCTION(0, "GPIOF15"), + STM32_FUNCTION(13, "FMC_A9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(96, "PG0"), + STM32_FUNCTION(0, "GPIOG0"), + STM32_FUNCTION(13, "FMC_A10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(97, "PG1"), + STM32_FUNCTION(0, "GPIOG1"), + STM32_FUNCTION(13, "FMC_A11"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(98, "PG2"), + STM32_FUNCTION(0, "GPIOG2"), + STM32_FUNCTION(13, "FMC_A12"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(99, "PG3"), + STM32_FUNCTION(0, "GPIOG3"), + STM32_FUNCTION(13, "FMC_A13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(100, "PG4"), + STM32_FUNCTION(0, "GPIOG4"), + STM32_FUNCTION(13, "FMC_A14 FMC_BA0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(101, "PG5"), + STM32_FUNCTION(0, "GPIOG5"), + STM32_FUNCTION(13, "FMC_A15 FMC_BA1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(102, "PG6"), + STM32_FUNCTION(0, "GPIOG6"), + STM32_FUNCTION(13, "FMC_INT2"), + STM32_FUNCTION(14, "DCMI_D12"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(103, "PG7"), + STM32_FUNCTION(0, "GPIOG7"), + STM32_FUNCTION(9, "USART6_CK"), + STM32_FUNCTION(13, "FMC_INT3"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(104, "PG8"), + STM32_FUNCTION(0, "GPIOG8"), + STM32_FUNCTION(6, "SPI6_NSS"), + STM32_FUNCTION(9, "USART6_RTS"), + STM32_FUNCTION(12, "ETH_PPS_OUT"), + STM32_FUNCTION(13, "FMC_SDCLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(105, "PG9"), + STM32_FUNCTION(0, "GPIOG9"), + STM32_FUNCTION(9, "USART6_RX"), + STM32_FUNCTION(13, "FMC_NE2 FMC_NCE3"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(106, "PG10"), + STM32_FUNCTION(0, "GPIOG10"), + STM32_FUNCTION(10, "LCD_G3"), + STM32_FUNCTION(13, "FMC_NCE4_1 FMC_NE3"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(107, "PG11"), + STM32_FUNCTION(0, "GPIOG11"), + STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"), + STM32_FUNCTION(13, "FMC_NCE4_2"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(108, "PG12"), + STM32_FUNCTION(0, "GPIOG12"), + STM32_FUNCTION(6, "SPI6_MISO"), + STM32_FUNCTION(9, "USART6_RTS"), + STM32_FUNCTION(10, "LCD_B4"), + STM32_FUNCTION(13, "FMC_NE4"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(109, "PG13"), + STM32_FUNCTION(0, "GPIOG13"), + STM32_FUNCTION(6, "SPI6_SCK"), + STM32_FUNCTION(9, "USART6_CTS"), + STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"), + STM32_FUNCTION(13, "FMC_A24"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(110, "PG14"), + STM32_FUNCTION(0, "GPIOG14"), + STM32_FUNCTION(6, "SPI6_MOSI"), + STM32_FUNCTION(9, "USART6_TX"), + STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"), + STM32_FUNCTION(13, "FMC_A25"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(111, "PG15"), + STM32_FUNCTION(0, "GPIOG15"), + STM32_FUNCTION(9, "USART6_CTS"), + STM32_FUNCTION(13, "FMC_SDNCAS"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(112, "PH0"), + STM32_FUNCTION(0, "GPIOH0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(113, "PH1"), + STM32_FUNCTION(0, "GPIOH1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(114, "PH2"), + STM32_FUNCTION(0, "GPIOH2"), + STM32_FUNCTION(12, "ETH_MII_CRS"), + STM32_FUNCTION(13, "FMC_SDCKE0"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(115, "PH3"), + STM32_FUNCTION(0, "GPIOH3"), + STM32_FUNCTION(12, "ETH_MII_COL"), + STM32_FUNCTION(13, "FMC_SDNE0"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(116, "PH4"), + STM32_FUNCTION(0, "GPIOH4"), + STM32_FUNCTION(5, "I2C2_SCL"), + STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(117, "PH5"), + STM32_FUNCTION(0, "GPIOH5"), + STM32_FUNCTION(5, "I2C2_SDA"), + STM32_FUNCTION(6, "SPI5_NSS"), + STM32_FUNCTION(13, "FMC_SDNWE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(118, "PH6"), + STM32_FUNCTION(0, "GPIOH6"), + STM32_FUNCTION(5, "I2C2_SMBA"), + STM32_FUNCTION(6, "SPI5_SCK"), + STM32_FUNCTION(10, "TIM12_CH1"), + STM32_FUNCTION(12, "ETH_MII_RXD2"), + STM32_FUNCTION(13, "FMC_SDNE1"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(119, "PH7"), + STM32_FUNCTION(0, "GPIOH7"), + STM32_FUNCTION(5, "I2C3_SCL"), + STM32_FUNCTION(6, "SPI5_MISO"), + STM32_FUNCTION(12, "ETH_MII_RXD3"), + STM32_FUNCTION(13, "FMC_SDCKE1"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(120, "PH8"), + STM32_FUNCTION(0, "GPIOH8"), + STM32_FUNCTION(5, "I2C3_SDA"), + STM32_FUNCTION(13, "FMC_D16"), + STM32_FUNCTION(14, "DCMI_HSYNC"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(121, "PH9"), + STM32_FUNCTION(0, "GPIOH9"), + STM32_FUNCTION(5, "I2C3_SMBA"), + STM32_FUNCTION(10, "TIM12_CH2"), + STM32_FUNCTION(13, "FMC_D17"), + STM32_FUNCTION(14, "DCMI_D0"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(122, "PH10"), + STM32_FUNCTION(0, "GPIOH10"), + STM32_FUNCTION(3, "TIM5_CH1"), + STM32_FUNCTION(13, "FMC_D18"), + STM32_FUNCTION(14, "DCMI_D1"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(123, "PH11"), + STM32_FUNCTION(0, "GPIOH11"), + STM32_FUNCTION(3, "TIM5_CH2"), + STM32_FUNCTION(13, "FMC_D19"), + STM32_FUNCTION(14, "DCMI_D2"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(124, "PH12"), + STM32_FUNCTION(0, "GPIOH12"), + STM32_FUNCTION(3, "TIM5_CH3"), + STM32_FUNCTION(13, "FMC_D20"), + STM32_FUNCTION(14, "DCMI_D3"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(125, "PH13"), + STM32_FUNCTION(0, "GPIOH13"), + STM32_FUNCTION(4, "TIM8_CH1N"), + STM32_FUNCTION(10, "CAN1_TX"), + STM32_FUNCTION(13, "FMC_D21"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(126, "PH14"), + STM32_FUNCTION(0, "GPIOH14"), + STM32_FUNCTION(4, "TIM8_CH2N"), + STM32_FUNCTION(13, "FMC_D22"), + STM32_FUNCTION(14, "DCMI_D4"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(127, "PH15"), + STM32_FUNCTION(0, "GPIOH15"), + STM32_FUNCTION(4, "TIM8_CH3N"), + STM32_FUNCTION(13, "FMC_D23"), + STM32_FUNCTION(14, "DCMI_D11"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(128, "PI0"), + STM32_FUNCTION(0, "GPIOI0"), + STM32_FUNCTION(3, "TIM5_CH4"), + STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), + STM32_FUNCTION(13, "FMC_D24"), + STM32_FUNCTION(14, "DCMI_D13"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(129, "PI1"), + STM32_FUNCTION(0, "GPIOI1"), + STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), + STM32_FUNCTION(13, "FMC_D25"), + STM32_FUNCTION(14, "DCMI_D8"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(130, "PI2"), + STM32_FUNCTION(0, "GPIOI2"), + STM32_FUNCTION(4, "TIM8_CH4"), + STM32_FUNCTION(6, "SPI2_MISO"), + STM32_FUNCTION(7, "I2S2EXT_SD"), + STM32_FUNCTION(13, "FMC_D26"), + STM32_FUNCTION(14, "DCMI_D9"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(131, "PI3"), + STM32_FUNCTION(0, "GPIOI3"), + STM32_FUNCTION(4, "TIM8_ETR"), + STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"), + STM32_FUNCTION(13, "FMC_D27"), + STM32_FUNCTION(14, "DCMI_D10"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(132, "PI4"), + STM32_FUNCTION(0, "GPIOI4"), + STM32_FUNCTION(4, "TIM8_BKIN"), + STM32_FUNCTION(13, "FMC_NBL2"), + STM32_FUNCTION(14, "DCMI_D5"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(133, "PI5"), + STM32_FUNCTION(0, "GPIOI5"), + STM32_FUNCTION(4, "TIM8_CH1"), + STM32_FUNCTION(13, "FMC_NBL3"), + STM32_FUNCTION(14, "DCMI_VSYNC"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(134, "PI6"), + STM32_FUNCTION(0, "GPIOI6"), + STM32_FUNCTION(4, "TIM8_CH2"), + STM32_FUNCTION(13, "FMC_D28"), + STM32_FUNCTION(14, "DCMI_D6"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(135, "PI7"), + STM32_FUNCTION(0, "GPIOI7"), + STM32_FUNCTION(4, "TIM8_CH3"), + STM32_FUNCTION(13, "FMC_D29"), + STM32_FUNCTION(14, "DCMI_D7"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(136, "PI8"), + STM32_FUNCTION(0, "GPIOI8"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(137, "PI9"), + STM32_FUNCTION(0, "GPIOI9"), + STM32_FUNCTION(10, "CAN1_RX"), + STM32_FUNCTION(13, "FMC_D30"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(138, "PI10"), + STM32_FUNCTION(0, "GPIOI10"), + STM32_FUNCTION(12, "ETH_MII_RX_ER"), + STM32_FUNCTION(13, "FMC_D31"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(139, "PI11"), + STM32_FUNCTION(0, "GPIOI11"), + STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(140, "PI12"), + STM32_FUNCTION(0, "GPIOI12"), + STM32_FUNCTION(15, "LCD_HSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(141, "PI13"), + STM32_FUNCTION(0, "GPIOI13"), + STM32_FUNCTION(15, "LCD_VSYNC"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(142, "PI14"), + STM32_FUNCTION(0, "GPIOI14"), + STM32_FUNCTION(15, "LCD_CLK"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(143, "PI15"), + STM32_FUNCTION(0, "GPIOI15"), + STM32_FUNCTION(15, "LCD_R0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(144, "PJ0"), + STM32_FUNCTION(0, "GPIOJ0"), + STM32_FUNCTION(15, "LCD_R1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(145, "PJ1"), + STM32_FUNCTION(0, "GPIOJ1"), + STM32_FUNCTION(15, "LCD_R2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(146, "PJ2"), + STM32_FUNCTION(0, "GPIOJ2"), + STM32_FUNCTION(15, "LCD_R3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(147, "PJ3"), + STM32_FUNCTION(0, "GPIOJ3"), + STM32_FUNCTION(15, "LCD_R4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(148, "PJ4"), + STM32_FUNCTION(0, "GPIOJ4"), + STM32_FUNCTION(15, "LCD_R5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(149, "PJ5"), + STM32_FUNCTION(0, "GPIOJ5"), + STM32_FUNCTION(15, "LCD_R6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(150, "PJ6"), + STM32_FUNCTION(0, "GPIOJ6"), + STM32_FUNCTION(15, "LCD_R7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(151, "PJ7"), + STM32_FUNCTION(0, "GPIOJ7"), + STM32_FUNCTION(15, "LCD_G0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(152, "PJ8"), + STM32_FUNCTION(0, "GPIOJ8"), + STM32_FUNCTION(15, "LCD_G1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(153, "PJ9"), + STM32_FUNCTION(0, "GPIOJ9"), + STM32_FUNCTION(15, "LCD_G2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(154, "PJ10"), + STM32_FUNCTION(0, "GPIOJ10"), + STM32_FUNCTION(15, "LCD_G3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(155, "PJ11"), + STM32_FUNCTION(0, "GPIOJ11"), + STM32_FUNCTION(15, "LCD_G4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(156, "PJ12"), + STM32_FUNCTION(0, "GPIOJ12"), + STM32_FUNCTION(15, "LCD_B0"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(157, "PJ13"), + STM32_FUNCTION(0, "GPIOJ13"), + STM32_FUNCTION(15, "LCD_B1"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(158, "PJ14"), + STM32_FUNCTION(0, "GPIOJ14"), + STM32_FUNCTION(15, "LCD_B2"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(159, "PJ15"), + STM32_FUNCTION(0, "GPIOJ15"), + STM32_FUNCTION(15, "LCD_B3"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(160, "PK0"), + STM32_FUNCTION(0, "GPIOK0"), + STM32_FUNCTION(15, "LCD_G5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(161, "PK1"), + STM32_FUNCTION(0, "GPIOK1"), + STM32_FUNCTION(15, "LCD_G6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(162, "PK2"), + STM32_FUNCTION(0, "GPIOK2"), + STM32_FUNCTION(15, "LCD_G7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(163, "PK3"), + STM32_FUNCTION(0, "GPIOK3"), + STM32_FUNCTION(15, "LCD_B4"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(164, "PK4"), + STM32_FUNCTION(0, "GPIOK4"), + STM32_FUNCTION(15, "LCD_B5"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(165, "PK5"), + STM32_FUNCTION(0, "GPIOK5"), + STM32_FUNCTION(15, "LCD_B6"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(166, "PK6"), + STM32_FUNCTION(0, "GPIOK6"), + STM32_FUNCTION(15, "LCD_B7"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), + STM32_PIN( + PINCTRL_PIN(167, "PK7"), + STM32_FUNCTION(0, "GPIOK7"), + STM32_FUNCTION(15, "LCD_DE"), + STM32_FUNCTION(16, "EVENTOUT"), + STM32_FUNCTION(17, "ANALOG") + ), +}; + +static struct stm32_pinctrl_match_data stm32f429_match_data = { + .pins = stm32f429_pins, + .npins = ARRAY_SIZE(stm32f429_pins), +}; + +static const struct of_device_id stm32f429_pctrl_match[] = { + { + .compatible = "st,stm32f429-pinctrl", + .data = &stm32f429_match_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, stm32f429_pctrl_match); + +static struct platform_driver stm32f429_pinctrl_driver = { + .probe = stm32_pctl_probe, + .driver = { + .name = "stm32f429-pinctrl", + .of_match_table = stm32f429_pctrl_match, + }, +}; + +static int __init stm32f429_pinctrl_init(void) +{ + return platform_driver_register(&stm32f429_pinctrl_driver); +} + +module_init(stm32f429_pinctrl_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("STM32F429 Pinctrl Driver"); +MODULE_AUTHOR("Maxime Coquelin <mcoquelin.stm32@gmail.com>"); diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index f8dbc8bec0e1..ac8388e67340 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -1,67 +1,67 @@ if ARCH_SUNXI -config PINCTRL_SUNXI_COMMON +config PINCTRL_SUNXI bool select PINMUX select GENERIC_PINCONF config PINCTRL_SUN4I_A10 def_bool MACH_SUN4I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN5I_A10S def_bool MACH_SUN5I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN5I_A13 def_bool MACH_SUN5I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN6I_A31 def_bool MACH_SUN6I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN6I_A31S def_bool MACH_SUN6I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN6I_A31_R def_bool MACH_SUN6I depends on RESET_CONTROLLER - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN7I_A20 def_bool MACH_SUN7I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN8I_A23 def_bool MACH_SUN8I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN8I_A33 def_bool MACH_SUN8I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN8I_A83T def_bool MACH_SUN8I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN8I_A23_R def_bool MACH_SUN8I depends on RESET_CONTROLLER - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN8I_H3 def_bool MACH_SUN8I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN9I_A80 def_bool MACH_SUN9I - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI config PINCTRL_SUN9I_A80_R def_bool MACH_SUN9I depends on RESET_CONTROLLER - select PINCTRL_SUNXI_COMMON + select PINCTRL_SUNXI endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index ef82f22bb9ef..dac1bd0cda4a 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -1,5 +1,5 @@ # Core -obj-$(CONFIG_PINCTRL_SUNXI_COMMON) += pinctrl-sunxi.o +obj-y += pinctrl-sunxi.o # SoC Drivers obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig new file mode 100644 index 000000000000..24e20cc08d5b --- /dev/null +++ b/drivers/pinctrl/tegra/Kconfig @@ -0,0 +1,30 @@ +config PINCTRL_TEGRA + bool + select PINMUX + select PINCONF + +config PINCTRL_TEGRA20 + bool + select PINCTRL_TEGRA + +config PINCTRL_TEGRA30 + bool + select PINCTRL_TEGRA + +config PINCTRL_TEGRA114 + bool + select PINCTRL_TEGRA + +config PINCTRL_TEGRA124 + bool + select PINCTRL_TEGRA + +config PINCTRL_TEGRA210 + bool + select PINCTRL_TEGRA + +config PINCTRL_TEGRA_XUSB + def_bool y if ARCH_TEGRA + select GENERIC_PHY + select PINCONF + select PINMUX diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile new file mode 100644 index 000000000000..a927379b6794 --- /dev/null +++ b/drivers/pinctrl/tegra/Makefile @@ -0,0 +1,7 @@ +obj-y += pinctrl-tegra.o +obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o +obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o +obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o +obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o +obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o +obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index bd3aa5a4fd6d..2f06029c9405 100644 --- a/drivers/pinctrl/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -24,8 +24,8 @@ #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> -#include "core.h" -#include "pinctrl-utils.h" +#include "../core.h" +#include "../pinctrl-utils.h" #define XUSB_PADCTL_ELPG_PROGRAM 0x01c #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 9da4da219a07..49388822c0e9 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -30,9 +30,9 @@ #include <linux/pinctrl/pinconf.h> #include <linux/slab.h> -#include "core.h" +#include "../core.h" +#include "../pinctrl-utils.h" #include "pinctrl-tegra.h" -#include "pinctrl-utils.h" struct tegra_pmx { struct device *dev; diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 1615db7e3a4b..1615db7e3a4b 100644 --- a/drivers/pinctrl/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/tegra/pinctrl-tegra114.c index 05e49d5137ab..05e49d5137ab 100644 --- a/drivers/pinctrl/pinctrl-tegra114.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra114.c diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/tegra/pinctrl-tegra124.c index 7cd44c7c296d..7cd44c7c296d 100644 --- a/drivers/pinctrl/pinctrl-tegra124.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra124.c diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index 4833db4433d9..4833db4433d9 100644 --- a/drivers/pinctrl/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c diff --git a/drivers/pinctrl/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c index 252b464901c0..252b464901c0 100644 --- a/drivers/pinctrl/pinctrl-tegra210.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/tegra/pinctrl-tegra30.c index 47b2fd8bb2e9..47b2fd8bb2e9 100644 --- a/drivers/pinctrl/pinctrl-tegra30.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra30.c |